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mips: sigaltstack args
[qemu/ar7.git] / linux-user / main.c
blobd695610349b79a8a418096731fc95e71d98595f6
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "cache-utils.h"
32 #include "cpu.h"
33 #include "tcg.h"
34 #include "qemu-timer.h"
35 #include "envlist.h"
36
37 #define DEBUG_LOGFILE "/tmp/qemu.log"
38
39 char *exec_path;
40
41 int singlestep;
42 unsigned long mmap_min_addr;
43 #if defined(CONFIG_USE_GUEST_BASE)
44 unsigned long guest_base;
45 int have_guest_base;
46 unsigned long reserved_va;
47 #endif
48
49 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
50 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
51
52 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
53 we allocate a bigger stack. Need a better solution, for example
54 by remapping the process stack directly at the right place */
55 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
56
57 void gemu_log(const char *fmt, ...)
58 {
59 va_list ap;
60
61 va_start(ap, fmt);
62 vfprintf(stderr, fmt, ap);
63 va_end(ap);
64 }
65
66 #if defined(TARGET_I386)
67 int cpu_get_pic_interrupt(CPUState *env)
68 {
69 return -1;
70 }
71 #endif
72
73 /* timers for rdtsc */
74
75 #if 0
76
77 static uint64_t emu_time;
78
79 int64_t cpu_get_real_ticks(void)
80 {
81 return emu_time++;
82 }
83
84 #endif
85
86 #if defined(CONFIG_USE_NPTL)
87 /***********************************************************/
88 /* Helper routines for implementing atomic operations. */
89
90 /* To implement exclusive operations we force all cpus to syncronise.
91 We don't require a full sync, only that no cpus are executing guest code.
92 The alternative is to map target atomic ops onto host equivalents,
93 which requires quite a lot of per host/target work. */
94 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
95 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
96 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
97 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
98 static int pending_cpus;
99
100 /* Make sure everything is in a consistent state for calling fork(). */
101 void fork_start(void)
102 {
103 pthread_mutex_lock(&tb_lock);
104 pthread_mutex_lock(&exclusive_lock);
105 mmap_fork_start();
106 }
107
108 void fork_end(int child)
109 {
110 mmap_fork_end(child);
111 if (child) {
112 /* Child processes created by fork() only have a single thread.
113 Discard information about the parent threads. */
114 first_cpu = thread_env;
115 thread_env->next_cpu = NULL;
116 pending_cpus = 0;
117 pthread_mutex_init(&exclusive_lock, NULL);
118 pthread_mutex_init(&cpu_list_mutex, NULL);
119 pthread_cond_init(&exclusive_cond, NULL);
120 pthread_cond_init(&exclusive_resume, NULL);
121 pthread_mutex_init(&tb_lock, NULL);
122 gdbserver_fork(thread_env);
123 } else {
124 pthread_mutex_unlock(&exclusive_lock);
125 pthread_mutex_unlock(&tb_lock);
126 }
127 }
128
129 /* Wait for pending exclusive operations to complete. The exclusive lock
130 must be held. */
131 static inline void exclusive_idle(void)
132 {
133 while (pending_cpus) {
134 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
135 }
136 }
137
138 /* Start an exclusive operation.
139 Must only be called from outside cpu_arm_exec. */
140 static inline void start_exclusive(void)
141 {
142 CPUState *other;
143 pthread_mutex_lock(&exclusive_lock);
144 exclusive_idle();
145
146 pending_cpus = 1;
147 /* Make all other cpus stop executing. */
148 for (other = first_cpu; other; other = other->next_cpu) {
149 if (other->running) {
150 pending_cpus++;
151 cpu_exit(other);
152 }
153 }
154 if (pending_cpus > 1) {
155 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
156 }
157 }
158
159 /* Finish an exclusive operation. */
160 static inline void end_exclusive(void)
161 {
162 pending_cpus = 0;
163 pthread_cond_broadcast(&exclusive_resume);
164 pthread_mutex_unlock(&exclusive_lock);
165 }
166
167 /* Wait for exclusive ops to finish, and begin cpu execution. */
168 static inline void cpu_exec_start(CPUState *env)
169 {
170 pthread_mutex_lock(&exclusive_lock);
171 exclusive_idle();
172 env->running = 1;
173 pthread_mutex_unlock(&exclusive_lock);
174 }
175
176 /* Mark cpu as not executing, and release pending exclusive ops. */
177 static inline void cpu_exec_end(CPUState *env)
178 {
179 pthread_mutex_lock(&exclusive_lock);
180 env->running = 0;
181 if (pending_cpus > 1) {
182 pending_cpus--;
183 if (pending_cpus == 1) {
184 pthread_cond_signal(&exclusive_cond);
185 }
186 }
187 exclusive_idle();
188 pthread_mutex_unlock(&exclusive_lock);
189 }
190
191 void cpu_list_lock(void)
192 {
193 pthread_mutex_lock(&cpu_list_mutex);
194 }
195
196 void cpu_list_unlock(void)
197 {
198 pthread_mutex_unlock(&cpu_list_mutex);
199 }
200 #else /* if !CONFIG_USE_NPTL */
201 /* These are no-ops because we are not threadsafe. */
202 static inline void cpu_exec_start(CPUState *env)
203 {
204 }
205
206 static inline void cpu_exec_end(CPUState *env)
207 {
208 }
209
210 static inline void start_exclusive(void)
211 {
212 }
213
214 static inline void end_exclusive(void)
215 {
216 }
217
218 void fork_start(void)
219 {
220 }
221
222 void fork_end(int child)
223 {
224 if (child) {
225 gdbserver_fork(thread_env);
226 }
227 }
228
229 void cpu_list_lock(void)
230 {
231 }
232
233 void cpu_list_unlock(void)
234 {
235 }
236 #endif
237
238
239 #ifdef TARGET_I386
240 /***********************************************************/
241 /* CPUX86 core interface */
242
243 void cpu_smm_update(CPUState *env)
244 {
245 }
246
247 uint64_t cpu_get_tsc(CPUX86State *env)
248 {
249 return cpu_get_real_ticks();
250 }
251
252 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
253 int flags)
254 {
255 unsigned int e1, e2;
256 uint32_t *p;
257 e1 = (addr << 16) | (limit & 0xffff);
258 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
259 e2 |= flags;
260 p = ptr;
261 p[0] = tswap32(e1);
262 p[1] = tswap32(e2);
263 }
264
265 static uint64_t *idt_table;
266 #ifdef TARGET_X86_64
267 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
268 uint64_t addr, unsigned int sel)
269 {
270 uint32_t *p, e1, e2;
271 e1 = (addr & 0xffff) | (sel << 16);
272 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
273 p = ptr;
274 p[0] = tswap32(e1);
275 p[1] = tswap32(e2);
276 p[2] = tswap32(addr >> 32);
277 p[3] = 0;
278 }
279 /* only dpl matters as we do only user space emulation */
280 static void set_idt(int n, unsigned int dpl)
281 {
282 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
283 }
284 #else
285 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
286 uint32_t addr, unsigned int sel)
287 {
288 uint32_t *p, e1, e2;
289 e1 = (addr & 0xffff) | (sel << 16);
290 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
291 p = ptr;
292 p[0] = tswap32(e1);
293 p[1] = tswap32(e2);
294 }
295
296 /* only dpl matters as we do only user space emulation */
297 static void set_idt(int n, unsigned int dpl)
298 {
299 set_gate(idt_table + n, 0, dpl, 0, 0);
300 }
301 #endif
302
303 void cpu_loop(CPUX86State *env)
304 {
305 int trapnr;
306 abi_ulong pc;
307 target_siginfo_t info;
308
309 for(;;) {
310 trapnr = cpu_x86_exec(env);
311 switch(trapnr) {
312 case 0x80:
313 /* linux syscall from int $0x80 */
314 env->regs[R_EAX] = do_syscall(env,
315 env->regs[R_EAX],
316 env->regs[R_EBX],
317 env->regs[R_ECX],
318 env->regs[R_EDX],
319 env->regs[R_ESI],
320 env->regs[R_EDI],
321 env->regs[R_EBP],
322 0, 0);
323 break;
324 #ifndef TARGET_ABI32
325 case EXCP_SYSCALL:
326 /* linux syscall from syscall instruction */
327 env->regs[R_EAX] = do_syscall(env,
328 env->regs[R_EAX],
329 env->regs[R_EDI],
330 env->regs[R_ESI],
331 env->regs[R_EDX],
332 env->regs[10],
333 env->regs[8],
334 env->regs[9],
335 0, 0);
336 env->eip = env->exception_next_eip;
337 break;
338 #endif
339 case EXCP0B_NOSEG:
340 case EXCP0C_STACK:
341 info.si_signo = SIGBUS;
342 info.si_errno = 0;
343 info.si_code = TARGET_SI_KERNEL;
344 info._sifields._sigfault._addr = 0;
345 queue_signal(env, info.si_signo, &info);
346 break;
347 case EXCP0D_GPF:
348 /* XXX: potential problem if ABI32 */
349 #ifndef TARGET_X86_64
350 if (env->eflags & VM_MASK) {
351 handle_vm86_fault(env);
352 } else
353 #endif
354 {
355 info.si_signo = SIGSEGV;
356 info.si_errno = 0;
357 info.si_code = TARGET_SI_KERNEL;
358 info._sifields._sigfault._addr = 0;
359 queue_signal(env, info.si_signo, &info);
360 }
361 break;
362 case EXCP0E_PAGE:
363 info.si_signo = SIGSEGV;
364 info.si_errno = 0;
365 if (!(env->error_code & 1))
366 info.si_code = TARGET_SEGV_MAPERR;
367 else
368 info.si_code = TARGET_SEGV_ACCERR;
369 info._sifields._sigfault._addr = env->cr[2];
370 queue_signal(env, info.si_signo, &info);
371 break;
372 case EXCP00_DIVZ:
373 #ifndef TARGET_X86_64
374 if (env->eflags & VM_MASK) {
375 handle_vm86_trap(env, trapnr);
376 } else
377 #endif
378 {
379 /* division by zero */
380 info.si_signo = SIGFPE;
381 info.si_errno = 0;
382 info.si_code = TARGET_FPE_INTDIV;
383 info._sifields._sigfault._addr = env->eip;
384 queue_signal(env, info.si_signo, &info);
385 }
386 break;
387 case EXCP01_DB:
388 case EXCP03_INT3:
389 #ifndef TARGET_X86_64
390 if (env->eflags & VM_MASK) {
391 handle_vm86_trap(env, trapnr);
392 } else
393 #endif
394 {
395 info.si_signo = SIGTRAP;
396 info.si_errno = 0;
397 if (trapnr == EXCP01_DB) {
398 info.si_code = TARGET_TRAP_BRKPT;
399 info._sifields._sigfault._addr = env->eip;
400 } else {
401 info.si_code = TARGET_SI_KERNEL;
402 info._sifields._sigfault._addr = 0;
403 }
404 queue_signal(env, info.si_signo, &info);
405 }
406 break;
407 case EXCP04_INTO:
408 case EXCP05_BOUND:
409 #ifndef TARGET_X86_64
410 if (env->eflags & VM_MASK) {
411 handle_vm86_trap(env, trapnr);
412 } else
413 #endif
414 {
415 info.si_signo = SIGSEGV;
416 info.si_errno = 0;
417 info.si_code = TARGET_SI_KERNEL;
418 info._sifields._sigfault._addr = 0;
419 queue_signal(env, info.si_signo, &info);
420 }
421 break;
422 case EXCP06_ILLOP:
423 info.si_signo = SIGILL;
424 info.si_errno = 0;
425 info.si_code = TARGET_ILL_ILLOPN;
426 info._sifields._sigfault._addr = env->eip;
427 queue_signal(env, info.si_signo, &info);
428 break;
429 case EXCP_INTERRUPT:
430 /* just indicate that signals should be handled asap */
431 break;
432 case EXCP_DEBUG:
433 {
434 int sig;
435
436 sig = gdb_handlesig (env, TARGET_SIGTRAP);
437 if (sig)
438 {
439 info.si_signo = sig;
440 info.si_errno = 0;
441 info.si_code = TARGET_TRAP_BRKPT;
442 queue_signal(env, info.si_signo, &info);
443 }
444 }
445 break;
446 default:
447 pc = env->segs[R_CS].base + env->eip;
448 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
449 (long)pc, trapnr);
450 abort();
451 }
452 process_pending_signals(env);
453 }
454 }
455 #endif
456
457 #ifdef TARGET_ARM
458
459 /* Handle a jump to the kernel code page. */
460 static int
461 do_kernel_trap(CPUARMState *env)
462 {
463 uint32_t addr;
464 uint32_t cpsr;
465 uint32_t val;
466
467 switch (env->regs[15]) {
468 case 0xffff0fa0: /* __kernel_memory_barrier */
469 /* ??? No-op. Will need to do better for SMP. */
470 break;
471 case 0xffff0fc0: /* __kernel_cmpxchg */
472 /* XXX: This only works between threads, not between processes.
473 It's probably possible to implement this with native host
474 operations. However things like ldrex/strex are much harder so
475 there's not much point trying. */
476 start_exclusive();
477 cpsr = cpsr_read(env);
478 addr = env->regs[2];
479 /* FIXME: This should SEGV if the access fails. */
480 if (get_user_u32(val, addr))
481 val = ~env->regs[0];
482 if (val == env->regs[0]) {
483 val = env->regs[1];
484 /* FIXME: Check for segfaults. */
485 put_user_u32(val, addr);
486 env->regs[0] = 0;
487 cpsr |= CPSR_C;
488 } else {
489 env->regs[0] = -1;
490 cpsr &= ~CPSR_C;
491 }
492 cpsr_write(env, cpsr, CPSR_C);
493 end_exclusive();
494 break;
495 case 0xffff0fe0: /* __kernel_get_tls */
496 env->regs[0] = env->cp15.c13_tls2;
497 break;
498 default:
499 return 1;
500 }
501 /* Jump back to the caller. */
502 addr = env->regs[14];
503 if (addr & 1) {
504 env->thumb = 1;
505 addr &= ~1;
506 }
507 env->regs[15] = addr;
508
509 return 0;
510 }
511
512 static int do_strex(CPUARMState *env)
513 {
514 uint32_t val;
515 int size;
516 int rc = 1;
517 int segv = 0;
518 uint32_t addr;
519 start_exclusive();
520 addr = env->exclusive_addr;
521 if (addr != env->exclusive_test) {
522 goto fail;
523 }
524 size = env->exclusive_info & 0xf;
525 switch (size) {
526 case 0:
527 segv = get_user_u8(val, addr);
528 break;
529 case 1:
530 segv = get_user_u16(val, addr);
531 break;
532 case 2:
533 case 3:
534 segv = get_user_u32(val, addr);
535 break;
536 default:
537 abort();
538 }
539 if (segv) {
540 env->cp15.c6_data = addr;
541 goto done;
542 }
543 if (val != env->exclusive_val) {
544 goto fail;
545 }
546 if (size == 3) {
547 segv = get_user_u32(val, addr + 4);
548 if (segv) {
549 env->cp15.c6_data = addr + 4;
550 goto done;
551 }
552 if (val != env->exclusive_high) {
553 goto fail;
554 }
555 }
556 val = env->regs[(env->exclusive_info >> 8) & 0xf];
557 switch (size) {
558 case 0:
559 segv = put_user_u8(val, addr);
560 break;
561 case 1:
562 segv = put_user_u16(val, addr);
563 break;
564 case 2:
565 case 3:
566 segv = put_user_u32(val, addr);
567 break;
568 }
569 if (segv) {
570 env->cp15.c6_data = addr;
571 goto done;
572 }
573 if (size == 3) {
574 val = env->regs[(env->exclusive_info >> 12) & 0xf];
575 segv = put_user_u32(val, addr + 4);
576 if (segv) {
577 env->cp15.c6_data = addr + 4;
578 goto done;
579 }
580 }
581 rc = 0;
582 fail:
583 env->regs[15] += 4;
584 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
585 done:
586 end_exclusive();
587 return segv;
588 }
589
590 void cpu_loop(CPUARMState *env)
591 {
592 int trapnr;
593 unsigned int n, insn;
594 target_siginfo_t info;
595 uint32_t addr;
596
597 for(;;) {
598 cpu_exec_start(env);
599 trapnr = cpu_arm_exec(env);
600 cpu_exec_end(env);
601 switch(trapnr) {
602 case EXCP_UDEF:
603 {
604 TaskState *ts = env->opaque;
605 uint32_t opcode;
606 int rc;
607
608 /* we handle the FPU emulation here, as Linux */
609 /* we get the opcode */
610 /* FIXME - what to do if get_user() fails? */
611 get_user_u32(opcode, env->regs[15]);
612
613 rc = EmulateAll(opcode, &ts->fpa, env);
614 if (rc == 0) { /* illegal instruction */
615 info.si_signo = SIGILL;
616 info.si_errno = 0;
617 info.si_code = TARGET_ILL_ILLOPN;
618 info._sifields._sigfault._addr = env->regs[15];
619 queue_signal(env, info.si_signo, &info);
620 } else if (rc < 0) { /* FP exception */
621 int arm_fpe=0;
622
623 /* translate softfloat flags to FPSR flags */
624 if (-rc & float_flag_invalid)
625 arm_fpe |= BIT_IOC;
626 if (-rc & float_flag_divbyzero)
627 arm_fpe |= BIT_DZC;
628 if (-rc & float_flag_overflow)
629 arm_fpe |= BIT_OFC;
630 if (-rc & float_flag_underflow)
631 arm_fpe |= BIT_UFC;
632 if (-rc & float_flag_inexact)
633 arm_fpe |= BIT_IXC;
634
635 FPSR fpsr = ts->fpa.fpsr;
636 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
637
638 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
639 info.si_signo = SIGFPE;
640 info.si_errno = 0;
641
642 /* ordered by priority, least first */
643 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
644 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
645 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
646 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
647 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
648
649 info._sifields._sigfault._addr = env->regs[15];
650 queue_signal(env, info.si_signo, &info);
651 } else {
652 env->regs[15] += 4;
653 }
654
655 /* accumulate unenabled exceptions */
656 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
657 fpsr |= BIT_IXC;
658 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
659 fpsr |= BIT_UFC;
660 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
661 fpsr |= BIT_OFC;
662 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
663 fpsr |= BIT_DZC;
664 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
665 fpsr |= BIT_IOC;
666 ts->fpa.fpsr=fpsr;
667 } else { /* everything OK */
668 /* increment PC */
669 env->regs[15] += 4;
670 }
671 }
672 break;
673 case EXCP_SWI:
674 case EXCP_BKPT:
675 {
676 env->eabi = 1;
677 /* system call */
678 if (trapnr == EXCP_BKPT) {
679 if (env->thumb) {
680 /* FIXME - what to do if get_user() fails? */
681 get_user_u16(insn, env->regs[15]);
682 n = insn & 0xff;
683 env->regs[15] += 2;
684 } else {
685 /* FIXME - what to do if get_user() fails? */
686 get_user_u32(insn, env->regs[15]);
687 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
688 env->regs[15] += 4;
689 }
690 } else {
691 if (env->thumb) {
692 /* FIXME - what to do if get_user() fails? */
693 get_user_u16(insn, env->regs[15] - 2);
694 n = insn & 0xff;
695 } else {
696 /* FIXME - what to do if get_user() fails? */
697 get_user_u32(insn, env->regs[15] - 4);
698 n = insn & 0xffffff;
699 }
700 }
701
702 if (n == ARM_NR_cacheflush) {
703 /* nop */
704 } else if (n == ARM_NR_semihosting
705 || n == ARM_NR_thumb_semihosting) {
706 env->regs[0] = do_arm_semihosting (env);
707 } else if (n == 0 || n >= ARM_SYSCALL_BASE
708 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
709 /* linux syscall */
710 if (env->thumb || n == 0) {
711 n = env->regs[7];
712 } else {
713 n -= ARM_SYSCALL_BASE;
714 env->eabi = 0;
715 }
716 if ( n > ARM_NR_BASE) {
717 switch (n) {
718 case ARM_NR_cacheflush:
719 /* nop */
720 break;
721 case ARM_NR_set_tls:
722 cpu_set_tls(env, env->regs[0]);
723 env->regs[0] = 0;
724 break;
725 default:
726 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
727 n);
728 env->regs[0] = -TARGET_ENOSYS;
729 break;
730 }
731 } else {
732 env->regs[0] = do_syscall(env,
733 n,
734 env->regs[0],
735 env->regs[1],
736 env->regs[2],
737 env->regs[3],
738 env->regs[4],
739 env->regs[5],
740 0, 0);
741 }
742 } else {
743 goto error;
744 }
745 }
746 break;
747 case EXCP_INTERRUPT:
748 /* just indicate that signals should be handled asap */
749 break;
750 case EXCP_PREFETCH_ABORT:
751 addr = env->cp15.c6_insn;
752 goto do_segv;
753 case EXCP_DATA_ABORT:
754 addr = env->cp15.c6_data;
755 goto do_segv;
756 do_segv:
757 {
758 info.si_signo = SIGSEGV;
759 info.si_errno = 0;
760 /* XXX: check env->error_code */
761 info.si_code = TARGET_SEGV_MAPERR;
762 info._sifields._sigfault._addr = addr;
763 queue_signal(env, info.si_signo, &info);
764 }
765 break;
766 case EXCP_DEBUG:
767 {
768 int sig;
769
770 sig = gdb_handlesig (env, TARGET_SIGTRAP);
771 if (sig)
772 {
773 info.si_signo = sig;
774 info.si_errno = 0;
775 info.si_code = TARGET_TRAP_BRKPT;
776 queue_signal(env, info.si_signo, &info);
777 }
778 }
779 break;
780 case EXCP_KERNEL_TRAP:
781 if (do_kernel_trap(env))
782 goto error;
783 break;
784 case EXCP_STREX:
785 if (do_strex(env)) {
786 addr = env->cp15.c6_data;
787 goto do_segv;
788 }
789 break;
790 default:
791 error:
792 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
793 trapnr);
794 cpu_dump_state(env, stderr, fprintf, 0);
795 abort();
796 }
797 process_pending_signals(env);
798 }
799 }
800
801 #endif
802
803 #ifdef TARGET_UNICORE32
804
805 void cpu_loop(CPUState *env)
806 {
807 int trapnr;
808 unsigned int n, insn;
809 target_siginfo_t info;
810
811 for (;;) {
812 cpu_exec_start(env);
813 trapnr = uc32_cpu_exec(env);
814 cpu_exec_end(env);
815 switch (trapnr) {
816 case UC32_EXCP_PRIV:
817 {
818 /* system call */
819 get_user_u32(insn, env->regs[31] - 4);
820 n = insn & 0xffffff;
821
822 if (n >= UC32_SYSCALL_BASE) {
823 /* linux syscall */
824 n -= UC32_SYSCALL_BASE;
825 if (n == UC32_SYSCALL_NR_set_tls) {
826 cpu_set_tls(env, env->regs[0]);
827 env->regs[0] = 0;
828 } else {
829 env->regs[0] = do_syscall(env,
830 n,
831 env->regs[0],
832 env->regs[1],
833 env->regs[2],
834 env->regs[3],
835 env->regs[4],
836 env->regs[5],
837 0, 0);
838 }
839 } else {
840 goto error;
841 }
842 }
843 break;
844 case UC32_EXCP_TRAP:
845 info.si_signo = SIGSEGV;
846 info.si_errno = 0;
847 /* XXX: check env->error_code */
848 info.si_code = TARGET_SEGV_MAPERR;
849 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
850 queue_signal(env, info.si_signo, &info);
851 break;
852 case EXCP_INTERRUPT:
853 /* just indicate that signals should be handled asap */
854 break;
855 case EXCP_DEBUG:
856 {
857 int sig;
858
859 sig = gdb_handlesig(env, TARGET_SIGTRAP);
860 if (sig) {
861 info.si_signo = sig;
862 info.si_errno = 0;
863 info.si_code = TARGET_TRAP_BRKPT;
864 queue_signal(env, info.si_signo, &info);
865 }
866 }
867 break;
868 default:
869 goto error;
870 }
871 process_pending_signals(env);
872 }
873
874 error:
875 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
876 cpu_dump_state(env, stderr, fprintf, 0);
877 abort();
878 }
879 #endif
880
881 #ifdef TARGET_SPARC
882 #define SPARC64_STACK_BIAS 2047
883
884 //#define DEBUG_WIN
885
886 /* WARNING: dealing with register windows _is_ complicated. More info
887 can be found at http://www.sics.se/~psm/sparcstack.html */
888 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
889 {
890 index = (index + cwp * 16) % (16 * env->nwindows);
891 /* wrap handling : if cwp is on the last window, then we use the
892 registers 'after' the end */
893 if (index < 8 && env->cwp == env->nwindows - 1)
894 index += 16 * env->nwindows;
895 return index;
896 }
897
898 /* save the register window 'cwp1' */
899 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
900 {
901 unsigned int i;
902 abi_ulong sp_ptr;
903
904 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
905 #ifdef TARGET_SPARC64
906 if (sp_ptr & 3)
907 sp_ptr += SPARC64_STACK_BIAS;
908 #endif
909 #if defined(DEBUG_WIN)
910 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
911 sp_ptr, cwp1);
912 #endif
913 for(i = 0; i < 16; i++) {
914 /* FIXME - what to do if put_user() fails? */
915 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
916 sp_ptr += sizeof(abi_ulong);
917 }
918 }
919
920 static void save_window(CPUSPARCState *env)
921 {
922 #ifndef TARGET_SPARC64
923 unsigned int new_wim;
924 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
925 ((1LL << env->nwindows) - 1);
926 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
927 env->wim = new_wim;
928 #else
929 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
930 env->cansave++;
931 env->canrestore--;
932 #endif
933 }
934
935 static void restore_window(CPUSPARCState *env)
936 {
937 #ifndef TARGET_SPARC64
938 unsigned int new_wim;
939 #endif
940 unsigned int i, cwp1;
941 abi_ulong sp_ptr;
942
943 #ifndef TARGET_SPARC64
944 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
945 ((1LL << env->nwindows) - 1);
946 #endif
947
948 /* restore the invalid window */
949 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
950 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
951 #ifdef TARGET_SPARC64
952 if (sp_ptr & 3)
953 sp_ptr += SPARC64_STACK_BIAS;
954 #endif
955 #if defined(DEBUG_WIN)
956 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
957 sp_ptr, cwp1);
958 #endif
959 for(i = 0; i < 16; i++) {
960 /* FIXME - what to do if get_user() fails? */
961 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
962 sp_ptr += sizeof(abi_ulong);
963 }
964 #ifdef TARGET_SPARC64
965 env->canrestore++;
966 if (env->cleanwin < env->nwindows - 1)
967 env->cleanwin++;
968 env->cansave--;
969 #else
970 env->wim = new_wim;
971 #endif
972 }
973
974 static void flush_windows(CPUSPARCState *env)
975 {
976 int offset, cwp1;
977
978 offset = 1;
979 for(;;) {
980 /* if restore would invoke restore_window(), then we can stop */
981 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
982 #ifndef TARGET_SPARC64
983 if (env->wim & (1 << cwp1))
984 break;
985 #else
986 if (env->canrestore == 0)
987 break;
988 env->cansave++;
989 env->canrestore--;
990 #endif
991 save_window_offset(env, cwp1);
992 offset++;
993 }
994 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
995 #ifndef TARGET_SPARC64
996 /* set wim so that restore will reload the registers */
997 env->wim = 1 << cwp1;
998 #endif
999 #if defined(DEBUG_WIN)
1000 printf("flush_windows: nb=%d\n", offset - 1);
1001 #endif
1002 }
1003
1004 void cpu_loop (CPUSPARCState *env)
1005 {
1006 int trapnr;
1007 abi_long ret;
1008 target_siginfo_t info;
1009
1010 while (1) {
1011 trapnr = cpu_sparc_exec (env);
1012
1013 switch (trapnr) {
1014 #ifndef TARGET_SPARC64
1015 case 0x88:
1016 case 0x90:
1017 #else
1018 case 0x110:
1019 case 0x16d:
1020 #endif
1021 ret = do_syscall (env, env->gregs[1],
1022 env->regwptr[0], env->regwptr[1],
1023 env->regwptr[2], env->regwptr[3],
1024 env->regwptr[4], env->regwptr[5],
1025 0, 0);
1026 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1027 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1028 env->xcc |= PSR_CARRY;
1029 #else
1030 env->psr |= PSR_CARRY;
1031 #endif
1032 ret = -ret;
1033 } else {
1034 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1035 env->xcc &= ~PSR_CARRY;
1036 #else
1037 env->psr &= ~PSR_CARRY;
1038 #endif
1039 }
1040 env->regwptr[0] = ret;
1041 /* next instruction */
1042 env->pc = env->npc;
1043 env->npc = env->npc + 4;
1044 break;
1045 case 0x83: /* flush windows */
1046 #ifdef TARGET_ABI32
1047 case 0x103:
1048 #endif
1049 flush_windows(env);
1050 /* next instruction */
1051 env->pc = env->npc;
1052 env->npc = env->npc + 4;
1053 break;
1054 #ifndef TARGET_SPARC64
1055 case TT_WIN_OVF: /* window overflow */
1056 save_window(env);
1057 break;
1058 case TT_WIN_UNF: /* window underflow */
1059 restore_window(env);
1060 break;
1061 case TT_TFAULT:
1062 case TT_DFAULT:
1063 {
1064 info.si_signo = SIGSEGV;
1065 info.si_errno = 0;
1066 /* XXX: check env->error_code */
1067 info.si_code = TARGET_SEGV_MAPERR;
1068 info._sifields._sigfault._addr = env->mmuregs[4];
1069 queue_signal(env, info.si_signo, &info);
1070 }
1071 break;
1072 #else
1073 case TT_SPILL: /* window overflow */
1074 save_window(env);
1075 break;
1076 case TT_FILL: /* window underflow */
1077 restore_window(env);
1078 break;
1079 case TT_TFAULT:
1080 case TT_DFAULT:
1081 {
1082 info.si_signo = SIGSEGV;
1083 info.si_errno = 0;
1084 /* XXX: check env->error_code */
1085 info.si_code = TARGET_SEGV_MAPERR;
1086 if (trapnr == TT_DFAULT)
1087 info._sifields._sigfault._addr = env->dmmuregs[4];
1088 else
1089 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1090 queue_signal(env, info.si_signo, &info);
1091 }
1092 break;
1093 #ifndef TARGET_ABI32
1094 case 0x16e:
1095 flush_windows(env);
1096 sparc64_get_context(env);
1097 break;
1098 case 0x16f:
1099 flush_windows(env);
1100 sparc64_set_context(env);
1101 break;
1102 #endif
1103 #endif
1104 case EXCP_INTERRUPT:
1105 /* just indicate that signals should be handled asap */
1106 break;
1107 case EXCP_DEBUG:
1108 {
1109 int sig;
1110
1111 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1112 if (sig)
1113 {
1114 info.si_signo = sig;
1115 info.si_errno = 0;
1116 info.si_code = TARGET_TRAP_BRKPT;
1117 queue_signal(env, info.si_signo, &info);
1118 }
1119 }
1120 break;
1121 default:
1122 printf ("Unhandled trap: 0x%x\n", trapnr);
1123 cpu_dump_state(env, stderr, fprintf, 0);
1124 exit (1);
1125 }
1126 process_pending_signals (env);
1127 }
1128 }
1129
1130 #endif
1131
1132 #ifdef TARGET_PPC
1133 static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1134 {
1135 /* TO FIX */
1136 return 0;
1137 }
1138
1139 uint64_t cpu_ppc_load_tbl (CPUState *env)
1140 {
1141 return cpu_ppc_get_tb(env);
1142 }
1143
1144 uint32_t cpu_ppc_load_tbu (CPUState *env)
1145 {
1146 return cpu_ppc_get_tb(env) >> 32;
1147 }
1148
1149 uint64_t cpu_ppc_load_atbl (CPUState *env)
1150 {
1151 return cpu_ppc_get_tb(env);
1152 }
1153
1154 uint32_t cpu_ppc_load_atbu (CPUState *env)
1155 {
1156 return cpu_ppc_get_tb(env) >> 32;
1157 }
1158
1159 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1160 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1161
1162 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
1163 {
1164 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1165 }
1166
1167 /* XXX: to be fixed */
1168 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1169 {
1170 return -1;
1171 }
1172
1173 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1174 {
1175 return -1;
1176 }
1177
1178 #define EXCP_DUMP(env, fmt, ...) \
1179 do { \
1180 fprintf(stderr, fmt , ## __VA_ARGS__); \
1181 cpu_dump_state(env, stderr, fprintf, 0); \
1182 qemu_log(fmt, ## __VA_ARGS__); \
1183 if (logfile) \
1184 log_cpu_state(env, 0); \
1185 } while (0)
1186
1187 static int do_store_exclusive(CPUPPCState *env)
1188 {
1189 target_ulong addr;
1190 target_ulong page_addr;
1191 target_ulong val;
1192 int flags;
1193 int segv = 0;
1194
1195 addr = env->reserve_ea;
1196 page_addr = addr & TARGET_PAGE_MASK;
1197 start_exclusive();
1198 mmap_lock();
1199 flags = page_get_flags(page_addr);
1200 if ((flags & PAGE_READ) == 0) {
1201 segv = 1;
1202 } else {
1203 int reg = env->reserve_info & 0x1f;
1204 int size = (env->reserve_info >> 5) & 0xf;
1205 int stored = 0;
1206
1207 if (addr == env->reserve_addr) {
1208 switch (size) {
1209 case 1: segv = get_user_u8(val, addr); break;
1210 case 2: segv = get_user_u16(val, addr); break;
1211 case 4: segv = get_user_u32(val, addr); break;
1212 #if defined(TARGET_PPC64)
1213 case 8: segv = get_user_u64(val, addr); break;
1214 #endif
1215 default: abort();
1216 }
1217 if (!segv && val == env->reserve_val) {
1218 val = env->gpr[reg];
1219 switch (size) {
1220 case 1: segv = put_user_u8(val, addr); break;
1221 case 2: segv = put_user_u16(val, addr); break;
1222 case 4: segv = put_user_u32(val, addr); break;
1223 #if defined(TARGET_PPC64)
1224 case 8: segv = put_user_u64(val, addr); break;
1225 #endif
1226 default: abort();
1227 }
1228 if (!segv) {
1229 stored = 1;
1230 }
1231 }
1232 }
1233 env->crf[0] = (stored << 1) | xer_so;
1234 env->reserve_addr = (target_ulong)-1;
1235 }
1236 if (!segv) {
1237 env->nip += 4;
1238 }
1239 mmap_unlock();
1240 end_exclusive();
1241 return segv;
1242 }
1243
1244 void cpu_loop(CPUPPCState *env)
1245 {
1246 target_siginfo_t info;
1247 int trapnr;
1248 uint32_t ret;
1249
1250 for(;;) {
1251 cpu_exec_start(env);
1252 trapnr = cpu_ppc_exec(env);
1253 cpu_exec_end(env);
1254 switch(trapnr) {
1255 case POWERPC_EXCP_NONE:
1256 /* Just go on */
1257 break;
1258 case POWERPC_EXCP_CRITICAL: /* Critical input */
1259 cpu_abort(env, "Critical interrupt while in user mode. "
1260 "Aborting\n");
1261 break;
1262 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1263 cpu_abort(env, "Machine check exception while in user mode. "
1264 "Aborting\n");
1265 break;
1266 case POWERPC_EXCP_DSI: /* Data storage exception */
1267 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1268 env->spr[SPR_DAR]);
1269 /* XXX: check this. Seems bugged */
1270 switch (env->error_code & 0xFF000000) {
1271 case 0x40000000:
1272 info.si_signo = TARGET_SIGSEGV;
1273 info.si_errno = 0;
1274 info.si_code = TARGET_SEGV_MAPERR;
1275 break;
1276 case 0x04000000:
1277 info.si_signo = TARGET_SIGILL;
1278 info.si_errno = 0;
1279 info.si_code = TARGET_ILL_ILLADR;
1280 break;
1281 case 0x08000000:
1282 info.si_signo = TARGET_SIGSEGV;
1283 info.si_errno = 0;
1284 info.si_code = TARGET_SEGV_ACCERR;
1285 break;
1286 default:
1287 /* Let's send a regular segfault... */
1288 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1289 env->error_code);
1290 info.si_signo = TARGET_SIGSEGV;
1291 info.si_errno = 0;
1292 info.si_code = TARGET_SEGV_MAPERR;
1293 break;
1294 }
1295 info._sifields._sigfault._addr = env->nip;
1296 queue_signal(env, info.si_signo, &info);
1297 break;
1298 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1299 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1300 "\n", env->spr[SPR_SRR0]);
1301 /* XXX: check this */
1302 switch (env->error_code & 0xFF000000) {
1303 case 0x40000000:
1304 info.si_signo = TARGET_SIGSEGV;
1305 info.si_errno = 0;
1306 info.si_code = TARGET_SEGV_MAPERR;
1307 break;
1308 case 0x10000000:
1309 case 0x08000000:
1310 info.si_signo = TARGET_SIGSEGV;
1311 info.si_errno = 0;
1312 info.si_code = TARGET_SEGV_ACCERR;
1313 break;
1314 default:
1315 /* Let's send a regular segfault... */
1316 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1317 env->error_code);
1318 info.si_signo = TARGET_SIGSEGV;
1319 info.si_errno = 0;
1320 info.si_code = TARGET_SEGV_MAPERR;
1321 break;
1322 }
1323 info._sifields._sigfault._addr = env->nip - 4;
1324 queue_signal(env, info.si_signo, &info);
1325 break;
1326 case POWERPC_EXCP_EXTERNAL: /* External input */
1327 cpu_abort(env, "External interrupt while in user mode. "
1328 "Aborting\n");
1329 break;
1330 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1331 EXCP_DUMP(env, "Unaligned memory access\n");
1332 /* XXX: check this */
1333 info.si_signo = TARGET_SIGBUS;
1334 info.si_errno = 0;
1335 info.si_code = TARGET_BUS_ADRALN;
1336 info._sifields._sigfault._addr = env->nip - 4;
1337 queue_signal(env, info.si_signo, &info);
1338 break;
1339 case POWERPC_EXCP_PROGRAM: /* Program exception */
1340 /* XXX: check this */
1341 switch (env->error_code & ~0xF) {
1342 case POWERPC_EXCP_FP:
1343 EXCP_DUMP(env, "Floating point program exception\n");
1344 info.si_signo = TARGET_SIGFPE;
1345 info.si_errno = 0;
1346 switch (env->error_code & 0xF) {
1347 case POWERPC_EXCP_FP_OX:
1348 info.si_code = TARGET_FPE_FLTOVF;
1349 break;
1350 case POWERPC_EXCP_FP_UX:
1351 info.si_code = TARGET_FPE_FLTUND;
1352 break;
1353 case POWERPC_EXCP_FP_ZX:
1354 case POWERPC_EXCP_FP_VXZDZ:
1355 info.si_code = TARGET_FPE_FLTDIV;
1356 break;
1357 case POWERPC_EXCP_FP_XX:
1358 info.si_code = TARGET_FPE_FLTRES;
1359 break;
1360 case POWERPC_EXCP_FP_VXSOFT:
1361 info.si_code = TARGET_FPE_FLTINV;
1362 break;
1363 case POWERPC_EXCP_FP_VXSNAN:
1364 case POWERPC_EXCP_FP_VXISI:
1365 case POWERPC_EXCP_FP_VXIDI:
1366 case POWERPC_EXCP_FP_VXIMZ:
1367 case POWERPC_EXCP_FP_VXVC:
1368 case POWERPC_EXCP_FP_VXSQRT:
1369 case POWERPC_EXCP_FP_VXCVI:
1370 info.si_code = TARGET_FPE_FLTSUB;
1371 break;
1372 default:
1373 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1374 env->error_code);
1375 break;
1376 }
1377 break;
1378 case POWERPC_EXCP_INVAL:
1379 EXCP_DUMP(env, "Invalid instruction\n");
1380 info.si_signo = TARGET_SIGILL;
1381 info.si_errno = 0;
1382 switch (env->error_code & 0xF) {
1383 case POWERPC_EXCP_INVAL_INVAL:
1384 info.si_code = TARGET_ILL_ILLOPC;
1385 break;
1386 case POWERPC_EXCP_INVAL_LSWX:
1387 info.si_code = TARGET_ILL_ILLOPN;
1388 break;
1389 case POWERPC_EXCP_INVAL_SPR:
1390 info.si_code = TARGET_ILL_PRVREG;
1391 break;
1392 case POWERPC_EXCP_INVAL_FP:
1393 info.si_code = TARGET_ILL_COPROC;
1394 break;
1395 default:
1396 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1397 env->error_code & 0xF);
1398 info.si_code = TARGET_ILL_ILLADR;
1399 break;
1400 }
1401 break;
1402 case POWERPC_EXCP_PRIV:
1403 EXCP_DUMP(env, "Privilege violation\n");
1404 info.si_signo = TARGET_SIGILL;
1405 info.si_errno = 0;
1406 switch (env->error_code & 0xF) {
1407 case POWERPC_EXCP_PRIV_OPC:
1408 info.si_code = TARGET_ILL_PRVOPC;
1409 break;
1410 case POWERPC_EXCP_PRIV_REG:
1411 info.si_code = TARGET_ILL_PRVREG;
1412 break;
1413 default:
1414 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1415 env->error_code & 0xF);
1416 info.si_code = TARGET_ILL_PRVOPC;
1417 break;
1418 }
1419 break;
1420 case POWERPC_EXCP_TRAP:
1421 cpu_abort(env, "Tried to call a TRAP\n");
1422 break;
1423 default:
1424 /* Should not happen ! */
1425 cpu_abort(env, "Unknown program exception (%02x)\n",
1426 env->error_code);
1427 break;
1428 }
1429 info._sifields._sigfault._addr = env->nip - 4;
1430 queue_signal(env, info.si_signo, &info);
1431 break;
1432 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1433 EXCP_DUMP(env, "No floating point allowed\n");
1434 info.si_signo = TARGET_SIGILL;
1435 info.si_errno = 0;
1436 info.si_code = TARGET_ILL_COPROC;
1437 info._sifields._sigfault._addr = env->nip - 4;
1438 queue_signal(env, info.si_signo, &info);
1439 break;
1440 case POWERPC_EXCP_SYSCALL: /* System call exception */
1441 cpu_abort(env, "Syscall exception while in user mode. "
1442 "Aborting\n");
1443 break;
1444 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1445 EXCP_DUMP(env, "No APU instruction allowed\n");
1446 info.si_signo = TARGET_SIGILL;
1447 info.si_errno = 0;
1448 info.si_code = TARGET_ILL_COPROC;
1449 info._sifields._sigfault._addr = env->nip - 4;
1450 queue_signal(env, info.si_signo, &info);
1451 break;
1452 case POWERPC_EXCP_DECR: /* Decrementer exception */
1453 cpu_abort(env, "Decrementer interrupt while in user mode. "
1454 "Aborting\n");
1455 break;
1456 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1457 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1458 "Aborting\n");
1459 break;
1460 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1461 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1462 "Aborting\n");
1463 break;
1464 case POWERPC_EXCP_DTLB: /* Data TLB error */
1465 cpu_abort(env, "Data TLB exception while in user mode. "
1466 "Aborting\n");
1467 break;
1468 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1469 cpu_abort(env, "Instruction TLB exception while in user mode. "
1470 "Aborting\n");
1471 break;
1472 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1473 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1474 info.si_signo = TARGET_SIGILL;
1475 info.si_errno = 0;
1476 info.si_code = TARGET_ILL_COPROC;
1477 info._sifields._sigfault._addr = env->nip - 4;
1478 queue_signal(env, info.si_signo, &info);
1479 break;
1480 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1481 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1482 break;
1483 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1484 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1485 break;
1486 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1487 cpu_abort(env, "Performance monitor exception not handled\n");
1488 break;
1489 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1490 cpu_abort(env, "Doorbell interrupt while in user mode. "
1491 "Aborting\n");
1492 break;
1493 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1494 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1495 "Aborting\n");
1496 break;
1497 case POWERPC_EXCP_RESET: /* System reset exception */
1498 cpu_abort(env, "Reset interrupt while in user mode. "
1499 "Aborting\n");
1500 break;
1501 case POWERPC_EXCP_DSEG: /* Data segment exception */
1502 cpu_abort(env, "Data segment exception while in user mode. "
1503 "Aborting\n");
1504 break;
1505 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1506 cpu_abort(env, "Instruction segment exception "
1507 "while in user mode. Aborting\n");
1508 break;
1509 /* PowerPC 64 with hypervisor mode support */
1510 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1511 cpu_abort(env, "Hypervisor decrementer interrupt "
1512 "while in user mode. Aborting\n");
1513 break;
1514 case POWERPC_EXCP_TRACE: /* Trace exception */
1515 /* Nothing to do:
1516 * we use this exception to emulate step-by-step execution mode.
1517 */
1518 break;
1519 /* PowerPC 64 with hypervisor mode support */
1520 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1521 cpu_abort(env, "Hypervisor data storage exception "
1522 "while in user mode. Aborting\n");
1523 break;
1524 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1525 cpu_abort(env, "Hypervisor instruction storage exception "
1526 "while in user mode. Aborting\n");
1527 break;
1528 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1529 cpu_abort(env, "Hypervisor data segment exception "
1530 "while in user mode. Aborting\n");
1531 break;
1532 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1533 cpu_abort(env, "Hypervisor instruction segment exception "
1534 "while in user mode. Aborting\n");
1535 break;
1536 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1537 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1538 info.si_signo = TARGET_SIGILL;
1539 info.si_errno = 0;
1540 info.si_code = TARGET_ILL_COPROC;
1541 info._sifields._sigfault._addr = env->nip - 4;
1542 queue_signal(env, info.si_signo, &info);
1543 break;
1544 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1545 cpu_abort(env, "Programable interval timer interrupt "
1546 "while in user mode. Aborting\n");
1547 break;
1548 case POWERPC_EXCP_IO: /* IO error exception */
1549 cpu_abort(env, "IO error exception while in user mode. "
1550 "Aborting\n");
1551 break;
1552 case POWERPC_EXCP_RUNM: /* Run mode exception */
1553 cpu_abort(env, "Run mode exception while in user mode. "
1554 "Aborting\n");
1555 break;
1556 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1557 cpu_abort(env, "Emulation trap exception not handled\n");
1558 break;
1559 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1560 cpu_abort(env, "Instruction fetch TLB exception "
1561 "while in user-mode. Aborting");
1562 break;
1563 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1564 cpu_abort(env, "Data load TLB exception while in user-mode. "
1565 "Aborting");
1566 break;
1567 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1568 cpu_abort(env, "Data store TLB exception while in user-mode. "
1569 "Aborting");
1570 break;
1571 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1572 cpu_abort(env, "Floating-point assist exception not handled\n");
1573 break;
1574 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1575 cpu_abort(env, "Instruction address breakpoint exception "
1576 "not handled\n");
1577 break;
1578 case POWERPC_EXCP_SMI: /* System management interrupt */
1579 cpu_abort(env, "System management interrupt while in user mode. "
1580 "Aborting\n");
1581 break;
1582 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1583 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1584 "Aborting\n");
1585 break;
1586 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1587 cpu_abort(env, "Performance monitor exception not handled\n");
1588 break;
1589 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1590 cpu_abort(env, "Vector assist exception not handled\n");
1591 break;
1592 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1593 cpu_abort(env, "Soft patch exception not handled\n");
1594 break;
1595 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1596 cpu_abort(env, "Maintenance exception while in user mode. "
1597 "Aborting\n");
1598 break;
1599 case POWERPC_EXCP_STOP: /* stop translation */
1600 /* We did invalidate the instruction cache. Go on */
1601 break;
1602 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1603 /* We just stopped because of a branch. Go on */
1604 break;
1605 case POWERPC_EXCP_SYSCALL_USER:
1606 /* system call in user-mode emulation */
1607 /* WARNING:
1608 * PPC ABI uses overflow flag in cr0 to signal an error
1609 * in syscalls.
1610 */
1611 #if 0
1612 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1613 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1614 #endif
1615 env->crf[0] &= ~0x1;
1616 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1617 env->gpr[5], env->gpr[6], env->gpr[7],
1618 env->gpr[8], 0, 0);
1619 if (ret == (uint32_t)(-TARGET_QEMU_ESIGRETURN)) {
1620 /* Returning from a successful sigreturn syscall.
1621 Avoid corrupting register state. */
1622 break;
1623 }
1624 if (ret > (uint32_t)(-515)) {
1625 env->crf[0] |= 0x1;
1626 ret = -ret;
1627 }
1628 env->gpr[3] = ret;
1629 #if 0
1630 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1631 #endif
1632 break;
1633 case POWERPC_EXCP_STCX:
1634 if (do_store_exclusive(env)) {
1635 info.si_signo = TARGET_SIGSEGV;
1636 info.si_errno = 0;
1637 info.si_code = TARGET_SEGV_MAPERR;
1638 info._sifields._sigfault._addr = env->nip;
1639 queue_signal(env, info.si_signo, &info);
1640 }
1641 break;
1642 case EXCP_DEBUG:
1643 {
1644 int sig;
1645
1646 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1647 if (sig) {
1648 info.si_signo = sig;
1649 info.si_errno = 0;
1650 info.si_code = TARGET_TRAP_BRKPT;
1651 queue_signal(env, info.si_signo, &info);
1652 }
1653 }
1654 break;
1655 case EXCP_INTERRUPT:
1656 /* just indicate that signals should be handled asap */
1657 break;
1658 default:
1659 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1660 break;
1661 }
1662 process_pending_signals(env);
1663 }
1664 }
1665 #endif
1666
1667 #ifdef TARGET_MIPS
1668
1669 #define MIPS_SYS(name, args) args,
1670
1671 static const uint8_t mips_syscall_args[] = {
1672 MIPS_SYS(sys_syscall , 0) /* 4000 */
1673 MIPS_SYS(sys_exit , 1)
1674 MIPS_SYS(sys_fork , 0)
1675 MIPS_SYS(sys_read , 3)
1676 MIPS_SYS(sys_write , 3)
1677 MIPS_SYS(sys_open , 3) /* 4005 */
1678 MIPS_SYS(sys_close , 1)
1679 MIPS_SYS(sys_waitpid , 3)
1680 MIPS_SYS(sys_creat , 2)
1681 MIPS_SYS(sys_link , 2)
1682 MIPS_SYS(sys_unlink , 1) /* 4010 */
1683 MIPS_SYS(sys_execve , 0)
1684 MIPS_SYS(sys_chdir , 1)
1685 MIPS_SYS(sys_time , 1)
1686 MIPS_SYS(sys_mknod , 3)
1687 MIPS_SYS(sys_chmod , 2) /* 4015 */
1688 MIPS_SYS(sys_lchown , 3)
1689 MIPS_SYS(sys_ni_syscall , 0)
1690 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1691 MIPS_SYS(sys_lseek , 3)
1692 MIPS_SYS(sys_getpid , 0) /* 4020 */
1693 MIPS_SYS(sys_mount , 5)
1694 MIPS_SYS(sys_oldumount , 1)
1695 MIPS_SYS(sys_setuid , 1)
1696 MIPS_SYS(sys_getuid , 0)
1697 MIPS_SYS(sys_stime , 1) /* 4025 */
1698 MIPS_SYS(sys_ptrace , 4)
1699 MIPS_SYS(sys_alarm , 1)
1700 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1701 MIPS_SYS(sys_pause , 0)
1702 MIPS_SYS(sys_utime , 2) /* 4030 */
1703 MIPS_SYS(sys_ni_syscall , 0)
1704 MIPS_SYS(sys_ni_syscall , 0)
1705 MIPS_SYS(sys_access , 2)
1706 MIPS_SYS(sys_nice , 1)
1707 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1708 MIPS_SYS(sys_sync , 0)
1709 MIPS_SYS(sys_kill , 2)
1710 MIPS_SYS(sys_rename , 2)
1711 MIPS_SYS(sys_mkdir , 2)
1712 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1713 MIPS_SYS(sys_dup , 1)
1714 MIPS_SYS(sys_pipe , 0)
1715 MIPS_SYS(sys_times , 1)
1716 MIPS_SYS(sys_ni_syscall , 0)
1717 MIPS_SYS(sys_brk , 1) /* 4045 */
1718 MIPS_SYS(sys_setgid , 1)
1719 MIPS_SYS(sys_getgid , 0)
1720 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1721 MIPS_SYS(sys_geteuid , 0)
1722 MIPS_SYS(sys_getegid , 0) /* 4050 */
1723 MIPS_SYS(sys_acct , 0)
1724 MIPS_SYS(sys_umount , 2)
1725 MIPS_SYS(sys_ni_syscall , 0)
1726 MIPS_SYS(sys_ioctl , 3)
1727 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1728 MIPS_SYS(sys_ni_syscall , 2)
1729 MIPS_SYS(sys_setpgid , 2)
1730 MIPS_SYS(sys_ni_syscall , 0)
1731 MIPS_SYS(sys_olduname , 1)
1732 MIPS_SYS(sys_umask , 1) /* 4060 */
1733 MIPS_SYS(sys_chroot , 1)
1734 MIPS_SYS(sys_ustat , 2)
1735 MIPS_SYS(sys_dup2 , 2)
1736 MIPS_SYS(sys_getppid , 0)
1737 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1738 MIPS_SYS(sys_setsid , 0)
1739 MIPS_SYS(sys_sigaction , 3)
1740 MIPS_SYS(sys_sgetmask , 0)
1741 MIPS_SYS(sys_ssetmask , 1)
1742 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1743 MIPS_SYS(sys_setregid , 2)
1744 MIPS_SYS(sys_sigsuspend , 0)
1745 MIPS_SYS(sys_sigpending , 1)
1746 MIPS_SYS(sys_sethostname , 2)
1747 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1748 MIPS_SYS(sys_getrlimit , 2)
1749 MIPS_SYS(sys_getrusage , 2)
1750 MIPS_SYS(sys_gettimeofday, 2)
1751 MIPS_SYS(sys_settimeofday, 2)
1752 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1753 MIPS_SYS(sys_setgroups , 2)
1754 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1755 MIPS_SYS(sys_symlink , 2)
1756 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1757 MIPS_SYS(sys_readlink , 3) /* 4085 */
1758 MIPS_SYS(sys_uselib , 1)
1759 MIPS_SYS(sys_swapon , 2)
1760 MIPS_SYS(sys_reboot , 3)
1761 MIPS_SYS(old_readdir , 3)
1762 MIPS_SYS(old_mmap , 6) /* 4090 */
1763 MIPS_SYS(sys_munmap , 2)
1764 MIPS_SYS(sys_truncate , 2)
1765 MIPS_SYS(sys_ftruncate , 2)
1766 MIPS_SYS(sys_fchmod , 2)
1767 MIPS_SYS(sys_fchown , 3) /* 4095 */
1768 MIPS_SYS(sys_getpriority , 2)
1769 MIPS_SYS(sys_setpriority , 3)
1770 MIPS_SYS(sys_ni_syscall , 0)
1771 MIPS_SYS(sys_statfs , 2)
1772 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1773 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1774 MIPS_SYS(sys_socketcall , 2)
1775 MIPS_SYS(sys_syslog , 3)
1776 MIPS_SYS(sys_setitimer , 3)
1777 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1778 MIPS_SYS(sys_newstat , 2)
1779 MIPS_SYS(sys_newlstat , 2)
1780 MIPS_SYS(sys_newfstat , 2)
1781 MIPS_SYS(sys_uname , 1)
1782 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1783 MIPS_SYS(sys_vhangup , 0)
1784 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1785 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1786 MIPS_SYS(sys_wait4 , 4)
1787 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1788 MIPS_SYS(sys_sysinfo , 1)
1789 MIPS_SYS(sys_ipc , 6)
1790 MIPS_SYS(sys_fsync , 1)
1791 MIPS_SYS(sys_sigreturn , 0)
1792 MIPS_SYS(sys_clone , 6) /* 4120 */
1793 MIPS_SYS(sys_setdomainname, 2)
1794 MIPS_SYS(sys_newuname , 1)
1795 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1796 MIPS_SYS(sys_adjtimex , 1)
1797 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1798 MIPS_SYS(sys_sigprocmask , 3)
1799 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1800 MIPS_SYS(sys_init_module , 5)
1801 MIPS_SYS(sys_delete_module, 1)
1802 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1803 MIPS_SYS(sys_quotactl , 0)
1804 MIPS_SYS(sys_getpgid , 1)
1805 MIPS_SYS(sys_fchdir , 1)
1806 MIPS_SYS(sys_bdflush , 2)
1807 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1808 MIPS_SYS(sys_personality , 1)
1809 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1810 MIPS_SYS(sys_setfsuid , 1)
1811 MIPS_SYS(sys_setfsgid , 1)
1812 MIPS_SYS(sys_llseek , 5) /* 4140 */
1813 MIPS_SYS(sys_getdents , 3)
1814 MIPS_SYS(sys_select , 5)
1815 MIPS_SYS(sys_flock , 2)
1816 MIPS_SYS(sys_msync , 3)
1817 MIPS_SYS(sys_readv , 3) /* 4145 */
1818 MIPS_SYS(sys_writev , 3)
1819 MIPS_SYS(sys_cacheflush , 3)
1820 MIPS_SYS(sys_cachectl , 3)
1821 MIPS_SYS(sys_sysmips , 4)
1822 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1823 MIPS_SYS(sys_getsid , 1)
1824 MIPS_SYS(sys_fdatasync , 0)
1825 MIPS_SYS(sys_sysctl , 1)
1826 MIPS_SYS(sys_mlock , 2)
1827 MIPS_SYS(sys_munlock , 2) /* 4155 */
1828 MIPS_SYS(sys_mlockall , 1)
1829 MIPS_SYS(sys_munlockall , 0)
1830 MIPS_SYS(sys_sched_setparam, 2)
1831 MIPS_SYS(sys_sched_getparam, 2)
1832 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1833 MIPS_SYS(sys_sched_getscheduler, 1)
1834 MIPS_SYS(sys_sched_yield , 0)
1835 MIPS_SYS(sys_sched_get_priority_max, 1)
1836 MIPS_SYS(sys_sched_get_priority_min, 1)
1837 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1838 MIPS_SYS(sys_nanosleep, 2)
1839 MIPS_SYS(sys_mremap , 4)
1840 MIPS_SYS(sys_accept , 3)
1841 MIPS_SYS(sys_bind , 3)
1842 MIPS_SYS(sys_connect , 3) /* 4170 */
1843 MIPS_SYS(sys_getpeername , 3)
1844 MIPS_SYS(sys_getsockname , 3)
1845 MIPS_SYS(sys_getsockopt , 5)
1846 MIPS_SYS(sys_listen , 2)
1847 MIPS_SYS(sys_recv , 4) /* 4175 */
1848 MIPS_SYS(sys_recvfrom , 6)
1849 MIPS_SYS(sys_recvmsg , 3)
1850 MIPS_SYS(sys_send , 4)
1851 MIPS_SYS(sys_sendmsg , 3)
1852 MIPS_SYS(sys_sendto , 6) /* 4180 */
1853 MIPS_SYS(sys_setsockopt , 5)
1854 MIPS_SYS(sys_shutdown , 2)
1855 MIPS_SYS(sys_socket , 3)
1856 MIPS_SYS(sys_socketpair , 4)
1857 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1858 MIPS_SYS(sys_getresuid , 3)
1859 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1860 MIPS_SYS(sys_poll , 3)
1861 MIPS_SYS(sys_nfsservctl , 3)
1862 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1863 MIPS_SYS(sys_getresgid , 3)
1864 MIPS_SYS(sys_prctl , 5)
1865 MIPS_SYS(sys_rt_sigreturn, 0)
1866 MIPS_SYS(sys_rt_sigaction, 4)
1867 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1868 MIPS_SYS(sys_rt_sigpending, 2)
1869 MIPS_SYS(sys_rt_sigtimedwait, 4)
1870 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1871 MIPS_SYS(sys_rt_sigsuspend, 0)
1872 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1873 MIPS_SYS(sys_pwrite64 , 6)
1874 MIPS_SYS(sys_chown , 3)
1875 MIPS_SYS(sys_getcwd , 2)
1876 MIPS_SYS(sys_capget , 2)
1877 MIPS_SYS(sys_capset , 2) /* 4205 */
1878 MIPS_SYS(sys_sigaltstack , 2)
1879 MIPS_SYS(sys_sendfile , 4)
1880 MIPS_SYS(sys_ni_syscall , 0)
1881 MIPS_SYS(sys_ni_syscall , 0)
1882 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1883 MIPS_SYS(sys_truncate64 , 4)
1884 MIPS_SYS(sys_ftruncate64 , 4)
1885 MIPS_SYS(sys_stat64 , 2)
1886 MIPS_SYS(sys_lstat64 , 2)
1887 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1888 MIPS_SYS(sys_pivot_root , 2)
1889 MIPS_SYS(sys_mincore , 3)
1890 MIPS_SYS(sys_madvise , 3)
1891 MIPS_SYS(sys_getdents64 , 3)
1892 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1893 MIPS_SYS(sys_ni_syscall , 0)
1894 MIPS_SYS(sys_gettid , 0)
1895 MIPS_SYS(sys_readahead , 5)
1896 MIPS_SYS(sys_setxattr , 5)
1897 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1898 MIPS_SYS(sys_fsetxattr , 5)
1899 MIPS_SYS(sys_getxattr , 4)
1900 MIPS_SYS(sys_lgetxattr , 4)
1901 MIPS_SYS(sys_fgetxattr , 4)
1902 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1903 MIPS_SYS(sys_llistxattr , 3)
1904 MIPS_SYS(sys_flistxattr , 3)
1905 MIPS_SYS(sys_removexattr , 2)
1906 MIPS_SYS(sys_lremovexattr, 2)
1907 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1908 MIPS_SYS(sys_tkill , 2)
1909 MIPS_SYS(sys_sendfile64 , 5)
1910 MIPS_SYS(sys_futex , 2)
1911 MIPS_SYS(sys_sched_setaffinity, 3)
1912 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1913 MIPS_SYS(sys_io_setup , 2)
1914 MIPS_SYS(sys_io_destroy , 1)
1915 MIPS_SYS(sys_io_getevents, 5)
1916 MIPS_SYS(sys_io_submit , 3)
1917 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1918 MIPS_SYS(sys_exit_group , 1)
1919 MIPS_SYS(sys_lookup_dcookie, 3)
1920 MIPS_SYS(sys_epoll_create, 1)
1921 MIPS_SYS(sys_epoll_ctl , 4)
1922 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1923 MIPS_SYS(sys_remap_file_pages, 5)
1924 MIPS_SYS(sys_set_tid_address, 1)
1925 MIPS_SYS(sys_restart_syscall, 0)
1926 MIPS_SYS(sys_fadvise64_64, 7)
1927 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1928 MIPS_SYS(sys_fstatfs64 , 2)
1929 MIPS_SYS(sys_timer_create, 3)
1930 MIPS_SYS(sys_timer_settime, 4)
1931 MIPS_SYS(sys_timer_gettime, 2)
1932 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1933 MIPS_SYS(sys_timer_delete, 1)
1934 MIPS_SYS(sys_clock_settime, 2)
1935 MIPS_SYS(sys_clock_gettime, 2)
1936 MIPS_SYS(sys_clock_getres, 2)
1937 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1938 MIPS_SYS(sys_tgkill , 3)
1939 MIPS_SYS(sys_utimes , 2)
1940 MIPS_SYS(sys_mbind , 4)
1941 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1942 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1943 MIPS_SYS(sys_mq_open , 4)
1944 MIPS_SYS(sys_mq_unlink , 1)
1945 MIPS_SYS(sys_mq_timedsend, 5)
1946 MIPS_SYS(sys_mq_timedreceive, 5)
1947 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1948 MIPS_SYS(sys_mq_getsetattr, 3)
1949 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1950 MIPS_SYS(sys_waitid , 4)
1951 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1952 MIPS_SYS(sys_add_key , 5)
1953 MIPS_SYS(sys_request_key, 4)
1954 MIPS_SYS(sys_keyctl , 5)
1955 MIPS_SYS(sys_set_thread_area, 1)
1956 MIPS_SYS(sys_inotify_init, 0)
1957 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1958 MIPS_SYS(sys_inotify_rm_watch, 2)
1959 MIPS_SYS(sys_migrate_pages, 4)
1960 MIPS_SYS(sys_openat, 4)
1961 MIPS_SYS(sys_mkdirat, 3)
1962 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1963 MIPS_SYS(sys_fchownat, 5)
1964 MIPS_SYS(sys_futimesat, 3)
1965 MIPS_SYS(sys_fstatat64, 4)
1966 MIPS_SYS(sys_unlinkat, 3)
1967 MIPS_SYS(sys_renameat, 4) /* 4295 */
1968 MIPS_SYS(sys_linkat, 5)
1969 MIPS_SYS(sys_symlinkat, 3)
1970 MIPS_SYS(sys_readlinkat, 4)
1971 MIPS_SYS(sys_fchmodat, 3)
1972 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1973 MIPS_SYS(sys_pselect6, 6)
1974 MIPS_SYS(sys_ppoll, 5)
1975 MIPS_SYS(sys_unshare, 1)
1976 MIPS_SYS(sys_splice, 4)
1977 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1978 MIPS_SYS(sys_tee, 4)
1979 MIPS_SYS(sys_vmsplice, 4)
1980 MIPS_SYS(sys_move_pages, 6)
1981 MIPS_SYS(sys_set_robust_list, 2)
1982 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1983 MIPS_SYS(sys_kexec_load, 4)
1984 MIPS_SYS(sys_getcpu, 3)
1985 MIPS_SYS(sys_epoll_pwait, 6)
1986 MIPS_SYS(sys_ioprio_set, 3)
1987 MIPS_SYS(sys_ioprio_get, 2)
1988 MIPS_SYS(sys_utimensat, 4)
1989 MIPS_SYS(sys_signalfd, 3)
1990 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
1991 MIPS_SYS(sys_eventfd, 1)
1992 MIPS_SYS(sys_fallocate, 6) /* 4320 */
1993 MIPS_SYS(sys_timerfd_create, 2)
1994 MIPS_SYS(sys_timerfd_gettime, 2)
1995 MIPS_SYS(sys_timerfd_settime, 4)
1996 MIPS_SYS(sys_signalfd4, 4)
1997 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
1998 MIPS_SYS(sys_epoll_create1, 1)
1999 MIPS_SYS(sys_dup3, 3)
2000 MIPS_SYS(sys_pipe2, 2)
2001 MIPS_SYS(sys_inotify_init1, 1)
2002 MIPS_SYS(sys_preadv, 6) /* 4330 */
2003 MIPS_SYS(sys_pwritev, 6)
2004 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2005 MIPS_SYS(sys_perf_event_open, 5)
2006 MIPS_SYS(sys_accept4, 4)
2007 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2008 MIPS_SYS(sys_fanotify_init, 2)
2009 MIPS_SYS(sys_fanotify_mark, 6)
2010 MIPS_SYS(sys_prlimit64, 4)
2011 MIPS_SYS(sys_name_to_handle_at, 5)
2012 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2013 MIPS_SYS(sys_clock_adjtime, 2)
2014 MIPS_SYS(sys_syncfs, 1)
2015 };
2016
2017 #undef MIPS_SYS
2018
2019 static int do_store_exclusive(CPUMIPSState *env)
2020 {
2021 target_ulong addr;
2022 target_ulong page_addr;
2023 target_ulong val;
2024 int flags;
2025 int segv = 0;
2026 int reg;
2027 int d;
2028
2029 addr = env->lladdr;
2030 page_addr = addr & TARGET_PAGE_MASK;
2031 start_exclusive();
2032 mmap_lock();
2033 flags = page_get_flags(page_addr);
2034 if ((flags & PAGE_READ) == 0) {
2035 segv = 1;
2036 } else {
2037 reg = env->llreg & 0x1f;
2038 d = (env->llreg & 0x20) != 0;
2039 if (d) {
2040 segv = get_user_s64(val, addr);
2041 } else {
2042 segv = get_user_s32(val, addr);
2043 }
2044 if (!segv) {
2045 if (val != env->llval) {
2046 env->active_tc.gpr[reg] = 0;
2047 } else {
2048 if (d) {
2049 segv = put_user_u64(env->llnewval, addr);
2050 } else {
2051 segv = put_user_u32(env->llnewval, addr);
2052 }
2053 if (!segv) {
2054 env->active_tc.gpr[reg] = 1;
2055 }
2056 }
2057 }
2058 }
2059 env->lladdr = -1;
2060 if (!segv) {
2061 env->active_tc.PC += 4;
2062 }
2063 mmap_unlock();
2064 end_exclusive();
2065 return segv;
2066 }
2067
2068 void cpu_loop(CPUMIPSState *env)
2069 {
2070 target_siginfo_t info;
2071 int trapnr, ret;
2072 unsigned int syscall_num;
2073
2074 for(;;) {
2075 cpu_exec_start(env);
2076 trapnr = cpu_mips_exec(env);
2077 cpu_exec_end(env);
2078 switch(trapnr) {
2079 case EXCP_SYSCALL:
2080 syscall_num = env->active_tc.gpr[2] - 4000;
2081 env->active_tc.PC += 4;
2082 if (syscall_num >= sizeof(mips_syscall_args)) {
2083 ret = -ENOSYS;
2084 } else {
2085 int nb_args;
2086 abi_ulong sp_reg;
2087 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2088
2089 nb_args = mips_syscall_args[syscall_num];
2090 sp_reg = env->active_tc.gpr[29];
2091 switch (nb_args) {
2092 /* these arguments are taken from the stack */
2093 /* FIXME - what to do if get_user() fails? */
2094 case 8: get_user_ual(arg8, sp_reg + 28);
2095 case 7: get_user_ual(arg7, sp_reg + 24);
2096 case 6: get_user_ual(arg6, sp_reg + 20);
2097 case 5: get_user_ual(arg5, sp_reg + 16);
2098 default:
2099 break;
2100 }
2101 ret = do_syscall(env, env->active_tc.gpr[2],
2102 env->active_tc.gpr[4],
2103 env->active_tc.gpr[5],
2104 env->active_tc.gpr[6],
2105 env->active_tc.gpr[7],
2106 arg5, arg6, arg7, arg8);
2107 }
2108 if (ret == -TARGET_QEMU_ESIGRETURN) {
2109 /* Returning from a successful sigreturn syscall.
2110 Avoid clobbering register state. */
2111 break;
2112 }
2113 if ((unsigned int)ret >= (unsigned int)(-1133)) {
2114 env->active_tc.gpr[7] = 1; /* error flag */
2115 ret = -ret;
2116 } else {
2117 env->active_tc.gpr[7] = 0; /* error flag */
2118 }
2119 env->active_tc.gpr[2] = ret;
2120 break;
2121 case EXCP_TLBL:
2122 case EXCP_TLBS:
2123 info.si_signo = TARGET_SIGSEGV;
2124 info.si_errno = 0;
2125 /* XXX: check env->error_code */
2126 info.si_code = TARGET_SEGV_MAPERR;
2127 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2128 queue_signal(env, info.si_signo, &info);
2129 break;
2130 case EXCP_CpU:
2131 case EXCP_RI:
2132 info.si_signo = TARGET_SIGILL;
2133 info.si_errno = 0;
2134 info.si_code = 0;
2135 queue_signal(env, info.si_signo, &info);
2136 break;
2137 case EXCP_INTERRUPT:
2138 /* just indicate that signals should be handled asap */
2139 break;
2140 case EXCP_DEBUG:
2141 {
2142 int sig;
2143
2144 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2145 if (sig)
2146 {
2147 info.si_signo = sig;
2148 info.si_errno = 0;
2149 info.si_code = TARGET_TRAP_BRKPT;
2150 queue_signal(env, info.si_signo, &info);
2151 }
2152 }
2153 break;
2154 case EXCP_SC:
2155 if (do_store_exclusive(env)) {
2156 info.si_signo = TARGET_SIGSEGV;
2157 info.si_errno = 0;
2158 info.si_code = TARGET_SEGV_MAPERR;
2159 info._sifields._sigfault._addr = env->active_tc.PC;
2160 queue_signal(env, info.si_signo, &info);
2161 }
2162 break;
2163 default:
2164 // error:
2165 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2166 trapnr);
2167 cpu_dump_state(env, stderr, fprintf, 0);
2168 abort();
2169 }
2170 process_pending_signals(env);
2171 }
2172 }
2173 #endif
2174
2175 #ifdef TARGET_SH4
2176 void cpu_loop (CPUState *env)
2177 {
2178 int trapnr, ret;
2179 target_siginfo_t info;
2180
2181 while (1) {
2182 trapnr = cpu_sh4_exec (env);
2183
2184 switch (trapnr) {
2185 case 0x160:
2186 env->pc += 2;
2187 ret = do_syscall(env,
2188 env->gregs[3],
2189 env->gregs[4],
2190 env->gregs[5],
2191 env->gregs[6],
2192 env->gregs[7],
2193 env->gregs[0],
2194 env->gregs[1],
2195 0, 0);
2196 env->gregs[0] = ret;
2197 break;
2198 case EXCP_INTERRUPT:
2199 /* just indicate that signals should be handled asap */
2200 break;
2201 case EXCP_DEBUG:
2202 {
2203 int sig;
2204
2205 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2206 if (sig)
2207 {
2208 info.si_signo = sig;
2209 info.si_errno = 0;
2210 info.si_code = TARGET_TRAP_BRKPT;
2211 queue_signal(env, info.si_signo, &info);
2212 }
2213 }
2214 break;
2215 case 0xa0:
2216 case 0xc0:
2217 info.si_signo = SIGSEGV;
2218 info.si_errno = 0;
2219 info.si_code = TARGET_SEGV_MAPERR;
2220 info._sifields._sigfault._addr = env->tea;
2221 queue_signal(env, info.si_signo, &info);
2222 break;
2223
2224 default:
2225 printf ("Unhandled trap: 0x%x\n", trapnr);
2226 cpu_dump_state(env, stderr, fprintf, 0);
2227 exit (1);
2228 }
2229 process_pending_signals (env);
2230 }
2231 }
2232 #endif
2233
2234 #ifdef TARGET_CRIS
2235 void cpu_loop (CPUState *env)
2236 {
2237 int trapnr, ret;
2238 target_siginfo_t info;
2239
2240 while (1) {
2241 trapnr = cpu_cris_exec (env);
2242 switch (trapnr) {
2243 case 0xaa:
2244 {
2245 info.si_signo = SIGSEGV;
2246 info.si_errno = 0;
2247 /* XXX: check env->error_code */
2248 info.si_code = TARGET_SEGV_MAPERR;
2249 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2250 queue_signal(env, info.si_signo, &info);
2251 }
2252 break;
2253 case EXCP_INTERRUPT:
2254 /* just indicate that signals should be handled asap */
2255 break;
2256 case EXCP_BREAK:
2257 ret = do_syscall(env,
2258 env->regs[9],
2259 env->regs[10],
2260 env->regs[11],
2261 env->regs[12],
2262 env->regs[13],
2263 env->pregs[7],
2264 env->pregs[11],
2265 0, 0);
2266 env->regs[10] = ret;
2267 break;
2268 case EXCP_DEBUG:
2269 {
2270 int sig;
2271
2272 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2273 if (sig)
2274 {
2275 info.si_signo = sig;
2276 info.si_errno = 0;
2277 info.si_code = TARGET_TRAP_BRKPT;
2278 queue_signal(env, info.si_signo, &info);
2279 }
2280 }
2281 break;
2282 default:
2283 printf ("Unhandled trap: 0x%x\n", trapnr);
2284 cpu_dump_state(env, stderr, fprintf, 0);
2285 exit (1);
2286 }
2287 process_pending_signals (env);
2288 }
2289 }
2290 #endif
2291
2292 #ifdef TARGET_MICROBLAZE
2293 void cpu_loop (CPUState *env)
2294 {
2295 int trapnr, ret;
2296 target_siginfo_t info;
2297
2298 while (1) {
2299 trapnr = cpu_mb_exec (env);
2300 switch (trapnr) {
2301 case 0xaa:
2302 {
2303 info.si_signo = SIGSEGV;
2304 info.si_errno = 0;
2305 /* XXX: check env->error_code */
2306 info.si_code = TARGET_SEGV_MAPERR;
2307 info._sifields._sigfault._addr = 0;
2308 queue_signal(env, info.si_signo, &info);
2309 }
2310 break;
2311 case EXCP_INTERRUPT:
2312 /* just indicate that signals should be handled asap */
2313 break;
2314 case EXCP_BREAK:
2315 /* Return address is 4 bytes after the call. */
2316 env->regs[14] += 4;
2317 ret = do_syscall(env,
2318 env->regs[12],
2319 env->regs[5],
2320 env->regs[6],
2321 env->regs[7],
2322 env->regs[8],
2323 env->regs[9],
2324 env->regs[10],
2325 0, 0);
2326 env->regs[3] = ret;
2327 env->sregs[SR_PC] = env->regs[14];
2328 break;
2329 case EXCP_HW_EXCP:
2330 env->regs[17] = env->sregs[SR_PC] + 4;
2331 if (env->iflags & D_FLAG) {
2332 env->sregs[SR_ESR] |= 1 << 12;
2333 env->sregs[SR_PC] -= 4;
2334 /* FIXME: if branch was immed, replay the imm aswell. */
2335 }
2336
2337 env->iflags &= ~(IMM_FLAG | D_FLAG);
2338
2339 switch (env->sregs[SR_ESR] & 31) {
2340 case ESR_EC_FPU:
2341 info.si_signo = SIGFPE;
2342 info.si_errno = 0;
2343 if (env->sregs[SR_FSR] & FSR_IO) {
2344 info.si_code = TARGET_FPE_FLTINV;
2345 }
2346 if (env->sregs[SR_FSR] & FSR_DZ) {
2347 info.si_code = TARGET_FPE_FLTDIV;
2348 }
2349 info._sifields._sigfault._addr = 0;
2350 queue_signal(env, info.si_signo, &info);
2351 break;
2352 default:
2353 printf ("Unhandled hw-exception: 0x%x\n",
2354 env->sregs[SR_ESR] & ESR_EC_MASK);
2355 cpu_dump_state(env, stderr, fprintf, 0);
2356 exit (1);
2357 break;
2358 }
2359 break;
2360 case EXCP_DEBUG:
2361 {
2362 int sig;
2363
2364 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2365 if (sig)
2366 {
2367 info.si_signo = sig;
2368 info.si_errno = 0;
2369 info.si_code = TARGET_TRAP_BRKPT;
2370 queue_signal(env, info.si_signo, &info);
2371 }
2372 }
2373 break;
2374 default:
2375 printf ("Unhandled trap: 0x%x\n", trapnr);
2376 cpu_dump_state(env, stderr, fprintf, 0);
2377 exit (1);
2378 }
2379 process_pending_signals (env);
2380 }
2381 }
2382 #endif
2383
2384 #ifdef TARGET_M68K
2385
2386 void cpu_loop(CPUM68KState *env)
2387 {
2388 int trapnr;
2389 unsigned int n;
2390 target_siginfo_t info;
2391 TaskState *ts = env->opaque;
2392
2393 for(;;) {
2394 trapnr = cpu_m68k_exec(env);
2395 switch(trapnr) {
2396 case EXCP_ILLEGAL:
2397 {
2398 if (ts->sim_syscalls) {
2399 uint16_t nr;
2400 nr = lduw(env->pc + 2);
2401 env->pc += 4;
2402 do_m68k_simcall(env, nr);
2403 } else {
2404 goto do_sigill;
2405 }
2406 }
2407 break;
2408 case EXCP_HALT_INSN:
2409 /* Semihosing syscall. */
2410 env->pc += 4;
2411 do_m68k_semihosting(env, env->dregs[0]);
2412 break;
2413 case EXCP_LINEA:
2414 case EXCP_LINEF:
2415 case EXCP_UNSUPPORTED:
2416 do_sigill:
2417 info.si_signo = SIGILL;
2418 info.si_errno = 0;
2419 info.si_code = TARGET_ILL_ILLOPN;
2420 info._sifields._sigfault._addr = env->pc;
2421 queue_signal(env, info.si_signo, &info);
2422 break;
2423 case EXCP_TRAP0:
2424 {
2425 ts->sim_syscalls = 0;
2426 n = env->dregs[0];
2427 env->pc += 2;
2428 env->dregs[0] = do_syscall(env,
2429 n,
2430 env->dregs[1],
2431 env->dregs[2],
2432 env->dregs[3],
2433 env->dregs[4],
2434 env->dregs[5],
2435 env->aregs[0],
2436 0, 0);
2437 }
2438 break;
2439 case EXCP_INTERRUPT:
2440 /* just indicate that signals should be handled asap */
2441 break;
2442 case EXCP_ACCESS:
2443 {
2444 info.si_signo = SIGSEGV;
2445 info.si_errno = 0;
2446 /* XXX: check env->error_code */
2447 info.si_code = TARGET_SEGV_MAPERR;
2448 info._sifields._sigfault._addr = env->mmu.ar;
2449 queue_signal(env, info.si_signo, &info);
2450 }
2451 break;
2452 case EXCP_DEBUG:
2453 {
2454 int sig;
2455
2456 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2457 if (sig)
2458 {
2459 info.si_signo = sig;
2460 info.si_errno = 0;
2461 info.si_code = TARGET_TRAP_BRKPT;
2462 queue_signal(env, info.si_signo, &info);
2463 }
2464 }
2465 break;
2466 default:
2467 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2468 trapnr);
2469 cpu_dump_state(env, stderr, fprintf, 0);
2470 abort();
2471 }
2472 process_pending_signals(env);
2473 }
2474 }
2475 #endif /* TARGET_M68K */
2476
2477 #ifdef TARGET_ALPHA
2478 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2479 {
2480 target_ulong addr, val, tmp;
2481 target_siginfo_t info;
2482 int ret = 0;
2483
2484 addr = env->lock_addr;
2485 tmp = env->lock_st_addr;
2486 env->lock_addr = -1;
2487 env->lock_st_addr = 0;
2488
2489 start_exclusive();
2490 mmap_lock();
2491
2492 if (addr == tmp) {
2493 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2494 goto do_sigsegv;
2495 }
2496
2497 if (val == env->lock_value) {
2498 tmp = env->ir[reg];
2499 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2500 goto do_sigsegv;
2501 }
2502 ret = 1;
2503 }
2504 }
2505 env->ir[reg] = ret;
2506 env->pc += 4;
2507
2508 mmap_unlock();
2509 end_exclusive();
2510 return;
2511
2512 do_sigsegv:
2513 mmap_unlock();
2514 end_exclusive();
2515
2516 info.si_signo = TARGET_SIGSEGV;
2517 info.si_errno = 0;
2518 info.si_code = TARGET_SEGV_MAPERR;
2519 info._sifields._sigfault._addr = addr;
2520 queue_signal(env, TARGET_SIGSEGV, &info);
2521 }
2522
2523 void cpu_loop (CPUState *env)
2524 {
2525 int trapnr;
2526 target_siginfo_t info;
2527 abi_long sysret;
2528
2529 while (1) {
2530 trapnr = cpu_alpha_exec (env);
2531
2532 /* All of the traps imply a transition through PALcode, which
2533 implies an REI instruction has been executed. Which means
2534 that the intr_flag should be cleared. */
2535 env->intr_flag = 0;
2536
2537 switch (trapnr) {
2538 case EXCP_RESET:
2539 fprintf(stderr, "Reset requested. Exit\n");
2540 exit(1);
2541 break;
2542 case EXCP_MCHK:
2543 fprintf(stderr, "Machine check exception. Exit\n");
2544 exit(1);
2545 break;
2546 case EXCP_SMP_INTERRUPT:
2547 case EXCP_CLK_INTERRUPT:
2548 case EXCP_DEV_INTERRUPT:
2549 fprintf(stderr, "External interrupt. Exit\n");
2550 exit(1);
2551 break;
2552 case EXCP_MMFAULT:
2553 env->lock_addr = -1;
2554 info.si_signo = TARGET_SIGSEGV;
2555 info.si_errno = 0;
2556 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
2557 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
2558 info._sifields._sigfault._addr = env->trap_arg0;
2559 queue_signal(env, info.si_signo, &info);
2560 break;
2561 case EXCP_UNALIGN:
2562 env->lock_addr = -1;
2563 info.si_signo = TARGET_SIGBUS;
2564 info.si_errno = 0;
2565 info.si_code = TARGET_BUS_ADRALN;
2566 info._sifields._sigfault._addr = env->trap_arg0;
2567 queue_signal(env, info.si_signo, &info);
2568 break;
2569 case EXCP_OPCDEC:
2570 do_sigill:
2571 env->lock_addr = -1;
2572 info.si_signo = TARGET_SIGILL;
2573 info.si_errno = 0;
2574 info.si_code = TARGET_ILL_ILLOPC;
2575 info._sifields._sigfault._addr = env->pc;
2576 queue_signal(env, info.si_signo, &info);
2577 break;
2578 case EXCP_ARITH:
2579 env->lock_addr = -1;
2580 info.si_signo = TARGET_SIGFPE;
2581 info.si_errno = 0;
2582 info.si_code = TARGET_FPE_FLTINV;
2583 info._sifields._sigfault._addr = env->pc;
2584 queue_signal(env, info.si_signo, &info);
2585 break;
2586 case EXCP_FEN:
2587 /* No-op. Linux simply re-enables the FPU. */
2588 break;
2589 case EXCP_CALL_PAL:
2590 env->lock_addr = -1;
2591 switch (env->error_code) {
2592 case 0x80:
2593 /* BPT */
2594 info.si_signo = TARGET_SIGTRAP;
2595 info.si_errno = 0;
2596 info.si_code = TARGET_TRAP_BRKPT;
2597 info._sifields._sigfault._addr = env->pc;
2598 queue_signal(env, info.si_signo, &info);
2599 break;
2600 case 0x81:
2601 /* BUGCHK */
2602 info.si_signo = TARGET_SIGTRAP;
2603 info.si_errno = 0;
2604 info.si_code = 0;
2605 info._sifields._sigfault._addr = env->pc;
2606 queue_signal(env, info.si_signo, &info);
2607 break;
2608 case 0x83:
2609 /* CALLSYS */
2610 trapnr = env->ir[IR_V0];
2611 sysret = do_syscall(env, trapnr,
2612 env->ir[IR_A0], env->ir[IR_A1],
2613 env->ir[IR_A2], env->ir[IR_A3],
2614 env->ir[IR_A4], env->ir[IR_A5],
2615 0, 0);
2616 if (trapnr == TARGET_NR_sigreturn
2617 || trapnr == TARGET_NR_rt_sigreturn) {
2618 break;
2619 }
2620 /* Syscall writes 0 to V0 to bypass error check, similar
2621 to how this is handled internal to Linux kernel. */
2622 if (env->ir[IR_V0] == 0) {
2623 env->ir[IR_V0] = sysret;
2624 } else {
2625 env->ir[IR_V0] = (sysret < 0 ? -sysret : sysret);
2626 env->ir[IR_A3] = (sysret < 0);
2627 }
2628 break;
2629 case 0x86:
2630 /* IMB */
2631 /* ??? We can probably elide the code using page_unprotect
2632 that is checking for self-modifying code. Instead we
2633 could simply call tb_flush here. Until we work out the
2634 changes required to turn off the extra write protection,
2635 this can be a no-op. */
2636 break;
2637 case 0x9E:
2638 /* RDUNIQUE */
2639 /* Handled in the translator for usermode. */
2640 abort();
2641 case 0x9F:
2642 /* WRUNIQUE */
2643 /* Handled in the translator for usermode. */
2644 abort();
2645 case 0xAA:
2646 /* GENTRAP */
2647 info.si_signo = TARGET_SIGFPE;
2648 switch (env->ir[IR_A0]) {
2649 case TARGET_GEN_INTOVF:
2650 info.si_code = TARGET_FPE_INTOVF;
2651 break;
2652 case TARGET_GEN_INTDIV:
2653 info.si_code = TARGET_FPE_INTDIV;
2654 break;
2655 case TARGET_GEN_FLTOVF:
2656 info.si_code = TARGET_FPE_FLTOVF;
2657 break;
2658 case TARGET_GEN_FLTUND:
2659 info.si_code = TARGET_FPE_FLTUND;
2660 break;
2661 case TARGET_GEN_FLTINV:
2662 info.si_code = TARGET_FPE_FLTINV;
2663 break;
2664 case TARGET_GEN_FLTINE:
2665 info.si_code = TARGET_FPE_FLTRES;
2666 break;
2667 case TARGET_GEN_ROPRAND:
2668 info.si_code = 0;
2669 break;
2670 default:
2671 info.si_signo = TARGET_SIGTRAP;
2672 info.si_code = 0;
2673 break;
2674 }
2675 info.si_errno = 0;
2676 info._sifields._sigfault._addr = env->pc;
2677 queue_signal(env, info.si_signo, &info);
2678 break;
2679 default:
2680 goto do_sigill;
2681 }
2682 break;
2683 case EXCP_DEBUG:
2684 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
2685 if (info.si_signo) {
2686 env->lock_addr = -1;
2687 info.si_errno = 0;
2688 info.si_code = TARGET_TRAP_BRKPT;
2689 queue_signal(env, info.si_signo, &info);
2690 }
2691 break;
2692 case EXCP_STL_C:
2693 case EXCP_STQ_C:
2694 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
2695 break;
2696 default:
2697 printf ("Unhandled trap: 0x%x\n", trapnr);
2698 cpu_dump_state(env, stderr, fprintf, 0);
2699 exit (1);
2700 }
2701 process_pending_signals (env);
2702 }
2703 }
2704 #endif /* TARGET_ALPHA */
2705
2706 #ifdef TARGET_S390X
2707 void cpu_loop(CPUS390XState *env)
2708 {
2709 int trapnr;
2710 target_siginfo_t info;
2711
2712 while (1) {
2713 trapnr = cpu_s390x_exec (env);
2714
2715 switch (trapnr) {
2716 case EXCP_INTERRUPT:
2717 /* just indicate that signals should be handled asap */
2718 break;
2719 case EXCP_DEBUG:
2720 {
2721 int sig;
2722
2723 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2724 if (sig) {
2725 info.si_signo = sig;
2726 info.si_errno = 0;
2727 info.si_code = TARGET_TRAP_BRKPT;
2728 queue_signal(env, info.si_signo, &info);
2729 }
2730 }
2731 break;
2732 case EXCP_SVC:
2733 {
2734 int n = env->int_svc_code;
2735 if (!n) {
2736 /* syscalls > 255 */
2737 n = env->regs[1];
2738 }
2739 env->psw.addr += env->int_svc_ilc;
2740 env->regs[2] = do_syscall(env, n,
2741 env->regs[2],
2742 env->regs[3],
2743 env->regs[4],
2744 env->regs[5],
2745 env->regs[6],
2746 env->regs[7],
2747 0, 0);
2748 }
2749 break;
2750 case EXCP_ADDR:
2751 {
2752 info.si_signo = SIGSEGV;
2753 info.si_errno = 0;
2754 /* XXX: check env->error_code */
2755 info.si_code = TARGET_SEGV_MAPERR;
2756 info._sifields._sigfault._addr = env->__excp_addr;
2757 queue_signal(env, info.si_signo, &info);
2758 }
2759 break;
2760 case EXCP_SPEC:
2761 {
2762 fprintf(stderr,"specification exception insn 0x%08x%04x\n", ldl(env->psw.addr), lduw(env->psw.addr + 4));
2763 info.si_signo = SIGILL;
2764 info.si_errno = 0;
2765 info.si_code = TARGET_ILL_ILLOPC;
2766 info._sifields._sigfault._addr = env->__excp_addr;
2767 queue_signal(env, info.si_signo, &info);
2768 }
2769 break;
2770 default:
2771 printf ("Unhandled trap: 0x%x\n", trapnr);
2772 cpu_dump_state(env, stderr, fprintf, 0);
2773 exit (1);
2774 }
2775 process_pending_signals (env);
2776 }
2777 }
2778
2779 #endif /* TARGET_S390X */
2780
2781 static void version(void)
2782 {
2783 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION
2784 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
2785 }
2786
2787 static void usage(void)
2788 {
2789 version();
2790 printf("usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
2791 "Linux CPU emulator (compiled for %s emulation)\n"
2792 "\n"
2793 "Standard options:\n"
2794 "-h print this help\n"
2795 "-version display version information and exit\n"
2796 "-g port wait gdb connection to port\n"
2797 "-L path set the elf interpreter prefix (default=%s)\n"
2798 "-s size set the stack size in bytes (default=%ld)\n"
2799 "-cpu model select CPU (-cpu ? for list)\n"
2800 "-drop-ld-preload drop LD_PRELOAD for target process\n"
2801 "-E var=value sets/modifies targets environment variable(s)\n"
2802 "-U var unsets targets environment variable(s)\n"
2803 "-0 argv0 forces target process argv[0] to be argv0\n"
2804 #if defined(CONFIG_USE_GUEST_BASE)
2805 "-B address set guest_base address to address\n"
2806 "-R size reserve size bytes for guest virtual address space\n"
2807 #endif
2808 "\n"
2809 "Debug options:\n"
2810 "-d options activate log (logfile=%s)\n"
2811 "-p pagesize set the host page size to 'pagesize'\n"
2812 "-singlestep always run in singlestep mode\n"
2813 "-strace log system calls\n"
2814 "\n"
2815 "Environment variables:\n"
2816 "QEMU_STRACE Print system calls and arguments similar to the\n"
2817 " 'strace' program. Enable by setting to any value.\n"
2818 "You can use -E and -U options to set/unset environment variables\n"
2819 "for target process. It is possible to provide several variables\n"
2820 "by repeating the option. For example:\n"
2821 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
2822 "Note that if you provide several changes to single variable\n"
2823 "last change will stay in effect.\n"
2824 ,
2825 TARGET_ARCH,
2826 interp_prefix,
2827 guest_stack_size,
2828 DEBUG_LOGFILE);
2829 exit(1);
2830 }
2831
2832 THREAD CPUState *thread_env;
2833
2834 void task_settid(TaskState *ts)
2835 {
2836 if (ts->ts_tid == 0) {
2837 #ifdef CONFIG_USE_NPTL
2838 ts->ts_tid = (pid_t)syscall(SYS_gettid);
2839 #else
2840 /* when no threads are used, tid becomes pid */
2841 ts->ts_tid = getpid();
2842 #endif
2843 }
2844 }
2845
2846 void stop_all_tasks(void)
2847 {
2848 /*
2849 * We trust that when using NPTL, start_exclusive()
2850 * handles thread stopping correctly.
2851 */
2852 start_exclusive();
2853 }
2854
2855 /* Assumes contents are already zeroed. */
2856 void init_task_state(TaskState *ts)
2857 {
2858 int i;
2859
2860 ts->used = 1;
2861 ts->first_free = ts->sigqueue_table;
2862 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2863 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2864 }
2865 ts->sigqueue_table[i].next = NULL;
2866 }
2867
2868 int main(int argc, char **argv, char **envp)
2869 {
2870 const char *filename;
2871 const char *cpu_model;
2872 const char *log_file = DEBUG_LOGFILE;
2873 const char *log_mask = NULL;
2874 struct target_pt_regs regs1, *regs = &regs1;
2875 struct image_info info1, *info = &info1;
2876 struct linux_binprm bprm;
2877 TaskState *ts;
2878 CPUState *env;
2879 int optind;
2880 const char *r;
2881 int gdbstub_port = 0;
2882 char **target_environ, **wrk;
2883 char **target_argv;
2884 int target_argc;
2885 envlist_t *envlist = NULL;
2886 const char *argv0 = NULL;
2887 int i;
2888 int ret;
2889
2890 if (argc <= 1)
2891 usage();
2892
2893 qemu_cache_utils_init(envp);
2894
2895 if ((envlist = envlist_create()) == NULL) {
2896 (void) fprintf(stderr, "Unable to allocate envlist\n");
2897 exit(1);
2898 }
2899
2900 /* add current environment into the list */
2901 for (wrk = environ; *wrk != NULL; wrk++) {
2902 (void) envlist_setenv(envlist, *wrk);
2903 }
2904
2905 /* Read the stack limit from the kernel. If it's "unlimited",
2906 then we can do little else besides use the default. */
2907 {
2908 struct rlimit lim;
2909 if (getrlimit(RLIMIT_STACK, &lim) == 0
2910 && lim.rlim_cur != RLIM_INFINITY
2911 && lim.rlim_cur == (target_long)lim.rlim_cur) {
2912 guest_stack_size = lim.rlim_cur;
2913 }
2914 }
2915
2916 cpu_model = NULL;
2917 #if defined(cpudef_setup)
2918 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
2919 #endif
2920
2921 optind = 1;
2922 for(;;) {
2923 if (optind >= argc)
2924 break;
2925 r = argv[optind];
2926 if (r[0] != '-')
2927 break;
2928 optind++;
2929 r++;
2930 if (!strcmp(r, "-")) {
2931 break;
2932 } else if (!strcmp(r, "d")) {
2933 if (optind >= argc) {
2934 break;
2935 }
2936 log_mask = argv[optind++];
2937 } else if (!strcmp(r, "D")) {
2938 if (optind >= argc) {
2939 break;
2940 }
2941 log_file = argv[optind++];
2942 } else if (!strcmp(r, "E")) {
2943 r = argv[optind++];
2944 if (envlist_setenv(envlist, r) != 0)
2945 usage();
2946 } else if (!strcmp(r, "ignore-environment")) {
2947 envlist_free(envlist);
2948 if ((envlist = envlist_create()) == NULL) {
2949 (void) fprintf(stderr, "Unable to allocate envlist\n");
2950 exit(1);
2951 }
2952 } else if (!strcmp(r, "U")) {
2953 r = argv[optind++];
2954 if (envlist_unsetenv(envlist, r) != 0)
2955 usage();
2956 } else if (!strcmp(r, "0")) {
2957 r = argv[optind++];
2958 argv0 = r;
2959 } else if (!strcmp(r, "s")) {
2960 if (optind >= argc)
2961 break;
2962 r = argv[optind++];
2963 guest_stack_size = strtoul(r, (char **)&r, 0);
2964 if (guest_stack_size == 0)
2965 usage();
2966 if (*r == 'M')
2967 guest_stack_size *= 1024 * 1024;
2968 else if (*r == 'k' || *r == 'K')
2969 guest_stack_size *= 1024;
2970 } else if (!strcmp(r, "L")) {
2971 interp_prefix = argv[optind++];
2972 } else if (!strcmp(r, "p")) {
2973 if (optind >= argc)
2974 break;
2975 qemu_host_page_size = atoi(argv[optind++]);
2976 if (qemu_host_page_size == 0 ||
2977 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
2978 fprintf(stderr, "page size must be a power of two\n");
2979 exit(1);
2980 }
2981 } else if (!strcmp(r, "g")) {
2982 if (optind >= argc)
2983 break;
2984 gdbstub_port = atoi(argv[optind++]);
2985 } else if (!strcmp(r, "r")) {
2986 qemu_uname_release = argv[optind++];
2987 } else if (!strcmp(r, "cpu")) {
2988 cpu_model = argv[optind++];
2989 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
2990 /* XXX: implement xxx_cpu_list for targets that still miss it */
2991 #if defined(cpu_list_id)
2992 cpu_list_id(stdout, &fprintf, "");
2993 #elif defined(cpu_list)
2994 cpu_list(stdout, &fprintf); /* deprecated */
2995 #endif
2996 exit(1);
2997 }
2998 #if defined(CONFIG_USE_GUEST_BASE)
2999 } else if (!strcmp(r, "B")) {
3000 guest_base = strtol(argv[optind++], NULL, 0);
3001 have_guest_base = 1;
3002 } else if (!strcmp(r, "R")) {
3003 char *p;
3004 int shift = 0;
3005 reserved_va = strtoul(argv[optind++], &p, 0);
3006 switch (*p) {
3007 case 'k':
3008 case 'K':
3009 shift = 10;
3010 break;
3011 case 'M':
3012 shift = 20;
3013 break;
3014 case 'G':
3015 shift = 30;
3016 break;
3017 }
3018 if (shift) {
3019 unsigned long unshifted = reserved_va;
3020 p++;
3021 reserved_va <<= shift;
3022 if (((reserved_va >> shift) != unshifted)
3023 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3024 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3025 #endif
3026 ) {
3027 fprintf(stderr, "Reserved virtual address too big\n");
3028 exit(1);
3029 }
3030 }
3031 if (*p) {
3032 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3033 exit(1);
3034 }
3035 #endif
3036 } else if (!strcmp(r, "drop-ld-preload")) {
3037 (void) envlist_unsetenv(envlist, "LD_PRELOAD");
3038 } else if (!strcmp(r, "singlestep")) {
3039 singlestep = 1;
3040 } else if (!strcmp(r, "strace")) {
3041 do_strace = 1;
3042 } else if (!strcmp(r, "version")) {
3043 version();
3044 exit(0);
3045 } else {
3046 usage();
3047 }
3048 }
3049 if (optind >= argc)
3050 usage();
3051 filename = argv[optind];
3052 exec_path = argv[optind];
3053
3054 /* init debug */
3055 cpu_set_log_filename(log_file);
3056 if (log_mask) {
3057 int mask;
3058 const CPULogItem *item;
3059
3060 mask = cpu_str_to_log_mask(log_mask);
3061 if (!mask) {
3062 printf("Log items (comma separated):\n");
3063 for (item = cpu_log_items; item->mask != 0; item++) {
3064 printf("%-10s %s\n", item->name, item->help);
3065 }
3066 exit(1);
3067 }
3068 cpu_set_log(mask);
3069 }
3070
3071 /* Zero out regs */
3072 memset(regs, 0, sizeof(struct target_pt_regs));
3073
3074 /* Zero out image_info */
3075 memset(info, 0, sizeof(struct image_info));
3076
3077 memset(&bprm, 0, sizeof (bprm));
3078
3079 /* Scan interp_prefix dir for replacement files. */
3080 init_paths(interp_prefix);
3081
3082 if (cpu_model == NULL) {
3083 #if defined(TARGET_I386)
3084 #ifdef TARGET_X86_64
3085 cpu_model = "qemu64";
3086 #else
3087 cpu_model = "qemu32";
3088 #endif
3089 #elif defined(TARGET_ARM)
3090 cpu_model = "any";
3091 #elif defined(TARGET_UNICORE32)
3092 cpu_model = "any";
3093 #elif defined(TARGET_M68K)
3094 cpu_model = "any";
3095 #elif defined(TARGET_SPARC)
3096 #ifdef TARGET_SPARC64
3097 cpu_model = "TI UltraSparc II";
3098 #else
3099 cpu_model = "Fujitsu MB86904";
3100 #endif
3101 #elif defined(TARGET_MIPS)
3102 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3103 cpu_model = "20Kc";
3104 #else
3105 cpu_model = "24Kf";
3106 #endif
3107 #elif defined(TARGET_PPC)
3108 #ifdef TARGET_PPC64
3109 cpu_model = "970fx";
3110 #else
3111 cpu_model = "750";
3112 #endif
3113 #else
3114 cpu_model = "any";
3115 #endif
3116 }
3117 cpu_exec_init_all(0);
3118 /* NOTE: we need to init the CPU at this stage to get
3119 qemu_host_page_size */
3120 env = cpu_init(cpu_model);
3121 if (!env) {
3122 fprintf(stderr, "Unable to find CPU definition\n");
3123 exit(1);
3124 }
3125 #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
3126 cpu_reset(env);
3127 #endif
3128
3129 thread_env = env;
3130
3131 if (getenv("QEMU_STRACE")) {
3132 do_strace = 1;
3133 }
3134
3135 target_environ = envlist_to_environ(envlist, NULL);
3136 envlist_free(envlist);
3137
3138 #if defined(CONFIG_USE_GUEST_BASE)
3139 /*
3140 * Now that page sizes are configured in cpu_init() we can do
3141 * proper page alignment for guest_base.
3142 */
3143 guest_base = HOST_PAGE_ALIGN(guest_base);
3144
3145 if (reserved_va) {
3146 void *p;
3147 int flags;
3148
3149 flags = MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE;
3150 if (have_guest_base) {
3151 flags |= MAP_FIXED;
3152 }
3153 p = mmap((void *)guest_base, reserved_va, PROT_NONE, flags, -1, 0);
3154 if (p == MAP_FAILED) {
3155 fprintf(stderr, "Unable to reserve guest address space\n");
3156 exit(1);
3157 }
3158 guest_base = (unsigned long)p;
3159 /* Make sure the address is properly aligned. */
3160 if (guest_base & ~qemu_host_page_mask) {
3161 munmap(p, reserved_va);
3162 p = mmap((void *)guest_base, reserved_va + qemu_host_page_size,
3163 PROT_NONE, flags, -1, 0);
3164 if (p == MAP_FAILED) {
3165 fprintf(stderr, "Unable to reserve guest address space\n");
3166 exit(1);
3167 }
3168 guest_base = HOST_PAGE_ALIGN((unsigned long)p);
3169 }
3170 qemu_log("Reserved 0x%lx bytes of guest address space\n", reserved_va);
3171 }
3172 #endif /* CONFIG_USE_GUEST_BASE */
3173
3174 /*
3175 * Read in mmap_min_addr kernel parameter. This value is used
3176 * When loading the ELF image to determine whether guest_base
3177 * is needed. It is also used in mmap_find_vma.
3178 */
3179 {
3180 FILE *fp;
3181
3182 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3183 unsigned long tmp;
3184 if (fscanf(fp, "%lu", &tmp) == 1) {
3185 mmap_min_addr = tmp;
3186 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3187 }
3188 fclose(fp);
3189 }
3190 }
3191
3192 /*
3193 * Prepare copy of argv vector for target.
3194 */
3195 target_argc = argc - optind;
3196 target_argv = calloc(target_argc + 1, sizeof (char *));
3197 if (target_argv == NULL) {
3198 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3199 exit(1);
3200 }
3201
3202 /*
3203 * If argv0 is specified (using '-0' switch) we replace
3204 * argv[0] pointer with the given one.
3205 */
3206 i = 0;
3207 if (argv0 != NULL) {
3208 target_argv[i++] = strdup(argv0);
3209 }
3210 for (; i < target_argc; i++) {
3211 target_argv[i] = strdup(argv[optind + i]);
3212 }
3213 target_argv[target_argc] = NULL;
3214
3215 ts = qemu_mallocz (sizeof(TaskState));
3216 init_task_state(ts);
3217 /* build Task State */
3218 ts->info = info;
3219 ts->bprm = &bprm;
3220 env->opaque = ts;
3221 task_settid(ts);
3222
3223 ret = loader_exec(filename, target_argv, target_environ, regs,
3224 info, &bprm);
3225 if (ret != 0) {
3226 printf("Error %d while loading %s\n", ret, filename);
3227 _exit(1);
3228 }
3229
3230 for (i = 0; i < target_argc; i++) {
3231 free(target_argv[i]);
3232 }
3233 free(target_argv);
3234
3235 for (wrk = target_environ; *wrk; wrk++) {
3236 free(*wrk);
3237 }
3238
3239 free(target_environ);
3240
3241 if (qemu_log_enabled()) {
3242 #if defined(CONFIG_USE_GUEST_BASE)
3243 qemu_log("guest_base 0x%lx\n", guest_base);
3244 #endif
3245 log_page_dump();
3246
3247 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
3248 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
3249 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
3250 info->start_code);
3251 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
3252 info->start_data);
3253 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
3254 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
3255 info->start_stack);
3256 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
3257 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
3258 }
3259
3260 target_set_brk(info->brk);
3261 syscall_init();
3262 signal_init();
3263
3264 #if defined(CONFIG_USE_GUEST_BASE)
3265 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
3266 generating the prologue until now so that the prologue can take
3267 the real value of GUEST_BASE into account. */
3268 tcg_prologue_init(&tcg_ctx);
3269 #endif
3270
3271 #if defined(TARGET_I386)
3272 cpu_x86_set_cpl(env, 3);
3273
3274 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
3275 env->hflags |= HF_PE_MASK;
3276 if (env->cpuid_features & CPUID_SSE) {
3277 env->cr[4] |= CR4_OSFXSR_MASK;
3278 env->hflags |= HF_OSFXSR_MASK;
3279 }
3280 #ifndef TARGET_ABI32
3281 /* enable 64 bit mode if possible */
3282 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
3283 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3284 exit(1);
3285 }
3286 env->cr[4] |= CR4_PAE_MASK;
3287 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
3288 env->hflags |= HF_LMA_MASK;
3289 #endif
3290
3291 /* flags setup : we activate the IRQs by default as in user mode */
3292 env->eflags |= IF_MASK;
3293
3294 /* linux register setup */
3295 #ifndef TARGET_ABI32
3296 env->regs[R_EAX] = regs->rax;
3297 env->regs[R_EBX] = regs->rbx;
3298 env->regs[R_ECX] = regs->rcx;
3299 env->regs[R_EDX] = regs->rdx;
3300 env->regs[R_ESI] = regs->rsi;
3301 env->regs[R_EDI] = regs->rdi;
3302 env->regs[R_EBP] = regs->rbp;
3303 env->regs[R_ESP] = regs->rsp;
3304 env->eip = regs->rip;
3305 #else
3306 env->regs[R_EAX] = regs->eax;
3307 env->regs[R_EBX] = regs->ebx;
3308 env->regs[R_ECX] = regs->ecx;
3309 env->regs[R_EDX] = regs->edx;
3310 env->regs[R_ESI] = regs->esi;
3311 env->regs[R_EDI] = regs->edi;
3312 env->regs[R_EBP] = regs->ebp;
3313 env->regs[R_ESP] = regs->esp;
3314 env->eip = regs->eip;
3315 #endif
3316
3317 /* linux interrupt setup */
3318 #ifndef TARGET_ABI32
3319 env->idt.limit = 511;
3320 #else
3321 env->idt.limit = 255;
3322 #endif
3323 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3324 PROT_READ|PROT_WRITE,
3325 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3326 idt_table = g2h(env->idt.base);
3327 set_idt(0, 0);
3328 set_idt(1, 0);
3329 set_idt(2, 0);
3330 set_idt(3, 3);
3331 set_idt(4, 3);
3332 set_idt(5, 0);
3333 set_idt(6, 0);
3334 set_idt(7, 0);
3335 set_idt(8, 0);
3336 set_idt(9, 0);
3337 set_idt(10, 0);
3338 set_idt(11, 0);
3339 set_idt(12, 0);
3340 set_idt(13, 0);
3341 set_idt(14, 0);
3342 set_idt(15, 0);
3343 set_idt(16, 0);
3344 set_idt(17, 0);
3345 set_idt(18, 0);
3346 set_idt(19, 0);
3347 set_idt(0x80, 3);
3348
3349 /* linux segment setup */
3350 {
3351 uint64_t *gdt_table;
3352 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3353 PROT_READ|PROT_WRITE,
3354 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3355 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
3356 gdt_table = g2h(env->gdt.base);
3357 #ifdef TARGET_ABI32
3358 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3359 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3360 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3361 #else
3362 /* 64 bit code segment */
3363 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3364 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3365 DESC_L_MASK |
3366 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3367 #endif
3368 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3369 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3370 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3371 }
3372 cpu_x86_load_seg(env, R_CS, __USER_CS);
3373 cpu_x86_load_seg(env, R_SS, __USER_DS);
3374 #ifdef TARGET_ABI32
3375 cpu_x86_load_seg(env, R_DS, __USER_DS);
3376 cpu_x86_load_seg(env, R_ES, __USER_DS);
3377 cpu_x86_load_seg(env, R_FS, __USER_DS);
3378 cpu_x86_load_seg(env, R_GS, __USER_DS);
3379 /* This hack makes Wine work... */
3380 env->segs[R_FS].selector = 0;
3381 #else
3382 cpu_x86_load_seg(env, R_DS, 0);
3383 cpu_x86_load_seg(env, R_ES, 0);
3384 cpu_x86_load_seg(env, R_FS, 0);
3385 cpu_x86_load_seg(env, R_GS, 0);
3386 #endif
3387 #elif defined(TARGET_ARM)
3388 {
3389 int i;
3390 cpsr_write(env, regs->uregs[16], 0xffffffff);
3391 for(i = 0; i < 16; i++) {
3392 env->regs[i] = regs->uregs[i];
3393 }
3394 }
3395 #elif defined(TARGET_UNICORE32)
3396 {
3397 int i;
3398 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
3399 for (i = 0; i < 32; i++) {
3400 env->regs[i] = regs->uregs[i];
3401 }
3402 }
3403 #elif defined(TARGET_SPARC)
3404 {
3405 int i;
3406 env->pc = regs->pc;
3407 env->npc = regs->npc;
3408 env->y = regs->y;
3409 for(i = 0; i < 8; i++)
3410 env->gregs[i] = regs->u_regs[i];
3411 for(i = 0; i < 8; i++)
3412 env->regwptr[i] = regs->u_regs[i + 8];
3413 }
3414 #elif defined(TARGET_PPC)
3415 {
3416 int i;
3417
3418 #if defined(TARGET_PPC64)
3419 #if defined(TARGET_ABI32)
3420 env->msr &= ~((target_ulong)1 << MSR_SF);
3421 #else
3422 env->msr |= (target_ulong)1 << MSR_SF;
3423 #endif
3424 #endif
3425 env->nip = regs->nip;
3426 for(i = 0; i < 32; i++) {
3427 env->gpr[i] = regs->gpr[i];
3428 }
3429 }
3430 #elif defined(TARGET_M68K)
3431 {
3432 env->pc = regs->pc;
3433 env->dregs[0] = regs->d0;
3434 env->dregs[1] = regs->d1;
3435 env->dregs[2] = regs->d2;
3436 env->dregs[3] = regs->d3;
3437 env->dregs[4] = regs->d4;
3438 env->dregs[5] = regs->d5;
3439 env->dregs[6] = regs->d6;
3440 env->dregs[7] = regs->d7;
3441 env->aregs[0] = regs->a0;
3442 env->aregs[1] = regs->a1;
3443 env->aregs[2] = regs->a2;
3444 env->aregs[3] = regs->a3;
3445 env->aregs[4] = regs->a4;
3446 env->aregs[5] = regs->a5;
3447 env->aregs[6] = regs->a6;
3448 env->aregs[7] = regs->usp;
3449 env->sr = regs->sr;
3450 ts->sim_syscalls = 1;
3451 }
3452 #elif defined(TARGET_MICROBLAZE)
3453 {
3454 env->regs[0] = regs->r0;
3455 env->regs[1] = regs->r1;
3456 env->regs[2] = regs->r2;
3457 env->regs[3] = regs->r3;
3458 env->regs[4] = regs->r4;
3459 env->regs[5] = regs->r5;
3460 env->regs[6] = regs->r6;
3461 env->regs[7] = regs->r7;
3462 env->regs[8] = regs->r8;
3463 env->regs[9] = regs->r9;
3464 env->regs[10] = regs->r10;
3465 env->regs[11] = regs->r11;
3466 env->regs[12] = regs->r12;
3467 env->regs[13] = regs->r13;
3468 env->regs[14] = regs->r14;
3469 env->regs[15] = regs->r15;
3470 env->regs[16] = regs->r16;
3471 env->regs[17] = regs->r17;
3472 env->regs[18] = regs->r18;
3473 env->regs[19] = regs->r19;
3474 env->regs[20] = regs->r20;
3475 env->regs[21] = regs->r21;
3476 env->regs[22] = regs->r22;
3477 env->regs[23] = regs->r23;
3478 env->regs[24] = regs->r24;
3479 env->regs[25] = regs->r25;
3480 env->regs[26] = regs->r26;
3481 env->regs[27] = regs->r27;
3482 env->regs[28] = regs->r28;
3483 env->regs[29] = regs->r29;
3484 env->regs[30] = regs->r30;
3485 env->regs[31] = regs->r31;
3486 env->sregs[SR_PC] = regs->pc;
3487 }
3488 #elif defined(TARGET_MIPS)
3489 {
3490 int i;
3491
3492 for(i = 0; i < 32; i++) {
3493 env->active_tc.gpr[i] = regs->regs[i];
3494 }
3495 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
3496 if (regs->cp0_epc & 1) {
3497 env->hflags |= MIPS_HFLAG_M16;
3498 }
3499 }
3500 #elif defined(TARGET_SH4)
3501 {
3502 int i;
3503
3504 for(i = 0; i < 16; i++) {
3505 env->gregs[i] = regs->regs[i];
3506 }
3507 env->pc = regs->pc;
3508 }
3509 #elif defined(TARGET_ALPHA)
3510 {
3511 int i;
3512
3513 for(i = 0; i < 28; i++) {
3514 env->ir[i] = ((abi_ulong *)regs)[i];
3515 }
3516 env->ir[IR_SP] = regs->usp;
3517 env->pc = regs->pc;
3518 }
3519 #elif defined(TARGET_CRIS)
3520 {
3521 env->regs[0] = regs->r0;
3522 env->regs[1] = regs->r1;
3523 env->regs[2] = regs->r2;
3524 env->regs[3] = regs->r3;
3525 env->regs[4] = regs->r4;
3526 env->regs[5] = regs->r5;
3527 env->regs[6] = regs->r6;
3528 env->regs[7] = regs->r7;
3529 env->regs[8] = regs->r8;
3530 env->regs[9] = regs->r9;
3531 env->regs[10] = regs->r10;
3532 env->regs[11] = regs->r11;
3533 env->regs[12] = regs->r12;
3534 env->regs[13] = regs->r13;
3535 env->regs[14] = info->start_stack;
3536 env->regs[15] = regs->acr;
3537 env->pc = regs->erp;
3538 }
3539 #elif defined(TARGET_S390X)
3540 {
3541 int i;
3542 for (i = 0; i < 16; i++) {
3543 env->regs[i] = regs->gprs[i];
3544 }
3545 env->psw.mask = regs->psw.mask;
3546 env->psw.addr = regs->psw.addr;
3547 }
3548 #else
3549 #error unsupported target CPU
3550 #endif
3551
3552 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
3553 ts->stack_base = info->start_stack;
3554 ts->heap_base = info->brk;
3555 /* This will be filled in on the first SYS_HEAPINFO call. */
3556 ts->heap_limit = 0;
3557 #endif
3558
3559 if (gdbstub_port) {
3560 gdbserver_start (gdbstub_port);
3561 gdb_handlesig(env, 0);
3562 }
3563 cpu_loop(env);
3564 /* never exits */
3565 return 0;
3566 }
AR7 emulation for QEMU