2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 static const TypeInfo spapr_intc_info
= {
27 .name
= TYPE_SPAPR_INTC
,
28 .parent
= TYPE_INTERFACE
,
29 .class_size
= sizeof(SpaprInterruptControllerClass
),
32 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
34 spapr
->irq_map_nr
= nr_msis
;
35 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
38 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
44 * The 'align_mask' parameter of bitmap_find_next_zero_area()
45 * should be one less than a power of 2; 0 means no
46 * alignment. Adapt the 'align' value of the former allocator
47 * to fit the requirements of bitmap_find_next_zero_area()
51 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
53 if (irq
== spapr
->irq_map_nr
) {
54 error_setg(errp
, "can't find a free %d-IRQ block", num
);
58 bitmap_set(spapr
->irq_map
, irq
, num
);
60 return irq
+ SPAPR_IRQ_MSI
;
63 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
65 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
68 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
69 SpaprIrq
*irq
, Error
**errp
)
71 MachineState
*machine
= MACHINE(spapr
);
72 Error
*local_err
= NULL
;
74 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
75 irq
->init_kvm(spapr
, &local_err
);
76 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
77 error_prepend(&local_err
,
78 "kernel_irqchip requested but unavailable: ");
79 error_propagate(errp
, local_err
);
88 * We failed to initialize the KVM device, fallback to
91 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
92 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
93 warn_report_err(local_err
);
101 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
103 if (!kvm_irqchip_in_kernel()) {
106 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
107 icp_resend(spapr_cpu_state(cpu
)->icp
);
113 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
115 Error
*local_err
= NULL
;
117 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
119 error_propagate(errp
, local_err
);
124 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
127 xics_kvm_connect(spapr
, errp
);
131 SpaprIrq spapr_irq_xics
= {
132 .nr_xirqs
= SPAPR_NR_XIRQS
,
133 .nr_msis
= SPAPR_NR_MSIS
,
137 .post_load
= spapr_irq_post_load_xics
,
138 .reset
= spapr_irq_reset_xics
,
139 .init_kvm
= spapr_irq_init_kvm_xics
,
146 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
148 return spapr_xive_post_load(spapr
->xive
, version_id
);
151 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
154 Error
*local_err
= NULL
;
157 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
159 /* (TCG) Set the OS CAM line of the thread interrupt context. */
160 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
163 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
165 error_propagate(errp
, local_err
);
169 /* Activate the XIVE MMIOs */
170 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
173 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
176 kvmppc_xive_connect(spapr
->xive
, errp
);
180 SpaprIrq spapr_irq_xive
= {
181 .nr_xirqs
= SPAPR_NR_XIRQS
,
182 .nr_msis
= SPAPR_NR_MSIS
,
186 .post_load
= spapr_irq_post_load_xive
,
187 .reset
= spapr_irq_reset_xive
,
188 .init_kvm
= spapr_irq_init_kvm_xive
,
192 * Dual XIVE and XICS IRQ backend.
194 * Both interrupt mode, XIVE and XICS, objects are created but the
195 * machine starts in legacy interrupt mode (XICS). It can be changed
196 * by the CAS negotiation process and, in that case, the new mode is
197 * activated after an extra machine reset.
201 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
204 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
206 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
207 &spapr_irq_xive
: &spapr_irq_xics
;
210 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
213 * Force a reset of the XIVE backend after migration. The machine
214 * defaults to XICS at startup.
216 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
217 if (kvm_irqchip_in_kernel()) {
218 xics_kvm_disconnect(spapr
, &error_fatal
);
220 spapr_irq_xive
.reset(spapr
, &error_fatal
);
223 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
226 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
228 Error
*local_err
= NULL
;
231 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
234 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
236 /* Destroy all KVM devices */
237 if (kvm_irqchip_in_kernel()) {
238 xics_kvm_disconnect(spapr
, &local_err
);
240 error_propagate(errp
, local_err
);
241 error_prepend(errp
, "KVM XICS disconnect failed: ");
244 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
246 error_propagate(errp
, local_err
);
247 error_prepend(errp
, "KVM XIVE disconnect failed: ");
252 spapr_irq_current(spapr
)->reset(spapr
, errp
);
256 * Define values in sync with the XIVE and XICS backend
258 SpaprIrq spapr_irq_dual
= {
259 .nr_xirqs
= SPAPR_NR_XIRQS
,
260 .nr_msis
= SPAPR_NR_MSIS
,
264 .post_load
= spapr_irq_post_load_dual
,
265 .reset
= spapr_irq_reset_dual
,
266 .init_kvm
= NULL
, /* should not be used */
270 static int spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
272 MachineState
*machine
= MACHINE(spapr
);
275 * Sanity checks on non-P9 machines. On these, XIVE is not
276 * advertised, see spapr_dt_ov5_platform_support()
278 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
279 0, spapr
->max_compat_pvr
)) {
281 * If the 'dual' interrupt mode is selected, force XICS as CAS
282 * negotiation is useless.
284 if (spapr
->irq
== &spapr_irq_dual
) {
285 spapr
->irq
= &spapr_irq_xics
;
290 * Non-P9 machines using only XIVE is a bogus setup. We have two
291 * scenarios to take into account because of the compat mode:
293 * 1. POWER7/8 machines should fail to init later on when creating
294 * the XIVE interrupt presenters because a POWER9 exception
297 * 2. POWER9 machines using the POWER8 compat mode won't fail and
298 * will let the OS boot with a partial XIVE setup : DT
299 * properties but no hcalls.
301 * To cover both and not confuse the OS, add an early failure in
304 if (spapr
->irq
== &spapr_irq_xive
) {
305 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
311 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
312 * re-created. Detect that early to avoid QEMU to exit later when the
316 spapr
->irq
== &spapr_irq_dual
&&
317 machine_kernel_irqchip_required(machine
) &&
318 xics_kvm_has_broken_disconnect(spapr
)) {
319 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
327 * sPAPR IRQ frontend routines for devices
329 #define ALL_INTCS(spapr_) \
330 { SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), }
332 int spapr_irq_cpu_intc_create(SpaprMachineState
*spapr
,
333 PowerPCCPU
*cpu
, Error
**errp
)
335 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
339 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
340 SpaprInterruptController
*intc
= intcs
[i
];
342 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
343 rc
= sicc
->cpu_intc_create(intc
, cpu
, errp
);
353 static void spapr_set_irq(void *opaque
, int irq
, int level
)
355 SpaprMachineState
*spapr
= SPAPR_MACHINE(opaque
);
356 SpaprInterruptControllerClass
*sicc
357 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
359 sicc
->set_irq(spapr
->active_intc
, irq
, level
);
362 void spapr_irq_print_info(SpaprMachineState
*spapr
, Monitor
*mon
)
364 SpaprInterruptControllerClass
*sicc
365 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
367 sicc
->print_info(spapr
->active_intc
, mon
);
370 void spapr_irq_dt(SpaprMachineState
*spapr
, uint32_t nr_servers
,
371 void *fdt
, uint32_t phandle
)
373 SpaprInterruptControllerClass
*sicc
374 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
376 sicc
->dt(spapr
->active_intc
, nr_servers
, fdt
, phandle
);
379 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
381 MachineState
*machine
= MACHINE(spapr
);
383 if (machine_kernel_irqchip_split(machine
)) {
384 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
388 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
390 "kernel_irqchip requested but only available with KVM");
394 if (spapr_irq_check(spapr
, errp
) < 0) {
398 /* Initialize the MSI IRQ allocator. */
399 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
400 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
403 if (spapr
->irq
->xics
) {
404 Error
*local_err
= NULL
;
407 obj
= object_new(TYPE_ICS_SPAPR
);
408 object_property_add_child(OBJECT(spapr
), "ics", obj
, &local_err
);
410 error_propagate(errp
, local_err
);
414 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
417 error_propagate(errp
, local_err
);
421 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
, "nr-irqs",
424 error_propagate(errp
, local_err
);
428 object_property_set_bool(obj
, true, "realized", &local_err
);
430 error_propagate(errp
, local_err
);
434 spapr
->ics
= ICS_SPAPR(obj
);
437 if (spapr
->irq
->xive
) {
438 uint32_t nr_servers
= spapr_max_server_number(spapr
);
442 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
443 qdev_prop_set_uint32(dev
, "nr-irqs",
444 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
446 * 8 XIVE END structures per CPU. One for each available
449 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
450 qdev_init_nofail(dev
);
452 spapr
->xive
= SPAPR_XIVE(dev
);
454 /* Enable the CPU IPIs */
455 for (i
= 0; i
< nr_servers
; ++i
) {
456 SpaprInterruptControllerClass
*sicc
457 = SPAPR_INTC_GET_CLASS(spapr
->xive
);
459 if (sicc
->claim_irq(SPAPR_INTC(spapr
->xive
), SPAPR_IRQ_IPI
+ i
,
465 spapr_xive_hcall_init(spapr
);
468 spapr
->qirqs
= qemu_allocate_irqs(spapr_set_irq
, spapr
,
469 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
472 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
474 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
478 assert(irq
>= SPAPR_XIRQ_BASE
);
479 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
481 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
482 SpaprInterruptController
*intc
= intcs
[i
];
484 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
485 rc
= sicc
->claim_irq(intc
, irq
, lsi
, errp
);
495 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
497 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
500 assert(irq
>= SPAPR_XIRQ_BASE
);
501 assert((irq
+ num
) <= (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
503 for (i
= irq
; i
< (irq
+ num
); i
++) {
504 for (j
= 0; j
< ARRAY_SIZE(intcs
); j
++) {
505 SpaprInterruptController
*intc
= intcs
[j
];
508 SpaprInterruptControllerClass
*sicc
509 = SPAPR_INTC_GET_CLASS(intc
);
510 sicc
->free_irq(intc
, i
);
516 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
519 * This interface is basically for VIO and PHB devices to find the
520 * right qemu_irq to manipulate, so we only allow access to the
521 * external irqs for now. Currently anything which needs to
522 * access the IPIs most naturally gets there via the guest side
523 * interfaces, we can change this if we need to in future.
525 assert(irq
>= SPAPR_XIRQ_BASE
);
526 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
529 assert(ics_valid_irq(spapr
->ics
, irq
));
532 assert(irq
< spapr
->xive
->nr_irqs
);
533 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
536 return spapr
->qirqs
[irq
];
539 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
541 spapr_irq_update_active_intc(spapr
);
542 return spapr
->irq
->post_load(spapr
, version_id
);
545 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
547 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
549 spapr_irq_update_active_intc(spapr
);
551 if (spapr
->irq
->reset
) {
552 spapr
->irq
->reset(spapr
, errp
);
556 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
558 const char *nodename
= "interrupt-controller";
561 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
563 error_setg(errp
, "Can't find node \"%s\": %s",
564 nodename
, fdt_strerror(offset
));
568 phandle
= fdt_get_phandle(fdt
, offset
);
570 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
577 static void set_active_intc(SpaprMachineState
*spapr
,
578 SpaprInterruptController
*new_intc
)
580 SpaprInterruptControllerClass
*sicc
;
584 if (new_intc
== spapr
->active_intc
) {
589 if (spapr
->active_intc
) {
590 sicc
= SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
591 if (sicc
->deactivate
) {
592 sicc
->deactivate(spapr
->active_intc
);
596 sicc
= SPAPR_INTC_GET_CLASS(new_intc
);
597 if (sicc
->activate
) {
598 sicc
->activate(new_intc
, &error_fatal
);
601 spapr
->active_intc
= new_intc
;
604 void spapr_irq_update_active_intc(SpaprMachineState
*spapr
)
606 SpaprInterruptController
*new_intc
;
610 * XXX before we run CAS, ov5_cas is initialized empty, which
611 * indicates XICS, even if we have ic-mode=xive. TODO: clean
612 * up the CAS path so that we have a clearer way of handling
615 new_intc
= SPAPR_INTC(spapr
->xive
);
616 } else if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
617 new_intc
= SPAPR_INTC(spapr
->xive
);
619 new_intc
= SPAPR_INTC(spapr
->ics
);
622 set_active_intc(spapr
, new_intc
);
626 * XICS legacy routines - to deprecate one day
629 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
633 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
634 if (num
> (ics
->nr_irqs
- first
)) {
637 for (i
= first
; i
< first
+ num
; ++i
) {
638 if (!ics_irq_free(ics
, i
)) {
642 if (i
== (first
+ num
)) {
650 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
652 ICSState
*ics
= spapr
->ics
;
658 * MSIMesage::data is used for storing VIRQ so
659 * it has to be aligned to num to support multiple
660 * MSI vectors. MSI-X is not affected by this.
661 * The hint is used for the first IRQ, the rest should
662 * be allocated continuously.
665 assert((num
== 1) || (num
== 2) || (num
== 4) ||
666 (num
== 8) || (num
== 16) || (num
== 32));
667 first
= ics_find_free_block(ics
, num
, num
);
669 first
= ics_find_free_block(ics
, num
, 1);
673 error_setg(errp
, "can't find a free %d-IRQ block", num
);
677 return first
+ ics
->offset
;
680 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
682 SpaprIrq spapr_irq_xics_legacy
= {
683 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
684 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
688 .post_load
= spapr_irq_post_load_xics
,
689 .reset
= spapr_irq_reset_xics
,
690 .init_kvm
= spapr_irq_init_kvm_xics
,
693 static void spapr_irq_register_types(void)
695 type_register_static(&spapr_intc_info
);
698 type_init(spapr_irq_register_types
)