2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5 * Copyright (c) 2013 Hervé Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/timer/m48t59.h"
27 #include "qemu/timer.h"
28 #include "sysemu/sysemu.h"
29 #include "hw/sysbus.h"
30 #include "hw/isa/isa.h"
31 #include "exec/address-spaces.h"
35 #if defined(DEBUG_NVRAM)
36 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
38 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
41 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
42 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
43 OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
44 #define M48TXX_SYS_BUS_CLASS(klass) \
45 OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
46 #define M48TXX_SYS_BUS(obj) \
47 OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
49 #define TYPE_M48TXX_ISA "isa-m48txx"
50 #define M48TXX_ISA_GET_CLASS(obj) \
51 OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
52 #define M48TXX_ISA_CLASS(klass) \
53 OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
54 #define M48TXX_ISA(obj) \
55 OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
58 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
59 * alarm and a watchdog timer and related control registers. In the
60 * PPC platform there is also a nvram lock function.
63 typedef struct M48txxInfo
{
65 const char *sysbus_name
;
66 uint32_t model
; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
72 * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
73 * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
74 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
78 /* Hardware parameters */
85 /* Alarm & watchdog */
87 QEMUTimer
*alrm_timer
;
91 /* Model parameters */
92 uint32_t model
; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
98 typedef struct M48txxISAState
{
105 typedef struct M48txxISADeviceClass
{
106 ISADeviceClass parent_class
;
108 } M48txxISADeviceClass
;
110 typedef struct M48txxSysBusState
{
111 SysBusDevice parent_obj
;
116 typedef struct M48txxSysBusDeviceClass
{
117 SysBusDeviceClass parent_class
;
119 } M48txxSysBusDeviceClass
;
121 static M48txxInfo m48txx_info
[] = {
123 .sysbus_name
= "sysbus-m48t02",
127 .sysbus_name
= "sysbus-m48t08",
131 .isa_name
= "isa-m48t59",
138 /* Fake timer functions */
140 /* Alarm management */
141 static void alarm_cb (void *opaque
)
145 M48t59State
*NVRAM
= opaque
;
147 qemu_set_irq(NVRAM
->IRQ
, 1);
148 if ((NVRAM
->buffer
[0x1FF5] & 0x80) == 0 &&
149 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
150 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
151 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
152 /* Repeat once a month */
153 qemu_get_timedate(&tm
, NVRAM
->time_offset
);
155 if (tm
.tm_mon
== 13) {
159 next_time
= qemu_timedate_diff(&tm
) - NVRAM
->time_offset
;
160 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
161 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
162 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
163 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
164 /* Repeat once a day */
165 next_time
= 24 * 60 * 60;
166 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
167 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
168 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
169 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
170 /* Repeat once an hour */
172 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
173 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
174 (NVRAM
->buffer
[0x1FF3] & 0x80) != 0 &&
175 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
176 /* Repeat once a minute */
179 /* Repeat once a second */
182 timer_mod(NVRAM
->alrm_timer
, qemu_clock_get_ns(rtc_clock
) +
184 qemu_set_irq(NVRAM
->IRQ
, 0);
187 static void set_alarm(M48t59State
*NVRAM
)
190 if (NVRAM
->alrm_timer
!= NULL
) {
191 timer_del(NVRAM
->alrm_timer
);
192 diff
= qemu_timedate_diff(&NVRAM
->alarm
) - NVRAM
->time_offset
;
194 timer_mod(NVRAM
->alrm_timer
, diff
* 1000);
198 /* RTC management helpers */
199 static inline void get_time(M48t59State
*NVRAM
, struct tm
*tm
)
201 qemu_get_timedate(tm
, NVRAM
->time_offset
);
204 static void set_time(M48t59State
*NVRAM
, struct tm
*tm
)
206 NVRAM
->time_offset
= qemu_timedate_diff(tm
);
210 /* Watchdog management */
211 static void watchdog_cb (void *opaque
)
213 M48t59State
*NVRAM
= opaque
;
215 NVRAM
->buffer
[0x1FF0] |= 0x80;
216 if (NVRAM
->buffer
[0x1FF7] & 0x80) {
217 NVRAM
->buffer
[0x1FF7] = 0x00;
218 NVRAM
->buffer
[0x1FFC] &= ~0x40;
219 /* May it be a hw CPU Reset instead ? */
220 qemu_system_reset_request();
222 qemu_set_irq(NVRAM
->IRQ
, 1);
223 qemu_set_irq(NVRAM
->IRQ
, 0);
227 static void set_up_watchdog(M48t59State
*NVRAM
, uint8_t value
)
229 uint64_t interval
; /* in 1/16 seconds */
231 NVRAM
->buffer
[0x1FF0] &= ~0x80;
232 if (NVRAM
->wd_timer
!= NULL
) {
233 timer_del(NVRAM
->wd_timer
);
235 interval
= (1 << (2 * (value
& 0x03))) * ((value
>> 2) & 0x1F);
236 timer_mod(NVRAM
->wd_timer
, ((uint64_t)time(NULL
) * 1000) +
237 ((interval
* 1000) >> 4));
242 /* Direct access to NVRAM */
243 void m48t59_write (void *opaque
, uint32_t addr
, uint32_t val
)
245 M48t59State
*NVRAM
= opaque
;
249 if (addr
> 0x1FF8 && addr
< 0x2000)
250 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__
, addr
, val
);
252 /* check for NVRAM access */
253 if ((NVRAM
->model
== 2 && addr
< 0x7f8) ||
254 (NVRAM
->model
== 8 && addr
< 0x1ff8) ||
255 (NVRAM
->model
== 59 && addr
< 0x1ff0)) {
262 /* flags register : read-only */
269 tmp
= from_bcd(val
& 0x7F);
270 if (tmp
>= 0 && tmp
<= 59) {
271 NVRAM
->alarm
.tm_sec
= tmp
;
272 NVRAM
->buffer
[0x1FF2] = val
;
278 tmp
= from_bcd(val
& 0x7F);
279 if (tmp
>= 0 && tmp
<= 59) {
280 NVRAM
->alarm
.tm_min
= tmp
;
281 NVRAM
->buffer
[0x1FF3] = val
;
287 tmp
= from_bcd(val
& 0x3F);
288 if (tmp
>= 0 && tmp
<= 23) {
289 NVRAM
->alarm
.tm_hour
= tmp
;
290 NVRAM
->buffer
[0x1FF4] = val
;
296 tmp
= from_bcd(val
& 0x3F);
298 NVRAM
->alarm
.tm_mday
= tmp
;
299 NVRAM
->buffer
[0x1FF5] = val
;
305 NVRAM
->buffer
[0x1FF6] = val
;
309 NVRAM
->buffer
[0x1FF7] = val
;
310 set_up_watchdog(NVRAM
, val
);
315 NVRAM
->buffer
[addr
] = (val
& ~0xA0) | 0x90;
320 tmp
= from_bcd(val
& 0x7F);
321 if (tmp
>= 0 && tmp
<= 59) {
322 get_time(NVRAM
, &tm
);
324 set_time(NVRAM
, &tm
);
326 if ((val
& 0x80) ^ (NVRAM
->buffer
[addr
] & 0x80)) {
328 NVRAM
->stop_time
= time(NULL
);
330 NVRAM
->time_offset
+= NVRAM
->stop_time
- time(NULL
);
331 NVRAM
->stop_time
= 0;
334 NVRAM
->buffer
[addr
] = val
& 0x80;
339 tmp
= from_bcd(val
& 0x7F);
340 if (tmp
>= 0 && tmp
<= 59) {
341 get_time(NVRAM
, &tm
);
343 set_time(NVRAM
, &tm
);
349 tmp
= from_bcd(val
& 0x3F);
350 if (tmp
>= 0 && tmp
<= 23) {
351 get_time(NVRAM
, &tm
);
353 set_time(NVRAM
, &tm
);
358 /* day of the week / century */
359 tmp
= from_bcd(val
& 0x07);
360 get_time(NVRAM
, &tm
);
362 set_time(NVRAM
, &tm
);
363 NVRAM
->buffer
[addr
] = val
& 0x40;
368 tmp
= from_bcd(val
& 0x3F);
370 get_time(NVRAM
, &tm
);
372 set_time(NVRAM
, &tm
);
378 tmp
= from_bcd(val
& 0x1F);
379 if (tmp
>= 1 && tmp
<= 12) {
380 get_time(NVRAM
, &tm
);
382 set_time(NVRAM
, &tm
);
389 if (tmp
>= 0 && tmp
<= 99) {
390 get_time(NVRAM
, &tm
);
391 if (NVRAM
->model
== 8) {
392 tm
.tm_year
= from_bcd(val
) + 68; // Base year is 1968
394 tm
.tm_year
= from_bcd(val
);
396 set_time(NVRAM
, &tm
);
400 /* Check lock registers state */
401 if (addr
>= 0x20 && addr
<= 0x2F && (NVRAM
->lock
& 1))
403 if (addr
>= 0x30 && addr
<= 0x3F && (NVRAM
->lock
& 2))
406 if (addr
< NVRAM
->size
) {
407 NVRAM
->buffer
[addr
] = val
& 0xFF;
413 uint32_t m48t59_read (void *opaque
, uint32_t addr
)
415 M48t59State
*NVRAM
= opaque
;
417 uint32_t retval
= 0xFF;
419 /* check for NVRAM access */
420 if ((NVRAM
->model
== 2 && addr
< 0x078f) ||
421 (NVRAM
->model
== 8 && addr
< 0x1ff8) ||
422 (NVRAM
->model
== 59 && addr
< 0x1ff0)) {
451 /* A read resets the watchdog */
452 set_up_watchdog(NVRAM
, NVRAM
->buffer
[0x1FF7]);
461 get_time(NVRAM
, &tm
);
462 retval
= (NVRAM
->buffer
[addr
] & 0x80) | to_bcd(tm
.tm_sec
);
467 get_time(NVRAM
, &tm
);
468 retval
= to_bcd(tm
.tm_min
);
473 get_time(NVRAM
, &tm
);
474 retval
= to_bcd(tm
.tm_hour
);
478 /* day of the week / century */
479 get_time(NVRAM
, &tm
);
480 retval
= NVRAM
->buffer
[addr
] | tm
.tm_wday
;
485 get_time(NVRAM
, &tm
);
486 retval
= to_bcd(tm
.tm_mday
);
491 get_time(NVRAM
, &tm
);
492 retval
= to_bcd(tm
.tm_mon
+ 1);
497 get_time(NVRAM
, &tm
);
498 if (NVRAM
->model
== 8) {
499 retval
= to_bcd(tm
.tm_year
- 68); // Base year is 1968
501 retval
= to_bcd(tm
.tm_year
);
505 /* Check lock registers state */
506 if (addr
>= 0x20 && addr
<= 0x2F && (NVRAM
->lock
& 1))
508 if (addr
>= 0x30 && addr
<= 0x3F && (NVRAM
->lock
& 2))
511 if (addr
< NVRAM
->size
) {
512 retval
= NVRAM
->buffer
[addr
];
516 if (addr
> 0x1FF9 && addr
< 0x2000)
517 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__
, addr
, retval
);
522 void m48t59_toggle_lock (void *opaque
, int lock
)
524 M48t59State
*NVRAM
= opaque
;
526 NVRAM
->lock
^= 1 << lock
;
529 /* IO access to NVRAM */
530 static void NVRAM_writeb(void *opaque
, hwaddr addr
, uint64_t val
,
533 M48t59State
*NVRAM
= opaque
;
535 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__
, addr
, val
);
538 NVRAM
->addr
&= ~0x00FF;
542 NVRAM
->addr
&= ~0xFF00;
543 NVRAM
->addr
|= val
<< 8;
546 m48t59_write(NVRAM
, NVRAM
->addr
, val
);
547 NVRAM
->addr
= 0x0000;
554 static uint64_t NVRAM_readb(void *opaque
, hwaddr addr
, unsigned size
)
556 M48t59State
*NVRAM
= opaque
;
561 retval
= m48t59_read(NVRAM
, NVRAM
->addr
);
567 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__
, addr
, retval
);
572 static void nvram_writeb (void *opaque
, hwaddr addr
, uint32_t value
)
574 M48t59State
*NVRAM
= opaque
;
576 m48t59_write(NVRAM
, addr
, value
& 0xff);
579 static void nvram_writew (void *opaque
, hwaddr addr
, uint32_t value
)
581 M48t59State
*NVRAM
= opaque
;
583 m48t59_write(NVRAM
, addr
, (value
>> 8) & 0xff);
584 m48t59_write(NVRAM
, addr
+ 1, value
& 0xff);
587 static void nvram_writel (void *opaque
, hwaddr addr
, uint32_t value
)
589 M48t59State
*NVRAM
= opaque
;
591 m48t59_write(NVRAM
, addr
, (value
>> 24) & 0xff);
592 m48t59_write(NVRAM
, addr
+ 1, (value
>> 16) & 0xff);
593 m48t59_write(NVRAM
, addr
+ 2, (value
>> 8) & 0xff);
594 m48t59_write(NVRAM
, addr
+ 3, value
& 0xff);
597 static uint32_t nvram_readb (void *opaque
, hwaddr addr
)
599 M48t59State
*NVRAM
= opaque
;
602 retval
= m48t59_read(NVRAM
, addr
);
606 static uint32_t nvram_readw (void *opaque
, hwaddr addr
)
608 M48t59State
*NVRAM
= opaque
;
611 retval
= m48t59_read(NVRAM
, addr
) << 8;
612 retval
|= m48t59_read(NVRAM
, addr
+ 1);
616 static uint32_t nvram_readl (void *opaque
, hwaddr addr
)
618 M48t59State
*NVRAM
= opaque
;
621 retval
= m48t59_read(NVRAM
, addr
) << 24;
622 retval
|= m48t59_read(NVRAM
, addr
+ 1) << 16;
623 retval
|= m48t59_read(NVRAM
, addr
+ 2) << 8;
624 retval
|= m48t59_read(NVRAM
, addr
+ 3);
628 static const MemoryRegionOps nvram_ops
= {
630 .read
= { nvram_readb
, nvram_readw
, nvram_readl
, },
631 .write
= { nvram_writeb
, nvram_writew
, nvram_writel
, },
633 .endianness
= DEVICE_NATIVE_ENDIAN
,
636 static const VMStateDescription vmstate_m48t59
= {
639 .minimum_version_id
= 1,
640 .fields
= (VMStateField
[]) {
641 VMSTATE_UINT8(lock
, M48t59State
),
642 VMSTATE_UINT16(addr
, M48t59State
),
643 VMSTATE_VBUFFER_UINT32(buffer
, M48t59State
, 0, NULL
, 0, size
),
644 VMSTATE_END_OF_LIST()
648 static void m48t59_reset_common(M48t59State
*NVRAM
)
652 if (NVRAM
->alrm_timer
!= NULL
)
653 timer_del(NVRAM
->alrm_timer
);
655 if (NVRAM
->wd_timer
!= NULL
)
656 timer_del(NVRAM
->wd_timer
);
659 static void m48t59_reset_isa(DeviceState
*d
)
661 M48txxISAState
*isa
= M48TXX_ISA(d
);
662 M48t59State
*NVRAM
= &isa
->state
;
664 m48t59_reset_common(NVRAM
);
667 static void m48t59_reset_sysbus(DeviceState
*d
)
669 M48txxSysBusState
*sys
= M48TXX_SYS_BUS(d
);
670 M48t59State
*NVRAM
= &sys
->state
;
672 m48t59_reset_common(NVRAM
);
675 static const MemoryRegionOps m48t59_io_ops
= {
677 .write
= NVRAM_writeb
,
679 .min_access_size
= 1,
680 .max_access_size
= 1,
682 .endianness
= DEVICE_LITTLE_ENDIAN
,
685 /* Initialisation routine */
686 M48t59State
*m48t59_init(qemu_irq IRQ
, hwaddr mem_base
,
687 uint32_t io_base
, uint16_t size
, int model
)
691 M48txxSysBusState
*d
;
695 for (i
= 0; i
< ARRAY_SIZE(m48txx_info
); i
++) {
696 if (!m48txx_info
[i
].sysbus_name
||
697 m48txx_info
[i
].size
!= size
||
698 m48txx_info
[i
].model
!= model
) {
702 dev
= qdev_create(NULL
, m48txx_info
[i
].sysbus_name
);
703 qdev_init_nofail(dev
);
704 s
= SYS_BUS_DEVICE(dev
);
705 d
= M48TXX_SYS_BUS(s
);
707 sysbus_connect_irq(s
, 0, IRQ
);
709 memory_region_add_subregion(get_system_io(), io_base
,
710 sysbus_mmio_get_region(s
, 1));
713 sysbus_mmio_map(s
, 0, mem_base
);
723 M48t59State
*m48t59_init_isa(ISABus
*bus
, uint32_t io_base
, uint16_t size
,
729 for (i
= 0; i
< ARRAY_SIZE(m48txx_info
); i
++) {
730 if (!m48txx_info
[i
].isa_name
||
731 m48txx_info
[i
].size
!= size
||
732 m48txx_info
[i
].model
!= model
) {
736 dev
= DEVICE(isa_create(bus
, m48txx_info
[i
].isa_name
));
737 qdev_prop_set_uint32(dev
, "iobase", io_base
);
738 qdev_init_nofail(dev
);
739 return &M48TXX_ISA(dev
)->state
;
746 static void m48t59_realize_common(M48t59State
*s
, Error
**errp
)
748 s
->buffer
= g_malloc0(s
->size
);
749 if (s
->model
== 59) {
750 s
->alrm_timer
= timer_new_ns(rtc_clock
, &alarm_cb
, s
);
751 s
->wd_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &watchdog_cb
, s
);
753 qemu_get_timedate(&s
->alarm
, 0);
755 vmstate_register(NULL
, -1, &vmstate_m48t59
, s
);
758 static void m48t59_isa_realize(DeviceState
*dev
, Error
**errp
)
760 M48txxISADeviceClass
*u
= M48TXX_ISA_GET_CLASS(dev
);
761 ISADevice
*isadev
= ISA_DEVICE(dev
);
762 M48txxISAState
*d
= M48TXX_ISA(dev
);
763 M48t59State
*s
= &d
->state
;
765 s
->model
= u
->info
.model
;
766 s
->size
= u
->info
.size
;
767 isa_init_irq(isadev
, &s
->IRQ
, 8);
768 m48t59_realize_common(s
, errp
);
769 memory_region_init_io(&d
->io
, OBJECT(dev
), &m48t59_io_ops
, s
, "m48t59", 4);
770 if (d
->io_base
!= 0) {
771 isa_register_ioport(isadev
, &d
->io
, d
->io_base
);
775 static int m48t59_init1(SysBusDevice
*dev
)
777 M48txxSysBusDeviceClass
*u
= M48TXX_SYS_BUS_GET_CLASS(dev
);
778 M48txxSysBusState
*d
= M48TXX_SYS_BUS(dev
);
779 Object
*o
= OBJECT(dev
);
780 M48t59State
*s
= &d
->state
;
783 s
->model
= u
->info
.model
;
784 s
->size
= u
->info
.size
;
785 sysbus_init_irq(dev
, &s
->IRQ
);
787 memory_region_init_io(&s
->iomem
, o
, &nvram_ops
, s
, "m48t59.nvram",
789 memory_region_init_io(&d
->io
, o
, &m48t59_io_ops
, s
, "m48t59", 4);
790 sysbus_init_mmio(dev
, &s
->iomem
);
791 sysbus_init_mmio(dev
, &d
->io
);
792 m48t59_realize_common(s
, &err
);
801 static Property m48t59_isa_properties
[] = {
802 DEFINE_PROP_UINT32("iobase", M48txxISAState
, io_base
, 0x74),
803 DEFINE_PROP_END_OF_LIST(),
806 static void m48txx_isa_class_init(ObjectClass
*klass
, void *data
)
808 DeviceClass
*dc
= DEVICE_CLASS(klass
);
810 dc
->realize
= m48t59_isa_realize
;
811 dc
->reset
= m48t59_reset_isa
;
812 dc
->props
= m48t59_isa_properties
;
815 static void m48txx_isa_concrete_class_init(ObjectClass
*klass
, void *data
)
817 M48txxISADeviceClass
*u
= M48TXX_ISA_CLASS(klass
);
818 M48txxInfo
*info
= data
;
823 static void m48txx_sysbus_class_init(ObjectClass
*klass
, void *data
)
825 DeviceClass
*dc
= DEVICE_CLASS(klass
);
826 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
828 k
->init
= m48t59_init1
;
829 dc
->reset
= m48t59_reset_sysbus
;
832 static void m48txx_sysbus_concrete_class_init(ObjectClass
*klass
, void *data
)
834 M48txxSysBusDeviceClass
*u
= M48TXX_SYS_BUS_CLASS(klass
);
835 M48txxInfo
*info
= data
;
840 static const TypeInfo m48txx_sysbus_type_info
= {
841 .name
= TYPE_M48TXX_SYS_BUS
,
842 .parent
= TYPE_SYS_BUS_DEVICE
,
843 .instance_size
= sizeof(M48txxSysBusState
),
845 .class_init
= m48txx_sysbus_class_init
,
848 static const TypeInfo m48txx_isa_type_info
= {
849 .name
= TYPE_M48TXX_ISA
,
850 .parent
= TYPE_ISA_DEVICE
,
851 .instance_size
= sizeof(M48txxISAState
),
853 .class_init
= m48txx_isa_class_init
,
856 static void m48t59_register_types(void)
858 TypeInfo sysbus_type_info
= {
859 .parent
= TYPE_M48TXX_SYS_BUS
,
860 .class_size
= sizeof(M48txxSysBusDeviceClass
),
861 .class_init
= m48txx_sysbus_concrete_class_init
,
863 TypeInfo isa_type_info
= {
864 .parent
= TYPE_M48TXX_ISA
,
865 .class_size
= sizeof(M48txxISADeviceClass
),
866 .class_init
= m48txx_isa_concrete_class_init
,
870 type_register_static(&m48txx_sysbus_type_info
);
871 type_register_static(&m48txx_isa_type_info
);
873 for (i
= 0; i
< ARRAY_SIZE(m48txx_info
); i
++) {
874 if (m48txx_info
[i
].sysbus_name
) {
875 sysbus_type_info
.name
= m48txx_info
[i
].sysbus_name
;
876 sysbus_type_info
.class_data
= &m48txx_info
[i
];
877 type_register(&sysbus_type_info
);
880 if (m48txx_info
[i
].isa_name
) {
881 isa_type_info
.name
= m48txx_info
[i
].isa_name
;
882 isa_type_info
.class_data
= &m48txx_info
[i
];
883 type_register(&isa_type_info
);
888 type_init(m48t59_register_types
)