ui/egl-helpers: Augment parameter list of egl_texture_blend() to convey scales of...
[qemu/ar7.git] / exec.c
blob03dd673d36d8ab4fcee56471abfbca81cf289c3e
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
23 #include "cpu.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
26 #include "tcg.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
32 #endif
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
39 #include "qemu.h"
40 #else /* !CONFIG_USER_ONLY */
41 #include "hw/hw.h"
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
53 #endif
55 #endif
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
63 #include "exec/log.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
68 #ifndef _WIN32
69 #include "qemu/mmap-alloc.h"
70 #endif
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
82 static MemoryRegion *system_memory;
83 static MemoryRegion *system_io;
85 AddressSpace address_space_io;
86 AddressSpace address_space_memory;
88 MemoryRegion io_mem_rom, io_mem_notdirty;
89 static MemoryRegion io_mem_unassigned;
90 #endif
92 #ifdef TARGET_PAGE_BITS_VARY
93 int target_page_bits;
94 bool target_page_bits_decided;
95 #endif
97 CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
99 /* current CPU in the current thread. It is only valid inside
100 cpu_exec() */
101 __thread CPUState *current_cpu;
102 /* 0 = Do not count executed instructions.
103 1 = Precise instruction counting.
104 2 = Adaptive rate instruction counting. */
105 int use_icount;
107 uintptr_t qemu_host_page_size;
108 intptr_t qemu_host_page_mask;
110 bool set_preferred_target_page_bits(int bits)
112 /* The target page size is the lowest common denominator for all
113 * the CPUs in the system, so we can only make it smaller, never
114 * larger. And we can't make it smaller once we've committed to
115 * a particular size.
117 #ifdef TARGET_PAGE_BITS_VARY
118 assert(bits >= TARGET_PAGE_BITS_MIN);
119 if (target_page_bits == 0 || target_page_bits > bits) {
120 if (target_page_bits_decided) {
121 return false;
123 target_page_bits = bits;
125 #endif
126 return true;
129 #if !defined(CONFIG_USER_ONLY)
131 static void finalize_target_page_bits(void)
133 #ifdef TARGET_PAGE_BITS_VARY
134 if (target_page_bits == 0) {
135 target_page_bits = TARGET_PAGE_BITS_MIN;
137 target_page_bits_decided = true;
138 #endif
141 typedef struct PhysPageEntry PhysPageEntry;
143 struct PhysPageEntry {
144 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
145 uint32_t skip : 6;
146 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
147 uint32_t ptr : 26;
150 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
152 /* Size of the L2 (and L3, etc) page tables. */
153 #define ADDR_SPACE_BITS 64
155 #define P_L2_BITS 9
156 #define P_L2_SIZE (1 << P_L2_BITS)
158 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
160 typedef PhysPageEntry Node[P_L2_SIZE];
162 typedef struct PhysPageMap {
163 struct rcu_head rcu;
165 unsigned sections_nb;
166 unsigned sections_nb_alloc;
167 unsigned nodes_nb;
168 unsigned nodes_nb_alloc;
169 Node *nodes;
170 MemoryRegionSection *sections;
171 } PhysPageMap;
173 struct AddressSpaceDispatch {
174 MemoryRegionSection *mru_section;
175 /* This is a multi-level map on the physical address space.
176 * The bottom level has pointers to MemoryRegionSections.
178 PhysPageEntry phys_map;
179 PhysPageMap map;
182 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
183 typedef struct subpage_t {
184 MemoryRegion iomem;
185 FlatView *fv;
186 hwaddr base;
187 uint16_t sub_section[];
188 } subpage_t;
190 #define PHYS_SECTION_UNASSIGNED 0
191 #define PHYS_SECTION_NOTDIRTY 1
192 #define PHYS_SECTION_ROM 2
193 #define PHYS_SECTION_WATCH 3
195 static void io_mem_init(void);
196 static void memory_map_init(void);
197 static void tcg_commit(MemoryListener *listener);
199 static MemoryRegion io_mem_watch;
202 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
203 * @cpu: the CPU whose AddressSpace this is
204 * @as: the AddressSpace itself
205 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
206 * @tcg_as_listener: listener for tracking changes to the AddressSpace
208 struct CPUAddressSpace {
209 CPUState *cpu;
210 AddressSpace *as;
211 struct AddressSpaceDispatch *memory_dispatch;
212 MemoryListener tcg_as_listener;
215 struct DirtyBitmapSnapshot {
216 ram_addr_t start;
217 ram_addr_t end;
218 unsigned long dirty[];
221 #endif
223 #if !defined(CONFIG_USER_ONLY)
225 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
227 static unsigned alloc_hint = 16;
228 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
229 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
230 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
231 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
232 alloc_hint = map->nodes_nb_alloc;
236 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
238 unsigned i;
239 uint32_t ret;
240 PhysPageEntry e;
241 PhysPageEntry *p;
243 ret = map->nodes_nb++;
244 p = map->nodes[ret];
245 assert(ret != PHYS_MAP_NODE_NIL);
246 assert(ret != map->nodes_nb_alloc);
248 e.skip = leaf ? 0 : 1;
249 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
250 for (i = 0; i < P_L2_SIZE; ++i) {
251 memcpy(&p[i], &e, sizeof(e));
253 return ret;
256 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
257 hwaddr *index, hwaddr *nb, uint16_t leaf,
258 int level)
260 PhysPageEntry *p;
261 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
263 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
264 lp->ptr = phys_map_node_alloc(map, level == 0);
266 p = map->nodes[lp->ptr];
267 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
269 while (*nb && lp < &p[P_L2_SIZE]) {
270 if ((*index & (step - 1)) == 0 && *nb >= step) {
271 lp->skip = 0;
272 lp->ptr = leaf;
273 *index += step;
274 *nb -= step;
275 } else {
276 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
278 ++lp;
282 static void phys_page_set(AddressSpaceDispatch *d,
283 hwaddr index, hwaddr nb,
284 uint16_t leaf)
286 /* Wildly overreserve - it doesn't matter much. */
287 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
289 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
292 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
293 * and update our entry so we can skip it and go directly to the destination.
295 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
297 unsigned valid_ptr = P_L2_SIZE;
298 int valid = 0;
299 PhysPageEntry *p;
300 int i;
302 if (lp->ptr == PHYS_MAP_NODE_NIL) {
303 return;
306 p = nodes[lp->ptr];
307 for (i = 0; i < P_L2_SIZE; i++) {
308 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
309 continue;
312 valid_ptr = i;
313 valid++;
314 if (p[i].skip) {
315 phys_page_compact(&p[i], nodes);
319 /* We can only compress if there's only one child. */
320 if (valid != 1) {
321 return;
324 assert(valid_ptr < P_L2_SIZE);
326 /* Don't compress if it won't fit in the # of bits we have. */
327 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
328 return;
331 lp->ptr = p[valid_ptr].ptr;
332 if (!p[valid_ptr].skip) {
333 /* If our only child is a leaf, make this a leaf. */
334 /* By design, we should have made this node a leaf to begin with so we
335 * should never reach here.
336 * But since it's so simple to handle this, let's do it just in case we
337 * change this rule.
339 lp->skip = 0;
340 } else {
341 lp->skip += p[valid_ptr].skip;
345 void address_space_dispatch_compact(AddressSpaceDispatch *d)
347 if (d->phys_map.skip) {
348 phys_page_compact(&d->phys_map, d->map.nodes);
352 static inline bool section_covers_addr(const MemoryRegionSection *section,
353 hwaddr addr)
355 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
356 * the section must cover the entire address space.
358 return int128_gethi(section->size) ||
359 range_covers_byte(section->offset_within_address_space,
360 int128_getlo(section->size), addr);
363 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
365 PhysPageEntry lp = d->phys_map, *p;
366 Node *nodes = d->map.nodes;
367 MemoryRegionSection *sections = d->map.sections;
368 hwaddr index = addr >> TARGET_PAGE_BITS;
369 int i;
371 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
372 if (lp.ptr == PHYS_MAP_NODE_NIL) {
373 return &sections[PHYS_SECTION_UNASSIGNED];
375 p = nodes[lp.ptr];
376 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
379 if (section_covers_addr(&sections[lp.ptr], addr)) {
380 return &sections[lp.ptr];
381 } else {
382 return &sections[PHYS_SECTION_UNASSIGNED];
386 /* Called from RCU critical section */
387 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
388 hwaddr addr,
389 bool resolve_subpage)
391 MemoryRegionSection *section = atomic_read(&d->mru_section);
392 subpage_t *subpage;
394 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
395 !section_covers_addr(section, addr)) {
396 section = phys_page_find(d, addr);
397 atomic_set(&d->mru_section, section);
399 if (resolve_subpage && section->mr->subpage) {
400 subpage = container_of(section->mr, subpage_t, iomem);
401 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
403 return section;
406 /* Called from RCU critical section */
407 static MemoryRegionSection *
408 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
409 hwaddr *plen, bool resolve_subpage)
411 MemoryRegionSection *section;
412 MemoryRegion *mr;
413 Int128 diff;
415 section = address_space_lookup_region(d, addr, resolve_subpage);
416 /* Compute offset within MemoryRegionSection */
417 addr -= section->offset_within_address_space;
419 /* Compute offset within MemoryRegion */
420 *xlat = addr + section->offset_within_region;
422 mr = section->mr;
424 /* MMIO registers can be expected to perform full-width accesses based only
425 * on their address, without considering adjacent registers that could
426 * decode to completely different MemoryRegions. When such registers
427 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
428 * regions overlap wildly. For this reason we cannot clamp the accesses
429 * here.
431 * If the length is small (as is the case for address_space_ldl/stl),
432 * everything works fine. If the incoming length is large, however,
433 * the caller really has to do the clamping through memory_access_size.
435 if (memory_region_is_ram(mr)) {
436 diff = int128_sub(section->size, int128_make64(addr));
437 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
439 return section;
443 * address_space_translate_iommu - translate an address through an IOMMU
444 * memory region and then through the target address space.
446 * @iommu_mr: the IOMMU memory region that we start the translation from
447 * @addr: the address to be translated through the MMU
448 * @xlat: the translated address offset within the destination memory region.
449 * It cannot be %NULL.
450 * @plen_out: valid read/write length of the translated address. It
451 * cannot be %NULL.
452 * @page_mask_out: page mask for the translated address. This
453 * should only be meaningful for IOMMU translated
454 * addresses, since there may be huge pages that this bit
455 * would tell. It can be %NULL if we don't care about it.
456 * @is_write: whether the translation operation is for write
457 * @is_mmio: whether this can be MMIO, set true if it can
458 * @target_as: the address space targeted by the IOMMU
459 * @attrs: transaction attributes
461 * This function is called from RCU critical section. It is the common
462 * part of flatview_do_translate and address_space_translate_cached.
464 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
465 hwaddr *xlat,
466 hwaddr *plen_out,
467 hwaddr *page_mask_out,
468 bool is_write,
469 bool is_mmio,
470 AddressSpace **target_as,
471 MemTxAttrs attrs)
473 MemoryRegionSection *section;
474 hwaddr page_mask = (hwaddr)-1;
476 do {
477 hwaddr addr = *xlat;
478 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
479 int iommu_idx = 0;
480 IOMMUTLBEntry iotlb;
482 if (imrc->attrs_to_index) {
483 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
486 iotlb = imrc->translate(iommu_mr, addr, is_write ?
487 IOMMU_WO : IOMMU_RO, iommu_idx);
489 if (!(iotlb.perm & (1 << is_write))) {
490 goto unassigned;
493 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
494 | (addr & iotlb.addr_mask));
495 page_mask &= iotlb.addr_mask;
496 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
497 *target_as = iotlb.target_as;
499 section = address_space_translate_internal(
500 address_space_to_dispatch(iotlb.target_as), addr, xlat,
501 plen_out, is_mmio);
503 iommu_mr = memory_region_get_iommu(section->mr);
504 } while (unlikely(iommu_mr));
506 if (page_mask_out) {
507 *page_mask_out = page_mask;
509 return *section;
511 unassigned:
512 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
516 * flatview_do_translate - translate an address in FlatView
518 * @fv: the flat view that we want to translate on
519 * @addr: the address to be translated in above address space
520 * @xlat: the translated address offset within memory region. It
521 * cannot be @NULL.
522 * @plen_out: valid read/write length of the translated address. It
523 * can be @NULL when we don't care about it.
524 * @page_mask_out: page mask for the translated address. This
525 * should only be meaningful for IOMMU translated
526 * addresses, since there may be huge pages that this bit
527 * would tell. It can be @NULL if we don't care about it.
528 * @is_write: whether the translation operation is for write
529 * @is_mmio: whether this can be MMIO, set true if it can
530 * @target_as: the address space targeted by the IOMMU
531 * @attrs: memory transaction attributes
533 * This function is called from RCU critical section
535 static MemoryRegionSection flatview_do_translate(FlatView *fv,
536 hwaddr addr,
537 hwaddr *xlat,
538 hwaddr *plen_out,
539 hwaddr *page_mask_out,
540 bool is_write,
541 bool is_mmio,
542 AddressSpace **target_as,
543 MemTxAttrs attrs)
545 MemoryRegionSection *section;
546 IOMMUMemoryRegion *iommu_mr;
547 hwaddr plen = (hwaddr)(-1);
549 if (!plen_out) {
550 plen_out = &plen;
553 section = address_space_translate_internal(
554 flatview_to_dispatch(fv), addr, xlat,
555 plen_out, is_mmio);
557 iommu_mr = memory_region_get_iommu(section->mr);
558 if (unlikely(iommu_mr)) {
559 return address_space_translate_iommu(iommu_mr, xlat,
560 plen_out, page_mask_out,
561 is_write, is_mmio,
562 target_as, attrs);
564 if (page_mask_out) {
565 /* Not behind an IOMMU, use default page size. */
566 *page_mask_out = ~TARGET_PAGE_MASK;
569 return *section;
572 /* Called from RCU critical section */
573 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
574 bool is_write, MemTxAttrs attrs)
576 MemoryRegionSection section;
577 hwaddr xlat, page_mask;
580 * This can never be MMIO, and we don't really care about plen,
581 * but page mask.
583 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
584 NULL, &page_mask, is_write, false, &as,
585 attrs);
587 /* Illegal translation */
588 if (section.mr == &io_mem_unassigned) {
589 goto iotlb_fail;
592 /* Convert memory region offset into address space offset */
593 xlat += section.offset_within_address_space -
594 section.offset_within_region;
596 return (IOMMUTLBEntry) {
597 .target_as = as,
598 .iova = addr & ~page_mask,
599 .translated_addr = xlat & ~page_mask,
600 .addr_mask = page_mask,
601 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
602 .perm = IOMMU_RW,
605 iotlb_fail:
606 return (IOMMUTLBEntry) {0};
609 /* Called from RCU critical section */
610 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
611 hwaddr *plen, bool is_write,
612 MemTxAttrs attrs)
614 MemoryRegion *mr;
615 MemoryRegionSection section;
616 AddressSpace *as = NULL;
618 /* This can be MMIO, so setup MMIO bit. */
619 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
620 is_write, true, &as, attrs);
621 mr = section.mr;
623 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
624 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
625 *plen = MIN(page, *plen);
628 return mr;
631 typedef struct TCGIOMMUNotifier {
632 IOMMUNotifier n;
633 MemoryRegion *mr;
634 CPUState *cpu;
635 int iommu_idx;
636 bool active;
637 } TCGIOMMUNotifier;
639 static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
641 TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n);
643 if (!notifier->active) {
644 return;
646 tlb_flush(notifier->cpu);
647 notifier->active = false;
648 /* We leave the notifier struct on the list to avoid reallocating it later.
649 * Generally the number of IOMMUs a CPU deals with will be small.
650 * In any case we can't unregister the iommu notifier from a notify
651 * callback.
655 static void tcg_register_iommu_notifier(CPUState *cpu,
656 IOMMUMemoryRegion *iommu_mr,
657 int iommu_idx)
659 /* Make sure this CPU has an IOMMU notifier registered for this
660 * IOMMU/IOMMU index combination, so that we can flush its TLB
661 * when the IOMMU tells us the mappings we've cached have changed.
663 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
664 TCGIOMMUNotifier *notifier;
665 int i;
667 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
668 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
669 if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) {
670 break;
673 if (i == cpu->iommu_notifiers->len) {
674 /* Not found, add a new entry at the end of the array */
675 cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1);
676 notifier = g_new0(TCGIOMMUNotifier, 1);
677 g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier;
679 notifier->mr = mr;
680 notifier->iommu_idx = iommu_idx;
681 notifier->cpu = cpu;
682 /* Rather than trying to register interest in the specific part
683 * of the iommu's address space that we've accessed and then
684 * expand it later as subsequent accesses touch more of it, we
685 * just register interest in the whole thing, on the assumption
686 * that iommu reconfiguration will be rare.
688 iommu_notifier_init(&notifier->n,
689 tcg_iommu_unmap_notify,
690 IOMMU_NOTIFIER_UNMAP,
692 HWADDR_MAX,
693 iommu_idx);
694 memory_region_register_iommu_notifier(notifier->mr, &notifier->n);
697 if (!notifier->active) {
698 notifier->active = true;
702 static void tcg_iommu_free_notifier_list(CPUState *cpu)
704 /* Destroy the CPU's notifier list */
705 int i;
706 TCGIOMMUNotifier *notifier;
708 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
709 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
710 memory_region_unregister_iommu_notifier(notifier->mr, &notifier->n);
711 g_free(notifier);
713 g_array_free(cpu->iommu_notifiers, true);
716 /* Called from RCU critical section */
717 MemoryRegionSection *
718 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
719 hwaddr *xlat, hwaddr *plen,
720 MemTxAttrs attrs, int *prot)
722 MemoryRegionSection *section;
723 IOMMUMemoryRegion *iommu_mr;
724 IOMMUMemoryRegionClass *imrc;
725 IOMMUTLBEntry iotlb;
726 int iommu_idx;
727 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
729 for (;;) {
730 section = address_space_translate_internal(d, addr, &addr, plen, false);
732 iommu_mr = memory_region_get_iommu(section->mr);
733 if (!iommu_mr) {
734 break;
737 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
739 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
740 tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);
741 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
742 * doesn't short-cut its translation table walk.
744 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);
745 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
746 | (addr & iotlb.addr_mask));
747 /* Update the caller's prot bits to remove permissions the IOMMU
748 * is giving us a failure response for. If we get down to no
749 * permissions left at all we can give up now.
751 if (!(iotlb.perm & IOMMU_RO)) {
752 *prot &= ~(PAGE_READ | PAGE_EXEC);
754 if (!(iotlb.perm & IOMMU_WO)) {
755 *prot &= ~PAGE_WRITE;
758 if (!*prot) {
759 goto translate_fail;
762 d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));
765 assert(!memory_region_is_iommu(section->mr));
766 *xlat = addr;
767 return section;
769 translate_fail:
770 return &d->map.sections[PHYS_SECTION_UNASSIGNED];
772 #endif
774 #if !defined(CONFIG_USER_ONLY)
776 static int cpu_common_post_load(void *opaque, int version_id)
778 CPUState *cpu = opaque;
780 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
781 version_id is increased. */
782 cpu->interrupt_request &= ~0x01;
783 tlb_flush(cpu);
785 /* loadvm has just updated the content of RAM, bypassing the
786 * usual mechanisms that ensure we flush TBs for writes to
787 * memory we've translated code from. So we must flush all TBs,
788 * which will now be stale.
790 tb_flush(cpu);
792 return 0;
795 static int cpu_common_pre_load(void *opaque)
797 CPUState *cpu = opaque;
799 cpu->exception_index = -1;
801 return 0;
804 static bool cpu_common_exception_index_needed(void *opaque)
806 CPUState *cpu = opaque;
808 return tcg_enabled() && cpu->exception_index != -1;
811 static const VMStateDescription vmstate_cpu_common_exception_index = {
812 .name = "cpu_common/exception_index",
813 .version_id = 1,
814 .minimum_version_id = 1,
815 .needed = cpu_common_exception_index_needed,
816 .fields = (VMStateField[]) {
817 VMSTATE_INT32(exception_index, CPUState),
818 VMSTATE_END_OF_LIST()
822 static bool cpu_common_crash_occurred_needed(void *opaque)
824 CPUState *cpu = opaque;
826 return cpu->crash_occurred;
829 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
830 .name = "cpu_common/crash_occurred",
831 .version_id = 1,
832 .minimum_version_id = 1,
833 .needed = cpu_common_crash_occurred_needed,
834 .fields = (VMStateField[]) {
835 VMSTATE_BOOL(crash_occurred, CPUState),
836 VMSTATE_END_OF_LIST()
840 const VMStateDescription vmstate_cpu_common = {
841 .name = "cpu_common",
842 .version_id = 1,
843 .minimum_version_id = 1,
844 .pre_load = cpu_common_pre_load,
845 .post_load = cpu_common_post_load,
846 .fields = (VMStateField[]) {
847 VMSTATE_UINT32(halted, CPUState),
848 VMSTATE_UINT32(interrupt_request, CPUState),
849 VMSTATE_END_OF_LIST()
851 .subsections = (const VMStateDescription*[]) {
852 &vmstate_cpu_common_exception_index,
853 &vmstate_cpu_common_crash_occurred,
854 NULL
858 #endif
860 CPUState *qemu_get_cpu(int index)
862 CPUState *cpu;
864 CPU_FOREACH(cpu) {
865 if (cpu->cpu_index == index) {
866 return cpu;
870 return NULL;
873 #if !defined(CONFIG_USER_ONLY)
874 void cpu_address_space_init(CPUState *cpu, int asidx,
875 const char *prefix, MemoryRegion *mr)
877 CPUAddressSpace *newas;
878 AddressSpace *as = g_new0(AddressSpace, 1);
879 char *as_name;
881 assert(mr);
882 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
883 address_space_init(as, mr, as_name);
884 g_free(as_name);
886 /* Target code should have set num_ases before calling us */
887 assert(asidx < cpu->num_ases);
889 if (asidx == 0) {
890 /* address space 0 gets the convenience alias */
891 cpu->as = as;
894 /* KVM cannot currently support multiple address spaces. */
895 assert(asidx == 0 || !kvm_enabled());
897 if (!cpu->cpu_ases) {
898 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
901 newas = &cpu->cpu_ases[asidx];
902 newas->cpu = cpu;
903 newas->as = as;
904 if (tcg_enabled()) {
905 newas->tcg_as_listener.commit = tcg_commit;
906 memory_listener_register(&newas->tcg_as_listener, as);
910 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
912 /* Return the AddressSpace corresponding to the specified index */
913 return cpu->cpu_ases[asidx].as;
915 #endif
917 void cpu_exec_unrealizefn(CPUState *cpu)
919 CPUClass *cc = CPU_GET_CLASS(cpu);
921 cpu_list_remove(cpu);
923 if (cc->vmsd != NULL) {
924 vmstate_unregister(NULL, cc->vmsd, cpu);
926 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
927 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
929 #ifndef CONFIG_USER_ONLY
930 tcg_iommu_free_notifier_list(cpu);
931 #endif
934 Property cpu_common_props[] = {
935 #ifndef CONFIG_USER_ONLY
936 /* Create a memory property for softmmu CPU object,
937 * so users can wire up its memory. (This can't go in qom/cpu.c
938 * because that file is compiled only once for both user-mode
939 * and system builds.) The default if no link is set up is to use
940 * the system address space.
942 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
943 MemoryRegion *),
944 #endif
945 DEFINE_PROP_END_OF_LIST(),
948 void cpu_exec_initfn(CPUState *cpu)
950 cpu->as = NULL;
951 cpu->num_ases = 0;
953 #ifndef CONFIG_USER_ONLY
954 cpu->thread_id = qemu_get_thread_id();
955 cpu->memory = system_memory;
956 object_ref(OBJECT(cpu->memory));
957 #endif
960 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
962 CPUClass *cc = CPU_GET_CLASS(cpu);
963 static bool tcg_target_initialized;
965 cpu_list_add(cpu);
967 if (tcg_enabled() && !tcg_target_initialized) {
968 tcg_target_initialized = true;
969 cc->tcg_initialize();
971 tlb_init(cpu);
973 #ifndef CONFIG_USER_ONLY
974 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
975 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
977 if (cc->vmsd != NULL) {
978 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
981 cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
982 #endif
985 const char *parse_cpu_model(const char *cpu_model)
987 ObjectClass *oc;
988 CPUClass *cc;
989 gchar **model_pieces;
990 const char *cpu_type;
992 model_pieces = g_strsplit(cpu_model, ",", 2);
994 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
995 if (oc == NULL) {
996 error_report("unable to find CPU model '%s'", model_pieces[0]);
997 g_strfreev(model_pieces);
998 exit(EXIT_FAILURE);
1001 cpu_type = object_class_get_name(oc);
1002 cc = CPU_CLASS(oc);
1003 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
1004 g_strfreev(model_pieces);
1005 return cpu_type;
1008 #if defined(CONFIG_USER_ONLY)
1009 void tb_invalidate_phys_addr(target_ulong addr)
1011 mmap_lock();
1012 tb_invalidate_phys_page_range(addr, addr + 1, 0);
1013 mmap_unlock();
1016 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1018 tb_invalidate_phys_addr(pc);
1020 #else
1021 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
1023 ram_addr_t ram_addr;
1024 MemoryRegion *mr;
1025 hwaddr l = 1;
1027 if (!tcg_enabled()) {
1028 return;
1031 rcu_read_lock();
1032 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
1033 if (!(memory_region_is_ram(mr)
1034 || memory_region_is_romd(mr))) {
1035 rcu_read_unlock();
1036 return;
1038 ram_addr = memory_region_get_ram_addr(mr) + addr;
1039 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1040 rcu_read_unlock();
1043 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1045 MemTxAttrs attrs;
1046 hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
1047 int asidx = cpu_asidx_from_attrs(cpu, attrs);
1048 if (phys != -1) {
1049 /* Locks grabbed by tb_invalidate_phys_addr */
1050 tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
1051 phys | (pc & ~TARGET_PAGE_MASK), attrs);
1054 #endif
1056 #if defined(CONFIG_USER_ONLY)
1057 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1062 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1063 int flags)
1065 return -ENOSYS;
1068 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1072 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1073 int flags, CPUWatchpoint **watchpoint)
1075 return -ENOSYS;
1077 #else
1078 /* Add a watchpoint. */
1079 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1080 int flags, CPUWatchpoint **watchpoint)
1082 CPUWatchpoint *wp;
1084 /* forbid ranges which are empty or run off the end of the address space */
1085 if (len == 0 || (addr + len - 1) < addr) {
1086 error_report("tried to set invalid watchpoint at %"
1087 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
1088 return -EINVAL;
1090 wp = g_malloc(sizeof(*wp));
1092 wp->vaddr = addr;
1093 wp->len = len;
1094 wp->flags = flags;
1096 /* keep all GDB-injected watchpoints in front */
1097 if (flags & BP_GDB) {
1098 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
1099 } else {
1100 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
1103 tlb_flush_page(cpu, addr);
1105 if (watchpoint)
1106 *watchpoint = wp;
1107 return 0;
1110 /* Remove a specific watchpoint. */
1111 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1112 int flags)
1114 CPUWatchpoint *wp;
1116 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1117 if (addr == wp->vaddr && len == wp->len
1118 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
1119 cpu_watchpoint_remove_by_ref(cpu, wp);
1120 return 0;
1123 return -ENOENT;
1126 /* Remove a specific watchpoint by reference. */
1127 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1129 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
1131 tlb_flush_page(cpu, watchpoint->vaddr);
1133 g_free(watchpoint);
1136 /* Remove all matching watchpoints. */
1137 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1139 CPUWatchpoint *wp, *next;
1141 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
1142 if (wp->flags & mask) {
1143 cpu_watchpoint_remove_by_ref(cpu, wp);
1148 /* Return true if this watchpoint address matches the specified
1149 * access (ie the address range covered by the watchpoint overlaps
1150 * partially or completely with the address range covered by the
1151 * access).
1153 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
1154 vaddr addr,
1155 vaddr len)
1157 /* We know the lengths are non-zero, but a little caution is
1158 * required to avoid errors in the case where the range ends
1159 * exactly at the top of the address space and so addr + len
1160 * wraps round to zero.
1162 vaddr wpend = wp->vaddr + wp->len - 1;
1163 vaddr addrend = addr + len - 1;
1165 return !(addr > wpend || wp->vaddr > addrend);
1168 #endif
1170 /* Add a breakpoint. */
1171 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1172 CPUBreakpoint **breakpoint)
1174 CPUBreakpoint *bp;
1176 bp = g_malloc(sizeof(*bp));
1178 bp->pc = pc;
1179 bp->flags = flags;
1181 /* keep all GDB-injected breakpoints in front */
1182 if (flags & BP_GDB) {
1183 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
1184 } else {
1185 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
1188 breakpoint_invalidate(cpu, pc);
1190 if (breakpoint) {
1191 *breakpoint = bp;
1193 return 0;
1196 /* Remove a specific breakpoint. */
1197 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
1199 CPUBreakpoint *bp;
1201 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1202 if (bp->pc == pc && bp->flags == flags) {
1203 cpu_breakpoint_remove_by_ref(cpu, bp);
1204 return 0;
1207 return -ENOENT;
1210 /* Remove a specific breakpoint by reference. */
1211 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1213 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1215 breakpoint_invalidate(cpu, breakpoint->pc);
1217 g_free(breakpoint);
1220 /* Remove all matching breakpoints. */
1221 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1223 CPUBreakpoint *bp, *next;
1225 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1226 if (bp->flags & mask) {
1227 cpu_breakpoint_remove_by_ref(cpu, bp);
1232 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1233 CPU loop after each instruction */
1234 void cpu_single_step(CPUState *cpu, int enabled)
1236 if (cpu->singlestep_enabled != enabled) {
1237 cpu->singlestep_enabled = enabled;
1238 if (kvm_enabled()) {
1239 kvm_update_guest_debug(cpu, 0);
1240 } else {
1241 /* must flush all the translated code to avoid inconsistencies */
1242 /* XXX: only flush what is necessary */
1243 tb_flush(cpu);
1248 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1250 va_list ap;
1251 va_list ap2;
1253 va_start(ap, fmt);
1254 va_copy(ap2, ap);
1255 fprintf(stderr, "qemu: fatal: ");
1256 vfprintf(stderr, fmt, ap);
1257 fprintf(stderr, "\n");
1258 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1259 if (qemu_log_separate()) {
1260 qemu_log_lock();
1261 qemu_log("qemu: fatal: ");
1262 qemu_log_vprintf(fmt, ap2);
1263 qemu_log("\n");
1264 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1265 qemu_log_flush();
1266 qemu_log_unlock();
1267 qemu_log_close();
1269 va_end(ap2);
1270 va_end(ap);
1271 replay_finish();
1272 #if defined(CONFIG_USER_ONLY)
1274 struct sigaction act;
1275 sigfillset(&act.sa_mask);
1276 act.sa_handler = SIG_DFL;
1277 act.sa_flags = 0;
1278 sigaction(SIGABRT, &act, NULL);
1280 #endif
1281 abort();
1284 #if !defined(CONFIG_USER_ONLY)
1285 /* Called from RCU critical section */
1286 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1288 RAMBlock *block;
1290 block = atomic_rcu_read(&ram_list.mru_block);
1291 if (block && addr - block->offset < block->max_length) {
1292 return block;
1294 RAMBLOCK_FOREACH(block) {
1295 if (addr - block->offset < block->max_length) {
1296 goto found;
1300 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1301 abort();
1303 found:
1304 /* It is safe to write mru_block outside the iothread lock. This
1305 * is what happens:
1307 * mru_block = xxx
1308 * rcu_read_unlock()
1309 * xxx removed from list
1310 * rcu_read_lock()
1311 * read mru_block
1312 * mru_block = NULL;
1313 * call_rcu(reclaim_ramblock, xxx);
1314 * rcu_read_unlock()
1316 * atomic_rcu_set is not needed here. The block was already published
1317 * when it was placed into the list. Here we're just making an extra
1318 * copy of the pointer.
1320 ram_list.mru_block = block;
1321 return block;
1324 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1326 CPUState *cpu;
1327 ram_addr_t start1;
1328 RAMBlock *block;
1329 ram_addr_t end;
1331 assert(tcg_enabled());
1332 end = TARGET_PAGE_ALIGN(start + length);
1333 start &= TARGET_PAGE_MASK;
1335 rcu_read_lock();
1336 block = qemu_get_ram_block(start);
1337 assert(block == qemu_get_ram_block(end - 1));
1338 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1339 CPU_FOREACH(cpu) {
1340 tlb_reset_dirty(cpu, start1, length);
1342 rcu_read_unlock();
1345 /* Note: start and end must be within the same ram block. */
1346 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1347 ram_addr_t length,
1348 unsigned client)
1350 DirtyMemoryBlocks *blocks;
1351 unsigned long end, page;
1352 bool dirty = false;
1354 if (length == 0) {
1355 return false;
1358 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1359 page = start >> TARGET_PAGE_BITS;
1361 rcu_read_lock();
1363 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1365 while (page < end) {
1366 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1367 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1368 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1370 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1371 offset, num);
1372 page += num;
1375 rcu_read_unlock();
1377 if (dirty && tcg_enabled()) {
1378 tlb_reset_dirty_range_all(start, length);
1381 return dirty;
1384 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1385 (ram_addr_t start, ram_addr_t length, unsigned client)
1387 DirtyMemoryBlocks *blocks;
1388 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1389 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1390 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1391 DirtyBitmapSnapshot *snap;
1392 unsigned long page, end, dest;
1394 snap = g_malloc0(sizeof(*snap) +
1395 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1396 snap->start = first;
1397 snap->end = last;
1399 page = first >> TARGET_PAGE_BITS;
1400 end = last >> TARGET_PAGE_BITS;
1401 dest = 0;
1403 rcu_read_lock();
1405 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1407 while (page < end) {
1408 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1409 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1410 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1412 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1413 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1414 offset >>= BITS_PER_LEVEL;
1416 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1417 blocks->blocks[idx] + offset,
1418 num);
1419 page += num;
1420 dest += num >> BITS_PER_LEVEL;
1423 rcu_read_unlock();
1425 if (tcg_enabled()) {
1426 tlb_reset_dirty_range_all(start, length);
1429 return snap;
1432 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1433 ram_addr_t start,
1434 ram_addr_t length)
1436 unsigned long page, end;
1438 assert(start >= snap->start);
1439 assert(start + length <= snap->end);
1441 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1442 page = (start - snap->start) >> TARGET_PAGE_BITS;
1444 while (page < end) {
1445 if (test_bit(page, snap->dirty)) {
1446 return true;
1448 page++;
1450 return false;
1453 /* Called from RCU critical section */
1454 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1455 MemoryRegionSection *section,
1456 target_ulong vaddr,
1457 hwaddr paddr, hwaddr xlat,
1458 int prot,
1459 target_ulong *address)
1461 hwaddr iotlb;
1462 CPUWatchpoint *wp;
1464 if (memory_region_is_ram(section->mr)) {
1465 /* Normal RAM. */
1466 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1467 if (!section->readonly) {
1468 iotlb |= PHYS_SECTION_NOTDIRTY;
1469 } else {
1470 iotlb |= PHYS_SECTION_ROM;
1472 } else {
1473 AddressSpaceDispatch *d;
1475 d = flatview_to_dispatch(section->fv);
1476 iotlb = section - d->map.sections;
1477 iotlb += xlat;
1480 /* Make accesses to pages with watchpoints go via the
1481 watchpoint trap routines. */
1482 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1483 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1484 /* Avoid trapping reads of pages with a write breakpoint. */
1485 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1486 iotlb = PHYS_SECTION_WATCH + paddr;
1487 *address |= TLB_MMIO;
1488 break;
1493 return iotlb;
1495 #endif /* defined(CONFIG_USER_ONLY) */
1497 #if !defined(CONFIG_USER_ONLY)
1499 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1500 uint16_t section);
1501 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1503 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1504 qemu_anon_ram_alloc;
1507 * Set a custom physical guest memory alloator.
1508 * Accelerators with unusual needs may need this. Hopefully, we can
1509 * get rid of it eventually.
1511 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1513 phys_mem_alloc = alloc;
1516 static uint16_t phys_section_add(PhysPageMap *map,
1517 MemoryRegionSection *section)
1519 /* The physical section number is ORed with a page-aligned
1520 * pointer to produce the iotlb entries. Thus it should
1521 * never overflow into the page-aligned value.
1523 assert(map->sections_nb < TARGET_PAGE_SIZE);
1525 if (map->sections_nb == map->sections_nb_alloc) {
1526 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1527 map->sections = g_renew(MemoryRegionSection, map->sections,
1528 map->sections_nb_alloc);
1530 map->sections[map->sections_nb] = *section;
1531 memory_region_ref(section->mr);
1532 return map->sections_nb++;
1535 static void phys_section_destroy(MemoryRegion *mr)
1537 bool have_sub_page = mr->subpage;
1539 memory_region_unref(mr);
1541 if (have_sub_page) {
1542 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1543 object_unref(OBJECT(&subpage->iomem));
1544 g_free(subpage);
1548 static void phys_sections_free(PhysPageMap *map)
1550 while (map->sections_nb > 0) {
1551 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1552 phys_section_destroy(section->mr);
1554 g_free(map->sections);
1555 g_free(map->nodes);
1558 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1560 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1561 subpage_t *subpage;
1562 hwaddr base = section->offset_within_address_space
1563 & TARGET_PAGE_MASK;
1564 MemoryRegionSection *existing = phys_page_find(d, base);
1565 MemoryRegionSection subsection = {
1566 .offset_within_address_space = base,
1567 .size = int128_make64(TARGET_PAGE_SIZE),
1569 hwaddr start, end;
1571 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1573 if (!(existing->mr->subpage)) {
1574 subpage = subpage_init(fv, base);
1575 subsection.fv = fv;
1576 subsection.mr = &subpage->iomem;
1577 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1578 phys_section_add(&d->map, &subsection));
1579 } else {
1580 subpage = container_of(existing->mr, subpage_t, iomem);
1582 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1583 end = start + int128_get64(section->size) - 1;
1584 subpage_register(subpage, start, end,
1585 phys_section_add(&d->map, section));
1589 static void register_multipage(FlatView *fv,
1590 MemoryRegionSection *section)
1592 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1593 hwaddr start_addr = section->offset_within_address_space;
1594 uint16_t section_index = phys_section_add(&d->map, section);
1595 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1596 TARGET_PAGE_BITS));
1598 assert(num_pages);
1599 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1602 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1604 MemoryRegionSection now = *section, remain = *section;
1605 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1607 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1608 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1609 - now.offset_within_address_space;
1611 now.size = int128_min(int128_make64(left), now.size);
1612 register_subpage(fv, &now);
1613 } else {
1614 now.size = int128_zero();
1616 while (int128_ne(remain.size, now.size)) {
1617 remain.size = int128_sub(remain.size, now.size);
1618 remain.offset_within_address_space += int128_get64(now.size);
1619 remain.offset_within_region += int128_get64(now.size);
1620 now = remain;
1621 if (int128_lt(remain.size, page_size)) {
1622 register_subpage(fv, &now);
1623 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1624 now.size = page_size;
1625 register_subpage(fv, &now);
1626 } else {
1627 now.size = int128_and(now.size, int128_neg(page_size));
1628 register_multipage(fv, &now);
1633 void qemu_flush_coalesced_mmio_buffer(void)
1635 if (kvm_enabled())
1636 kvm_flush_coalesced_mmio_buffer();
1639 void qemu_mutex_lock_ramlist(void)
1641 qemu_mutex_lock(&ram_list.mutex);
1644 void qemu_mutex_unlock_ramlist(void)
1646 qemu_mutex_unlock(&ram_list.mutex);
1649 void ram_block_dump(Monitor *mon)
1651 RAMBlock *block;
1652 char *psize;
1654 rcu_read_lock();
1655 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1656 "Block Name", "PSize", "Offset", "Used", "Total");
1657 RAMBLOCK_FOREACH(block) {
1658 psize = size_to_str(block->page_size);
1659 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1660 " 0x%016" PRIx64 "\n", block->idstr, psize,
1661 (uint64_t)block->offset,
1662 (uint64_t)block->used_length,
1663 (uint64_t)block->max_length);
1664 g_free(psize);
1666 rcu_read_unlock();
1669 #ifdef __linux__
1671 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1672 * may or may not name the same files / on the same filesystem now as
1673 * when we actually open and map them. Iterate over the file
1674 * descriptors instead, and use qemu_fd_getpagesize().
1676 static int find_max_supported_pagesize(Object *obj, void *opaque)
1678 long *hpsize_min = opaque;
1680 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1681 long hpsize = host_memory_backend_pagesize(MEMORY_BACKEND(obj));
1683 if (hpsize < *hpsize_min) {
1684 *hpsize_min = hpsize;
1688 return 0;
1691 long qemu_getrampagesize(void)
1693 long hpsize = LONG_MAX;
1694 long mainrampagesize;
1695 Object *memdev_root;
1697 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1699 /* it's possible we have memory-backend objects with
1700 * hugepage-backed RAM. these may get mapped into system
1701 * address space via -numa parameters or memory hotplug
1702 * hooks. we want to take these into account, but we
1703 * also want to make sure these supported hugepage
1704 * sizes are applicable across the entire range of memory
1705 * we may boot from, so we take the min across all
1706 * backends, and assume normal pages in cases where a
1707 * backend isn't backed by hugepages.
1709 memdev_root = object_resolve_path("/objects", NULL);
1710 if (memdev_root) {
1711 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1713 if (hpsize == LONG_MAX) {
1714 /* No additional memory regions found ==> Report main RAM page size */
1715 return mainrampagesize;
1718 /* If NUMA is disabled or the NUMA nodes are not backed with a
1719 * memory-backend, then there is at least one node using "normal" RAM,
1720 * so if its page size is smaller we have got to report that size instead.
1722 if (hpsize > mainrampagesize &&
1723 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1724 static bool warned;
1725 if (!warned) {
1726 error_report("Huge page support disabled (n/a for main memory).");
1727 warned = true;
1729 return mainrampagesize;
1732 return hpsize;
1734 #else
1735 long qemu_getrampagesize(void)
1737 return getpagesize();
1739 #endif
1741 #ifdef CONFIG_POSIX
1742 static int64_t get_file_size(int fd)
1744 int64_t size = lseek(fd, 0, SEEK_END);
1745 if (size < 0) {
1746 return -errno;
1748 return size;
1751 static int file_ram_open(const char *path,
1752 const char *region_name,
1753 bool *created,
1754 Error **errp)
1756 char *filename;
1757 char *sanitized_name;
1758 char *c;
1759 int fd = -1;
1761 *created = false;
1762 for (;;) {
1763 fd = open(path, O_RDWR);
1764 if (fd >= 0) {
1765 /* @path names an existing file, use it */
1766 break;
1768 if (errno == ENOENT) {
1769 /* @path names a file that doesn't exist, create it */
1770 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1771 if (fd >= 0) {
1772 *created = true;
1773 break;
1775 } else if (errno == EISDIR) {
1776 /* @path names a directory, create a file there */
1777 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1778 sanitized_name = g_strdup(region_name);
1779 for (c = sanitized_name; *c != '\0'; c++) {
1780 if (*c == '/') {
1781 *c = '_';
1785 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1786 sanitized_name);
1787 g_free(sanitized_name);
1789 fd = mkstemp(filename);
1790 if (fd >= 0) {
1791 unlink(filename);
1792 g_free(filename);
1793 break;
1795 g_free(filename);
1797 if (errno != EEXIST && errno != EINTR) {
1798 error_setg_errno(errp, errno,
1799 "can't open backing store %s for guest RAM",
1800 path);
1801 return -1;
1804 * Try again on EINTR and EEXIST. The latter happens when
1805 * something else creates the file between our two open().
1809 return fd;
1812 static void *file_ram_alloc(RAMBlock *block,
1813 ram_addr_t memory,
1814 int fd,
1815 bool truncate,
1816 Error **errp)
1818 void *area;
1820 block->page_size = qemu_fd_getpagesize(fd);
1821 if (block->mr->align % block->page_size) {
1822 error_setg(errp, "alignment 0x%" PRIx64
1823 " must be multiples of page size 0x%zx",
1824 block->mr->align, block->page_size);
1825 return NULL;
1826 } else if (block->mr->align && !is_power_of_2(block->mr->align)) {
1827 error_setg(errp, "alignment 0x%" PRIx64
1828 " must be a power of two", block->mr->align);
1829 return NULL;
1831 block->mr->align = MAX(block->page_size, block->mr->align);
1832 #if defined(__s390x__)
1833 if (kvm_enabled()) {
1834 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1836 #endif
1838 if (memory < block->page_size) {
1839 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1840 "or larger than page size 0x%zx",
1841 memory, block->page_size);
1842 return NULL;
1845 memory = ROUND_UP(memory, block->page_size);
1848 * ftruncate is not supported by hugetlbfs in older
1849 * hosts, so don't bother bailing out on errors.
1850 * If anything goes wrong with it under other filesystems,
1851 * mmap will fail.
1853 * Do not truncate the non-empty backend file to avoid corrupting
1854 * the existing data in the file. Disabling shrinking is not
1855 * enough. For example, the current vNVDIMM implementation stores
1856 * the guest NVDIMM labels at the end of the backend file. If the
1857 * backend file is later extended, QEMU will not be able to find
1858 * those labels. Therefore, extending the non-empty backend file
1859 * is disabled as well.
1861 if (truncate && ftruncate(fd, memory)) {
1862 perror("ftruncate");
1865 area = qemu_ram_mmap(fd, memory, block->mr->align,
1866 block->flags & RAM_SHARED);
1867 if (area == MAP_FAILED) {
1868 error_setg_errno(errp, errno,
1869 "unable to map backing store for guest RAM");
1870 return NULL;
1873 if (mem_prealloc) {
1874 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1875 if (errp && *errp) {
1876 qemu_ram_munmap(fd, area, memory);
1877 return NULL;
1881 block->fd = fd;
1882 return area;
1884 #endif
1886 /* Allocate space within the ram_addr_t space that governs the
1887 * dirty bitmaps.
1888 * Called with the ramlist lock held.
1890 static ram_addr_t find_ram_offset(ram_addr_t size)
1892 RAMBlock *block, *next_block;
1893 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1895 assert(size != 0); /* it would hand out same offset multiple times */
1897 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1898 return 0;
1901 RAMBLOCK_FOREACH(block) {
1902 ram_addr_t candidate, next = RAM_ADDR_MAX;
1904 /* Align blocks to start on a 'long' in the bitmap
1905 * which makes the bitmap sync'ing take the fast path.
1907 candidate = block->offset + block->max_length;
1908 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1910 /* Search for the closest following block
1911 * and find the gap.
1913 RAMBLOCK_FOREACH(next_block) {
1914 if (next_block->offset >= candidate) {
1915 next = MIN(next, next_block->offset);
1919 /* If it fits remember our place and remember the size
1920 * of gap, but keep going so that we might find a smaller
1921 * gap to fill so avoiding fragmentation.
1923 if (next - candidate >= size && next - candidate < mingap) {
1924 offset = candidate;
1925 mingap = next - candidate;
1928 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
1931 if (offset == RAM_ADDR_MAX) {
1932 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1933 (uint64_t)size);
1934 abort();
1937 trace_find_ram_offset(size, offset);
1939 return offset;
1942 static unsigned long last_ram_page(void)
1944 RAMBlock *block;
1945 ram_addr_t last = 0;
1947 rcu_read_lock();
1948 RAMBLOCK_FOREACH(block) {
1949 last = MAX(last, block->offset + block->max_length);
1951 rcu_read_unlock();
1952 return last >> TARGET_PAGE_BITS;
1955 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1957 int ret;
1959 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1960 if (!machine_dump_guest_core(current_machine)) {
1961 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1962 if (ret) {
1963 perror("qemu_madvise");
1964 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1965 "but dump_guest_core=off specified\n");
1970 const char *qemu_ram_get_idstr(RAMBlock *rb)
1972 return rb->idstr;
1975 bool qemu_ram_is_shared(RAMBlock *rb)
1977 return rb->flags & RAM_SHARED;
1980 /* Note: Only set at the start of postcopy */
1981 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
1983 return rb->flags & RAM_UF_ZEROPAGE;
1986 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
1988 rb->flags |= RAM_UF_ZEROPAGE;
1991 bool qemu_ram_is_migratable(RAMBlock *rb)
1993 return rb->flags & RAM_MIGRATABLE;
1996 void qemu_ram_set_migratable(RAMBlock *rb)
1998 rb->flags |= RAM_MIGRATABLE;
2001 void qemu_ram_unset_migratable(RAMBlock *rb)
2003 rb->flags &= ~RAM_MIGRATABLE;
2006 /* Called with iothread lock held. */
2007 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
2009 RAMBlock *block;
2011 assert(new_block);
2012 assert(!new_block->idstr[0]);
2014 if (dev) {
2015 char *id = qdev_get_dev_path(dev);
2016 if (id) {
2017 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
2018 g_free(id);
2021 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
2023 rcu_read_lock();
2024 RAMBLOCK_FOREACH(block) {
2025 if (block != new_block &&
2026 !strcmp(block->idstr, new_block->idstr)) {
2027 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
2028 new_block->idstr);
2029 abort();
2032 rcu_read_unlock();
2035 /* Called with iothread lock held. */
2036 void qemu_ram_unset_idstr(RAMBlock *block)
2038 /* FIXME: arch_init.c assumes that this is not called throughout
2039 * migration. Ignore the problem since hot-unplug during migration
2040 * does not work anyway.
2042 if (block) {
2043 memset(block->idstr, 0, sizeof(block->idstr));
2047 size_t qemu_ram_pagesize(RAMBlock *rb)
2049 return rb->page_size;
2052 /* Returns the largest size of page in use */
2053 size_t qemu_ram_pagesize_largest(void)
2055 RAMBlock *block;
2056 size_t largest = 0;
2058 RAMBLOCK_FOREACH(block) {
2059 largest = MAX(largest, qemu_ram_pagesize(block));
2062 return largest;
2065 static int memory_try_enable_merging(void *addr, size_t len)
2067 if (!machine_mem_merge(current_machine)) {
2068 /* disabled by the user */
2069 return 0;
2072 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
2075 /* Only legal before guest might have detected the memory size: e.g. on
2076 * incoming migration, or right after reset.
2078 * As memory core doesn't know how is memory accessed, it is up to
2079 * resize callback to update device state and/or add assertions to detect
2080 * misuse, if necessary.
2082 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
2084 assert(block);
2086 newsize = HOST_PAGE_ALIGN(newsize);
2088 if (block->used_length == newsize) {
2089 return 0;
2092 if (!(block->flags & RAM_RESIZEABLE)) {
2093 error_setg_errno(errp, EINVAL,
2094 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2095 " in != 0x" RAM_ADDR_FMT, block->idstr,
2096 newsize, block->used_length);
2097 return -EINVAL;
2100 if (block->max_length < newsize) {
2101 error_setg_errno(errp, EINVAL,
2102 "Length too large: %s: 0x" RAM_ADDR_FMT
2103 " > 0x" RAM_ADDR_FMT, block->idstr,
2104 newsize, block->max_length);
2105 return -EINVAL;
2108 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
2109 block->used_length = newsize;
2110 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
2111 DIRTY_CLIENTS_ALL);
2112 memory_region_set_size(block->mr, newsize);
2113 if (block->resized) {
2114 block->resized(block->idstr, newsize, block->host);
2116 return 0;
2119 /* Called with ram_list.mutex held */
2120 static void dirty_memory_extend(ram_addr_t old_ram_size,
2121 ram_addr_t new_ram_size)
2123 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
2124 DIRTY_MEMORY_BLOCK_SIZE);
2125 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
2126 DIRTY_MEMORY_BLOCK_SIZE);
2127 int i;
2129 /* Only need to extend if block count increased */
2130 if (new_num_blocks <= old_num_blocks) {
2131 return;
2134 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
2135 DirtyMemoryBlocks *old_blocks;
2136 DirtyMemoryBlocks *new_blocks;
2137 int j;
2139 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
2140 new_blocks = g_malloc(sizeof(*new_blocks) +
2141 sizeof(new_blocks->blocks[0]) * new_num_blocks);
2143 if (old_num_blocks) {
2144 memcpy(new_blocks->blocks, old_blocks->blocks,
2145 old_num_blocks * sizeof(old_blocks->blocks[0]));
2148 for (j = old_num_blocks; j < new_num_blocks; j++) {
2149 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
2152 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
2154 if (old_blocks) {
2155 g_free_rcu(old_blocks, rcu);
2160 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
2162 RAMBlock *block;
2163 RAMBlock *last_block = NULL;
2164 ram_addr_t old_ram_size, new_ram_size;
2165 Error *err = NULL;
2167 old_ram_size = last_ram_page();
2169 qemu_mutex_lock_ramlist();
2170 new_block->offset = find_ram_offset(new_block->max_length);
2172 if (!new_block->host) {
2173 if (xen_enabled()) {
2174 xen_ram_alloc(new_block->offset, new_block->max_length,
2175 new_block->mr, &err);
2176 if (err) {
2177 error_propagate(errp, err);
2178 qemu_mutex_unlock_ramlist();
2179 return;
2181 } else {
2182 new_block->host = phys_mem_alloc(new_block->max_length,
2183 &new_block->mr->align, shared);
2184 if (!new_block->host) {
2185 error_setg_errno(errp, errno,
2186 "cannot set up guest memory '%s'",
2187 memory_region_name(new_block->mr));
2188 qemu_mutex_unlock_ramlist();
2189 return;
2191 memory_try_enable_merging(new_block->host, new_block->max_length);
2195 new_ram_size = MAX(old_ram_size,
2196 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
2197 if (new_ram_size > old_ram_size) {
2198 dirty_memory_extend(old_ram_size, new_ram_size);
2200 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2201 * QLIST (which has an RCU-friendly variant) does not have insertion at
2202 * tail, so save the last element in last_block.
2204 RAMBLOCK_FOREACH(block) {
2205 last_block = block;
2206 if (block->max_length < new_block->max_length) {
2207 break;
2210 if (block) {
2211 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2212 } else if (last_block) {
2213 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2214 } else { /* list is empty */
2215 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2217 ram_list.mru_block = NULL;
2219 /* Write list before version */
2220 smp_wmb();
2221 ram_list.version++;
2222 qemu_mutex_unlock_ramlist();
2224 cpu_physical_memory_set_dirty_range(new_block->offset,
2225 new_block->used_length,
2226 DIRTY_CLIENTS_ALL);
2228 if (new_block->host) {
2229 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2230 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2231 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2232 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
2233 ram_block_notify_add(new_block->host, new_block->max_length);
2237 #ifdef CONFIG_POSIX
2238 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2239 uint32_t ram_flags, int fd,
2240 Error **errp)
2242 RAMBlock *new_block;
2243 Error *local_err = NULL;
2244 int64_t file_size;
2246 /* Just support these ram flags by now. */
2247 assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0);
2249 if (xen_enabled()) {
2250 error_setg(errp, "-mem-path not supported with Xen");
2251 return NULL;
2254 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2255 error_setg(errp,
2256 "host lacks kvm mmu notifiers, -mem-path unsupported");
2257 return NULL;
2260 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2262 * file_ram_alloc() needs to allocate just like
2263 * phys_mem_alloc, but we haven't bothered to provide
2264 * a hook there.
2266 error_setg(errp,
2267 "-mem-path not supported with this accelerator");
2268 return NULL;
2271 size = HOST_PAGE_ALIGN(size);
2272 file_size = get_file_size(fd);
2273 if (file_size > 0 && file_size < size) {
2274 error_setg(errp, "backing store %s size 0x%" PRIx64
2275 " does not match 'size' option 0x" RAM_ADDR_FMT,
2276 mem_path, file_size, size);
2277 return NULL;
2280 new_block = g_malloc0(sizeof(*new_block));
2281 new_block->mr = mr;
2282 new_block->used_length = size;
2283 new_block->max_length = size;
2284 new_block->flags = ram_flags;
2285 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2286 if (!new_block->host) {
2287 g_free(new_block);
2288 return NULL;
2291 ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED);
2292 if (local_err) {
2293 g_free(new_block);
2294 error_propagate(errp, local_err);
2295 return NULL;
2297 return new_block;
2302 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2303 uint32_t ram_flags, const char *mem_path,
2304 Error **errp)
2306 int fd;
2307 bool created;
2308 RAMBlock *block;
2310 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2311 if (fd < 0) {
2312 return NULL;
2315 block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, errp);
2316 if (!block) {
2317 if (created) {
2318 unlink(mem_path);
2320 close(fd);
2321 return NULL;
2324 return block;
2326 #endif
2328 static
2329 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2330 void (*resized)(const char*,
2331 uint64_t length,
2332 void *host),
2333 void *host, bool resizeable, bool share,
2334 MemoryRegion *mr, Error **errp)
2336 RAMBlock *new_block;
2337 Error *local_err = NULL;
2339 size = HOST_PAGE_ALIGN(size);
2340 max_size = HOST_PAGE_ALIGN(max_size);
2341 new_block = g_malloc0(sizeof(*new_block));
2342 new_block->mr = mr;
2343 new_block->resized = resized;
2344 new_block->used_length = size;
2345 new_block->max_length = max_size;
2346 assert(max_size >= size);
2347 new_block->fd = -1;
2348 new_block->page_size = getpagesize();
2349 new_block->host = host;
2350 if (host) {
2351 new_block->flags |= RAM_PREALLOC;
2353 if (resizeable) {
2354 new_block->flags |= RAM_RESIZEABLE;
2356 ram_block_add(new_block, &local_err, share);
2357 if (local_err) {
2358 g_free(new_block);
2359 error_propagate(errp, local_err);
2360 return NULL;
2362 return new_block;
2365 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2366 MemoryRegion *mr, Error **errp)
2368 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2369 false, mr, errp);
2372 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2373 MemoryRegion *mr, Error **errp)
2375 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2376 share, mr, errp);
2379 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2380 void (*resized)(const char*,
2381 uint64_t length,
2382 void *host),
2383 MemoryRegion *mr, Error **errp)
2385 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2386 false, mr, errp);
2389 static void reclaim_ramblock(RAMBlock *block)
2391 if (block->flags & RAM_PREALLOC) {
2393 } else if (xen_enabled()) {
2394 xen_invalidate_map_cache_entry(block->host);
2395 #ifndef _WIN32
2396 } else if (block->fd >= 0) {
2397 qemu_ram_munmap(block->fd, block->host, block->max_length);
2398 close(block->fd);
2399 #endif
2400 } else {
2401 qemu_anon_ram_free(block->host, block->max_length);
2403 g_free(block);
2406 void qemu_ram_free(RAMBlock *block)
2408 if (!block) {
2409 return;
2412 if (block->host) {
2413 ram_block_notify_remove(block->host, block->max_length);
2416 qemu_mutex_lock_ramlist();
2417 QLIST_REMOVE_RCU(block, next);
2418 ram_list.mru_block = NULL;
2419 /* Write list before version */
2420 smp_wmb();
2421 ram_list.version++;
2422 call_rcu(block, reclaim_ramblock, rcu);
2423 qemu_mutex_unlock_ramlist();
2426 #ifndef _WIN32
2427 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2429 RAMBlock *block;
2430 ram_addr_t offset;
2431 int flags;
2432 void *area, *vaddr;
2434 RAMBLOCK_FOREACH(block) {
2435 offset = addr - block->offset;
2436 if (offset < block->max_length) {
2437 vaddr = ramblock_ptr(block, offset);
2438 if (block->flags & RAM_PREALLOC) {
2440 } else if (xen_enabled()) {
2441 abort();
2442 } else {
2443 flags = MAP_FIXED;
2444 if (block->fd >= 0) {
2445 flags |= (block->flags & RAM_SHARED ?
2446 MAP_SHARED : MAP_PRIVATE);
2447 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2448 flags, block->fd, offset);
2449 } else {
2451 * Remap needs to match alloc. Accelerators that
2452 * set phys_mem_alloc never remap. If they did,
2453 * we'd need a remap hook here.
2455 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2457 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2458 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2459 flags, -1, 0);
2461 if (area != vaddr) {
2462 error_report("Could not remap addr: "
2463 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2464 length, addr);
2465 exit(1);
2467 memory_try_enable_merging(vaddr, length);
2468 qemu_ram_setup_dump(vaddr, length);
2473 #endif /* !_WIN32 */
2475 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2476 * This should not be used for general purpose DMA. Use address_space_map
2477 * or address_space_rw instead. For local memory (e.g. video ram) that the
2478 * device owns, use memory_region_get_ram_ptr.
2480 * Called within RCU critical section.
2482 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2484 RAMBlock *block = ram_block;
2486 if (block == NULL) {
2487 block = qemu_get_ram_block(addr);
2488 addr -= block->offset;
2491 if (xen_enabled() && block->host == NULL) {
2492 /* We need to check if the requested address is in the RAM
2493 * because we don't want to map the entire memory in QEMU.
2494 * In that case just map until the end of the page.
2496 if (block->offset == 0) {
2497 return xen_map_cache(addr, 0, 0, false);
2500 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2502 return ramblock_ptr(block, addr);
2505 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2506 * but takes a size argument.
2508 * Called within RCU critical section.
2510 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2511 hwaddr *size, bool lock)
2513 RAMBlock *block = ram_block;
2514 if (*size == 0) {
2515 return NULL;
2518 if (block == NULL) {
2519 block = qemu_get_ram_block(addr);
2520 addr -= block->offset;
2522 *size = MIN(*size, block->max_length - addr);
2524 if (xen_enabled() && block->host == NULL) {
2525 /* We need to check if the requested address is in the RAM
2526 * because we don't want to map the entire memory in QEMU.
2527 * In that case just map the requested area.
2529 if (block->offset == 0) {
2530 return xen_map_cache(addr, *size, lock, lock);
2533 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2536 return ramblock_ptr(block, addr);
2539 /* Return the offset of a hostpointer within a ramblock */
2540 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2542 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2543 assert((uintptr_t)host >= (uintptr_t)rb->host);
2544 assert(res < rb->max_length);
2546 return res;
2550 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2551 * in that RAMBlock.
2553 * ptr: Host pointer to look up
2554 * round_offset: If true round the result offset down to a page boundary
2555 * *ram_addr: set to result ram_addr
2556 * *offset: set to result offset within the RAMBlock
2558 * Returns: RAMBlock (or NULL if not found)
2560 * By the time this function returns, the returned pointer is not protected
2561 * by RCU anymore. If the caller is not within an RCU critical section and
2562 * does not hold the iothread lock, it must have other means of protecting the
2563 * pointer, such as a reference to the region that includes the incoming
2564 * ram_addr_t.
2566 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2567 ram_addr_t *offset)
2569 RAMBlock *block;
2570 uint8_t *host = ptr;
2572 if (xen_enabled()) {
2573 ram_addr_t ram_addr;
2574 rcu_read_lock();
2575 ram_addr = xen_ram_addr_from_mapcache(ptr);
2576 block = qemu_get_ram_block(ram_addr);
2577 if (block) {
2578 *offset = ram_addr - block->offset;
2580 rcu_read_unlock();
2581 return block;
2584 rcu_read_lock();
2585 block = atomic_rcu_read(&ram_list.mru_block);
2586 if (block && block->host && host - block->host < block->max_length) {
2587 goto found;
2590 RAMBLOCK_FOREACH(block) {
2591 /* This case append when the block is not mapped. */
2592 if (block->host == NULL) {
2593 continue;
2595 if (host - block->host < block->max_length) {
2596 goto found;
2600 rcu_read_unlock();
2601 return NULL;
2603 found:
2604 *offset = (host - block->host);
2605 if (round_offset) {
2606 *offset &= TARGET_PAGE_MASK;
2608 rcu_read_unlock();
2609 return block;
2613 * Finds the named RAMBlock
2615 * name: The name of RAMBlock to find
2617 * Returns: RAMBlock (or NULL if not found)
2619 RAMBlock *qemu_ram_block_by_name(const char *name)
2621 RAMBlock *block;
2623 RAMBLOCK_FOREACH(block) {
2624 if (!strcmp(name, block->idstr)) {
2625 return block;
2629 return NULL;
2632 /* Some of the softmmu routines need to translate from a host pointer
2633 (typically a TLB entry) back to a ram offset. */
2634 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2636 RAMBlock *block;
2637 ram_addr_t offset;
2639 block = qemu_ram_block_from_host(ptr, false, &offset);
2640 if (!block) {
2641 return RAM_ADDR_INVALID;
2644 return block->offset + offset;
2647 /* Called within RCU critical section. */
2648 void memory_notdirty_write_prepare(NotDirtyInfo *ndi,
2649 CPUState *cpu,
2650 vaddr mem_vaddr,
2651 ram_addr_t ram_addr,
2652 unsigned size)
2654 ndi->cpu = cpu;
2655 ndi->ram_addr = ram_addr;
2656 ndi->mem_vaddr = mem_vaddr;
2657 ndi->size = size;
2658 ndi->pages = NULL;
2660 assert(tcg_enabled());
2661 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2662 ndi->pages = page_collection_lock(ram_addr, ram_addr + size);
2663 tb_invalidate_phys_page_fast(ndi->pages, ram_addr, size);
2667 /* Called within RCU critical section. */
2668 void memory_notdirty_write_complete(NotDirtyInfo *ndi)
2670 if (ndi->pages) {
2671 assert(tcg_enabled());
2672 page_collection_unlock(ndi->pages);
2673 ndi->pages = NULL;
2676 /* Set both VGA and migration bits for simplicity and to remove
2677 * the notdirty callback faster.
2679 cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size,
2680 DIRTY_CLIENTS_NOCODE);
2681 /* we remove the notdirty callback only if the code has been
2682 flushed */
2683 if (!cpu_physical_memory_is_clean(ndi->ram_addr)) {
2684 tlb_set_dirty(ndi->cpu, ndi->mem_vaddr);
2688 /* Called within RCU critical section. */
2689 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2690 uint64_t val, unsigned size)
2692 NotDirtyInfo ndi;
2694 memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr,
2695 ram_addr, size);
2697 stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val);
2698 memory_notdirty_write_complete(&ndi);
2701 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2702 unsigned size, bool is_write,
2703 MemTxAttrs attrs)
2705 return is_write;
2708 static const MemoryRegionOps notdirty_mem_ops = {
2709 .write = notdirty_mem_write,
2710 .valid.accepts = notdirty_mem_accepts,
2711 .endianness = DEVICE_NATIVE_ENDIAN,
2712 .valid = {
2713 .min_access_size = 1,
2714 .max_access_size = 8,
2715 .unaligned = false,
2717 .impl = {
2718 .min_access_size = 1,
2719 .max_access_size = 8,
2720 .unaligned = false,
2724 /* Generate a debug exception if a watchpoint has been hit. */
2725 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2727 CPUState *cpu = current_cpu;
2728 CPUClass *cc = CPU_GET_CLASS(cpu);
2729 target_ulong vaddr;
2730 CPUWatchpoint *wp;
2732 assert(tcg_enabled());
2733 if (cpu->watchpoint_hit) {
2734 /* We re-entered the check after replacing the TB. Now raise
2735 * the debug interrupt so that is will trigger after the
2736 * current instruction. */
2737 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2738 return;
2740 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2741 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2742 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2743 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2744 && (wp->flags & flags)) {
2745 if (flags == BP_MEM_READ) {
2746 wp->flags |= BP_WATCHPOINT_HIT_READ;
2747 } else {
2748 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2750 wp->hitaddr = vaddr;
2751 wp->hitattrs = attrs;
2752 if (!cpu->watchpoint_hit) {
2753 if (wp->flags & BP_CPU &&
2754 !cc->debug_check_watchpoint(cpu, wp)) {
2755 wp->flags &= ~BP_WATCHPOINT_HIT;
2756 continue;
2758 cpu->watchpoint_hit = wp;
2760 mmap_lock();
2761 tb_check_watchpoint(cpu);
2762 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2763 cpu->exception_index = EXCP_DEBUG;
2764 mmap_unlock();
2765 cpu_loop_exit(cpu);
2766 } else {
2767 /* Force execution of one insn next time. */
2768 cpu->cflags_next_tb = 1 | curr_cflags();
2769 mmap_unlock();
2770 cpu_loop_exit_noexc(cpu);
2773 } else {
2774 wp->flags &= ~BP_WATCHPOINT_HIT;
2779 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2780 so these check for a hit then pass through to the normal out-of-line
2781 phys routines. */
2782 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2783 unsigned size, MemTxAttrs attrs)
2785 MemTxResult res;
2786 uint64_t data;
2787 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2788 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2790 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2791 switch (size) {
2792 case 1:
2793 data = address_space_ldub(as, addr, attrs, &res);
2794 break;
2795 case 2:
2796 data = address_space_lduw(as, addr, attrs, &res);
2797 break;
2798 case 4:
2799 data = address_space_ldl(as, addr, attrs, &res);
2800 break;
2801 case 8:
2802 data = address_space_ldq(as, addr, attrs, &res);
2803 break;
2804 default: abort();
2806 *pdata = data;
2807 return res;
2810 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2811 uint64_t val, unsigned size,
2812 MemTxAttrs attrs)
2814 MemTxResult res;
2815 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2816 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2818 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2819 switch (size) {
2820 case 1:
2821 address_space_stb(as, addr, val, attrs, &res);
2822 break;
2823 case 2:
2824 address_space_stw(as, addr, val, attrs, &res);
2825 break;
2826 case 4:
2827 address_space_stl(as, addr, val, attrs, &res);
2828 break;
2829 case 8:
2830 address_space_stq(as, addr, val, attrs, &res);
2831 break;
2832 default: abort();
2834 return res;
2837 static const MemoryRegionOps watch_mem_ops = {
2838 .read_with_attrs = watch_mem_read,
2839 .write_with_attrs = watch_mem_write,
2840 .endianness = DEVICE_NATIVE_ENDIAN,
2841 .valid = {
2842 .min_access_size = 1,
2843 .max_access_size = 8,
2844 .unaligned = false,
2846 .impl = {
2847 .min_access_size = 1,
2848 .max_access_size = 8,
2849 .unaligned = false,
2853 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2854 MemTxAttrs attrs, uint8_t *buf, int len);
2855 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2856 const uint8_t *buf, int len);
2857 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
2858 bool is_write, MemTxAttrs attrs);
2860 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2861 unsigned len, MemTxAttrs attrs)
2863 subpage_t *subpage = opaque;
2864 uint8_t buf[8];
2865 MemTxResult res;
2867 #if defined(DEBUG_SUBPAGE)
2868 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2869 subpage, len, addr);
2870 #endif
2871 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2872 if (res) {
2873 return res;
2875 *data = ldn_p(buf, len);
2876 return MEMTX_OK;
2879 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2880 uint64_t value, unsigned len, MemTxAttrs attrs)
2882 subpage_t *subpage = opaque;
2883 uint8_t buf[8];
2885 #if defined(DEBUG_SUBPAGE)
2886 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2887 " value %"PRIx64"\n",
2888 __func__, subpage, len, addr, value);
2889 #endif
2890 stn_p(buf, len, value);
2891 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2894 static bool subpage_accepts(void *opaque, hwaddr addr,
2895 unsigned len, bool is_write,
2896 MemTxAttrs attrs)
2898 subpage_t *subpage = opaque;
2899 #if defined(DEBUG_SUBPAGE)
2900 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2901 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2902 #endif
2904 return flatview_access_valid(subpage->fv, addr + subpage->base,
2905 len, is_write, attrs);
2908 static const MemoryRegionOps subpage_ops = {
2909 .read_with_attrs = subpage_read,
2910 .write_with_attrs = subpage_write,
2911 .impl.min_access_size = 1,
2912 .impl.max_access_size = 8,
2913 .valid.min_access_size = 1,
2914 .valid.max_access_size = 8,
2915 .valid.accepts = subpage_accepts,
2916 .endianness = DEVICE_NATIVE_ENDIAN,
2919 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2920 uint16_t section)
2922 int idx, eidx;
2924 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2925 return -1;
2926 idx = SUBPAGE_IDX(start);
2927 eidx = SUBPAGE_IDX(end);
2928 #if defined(DEBUG_SUBPAGE)
2929 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2930 __func__, mmio, start, end, idx, eidx, section);
2931 #endif
2932 for (; idx <= eidx; idx++) {
2933 mmio->sub_section[idx] = section;
2936 return 0;
2939 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
2941 subpage_t *mmio;
2943 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2944 mmio->fv = fv;
2945 mmio->base = base;
2946 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2947 NULL, TARGET_PAGE_SIZE);
2948 mmio->iomem.subpage = true;
2949 #if defined(DEBUG_SUBPAGE)
2950 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2951 mmio, base, TARGET_PAGE_SIZE);
2952 #endif
2953 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2955 return mmio;
2958 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
2960 assert(fv);
2961 MemoryRegionSection section = {
2962 .fv = fv,
2963 .mr = mr,
2964 .offset_within_address_space = 0,
2965 .offset_within_region = 0,
2966 .size = int128_2_64(),
2969 return phys_section_add(map, &section);
2972 static void readonly_mem_write(void *opaque, hwaddr addr,
2973 uint64_t val, unsigned size)
2975 /* Ignore any write to ROM. */
2978 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
2979 unsigned size, bool is_write,
2980 MemTxAttrs attrs)
2982 return is_write;
2985 /* This will only be used for writes, because reads are special cased
2986 * to directly access the underlying host ram.
2988 static const MemoryRegionOps readonly_mem_ops = {
2989 .write = readonly_mem_write,
2990 .valid.accepts = readonly_mem_accepts,
2991 .endianness = DEVICE_NATIVE_ENDIAN,
2992 .valid = {
2993 .min_access_size = 1,
2994 .max_access_size = 8,
2995 .unaligned = false,
2997 .impl = {
2998 .min_access_size = 1,
2999 .max_access_size = 8,
3000 .unaligned = false,
3004 MemoryRegionSection *iotlb_to_section(CPUState *cpu,
3005 hwaddr index, MemTxAttrs attrs)
3007 int asidx = cpu_asidx_from_attrs(cpu, attrs);
3008 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
3009 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
3010 MemoryRegionSection *sections = d->map.sections;
3012 return &sections[index & ~TARGET_PAGE_MASK];
3015 static void io_mem_init(void)
3017 memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops,
3018 NULL, NULL, UINT64_MAX);
3019 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
3020 NULL, UINT64_MAX);
3022 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3023 * which can be called without the iothread mutex.
3025 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
3026 NULL, UINT64_MAX);
3027 memory_region_clear_global_locking(&io_mem_notdirty);
3029 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
3030 NULL, UINT64_MAX);
3033 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
3035 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
3036 uint16_t n;
3038 n = dummy_section(&d->map, fv, &io_mem_unassigned);
3039 assert(n == PHYS_SECTION_UNASSIGNED);
3040 n = dummy_section(&d->map, fv, &io_mem_notdirty);
3041 assert(n == PHYS_SECTION_NOTDIRTY);
3042 n = dummy_section(&d->map, fv, &io_mem_rom);
3043 assert(n == PHYS_SECTION_ROM);
3044 n = dummy_section(&d->map, fv, &io_mem_watch);
3045 assert(n == PHYS_SECTION_WATCH);
3047 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
3049 return d;
3052 void address_space_dispatch_free(AddressSpaceDispatch *d)
3054 phys_sections_free(&d->map);
3055 g_free(d);
3058 static void tcg_commit(MemoryListener *listener)
3060 CPUAddressSpace *cpuas;
3061 AddressSpaceDispatch *d;
3063 assert(tcg_enabled());
3064 /* since each CPU stores ram addresses in its TLB cache, we must
3065 reset the modified entries */
3066 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
3067 cpu_reloading_memory_map();
3068 /* The CPU and TLB are protected by the iothread lock.
3069 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3070 * may have split the RCU critical section.
3072 d = address_space_to_dispatch(cpuas->as);
3073 atomic_rcu_set(&cpuas->memory_dispatch, d);
3074 tlb_flush(cpuas->cpu);
3077 static void memory_map_init(void)
3079 system_memory = g_malloc(sizeof(*system_memory));
3081 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
3082 address_space_init(&address_space_memory, system_memory, "memory");
3084 system_io = g_malloc(sizeof(*system_io));
3085 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
3086 65536);
3087 address_space_init(&address_space_io, system_io, "I/O");
3090 MemoryRegion *get_system_memory(void)
3092 return system_memory;
3095 MemoryRegion *get_system_io(void)
3097 return system_io;
3100 #endif /* !defined(CONFIG_USER_ONLY) */
3102 /* physical memory access (slow version, mainly for debug) */
3103 #if defined(CONFIG_USER_ONLY)
3104 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3105 uint8_t *buf, int len, int is_write)
3107 int l, flags;
3108 target_ulong page;
3109 void * p;
3111 while (len > 0) {
3112 page = addr & TARGET_PAGE_MASK;
3113 l = (page + TARGET_PAGE_SIZE) - addr;
3114 if (l > len)
3115 l = len;
3116 flags = page_get_flags(page);
3117 if (!(flags & PAGE_VALID))
3118 return -1;
3119 if (is_write) {
3120 if (!(flags & PAGE_WRITE))
3121 return -1;
3122 /* XXX: this code should not depend on lock_user */
3123 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
3124 return -1;
3125 memcpy(p, buf, l);
3126 unlock_user(p, addr, l);
3127 } else {
3128 if (!(flags & PAGE_READ))
3129 return -1;
3130 /* XXX: this code should not depend on lock_user */
3131 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3132 return -1;
3133 memcpy(buf, p, l);
3134 unlock_user(p, addr, 0);
3136 len -= l;
3137 buf += l;
3138 addr += l;
3140 return 0;
3143 #else
3145 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
3146 hwaddr length)
3148 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
3149 addr += memory_region_get_ram_addr(mr);
3151 /* No early return if dirty_log_mask is or becomes 0, because
3152 * cpu_physical_memory_set_dirty_range will still call
3153 * xen_modified_memory.
3155 if (dirty_log_mask) {
3156 dirty_log_mask =
3157 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
3159 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
3160 assert(tcg_enabled());
3161 tb_invalidate_phys_range(addr, addr + length);
3162 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
3164 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
3167 void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size)
3170 * In principle this function would work on other memory region types too,
3171 * but the ROM device use case is the only one where this operation is
3172 * necessary. Other memory regions should use the
3173 * address_space_read/write() APIs.
3175 assert(memory_region_is_romd(mr));
3177 invalidate_and_set_dirty(mr, addr, size);
3180 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
3182 unsigned access_size_max = mr->ops->valid.max_access_size;
3184 /* Regions are assumed to support 1-4 byte accesses unless
3185 otherwise specified. */
3186 if (access_size_max == 0) {
3187 access_size_max = 4;
3190 /* Bound the maximum access by the alignment of the address. */
3191 if (!mr->ops->impl.unaligned) {
3192 unsigned align_size_max = addr & -addr;
3193 if (align_size_max != 0 && align_size_max < access_size_max) {
3194 access_size_max = align_size_max;
3198 /* Don't attempt accesses larger than the maximum. */
3199 if (l > access_size_max) {
3200 l = access_size_max;
3202 l = pow2floor(l);
3204 return l;
3207 static bool prepare_mmio_access(MemoryRegion *mr)
3209 bool unlocked = !qemu_mutex_iothread_locked();
3210 bool release_lock = false;
3212 if (unlocked && mr->global_locking) {
3213 qemu_mutex_lock_iothread();
3214 unlocked = false;
3215 release_lock = true;
3217 if (mr->flush_coalesced_mmio) {
3218 if (unlocked) {
3219 qemu_mutex_lock_iothread();
3221 qemu_flush_coalesced_mmio_buffer();
3222 if (unlocked) {
3223 qemu_mutex_unlock_iothread();
3227 return release_lock;
3230 /* Called within RCU critical section. */
3231 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3232 MemTxAttrs attrs,
3233 const uint8_t *buf,
3234 int len, hwaddr addr1,
3235 hwaddr l, MemoryRegion *mr)
3237 uint8_t *ptr;
3238 uint64_t val;
3239 MemTxResult result = MEMTX_OK;
3240 bool release_lock = false;
3242 for (;;) {
3243 if (!memory_access_is_direct(mr, true)) {
3244 release_lock |= prepare_mmio_access(mr);
3245 l = memory_access_size(mr, l, addr1);
3246 /* XXX: could force current_cpu to NULL to avoid
3247 potential bugs */
3248 val = ldn_p(buf, l);
3249 result |= memory_region_dispatch_write(mr, addr1, val, l, attrs);
3250 } else {
3251 /* RAM case */
3252 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3253 memcpy(ptr, buf, l);
3254 invalidate_and_set_dirty(mr, addr1, l);
3257 if (release_lock) {
3258 qemu_mutex_unlock_iothread();
3259 release_lock = false;
3262 len -= l;
3263 buf += l;
3264 addr += l;
3266 if (!len) {
3267 break;
3270 l = len;
3271 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3274 return result;
3277 /* Called from RCU critical section. */
3278 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3279 const uint8_t *buf, int len)
3281 hwaddr l;
3282 hwaddr addr1;
3283 MemoryRegion *mr;
3284 MemTxResult result = MEMTX_OK;
3286 l = len;
3287 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3288 result = flatview_write_continue(fv, addr, attrs, buf, len,
3289 addr1, l, mr);
3291 return result;
3294 /* Called within RCU critical section. */
3295 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3296 MemTxAttrs attrs, uint8_t *buf,
3297 int len, hwaddr addr1, hwaddr l,
3298 MemoryRegion *mr)
3300 uint8_t *ptr;
3301 uint64_t val;
3302 MemTxResult result = MEMTX_OK;
3303 bool release_lock = false;
3305 for (;;) {
3306 if (!memory_access_is_direct(mr, false)) {
3307 /* I/O case */
3308 release_lock |= prepare_mmio_access(mr);
3309 l = memory_access_size(mr, l, addr1);
3310 result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs);
3311 stn_p(buf, l, val);
3312 } else {
3313 /* RAM case */
3314 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3315 memcpy(buf, ptr, l);
3318 if (release_lock) {
3319 qemu_mutex_unlock_iothread();
3320 release_lock = false;
3323 len -= l;
3324 buf += l;
3325 addr += l;
3327 if (!len) {
3328 break;
3331 l = len;
3332 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3335 return result;
3338 /* Called from RCU critical section. */
3339 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3340 MemTxAttrs attrs, uint8_t *buf, int len)
3342 hwaddr l;
3343 hwaddr addr1;
3344 MemoryRegion *mr;
3346 l = len;
3347 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3348 return flatview_read_continue(fv, addr, attrs, buf, len,
3349 addr1, l, mr);
3352 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3353 MemTxAttrs attrs, uint8_t *buf, int len)
3355 MemTxResult result = MEMTX_OK;
3356 FlatView *fv;
3358 if (len > 0) {
3359 rcu_read_lock();
3360 fv = address_space_to_flatview(as);
3361 result = flatview_read(fv, addr, attrs, buf, len);
3362 rcu_read_unlock();
3365 return result;
3368 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3369 MemTxAttrs attrs,
3370 const uint8_t *buf, int len)
3372 MemTxResult result = MEMTX_OK;
3373 FlatView *fv;
3375 if (len > 0) {
3376 rcu_read_lock();
3377 fv = address_space_to_flatview(as);
3378 result = flatview_write(fv, addr, attrs, buf, len);
3379 rcu_read_unlock();
3382 return result;
3385 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3386 uint8_t *buf, int len, bool is_write)
3388 if (is_write) {
3389 return address_space_write(as, addr, attrs, buf, len);
3390 } else {
3391 return address_space_read_full(as, addr, attrs, buf, len);
3395 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3396 int len, int is_write)
3398 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3399 buf, len, is_write);
3402 enum write_rom_type {
3403 WRITE_DATA,
3404 FLUSH_CACHE,
3407 static inline MemTxResult address_space_write_rom_internal(AddressSpace *as,
3408 hwaddr addr,
3409 MemTxAttrs attrs,
3410 const uint8_t *buf,
3411 int len,
3412 enum write_rom_type type)
3414 hwaddr l;
3415 uint8_t *ptr;
3416 hwaddr addr1;
3417 MemoryRegion *mr;
3419 rcu_read_lock();
3420 while (len > 0) {
3421 l = len;
3422 mr = address_space_translate(as, addr, &addr1, &l, true, attrs);
3424 if (!(memory_region_is_ram(mr) ||
3425 memory_region_is_romd(mr))) {
3426 l = memory_access_size(mr, l, addr1);
3427 } else {
3428 /* ROM/RAM case */
3429 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3430 switch (type) {
3431 case WRITE_DATA:
3432 memcpy(ptr, buf, l);
3433 invalidate_and_set_dirty(mr, addr1, l);
3434 break;
3435 case FLUSH_CACHE:
3436 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3437 break;
3440 len -= l;
3441 buf += l;
3442 addr += l;
3444 rcu_read_unlock();
3445 return MEMTX_OK;
3448 /* used for ROM loading : can write in RAM and ROM */
3449 MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr,
3450 MemTxAttrs attrs,
3451 const uint8_t *buf, int len)
3453 return address_space_write_rom_internal(as, addr, attrs,
3454 buf, len, WRITE_DATA);
3457 void cpu_flush_icache_range(hwaddr start, int len)
3460 * This function should do the same thing as an icache flush that was
3461 * triggered from within the guest. For TCG we are always cache coherent,
3462 * so there is no need to flush anything. For KVM / Xen we need to flush
3463 * the host's instruction cache at least.
3465 if (tcg_enabled()) {
3466 return;
3469 address_space_write_rom_internal(&address_space_memory,
3470 start, MEMTXATTRS_UNSPECIFIED,
3471 NULL, len, FLUSH_CACHE);
3474 typedef struct {
3475 MemoryRegion *mr;
3476 void *buffer;
3477 hwaddr addr;
3478 hwaddr len;
3479 bool in_use;
3480 } BounceBuffer;
3482 static BounceBuffer bounce;
3484 typedef struct MapClient {
3485 QEMUBH *bh;
3486 QLIST_ENTRY(MapClient) link;
3487 } MapClient;
3489 QemuMutex map_client_list_lock;
3490 static QLIST_HEAD(, MapClient) map_client_list
3491 = QLIST_HEAD_INITIALIZER(map_client_list);
3493 static void cpu_unregister_map_client_do(MapClient *client)
3495 QLIST_REMOVE(client, link);
3496 g_free(client);
3499 static void cpu_notify_map_clients_locked(void)
3501 MapClient *client;
3503 while (!QLIST_EMPTY(&map_client_list)) {
3504 client = QLIST_FIRST(&map_client_list);
3505 qemu_bh_schedule(client->bh);
3506 cpu_unregister_map_client_do(client);
3510 void cpu_register_map_client(QEMUBH *bh)
3512 MapClient *client = g_malloc(sizeof(*client));
3514 qemu_mutex_lock(&map_client_list_lock);
3515 client->bh = bh;
3516 QLIST_INSERT_HEAD(&map_client_list, client, link);
3517 if (!atomic_read(&bounce.in_use)) {
3518 cpu_notify_map_clients_locked();
3520 qemu_mutex_unlock(&map_client_list_lock);
3523 void cpu_exec_init_all(void)
3525 qemu_mutex_init(&ram_list.mutex);
3526 /* The data structures we set up here depend on knowing the page size,
3527 * so no more changes can be made after this point.
3528 * In an ideal world, nothing we did before we had finished the
3529 * machine setup would care about the target page size, and we could
3530 * do this much later, rather than requiring board models to state
3531 * up front what their requirements are.
3533 finalize_target_page_bits();
3534 io_mem_init();
3535 memory_map_init();
3536 qemu_mutex_init(&map_client_list_lock);
3539 void cpu_unregister_map_client(QEMUBH *bh)
3541 MapClient *client;
3543 qemu_mutex_lock(&map_client_list_lock);
3544 QLIST_FOREACH(client, &map_client_list, link) {
3545 if (client->bh == bh) {
3546 cpu_unregister_map_client_do(client);
3547 break;
3550 qemu_mutex_unlock(&map_client_list_lock);
3553 static void cpu_notify_map_clients(void)
3555 qemu_mutex_lock(&map_client_list_lock);
3556 cpu_notify_map_clients_locked();
3557 qemu_mutex_unlock(&map_client_list_lock);
3560 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
3561 bool is_write, MemTxAttrs attrs)
3563 MemoryRegion *mr;
3564 hwaddr l, xlat;
3566 while (len > 0) {
3567 l = len;
3568 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3569 if (!memory_access_is_direct(mr, is_write)) {
3570 l = memory_access_size(mr, l, addr);
3571 if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
3572 return false;
3576 len -= l;
3577 addr += l;
3579 return true;
3582 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3583 int len, bool is_write,
3584 MemTxAttrs attrs)
3586 FlatView *fv;
3587 bool result;
3589 rcu_read_lock();
3590 fv = address_space_to_flatview(as);
3591 result = flatview_access_valid(fv, addr, len, is_write, attrs);
3592 rcu_read_unlock();
3593 return result;
3596 static hwaddr
3597 flatview_extend_translation(FlatView *fv, hwaddr addr,
3598 hwaddr target_len,
3599 MemoryRegion *mr, hwaddr base, hwaddr len,
3600 bool is_write, MemTxAttrs attrs)
3602 hwaddr done = 0;
3603 hwaddr xlat;
3604 MemoryRegion *this_mr;
3606 for (;;) {
3607 target_len -= len;
3608 addr += len;
3609 done += len;
3610 if (target_len == 0) {
3611 return done;
3614 len = target_len;
3615 this_mr = flatview_translate(fv, addr, &xlat,
3616 &len, is_write, attrs);
3617 if (this_mr != mr || xlat != base + done) {
3618 return done;
3623 /* Map a physical memory region into a host virtual address.
3624 * May map a subset of the requested range, given by and returned in *plen.
3625 * May return NULL if resources needed to perform the mapping are exhausted.
3626 * Use only for reads OR writes - not for read-modify-write operations.
3627 * Use cpu_register_map_client() to know when retrying the map operation is
3628 * likely to succeed.
3630 void *address_space_map(AddressSpace *as,
3631 hwaddr addr,
3632 hwaddr *plen,
3633 bool is_write,
3634 MemTxAttrs attrs)
3636 hwaddr len = *plen;
3637 hwaddr l, xlat;
3638 MemoryRegion *mr;
3639 void *ptr;
3640 FlatView *fv;
3642 if (len == 0) {
3643 return NULL;
3646 l = len;
3647 rcu_read_lock();
3648 fv = address_space_to_flatview(as);
3649 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3651 if (!memory_access_is_direct(mr, is_write)) {
3652 if (atomic_xchg(&bounce.in_use, true)) {
3653 rcu_read_unlock();
3654 return NULL;
3656 /* Avoid unbounded allocations */
3657 l = MIN(l, TARGET_PAGE_SIZE);
3658 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3659 bounce.addr = addr;
3660 bounce.len = l;
3662 memory_region_ref(mr);
3663 bounce.mr = mr;
3664 if (!is_write) {
3665 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3666 bounce.buffer, l);
3669 rcu_read_unlock();
3670 *plen = l;
3671 return bounce.buffer;
3675 memory_region_ref(mr);
3676 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3677 l, is_write, attrs);
3678 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3679 rcu_read_unlock();
3681 return ptr;
3684 /* Unmaps a memory region previously mapped by address_space_map().
3685 * Will also mark the memory as dirty if is_write == 1. access_len gives
3686 * the amount of memory that was actually read or written by the caller.
3688 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3689 int is_write, hwaddr access_len)
3691 if (buffer != bounce.buffer) {
3692 MemoryRegion *mr;
3693 ram_addr_t addr1;
3695 mr = memory_region_from_host(buffer, &addr1);
3696 assert(mr != NULL);
3697 if (is_write) {
3698 invalidate_and_set_dirty(mr, addr1, access_len);
3700 if (xen_enabled()) {
3701 xen_invalidate_map_cache_entry(buffer);
3703 memory_region_unref(mr);
3704 return;
3706 if (is_write) {
3707 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3708 bounce.buffer, access_len);
3710 qemu_vfree(bounce.buffer);
3711 bounce.buffer = NULL;
3712 memory_region_unref(bounce.mr);
3713 atomic_mb_set(&bounce.in_use, false);
3714 cpu_notify_map_clients();
3717 void *cpu_physical_memory_map(hwaddr addr,
3718 hwaddr *plen,
3719 int is_write)
3721 return address_space_map(&address_space_memory, addr, plen, is_write,
3722 MEMTXATTRS_UNSPECIFIED);
3725 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3726 int is_write, hwaddr access_len)
3728 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3731 #define ARG1_DECL AddressSpace *as
3732 #define ARG1 as
3733 #define SUFFIX
3734 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3735 #define RCU_READ_LOCK(...) rcu_read_lock()
3736 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3737 #include "memory_ldst.inc.c"
3739 int64_t address_space_cache_init(MemoryRegionCache *cache,
3740 AddressSpace *as,
3741 hwaddr addr,
3742 hwaddr len,
3743 bool is_write)
3745 AddressSpaceDispatch *d;
3746 hwaddr l;
3747 MemoryRegion *mr;
3749 assert(len > 0);
3751 l = len;
3752 cache->fv = address_space_get_flatview(as);
3753 d = flatview_to_dispatch(cache->fv);
3754 cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true);
3756 mr = cache->mrs.mr;
3757 memory_region_ref(mr);
3758 if (memory_access_is_direct(mr, is_write)) {
3759 /* We don't care about the memory attributes here as we're only
3760 * doing this if we found actual RAM, which behaves the same
3761 * regardless of attributes; so UNSPECIFIED is fine.
3763 l = flatview_extend_translation(cache->fv, addr, len, mr,
3764 cache->xlat, l, is_write,
3765 MEMTXATTRS_UNSPECIFIED);
3766 cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
3767 } else {
3768 cache->ptr = NULL;
3771 cache->len = l;
3772 cache->is_write = is_write;
3773 return l;
3776 void address_space_cache_invalidate(MemoryRegionCache *cache,
3777 hwaddr addr,
3778 hwaddr access_len)
3780 assert(cache->is_write);
3781 if (likely(cache->ptr)) {
3782 invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len);
3786 void address_space_cache_destroy(MemoryRegionCache *cache)
3788 if (!cache->mrs.mr) {
3789 return;
3792 if (xen_enabled()) {
3793 xen_invalidate_map_cache_entry(cache->ptr);
3795 memory_region_unref(cache->mrs.mr);
3796 flatview_unref(cache->fv);
3797 cache->mrs.mr = NULL;
3798 cache->fv = NULL;
3801 /* Called from RCU critical section. This function has the same
3802 * semantics as address_space_translate, but it only works on a
3803 * predefined range of a MemoryRegion that was mapped with
3804 * address_space_cache_init.
3806 static inline MemoryRegion *address_space_translate_cached(
3807 MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
3808 hwaddr *plen, bool is_write, MemTxAttrs attrs)
3810 MemoryRegionSection section;
3811 MemoryRegion *mr;
3812 IOMMUMemoryRegion *iommu_mr;
3813 AddressSpace *target_as;
3815 assert(!cache->ptr);
3816 *xlat = addr + cache->xlat;
3818 mr = cache->mrs.mr;
3819 iommu_mr = memory_region_get_iommu(mr);
3820 if (!iommu_mr) {
3821 /* MMIO region. */
3822 return mr;
3825 section = address_space_translate_iommu(iommu_mr, xlat, plen,
3826 NULL, is_write, true,
3827 &target_as, attrs);
3828 return section.mr;
3831 /* Called from RCU critical section. address_space_read_cached uses this
3832 * out of line function when the target is an MMIO or IOMMU region.
3834 void
3835 address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3836 void *buf, int len)
3838 hwaddr addr1, l;
3839 MemoryRegion *mr;
3841 l = len;
3842 mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
3843 MEMTXATTRS_UNSPECIFIED);
3844 flatview_read_continue(cache->fv,
3845 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3846 addr1, l, mr);
3849 /* Called from RCU critical section. address_space_write_cached uses this
3850 * out of line function when the target is an MMIO or IOMMU region.
3852 void
3853 address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3854 const void *buf, int len)
3856 hwaddr addr1, l;
3857 MemoryRegion *mr;
3859 l = len;
3860 mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
3861 MEMTXATTRS_UNSPECIFIED);
3862 flatview_write_continue(cache->fv,
3863 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3864 addr1, l, mr);
3867 #define ARG1_DECL MemoryRegionCache *cache
3868 #define ARG1 cache
3869 #define SUFFIX _cached_slow
3870 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3871 #define RCU_READ_LOCK() ((void)0)
3872 #define RCU_READ_UNLOCK() ((void)0)
3873 #include "memory_ldst.inc.c"
3875 /* virtual memory access for debug (includes writing to ROM) */
3876 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3877 uint8_t *buf, int len, int is_write)
3879 int l;
3880 hwaddr phys_addr;
3881 target_ulong page;
3883 cpu_synchronize_state(cpu);
3884 while (len > 0) {
3885 int asidx;
3886 MemTxAttrs attrs;
3888 page = addr & TARGET_PAGE_MASK;
3889 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3890 asidx = cpu_asidx_from_attrs(cpu, attrs);
3891 /* if no physical page mapped, return an error */
3892 if (phys_addr == -1)
3893 return -1;
3894 l = (page + TARGET_PAGE_SIZE) - addr;
3895 if (l > len)
3896 l = len;
3897 phys_addr += (addr & ~TARGET_PAGE_MASK);
3898 if (is_write) {
3899 address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr,
3900 attrs, buf, l);
3901 } else {
3902 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3903 attrs, buf, l, 0);
3905 len -= l;
3906 buf += l;
3907 addr += l;
3909 return 0;
3913 * Allows code that needs to deal with migration bitmaps etc to still be built
3914 * target independent.
3916 size_t qemu_target_page_size(void)
3918 return TARGET_PAGE_SIZE;
3921 int qemu_target_page_bits(void)
3923 return TARGET_PAGE_BITS;
3926 int qemu_target_page_bits_min(void)
3928 return TARGET_PAGE_BITS_MIN;
3930 #endif
3932 bool target_words_bigendian(void)
3934 #if defined(TARGET_WORDS_BIGENDIAN)
3935 return true;
3936 #else
3937 return false;
3938 #endif
3941 #ifndef CONFIG_USER_ONLY
3942 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3944 MemoryRegion*mr;
3945 hwaddr l = 1;
3946 bool res;
3948 rcu_read_lock();
3949 mr = address_space_translate(&address_space_memory,
3950 phys_addr, &phys_addr, &l, false,
3951 MEMTXATTRS_UNSPECIFIED);
3953 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3954 rcu_read_unlock();
3955 return res;
3958 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3960 RAMBlock *block;
3961 int ret = 0;
3963 rcu_read_lock();
3964 RAMBLOCK_FOREACH(block) {
3965 ret = func(block->idstr, block->host, block->offset,
3966 block->used_length, opaque);
3967 if (ret) {
3968 break;
3971 rcu_read_unlock();
3972 return ret;
3975 int qemu_ram_foreach_migratable_block(RAMBlockIterFunc func, void *opaque)
3977 RAMBlock *block;
3978 int ret = 0;
3980 rcu_read_lock();
3981 RAMBLOCK_FOREACH(block) {
3982 if (!qemu_ram_is_migratable(block)) {
3983 continue;
3985 ret = func(block->idstr, block->host, block->offset,
3986 block->used_length, opaque);
3987 if (ret) {
3988 break;
3991 rcu_read_unlock();
3992 return ret;
3996 * Unmap pages of memory from start to start+length such that
3997 * they a) read as 0, b) Trigger whatever fault mechanism
3998 * the OS provides for postcopy.
3999 * The pages must be unmapped by the end of the function.
4000 * Returns: 0 on success, none-0 on failure
4003 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
4005 int ret = -1;
4007 uint8_t *host_startaddr = rb->host + start;
4009 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
4010 error_report("ram_block_discard_range: Unaligned start address: %p",
4011 host_startaddr);
4012 goto err;
4015 if ((start + length) <= rb->used_length) {
4016 bool need_madvise, need_fallocate;
4017 uint8_t *host_endaddr = host_startaddr + length;
4018 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
4019 error_report("ram_block_discard_range: Unaligned end address: %p",
4020 host_endaddr);
4021 goto err;
4024 errno = ENOTSUP; /* If we are missing MADVISE etc */
4026 /* The logic here is messy;
4027 * madvise DONTNEED fails for hugepages
4028 * fallocate works on hugepages and shmem
4030 need_madvise = (rb->page_size == qemu_host_page_size);
4031 need_fallocate = rb->fd != -1;
4032 if (need_fallocate) {
4033 /* For a file, this causes the area of the file to be zero'd
4034 * if read, and for hugetlbfs also causes it to be unmapped
4035 * so a userfault will trigger.
4037 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4038 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
4039 start, length);
4040 if (ret) {
4041 ret = -errno;
4042 error_report("ram_block_discard_range: Failed to fallocate "
4043 "%s:%" PRIx64 " +%zx (%d)",
4044 rb->idstr, start, length, ret);
4045 goto err;
4047 #else
4048 ret = -ENOSYS;
4049 error_report("ram_block_discard_range: fallocate not available/file"
4050 "%s:%" PRIx64 " +%zx (%d)",
4051 rb->idstr, start, length, ret);
4052 goto err;
4053 #endif
4055 if (need_madvise) {
4056 /* For normal RAM this causes it to be unmapped,
4057 * for shared memory it causes the local mapping to disappear
4058 * and to fall back on the file contents (which we just
4059 * fallocate'd away).
4061 #if defined(CONFIG_MADVISE)
4062 ret = madvise(host_startaddr, length, MADV_DONTNEED);
4063 if (ret) {
4064 ret = -errno;
4065 error_report("ram_block_discard_range: Failed to discard range "
4066 "%s:%" PRIx64 " +%zx (%d)",
4067 rb->idstr, start, length, ret);
4068 goto err;
4070 #else
4071 ret = -ENOSYS;
4072 error_report("ram_block_discard_range: MADVISE not available"
4073 "%s:%" PRIx64 " +%zx (%d)",
4074 rb->idstr, start, length, ret);
4075 goto err;
4076 #endif
4078 trace_ram_block_discard_range(rb->idstr, host_startaddr, length,
4079 need_madvise, need_fallocate, ret);
4080 } else {
4081 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4082 "/%zx/" RAM_ADDR_FMT")",
4083 rb->idstr, start, length, rb->used_length);
4086 err:
4087 return ret;
4090 bool ramblock_is_pmem(RAMBlock *rb)
4092 return rb->flags & RAM_PMEM;
4095 #endif
4097 void page_size_init(void)
4099 /* NOTE: we can always suppose that qemu_host_page_size >=
4100 TARGET_PAGE_SIZE */
4101 if (qemu_host_page_size == 0) {
4102 qemu_host_page_size = qemu_real_host_page_size;
4104 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
4105 qemu_host_page_size = TARGET_PAGE_SIZE;
4107 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
4110 #if !defined(CONFIG_USER_ONLY)
4112 static void mtree_print_phys_entries(fprintf_function mon, void *f,
4113 int start, int end, int skip, int ptr)
4115 if (start == end - 1) {
4116 mon(f, "\t%3d ", start);
4117 } else {
4118 mon(f, "\t%3d..%-3d ", start, end - 1);
4120 mon(f, " skip=%d ", skip);
4121 if (ptr == PHYS_MAP_NODE_NIL) {
4122 mon(f, " ptr=NIL");
4123 } else if (!skip) {
4124 mon(f, " ptr=#%d", ptr);
4125 } else {
4126 mon(f, " ptr=[%d]", ptr);
4128 mon(f, "\n");
4131 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4132 int128_sub((size), int128_one())) : 0)
4134 void mtree_print_dispatch(fprintf_function mon, void *f,
4135 AddressSpaceDispatch *d, MemoryRegion *root)
4137 int i;
4139 mon(f, " Dispatch\n");
4140 mon(f, " Physical sections\n");
4142 for (i = 0; i < d->map.sections_nb; ++i) {
4143 MemoryRegionSection *s = d->map.sections + i;
4144 const char *names[] = { " [unassigned]", " [not dirty]",
4145 " [ROM]", " [watch]" };
4147 mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s",
4149 s->offset_within_address_space,
4150 s->offset_within_address_space + MR_SIZE(s->mr->size),
4151 s->mr->name ? s->mr->name : "(noname)",
4152 i < ARRAY_SIZE(names) ? names[i] : "",
4153 s->mr == root ? " [ROOT]" : "",
4154 s == d->mru_section ? " [MRU]" : "",
4155 s->mr->is_iommu ? " [iommu]" : "");
4157 if (s->mr->alias) {
4158 mon(f, " alias=%s", s->mr->alias->name ?
4159 s->mr->alias->name : "noname");
4161 mon(f, "\n");
4164 mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4165 P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip);
4166 for (i = 0; i < d->map.nodes_nb; ++i) {
4167 int j, jprev;
4168 PhysPageEntry prev;
4169 Node *n = d->map.nodes + i;
4171 mon(f, " [%d]\n", i);
4173 for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) {
4174 PhysPageEntry *pe = *n + j;
4176 if (pe->ptr == prev.ptr && pe->skip == prev.skip) {
4177 continue;
4180 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
4182 jprev = j;
4183 prev = *pe;
4186 if (jprev != ARRAY_SIZE(*n)) {
4187 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
4192 #endif