hw/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "sysbus.h"
  11 #include "primecell.h"
  12 #include "devices.h"
  13 #include "boards.h"
  14 #include "arm-misc.h"
  15 #include "net.h"
  16 #include "exec-memory.h"
  17 #include "sysemu.h"
  18
  19 typedef struct {
  20     SysBusDevice busdev;
  21     uint32_t memsz;
  22     MemoryRegion flash;
  23     bool flash_mapped;
  24     uint32_t cm_osc;
  25     uint32_t cm_ctrl;
  26     uint32_t cm_lock;
  27     uint32_t cm_auxosc;
  28     uint32_t cm_sdram;
  29     uint32_t cm_init;
  30     uint32_t cm_flags;
  31     uint32_t cm_nvflags;
  32     uint32_t int_level;
  33     uint32_t irq_enabled;
  34     uint32_t fiq_enabled;
  35 } integratorcm_state;
  36
  37 static uint8_t integrator_spd[128] = {
  38    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  39    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  40 };
  41
  42 static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
  43 {
  44     integratorcm_state *s = (integratorcm_state *)opaque;
  45     if (offset >= 0x100 && offset < 0x200) {
  46         /* CM_SPD */
  47         if (offset >= 0x180)
  48             return 0;
  49         return integrator_spd[offset >> 2];
  50     }
  51     switch (offset >> 2) {
  52     case 0: /* CM_ID */
  53         return 0x411a3001;
  54     case 1: /* CM_PROC */
  55         return 0;
  56     case 2: /* CM_OSC */
  57         return s->cm_osc;
  58     case 3: /* CM_CTRL */
  59         return s->cm_ctrl;
  60     case 4: /* CM_STAT */
  61         return 0x00100000;
  62     case 5: /* CM_LOCK */
  63         if (s->cm_lock == 0xa05f) {
  64             return 0x1a05f;
  65         } else {
  66             return s->cm_lock;
  67         }
  68     case 6: /* CM_LMBUSCNT */
  69         /* ??? High frequency timer.  */
  70         hw_error("integratorcm_read: CM_LMBUSCNT");
  71     case 7: /* CM_AUXOSC */
  72         return s->cm_auxosc;
  73     case 8: /* CM_SDRAM */
  74         return s->cm_sdram;
  75     case 9: /* CM_INIT */
  76         return s->cm_init;
  77     case 10: /* CM_REFCT */
  78         /* ??? High frequency timer.  */
  79         hw_error("integratorcm_read: CM_REFCT");
  80     case 12: /* CM_FLAGS */
  81         return s->cm_flags;
  82     case 14: /* CM_NVFLAGS */
  83         return s->cm_nvflags;
  84     case 16: /* CM_IRQ_STAT */
  85         return s->int_level & s->irq_enabled;
  86     case 17: /* CM_IRQ_RSTAT */
  87         return s->int_level;
  88     case 18: /* CM_IRQ_ENSET */
  89         return s->irq_enabled;
  90     case 20: /* CM_SOFT_INTSET */
  91         return s->int_level & 1;
  92     case 24: /* CM_FIQ_STAT */
  93         return s->int_level & s->fiq_enabled;
  94     case 25: /* CM_FIQ_RSTAT */
  95         return s->int_level;
  96     case 26: /* CM_FIQ_ENSET */
  97         return s->fiq_enabled;
  98     case 32: /* CM_VOLTAGE_CTL0 */
  99     case 33: /* CM_VOLTAGE_CTL1 */
 100     case 34: /* CM_VOLTAGE_CTL2 */
 101     case 35: /* CM_VOLTAGE_CTL3 */
 102         /* ??? Voltage control unimplemented.  */
 103         return 0;
 104     default:
 105         hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
 106                  (int)offset);
 107         return 0;
 108     }
 109 }
 110
 111 static void integratorcm_do_remap(integratorcm_state *s, int flash)
 112 {
 113     if (flash) {
 114         if (s->flash_mapped) {
 115             sysbus_del_memory(&s->busdev, &s->flash);
 116             s->flash_mapped = false;
 117         }
 118     } else {
 119         if (!s->flash_mapped) {
 120             sysbus_add_memory_overlap(&s->busdev, 0, &s->flash, 1);
 121             s->flash_mapped = true;
 122         }
 123     }
 124     //??? tlb_flush (cpu_single_env, 1);
 125 }
 126
 127 static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
 128 {
 129     if (value & 8) {
 130         qemu_system_reset_request();
 131     }
 132     if ((s->cm_ctrl ^ value) & 4) {
 133         integratorcm_do_remap(s, (value & 4) == 0);
 134     }
 135     if ((s->cm_ctrl ^ value) & 1) {
 136         /* (value & 1) != 0 means the green "MISC LED" is lit.
 137          * We don't have any nice place to display LEDs. printf is a bad
 138          * idea because Linux uses the LED as a heartbeat and the output
 139          * will swamp anything else on the terminal.
 140          */
 141     }
 142     /* Note that the RESET bit [3] always reads as zero */
 143     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
 144 }
 145
 146 static void integratorcm_update(integratorcm_state *s)
 147 {
 148     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 149        are active.  */
 150     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 151         hw_error("Core module interrupt\n");
 152 }
 153
 154 static void integratorcm_write(void *opaque, target_phys_addr_t offset,
 155                                uint32_t value)
 156 {
 157     integratorcm_state *s = (integratorcm_state *)opaque;
 158     switch (offset >> 2) {
 159     case 2: /* CM_OSC */
 160         if (s->cm_lock == 0xa05f)
 161             s->cm_osc = value;
 162         break;
 163     case 3: /* CM_CTRL */
 164         integratorcm_set_ctrl(s, value);
 165         break;
 166     case 5: /* CM_LOCK */
 167         s->cm_lock = value & 0xffff;
 168         break;
 169     case 7: /* CM_AUXOSC */
 170         if (s->cm_lock == 0xa05f)
 171             s->cm_auxosc = value;
 172         break;
 173     case 8: /* CM_SDRAM */
 174         s->cm_sdram = value;
 175         break;
 176     case 9: /* CM_INIT */
 177         /* ??? This can change the memory bus frequency.  */
 178         s->cm_init = value;
 179         break;
 180     case 12: /* CM_FLAGSS */
 181         s->cm_flags |= value;
 182         break;
 183     case 13: /* CM_FLAGSC */
 184         s->cm_flags &= ~value;
 185         break;
 186     case 14: /* CM_NVFLAGSS */
 187         s->cm_nvflags |= value;
 188         break;
 189     case 15: /* CM_NVFLAGSS */
 190         s->cm_nvflags &= ~value;
 191         break;
 192     case 18: /* CM_IRQ_ENSET */
 193         s->irq_enabled |= value;
 194         integratorcm_update(s);
 195         break;
 196     case 19: /* CM_IRQ_ENCLR */
 197         s->irq_enabled &= ~value;
 198         integratorcm_update(s);
 199         break;
 200     case 20: /* CM_SOFT_INTSET */
 201         s->int_level |= (value & 1);
 202         integratorcm_update(s);
 203         break;
 204     case 21: /* CM_SOFT_INTCLR */
 205         s->int_level &= ~(value & 1);
 206         integratorcm_update(s);
 207         break;
 208     case 26: /* CM_FIQ_ENSET */
 209         s->fiq_enabled |= value;
 210         integratorcm_update(s);
 211         break;
 212     case 27: /* CM_FIQ_ENCLR */
 213         s->fiq_enabled &= ~value;
 214         integratorcm_update(s);
 215         break;
 216     case 32: /* CM_VOLTAGE_CTL0 */
 217     case 33: /* CM_VOLTAGE_CTL1 */
 218     case 34: /* CM_VOLTAGE_CTL2 */
 219     case 35: /* CM_VOLTAGE_CTL3 */
 220         /* ??? Voltage control unimplemented.  */
 221         break;
 222     default:
 223         hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
 224                  (int)offset);
 225         break;
 226     }
 227 }
 228
 229 /* Integrator/CM control registers.  */
 230
 231 static CPUReadMemoryFunc * const integratorcm_readfn[] = {
 232    integratorcm_read,
 233    integratorcm_read,
 234    integratorcm_read
 235 };
 236
 237 static CPUWriteMemoryFunc * const integratorcm_writefn[] = {
 238    integratorcm_write,
 239    integratorcm_write,
 240    integratorcm_write
 241 };
 242
 243 static int integratorcm_init(SysBusDevice *dev)
 244 {
 245     int iomemtype;
 246     integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
 247
 248     s->cm_osc = 0x01000048;
 249     /* ??? What should the high bits of this value be?  */
 250     s->cm_auxosc = 0x0007feff;
 251     s->cm_sdram = 0x00011122;
 252     if (s->memsz >= 256) {
 253         integrator_spd[31] = 64;
 254         s->cm_sdram |= 0x10;
 255     } else if (s->memsz >= 128) {
 256         integrator_spd[31] = 32;
 257         s->cm_sdram |= 0x0c;
 258     } else if (s->memsz >= 64) {
 259         integrator_spd[31] = 16;
 260         s->cm_sdram |= 0x08;
 261     } else if (s->memsz >= 32) {
 262         integrator_spd[31] = 4;
 263         s->cm_sdram |= 0x04;
 264     } else {
 265         integrator_spd[31] = 2;
 266     }
 267     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 268     s->cm_init = 0x00000112;
 269     memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000);
 270     s->flash_mapped = false;
 271
 272     iomemtype = cpu_register_io_memory(integratorcm_readfn,
 273                                        integratorcm_writefn, s,
 274                                        DEVICE_NATIVE_ENDIAN);
 275     sysbus_init_mmio(dev, 0x00800000, iomemtype);
 276     integratorcm_do_remap(s, 1);
 277     /* ??? Save/restore.  */
 278     return 0;
 279 }
 280
 281 /* Integrator/CP hardware emulation.  */
 282 /* Primary interrupt controller.  */
 283
 284 typedef struct icp_pic_state
 285 {
 286   SysBusDevice busdev;
 287   uint32_t level;
 288   uint32_t irq_enabled;
 289   uint32_t fiq_enabled;
 290   qemu_irq parent_irq;
 291   qemu_irq parent_fiq;
 292 } icp_pic_state;
 293
 294 static void icp_pic_update(icp_pic_state *s)
 295 {
 296     uint32_t flags;
 297
 298     flags = (s->level & s->irq_enabled);
 299     qemu_set_irq(s->parent_irq, flags != 0);
 300     flags = (s->level & s->fiq_enabled);
 301     qemu_set_irq(s->parent_fiq, flags != 0);
 302 }
 303
 304 static void icp_pic_set_irq(void *opaque, int irq, int level)
 305 {
 306     icp_pic_state *s = (icp_pic_state *)opaque;
 307     if (level)
 308         s->level |= 1 << irq;
 309     else
 310         s->level &= ~(1 << irq);
 311     icp_pic_update(s);
 312 }
 313
 314 static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
 315 {
 316     icp_pic_state *s = (icp_pic_state *)opaque;
 317
 318     switch (offset >> 2) {
 319     case 0: /* IRQ_STATUS */
 320         return s->level & s->irq_enabled;
 321     case 1: /* IRQ_RAWSTAT */
 322         return s->level;
 323     case 2: /* IRQ_ENABLESET */
 324         return s->irq_enabled;
 325     case 4: /* INT_SOFTSET */
 326         return s->level & 1;
 327     case 8: /* FRQ_STATUS */
 328         return s->level & s->fiq_enabled;
 329     case 9: /* FRQ_RAWSTAT */
 330         return s->level;
 331     case 10: /* FRQ_ENABLESET */
 332         return s->fiq_enabled;
 333     case 3: /* IRQ_ENABLECLR */
 334     case 5: /* INT_SOFTCLR */
 335     case 11: /* FRQ_ENABLECLR */
 336     default:
 337         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
 338         return 0;
 339     }
 340 }
 341
 342 static void icp_pic_write(void *opaque, target_phys_addr_t offset,
 343                           uint32_t value)
 344 {
 345     icp_pic_state *s = (icp_pic_state *)opaque;
 346
 347     switch (offset >> 2) {
 348     case 2: /* IRQ_ENABLESET */
 349         s->irq_enabled |= value;
 350         break;
 351     case 3: /* IRQ_ENABLECLR */
 352         s->irq_enabled &= ~value;
 353         break;
 354     case 4: /* INT_SOFTSET */
 355         if (value & 1)
 356             icp_pic_set_irq(s, 0, 1);
 357         break;
 358     case 5: /* INT_SOFTCLR */
 359         if (value & 1)
 360             icp_pic_set_irq(s, 0, 0);
 361         break;
 362     case 10: /* FRQ_ENABLESET */
 363         s->fiq_enabled |= value;
 364         break;
 365     case 11: /* FRQ_ENABLECLR */
 366         s->fiq_enabled &= ~value;
 367         break;
 368     case 0: /* IRQ_STATUS */
 369     case 1: /* IRQ_RAWSTAT */
 370     case 8: /* FRQ_STATUS */
 371     case 9: /* FRQ_RAWSTAT */
 372     default:
 373         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
 374         return;
 375     }
 376     icp_pic_update(s);
 377 }
 378
 379 static CPUReadMemoryFunc * const icp_pic_readfn[] = {
 380    icp_pic_read,
 381    icp_pic_read,
 382    icp_pic_read
 383 };
 384
 385 static CPUWriteMemoryFunc * const icp_pic_writefn[] = {
 386    icp_pic_write,
 387    icp_pic_write,
 388    icp_pic_write
 389 };
 390
 391 static int icp_pic_init(SysBusDevice *dev)
 392 {
 393     icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
 394     int iomemtype;
 395
 396     qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
 397     sysbus_init_irq(dev, &s->parent_irq);
 398     sysbus_init_irq(dev, &s->parent_fiq);
 399     iomemtype = cpu_register_io_memory(icp_pic_readfn,
 400                                        icp_pic_writefn, s,
 401                                        DEVICE_NATIVE_ENDIAN);
 402     sysbus_init_mmio(dev, 0x00800000, iomemtype);
 403     return 0;
 404 }
 405
 406 /* CP control registers.  */
 407 static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
 408 {
 409     switch (offset >> 2) {
 410     case 0: /* CP_IDFIELD */
 411         return 0x41034003;
 412     case 1: /* CP_FLASHPROG */
 413         return 0;
 414     case 2: /* CP_INTREG */
 415         return 0;
 416     case 3: /* CP_DECODE */
 417         return 0x11;
 418     default:
 419         hw_error("icp_control_read: Bad offset %x\n", (int)offset);
 420         return 0;
 421     }
 422 }
 423
 424 static void icp_control_write(void *opaque, target_phys_addr_t offset,
 425                           uint32_t value)
 426 {
 427     switch (offset >> 2) {
 428     case 1: /* CP_FLASHPROG */
 429     case 2: /* CP_INTREG */
 430     case 3: /* CP_DECODE */
 431         /* Nothing interesting implemented yet.  */
 432         break;
 433     default:
 434         hw_error("icp_control_write: Bad offset %x\n", (int)offset);
 435     }
 436 }
 437 static CPUReadMemoryFunc * const icp_control_readfn[] = {
 438    icp_control_read,
 439    icp_control_read,
 440    icp_control_read
 441 };
 442
 443 static CPUWriteMemoryFunc * const icp_control_writefn[] = {
 444    icp_control_write,
 445    icp_control_write,
 446    icp_control_write
 447 };
 448
 449 static void icp_control_init(uint32_t base)
 450 {
 451     int iomemtype;
 452
 453     iomemtype = cpu_register_io_memory(icp_control_readfn,
 454                                        icp_control_writefn, NULL,
 455                                        DEVICE_NATIVE_ENDIAN);
 456     cpu_register_physical_memory(base, 0x00800000, iomemtype);
 457     /* ??? Save/restore.  */
 458 }
 459
 460
 461 /* Board init.  */
 462
 463 static struct arm_boot_info integrator_binfo = {
 464     .loader_start = 0x0,
 465     .board_id = 0x113,
 466 };
 467
 468 static void integratorcp_init(ram_addr_t ram_size,
 469                      const char *boot_device,
 470                      const char *kernel_filename, const char *kernel_cmdline,
 471                      const char *initrd_filename, const char *cpu_model)
 472 {
 473     CPUState *env;
 474     MemoryRegion *address_space_mem = get_system_memory();
 475     MemoryRegion *ram = g_new(MemoryRegion, 1);
 476     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 477     qemu_irq pic[32];
 478     qemu_irq *cpu_pic;
 479     DeviceState *dev;
 480     int i;
 481
 482     if (!cpu_model)
 483         cpu_model = "arm926";
 484     env = cpu_init(cpu_model);
 485     if (!env) {
 486         fprintf(stderr, "Unable to find CPU definition\n");
 487         exit(1);
 488     }
 489     memory_region_init_ram(ram, NULL, "integrator.ram", ram_size);
 490     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 491     /* ??? RAM should repeat to fill physical memory space.  */
 492     /* SDRAM at address zero*/
 493     memory_region_add_subregion(address_space_mem, 0, ram);
 494     /* And again at address 0x80000000 */
 495     memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
 496     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
 497
 498     dev = qdev_create(NULL, "integrator_core");
 499     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 500     qdev_init_nofail(dev);
 501     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 502
 503     cpu_pic = arm_pic_init_cpu(env);
 504     dev = sysbus_create_varargs("integrator_pic", 0x14000000,
 505                                 cpu_pic[ARM_PIC_CPU_IRQ],
 506                                 cpu_pic[ARM_PIC_CPU_FIQ], NULL);
 507     for (i = 0; i < 32; i++) {
 508         pic[i] = qdev_get_gpio_in(dev, i);
 509     }
 510     sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
 511     sysbus_create_varargs("integrator_pit", 0x13000000,
 512                           pic[5], pic[6], pic[7], NULL);
 513     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 514     sysbus_create_simple("pl011", 0x16000000, pic[1]);
 515     sysbus_create_simple("pl011", 0x17000000, pic[2]);
 516     icp_control_init(0xcb000000);
 517     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 518     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 519     sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 520     if (nd_table[0].vlan)
 521         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 522
 523     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
 524
 525     integrator_binfo.ram_size = ram_size;
 526     integrator_binfo.kernel_filename = kernel_filename;
 527     integrator_binfo.kernel_cmdline = kernel_cmdline;
 528     integrator_binfo.initrd_filename = initrd_filename;
 529     arm_load_kernel(env, &integrator_binfo);
 530 }
 531
 532 static QEMUMachine integratorcp_machine = {
 533     .name = "integratorcp",
 534     .desc = "ARM Integrator/CP (ARM926EJ-S)",
 535     .init = integratorcp_init,
 536     .is_default = 1,
 537 };
 538
 539 static void integratorcp_machine_init(void)
 540 {
 541     qemu_register_machine(&integratorcp_machine);
 542 }
 543
 544 machine_init(integratorcp_machine_init);
 545
 546 static SysBusDeviceInfo core_info = {
 547     .init = integratorcm_init,
 548     .qdev.name  = "integrator_core",
 549     .qdev.size  = sizeof(integratorcm_state),
 550     .qdev.props = (Property[]) {
 551         DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0),
 552         DEFINE_PROP_END_OF_LIST(),
 553     }
 554 };
 555
 556 static void integratorcp_register_devices(void)
 557 {
 558     sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init);
 559     sysbus_register_withprop(&core_info);
 560 }
 561
 562 device_init(integratorcp_register_devices)