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[qemu/ar7.git] / qom / cpu.c
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1 /*
2 * QEMU CPU model
4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
24 #include "qom/cpu.h"
25 #include "sysemu/hw_accel.h"
26 #include "qemu/notify.h"
27 #include "qemu/log.h"
28 #include "exec/log.h"
29 #include "exec/cpu-common.h"
30 #include "qemu/error-report.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/boards.h"
33 #include "hw/qdev-properties.h"
34 #include "trace-root.h"
36 CPUInterruptHandler cpu_interrupt_handler;
38 CPUState *cpu_by_arch_id(int64_t id)
40 CPUState *cpu;
42 CPU_FOREACH(cpu) {
43 CPUClass *cc = CPU_GET_CLASS(cpu);
45 if (cc->get_arch_id(cpu) == id) {
46 return cpu;
49 return NULL;
52 bool cpu_exists(int64_t id)
54 return !!cpu_by_arch_id(id);
57 CPUState *cpu_create(const char *typename)
59 Error *err = NULL;
60 CPUState *cpu = CPU(object_new(typename));
61 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
62 if (err != NULL) {
63 error_report_err(err);
64 object_unref(OBJECT(cpu));
65 exit(EXIT_FAILURE);
67 return cpu;
70 bool cpu_paging_enabled(const CPUState *cpu)
72 CPUClass *cc = CPU_GET_CLASS(cpu);
74 return cc->get_paging_enabled(cpu);
77 static bool cpu_common_get_paging_enabled(const CPUState *cpu)
79 return false;
82 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
83 Error **errp)
85 CPUClass *cc = CPU_GET_CLASS(cpu);
87 cc->get_memory_mapping(cpu, list, errp);
90 static void cpu_common_get_memory_mapping(CPUState *cpu,
91 MemoryMappingList *list,
92 Error **errp)
94 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
97 /* Resetting the IRQ comes from across the code base so we take the
98 * BQL here if we need to. cpu_interrupt assumes it is held.*/
99 void cpu_reset_interrupt(CPUState *cpu, int mask)
101 bool need_lock = !qemu_mutex_iothread_locked();
103 if (need_lock) {
104 qemu_mutex_lock_iothread();
106 cpu->interrupt_request &= ~mask;
107 if (need_lock) {
108 qemu_mutex_unlock_iothread();
112 void cpu_exit(CPUState *cpu)
114 atomic_set(&cpu->exit_request, 1);
115 /* Ensure cpu_exec will see the exit request after TCG has exited. */
116 smp_wmb();
117 atomic_set(&cpu->icount_decr.u16.high, -1);
120 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
121 void *opaque)
123 CPUClass *cc = CPU_GET_CLASS(cpu);
125 return (*cc->write_elf32_qemunote)(f, cpu, opaque);
128 static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
129 CPUState *cpu, void *opaque)
131 return 0;
134 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
135 int cpuid, void *opaque)
137 CPUClass *cc = CPU_GET_CLASS(cpu);
139 return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
142 static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
143 CPUState *cpu, int cpuid,
144 void *opaque)
146 return -1;
149 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
150 void *opaque)
152 CPUClass *cc = CPU_GET_CLASS(cpu);
154 return (*cc->write_elf64_qemunote)(f, cpu, opaque);
157 static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
158 CPUState *cpu, void *opaque)
160 return 0;
163 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
164 int cpuid, void *opaque)
166 CPUClass *cc = CPU_GET_CLASS(cpu);
168 return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
171 static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
172 CPUState *cpu, int cpuid,
173 void *opaque)
175 return -1;
179 static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg)
181 return 0;
184 static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
186 return 0;
189 static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
191 /* If no extra check is required, QEMU watchpoint match can be considered
192 * as an architectural match.
194 return true;
197 static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
199 return target_words_bigendian();
202 static void cpu_common_noop(CPUState *cpu)
206 static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
208 return false;
211 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
213 CPUClass *cc = CPU_GET_CLASS(cpu);
214 GuestPanicInformation *res = NULL;
216 if (cc->get_crash_info) {
217 res = cc->get_crash_info(cpu);
219 return res;
222 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
223 int flags)
225 CPUClass *cc = CPU_GET_CLASS(cpu);
227 if (cc->dump_state) {
228 cpu_synchronize_state(cpu);
229 cc->dump_state(cpu, f, cpu_fprintf, flags);
233 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
234 int flags)
236 CPUClass *cc = CPU_GET_CLASS(cpu);
238 if (cc->dump_statistics) {
239 cc->dump_statistics(cpu, f, cpu_fprintf, flags);
243 void cpu_reset(CPUState *cpu)
245 CPUClass *klass = CPU_GET_CLASS(cpu);
247 if (klass->reset != NULL) {
248 (*klass->reset)(cpu);
251 trace_guest_cpu_reset(cpu);
254 static void cpu_common_reset(CPUState *cpu)
256 CPUClass *cc = CPU_GET_CLASS(cpu);
258 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
259 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
260 log_cpu_state(cpu, cc->reset_dump_flags);
263 cpu->interrupt_request = 0;
264 cpu->halted = 0;
265 cpu->mem_io_pc = 0;
266 cpu->mem_io_vaddr = 0;
267 cpu->icount_extra = 0;
268 cpu->icount_decr.u32 = 0;
269 cpu->can_do_io = 1;
270 cpu->exception_index = -1;
271 cpu->crash_occurred = false;
272 cpu->cflags_next_tb = -1;
274 if (tcg_enabled()) {
275 cpu_tb_jmp_cache_clear(cpu);
277 tcg_flush_softmmu_tlb(cpu);
281 static bool cpu_common_has_work(CPUState *cs)
283 return false;
286 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
288 CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
290 assert(cpu_model && cc->class_by_name);
291 return cc->class_by_name(cpu_model);
294 static void cpu_common_parse_features(const char *typename, char *features,
295 Error **errp)
297 char *val;
298 static bool cpu_globals_initialized;
299 /* Single "key=value" string being parsed */
300 char *featurestr = features ? strtok(features, ",") : NULL;
302 /* should be called only once, catch invalid users */
303 assert(!cpu_globals_initialized);
304 cpu_globals_initialized = true;
306 while (featurestr) {
307 val = strchr(featurestr, '=');
308 if (val) {
309 GlobalProperty *prop = g_new0(typeof(*prop), 1);
310 *val = 0;
311 val++;
312 prop->driver = typename;
313 prop->property = g_strdup(featurestr);
314 prop->value = g_strdup(val);
315 prop->errp = &error_fatal;
316 qdev_prop_register_global(prop);
317 } else {
318 error_setg(errp, "Expected key=value format, found %s.",
319 featurestr);
320 return;
322 featurestr = strtok(NULL, ",");
326 static void cpu_common_realizefn(DeviceState *dev, Error **errp)
328 CPUState *cpu = CPU(dev);
329 Object *machine = qdev_get_machine();
331 /* qdev_get_machine() can return something that's not TYPE_MACHINE
332 * if this is one of the user-only emulators; in that case there's
333 * no need to check the ignore_memory_transaction_failures board flag.
335 if (object_dynamic_cast(machine, TYPE_MACHINE)) {
336 ObjectClass *oc = object_get_class(machine);
337 MachineClass *mc = MACHINE_CLASS(oc);
339 if (mc) {
340 cpu->ignore_memory_transaction_failures =
341 mc->ignore_memory_transaction_failures;
345 if (dev->hotplugged) {
346 cpu_synchronize_post_init(cpu);
347 cpu_resume(cpu);
350 /* NOTE: latest generic point where the cpu is fully realized */
351 trace_init_vcpu(cpu);
354 static void cpu_common_unrealizefn(DeviceState *dev, Error **errp)
356 CPUState *cpu = CPU(dev);
357 /* NOTE: latest generic point before the cpu is fully unrealized */
358 trace_fini_vcpu(cpu);
359 cpu_exec_unrealizefn(cpu);
362 static void cpu_common_initfn(Object *obj)
364 CPUState *cpu = CPU(obj);
365 CPUClass *cc = CPU_GET_CLASS(obj);
367 cpu->cpu_index = UNASSIGNED_CPU_INDEX;
368 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
369 /* *-user doesn't have configurable SMP topology */
370 /* the default value is changed by qemu_init_vcpu() for softmmu */
371 cpu->nr_cores = 1;
372 cpu->nr_threads = 1;
374 qemu_mutex_init(&cpu->work_mutex);
375 QTAILQ_INIT(&cpu->breakpoints);
376 QTAILQ_INIT(&cpu->watchpoints);
378 cpu_exec_initfn(cpu);
381 static void cpu_common_finalize(Object *obj)
385 static int64_t cpu_common_get_arch_id(CPUState *cpu)
387 return cpu->cpu_index;
390 static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
392 return addr;
395 static void generic_handle_interrupt(CPUState *cpu, int mask)
397 cpu->interrupt_request |= mask;
399 if (!qemu_cpu_is_self(cpu)) {
400 qemu_cpu_kick(cpu);
404 CPUInterruptHandler cpu_interrupt_handler = generic_handle_interrupt;
406 static void cpu_class_init(ObjectClass *klass, void *data)
408 DeviceClass *dc = DEVICE_CLASS(klass);
409 CPUClass *k = CPU_CLASS(klass);
411 k->parse_features = cpu_common_parse_features;
412 k->reset = cpu_common_reset;
413 k->get_arch_id = cpu_common_get_arch_id;
414 k->has_work = cpu_common_has_work;
415 k->get_paging_enabled = cpu_common_get_paging_enabled;
416 k->get_memory_mapping = cpu_common_get_memory_mapping;
417 k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
418 k->write_elf32_note = cpu_common_write_elf32_note;
419 k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
420 k->write_elf64_note = cpu_common_write_elf64_note;
421 k->gdb_read_register = cpu_common_gdb_read_register;
422 k->gdb_write_register = cpu_common_gdb_write_register;
423 k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
424 k->debug_excp_handler = cpu_common_noop;
425 k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
426 k->cpu_exec_enter = cpu_common_noop;
427 k->cpu_exec_exit = cpu_common_noop;
428 k->cpu_exec_interrupt = cpu_common_exec_interrupt;
429 k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
430 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
431 dc->realize = cpu_common_realizefn;
432 dc->unrealize = cpu_common_unrealizefn;
433 dc->props = cpu_common_props;
435 * Reason: CPUs still need special care by board code: wiring up
436 * IRQs, adding reset handlers, halting non-first CPUs, ...
438 dc->user_creatable = false;
441 static const TypeInfo cpu_type_info = {
442 .name = TYPE_CPU,
443 .parent = TYPE_DEVICE,
444 .instance_size = sizeof(CPUState),
445 .instance_init = cpu_common_initfn,
446 .instance_finalize = cpu_common_finalize,
447 .abstract = true,
448 .class_size = sizeof(CPUClass),
449 .class_init = cpu_class_init,
452 static void cpu_register_types(void)
454 type_register_static(&cpu_type_info);
457 type_init(cpu_register_types)