2 * PowerPC floating point and SPE emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 /*****************************************************************************/
23 /* Floating point operations helpers */
24 uint64_t helper_float32_to_float64(CPUPPCState
*env
, uint32_t arg
)
30 d
.d
= float32_to_float64(f
.f
, &env
->fp_status
);
34 uint32_t helper_float64_to_float32(CPUPPCState
*env
, uint64_t arg
)
40 f
.f
= float64_to_float32(d
.d
, &env
->fp_status
);
44 static inline int isden(float64 d
)
50 return ((u
.ll
>> 52) & 0x7FF) == 0;
53 static inline int ppc_float32_get_unbiased_exp(float32 f
)
55 return ((f
>> 23) & 0xFF) - 127;
58 static inline int ppc_float64_get_unbiased_exp(float64 f
)
60 return ((f
>> 52) & 0x7FF) - 1023;
63 uint32_t helper_compute_fprf(CPUPPCState
*env
, uint64_t arg
, uint32_t set_fprf
)
70 isneg
= float64_is_neg(farg
.d
);
71 if (unlikely(float64_is_any_nan(farg
.d
))) {
72 if (float64_is_signaling_nan(farg
.d
)) {
73 /* Signaling NaN: flags are undefined */
79 } else if (unlikely(float64_is_infinity(farg
.d
))) {
87 if (float64_is_zero(farg
.d
)) {
96 /* Denormalized numbers */
99 /* Normalized numbers */
110 /* We update FPSCR_FPRF */
111 env
->fpscr
&= ~(0x1F << FPSCR_FPRF
);
112 env
->fpscr
|= ret
<< FPSCR_FPRF
;
114 /* We just need fpcc to update Rc1 */
118 /* Floating-point invalid operations exception */
119 static inline uint64_t fload_invalid_op_excp(CPUPPCState
*env
, int op
,
122 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
128 case POWERPC_EXCP_FP_VXSNAN
:
129 env
->fpscr
|= 1 << FPSCR_VXSNAN
;
131 case POWERPC_EXCP_FP_VXSOFT
:
132 env
->fpscr
|= 1 << FPSCR_VXSOFT
;
134 case POWERPC_EXCP_FP_VXISI
:
135 /* Magnitude subtraction of infinities */
136 env
->fpscr
|= 1 << FPSCR_VXISI
;
138 case POWERPC_EXCP_FP_VXIDI
:
139 /* Division of infinity by infinity */
140 env
->fpscr
|= 1 << FPSCR_VXIDI
;
142 case POWERPC_EXCP_FP_VXZDZ
:
143 /* Division of zero by zero */
144 env
->fpscr
|= 1 << FPSCR_VXZDZ
;
146 case POWERPC_EXCP_FP_VXIMZ
:
147 /* Multiplication of zero by infinity */
148 env
->fpscr
|= 1 << FPSCR_VXIMZ
;
150 case POWERPC_EXCP_FP_VXVC
:
151 /* Ordered comparison of NaN */
152 env
->fpscr
|= 1 << FPSCR_VXVC
;
154 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
155 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
157 /* We must update the target FPR before raising the exception */
159 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
160 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_VXVC
;
161 /* Update the floating-point enabled exception summary */
162 env
->fpscr
|= 1 << FPSCR_FEX
;
163 /* Exception is differed */
167 case POWERPC_EXCP_FP_VXSQRT
:
168 /* Square root of a negative number */
169 env
->fpscr
|= 1 << FPSCR_VXSQRT
;
171 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
173 /* Set the result to quiet NaN */
174 ret
= 0x7FF8000000000000ULL
;
176 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
177 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
181 case POWERPC_EXCP_FP_VXCVI
:
182 /* Invalid conversion */
183 env
->fpscr
|= 1 << FPSCR_VXCVI
;
184 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
186 /* Set the result to quiet NaN */
187 ret
= 0x7FF8000000000000ULL
;
189 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
190 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
195 /* Update the floating-point invalid operation summary */
196 env
->fpscr
|= 1 << FPSCR_VX
;
197 /* Update the floating-point exception summary */
198 env
->fpscr
|= 1 << FPSCR_FX
;
200 /* Update the floating-point enabled exception summary */
201 env
->fpscr
|= 1 << FPSCR_FEX
;
202 if (msr_fe0
!= 0 || msr_fe1
!= 0) {
203 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
204 POWERPC_EXCP_FP
| op
);
210 static inline void float_zero_divide_excp(CPUPPCState
*env
)
212 env
->fpscr
|= 1 << FPSCR_ZX
;
213 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
214 /* Update the floating-point exception summary */
215 env
->fpscr
|= 1 << FPSCR_FX
;
217 /* Update the floating-point enabled exception summary */
218 env
->fpscr
|= 1 << FPSCR_FEX
;
219 if (msr_fe0
!= 0 || msr_fe1
!= 0) {
220 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
221 POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
);
226 static inline void float_overflow_excp(CPUPPCState
*env
)
228 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
230 env
->fpscr
|= 1 << FPSCR_OX
;
231 /* Update the floating-point exception summary */
232 env
->fpscr
|= 1 << FPSCR_FX
;
234 /* XXX: should adjust the result */
235 /* Update the floating-point enabled exception summary */
236 env
->fpscr
|= 1 << FPSCR_FEX
;
237 /* We must update the target FPR before raising the exception */
238 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
239 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
241 env
->fpscr
|= 1 << FPSCR_XX
;
242 env
->fpscr
|= 1 << FPSCR_FI
;
246 static inline void float_underflow_excp(CPUPPCState
*env
)
248 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
250 env
->fpscr
|= 1 << FPSCR_UX
;
251 /* Update the floating-point exception summary */
252 env
->fpscr
|= 1 << FPSCR_FX
;
254 /* XXX: should adjust the result */
255 /* Update the floating-point enabled exception summary */
256 env
->fpscr
|= 1 << FPSCR_FEX
;
257 /* We must update the target FPR before raising the exception */
258 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
259 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
263 static inline void float_inexact_excp(CPUPPCState
*env
)
265 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
267 env
->fpscr
|= 1 << FPSCR_XX
;
268 /* Update the floating-point exception summary */
269 env
->fpscr
|= 1 << FPSCR_FX
;
271 /* Update the floating-point enabled exception summary */
272 env
->fpscr
|= 1 << FPSCR_FEX
;
273 /* We must update the target FPR before raising the exception */
274 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
275 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
279 static inline void fpscr_set_rounding_mode(CPUPPCState
*env
)
283 /* Set rounding mode */
286 /* Best approximation (round to nearest) */
287 rnd_type
= float_round_nearest_even
;
290 /* Smaller magnitude (round toward zero) */
291 rnd_type
= float_round_to_zero
;
294 /* Round toward +infinite */
295 rnd_type
= float_round_up
;
299 /* Round toward -infinite */
300 rnd_type
= float_round_down
;
303 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
306 void helper_fpscr_clrbit(CPUPPCState
*env
, uint32_t bit
)
310 prev
= (env
->fpscr
>> bit
) & 1;
311 env
->fpscr
&= ~(1 << bit
);
316 fpscr_set_rounding_mode(env
);
324 void helper_fpscr_setbit(CPUPPCState
*env
, uint32_t bit
)
326 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
329 prev
= (env
->fpscr
>> bit
) & 1;
330 env
->fpscr
|= 1 << bit
;
334 env
->fpscr
|= 1 << FPSCR_FX
;
340 env
->fpscr
|= 1 << FPSCR_FX
;
346 env
->fpscr
|= 1 << FPSCR_FX
;
352 env
->fpscr
|= 1 << FPSCR_FX
;
358 env
->fpscr
|= 1 << FPSCR_FX
;
372 env
->fpscr
|= 1 << FPSCR_VX
;
373 env
->fpscr
|= 1 << FPSCR_FX
;
381 env
->error_code
= POWERPC_EXCP_FP
;
383 env
->error_code
|= POWERPC_EXCP_FP_VXSNAN
;
386 env
->error_code
|= POWERPC_EXCP_FP_VXISI
;
389 env
->error_code
|= POWERPC_EXCP_FP_VXIDI
;
392 env
->error_code
|= POWERPC_EXCP_FP_VXZDZ
;
395 env
->error_code
|= POWERPC_EXCP_FP_VXIMZ
;
398 env
->error_code
|= POWERPC_EXCP_FP_VXVC
;
401 env
->error_code
|= POWERPC_EXCP_FP_VXSOFT
;
404 env
->error_code
|= POWERPC_EXCP_FP_VXSQRT
;
407 env
->error_code
|= POWERPC_EXCP_FP_VXCVI
;
415 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
422 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
429 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
;
436 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
442 fpscr_set_rounding_mode(env
);
447 /* Update the floating-point enabled exception summary */
448 env
->fpscr
|= 1 << FPSCR_FEX
;
449 /* We have to update Rc1 before raising the exception */
450 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
456 void helper_store_fpscr(CPUPPCState
*env
, uint64_t arg
, uint32_t mask
)
458 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
459 target_ulong prev
, new;
463 new = (target_ulong
)arg
;
464 new &= ~0x60000000LL
;
465 new |= prev
& 0x60000000LL
;
466 for (i
= 0; i
< sizeof(target_ulong
) * 2; i
++) {
467 if (mask
& (1 << i
)) {
468 env
->fpscr
&= ~(0xFLL
<< (4 * i
));
469 env
->fpscr
|= new & (0xFLL
<< (4 * i
));
472 /* Update VX and FEX */
474 env
->fpscr
|= 1 << FPSCR_VX
;
476 env
->fpscr
&= ~(1 << FPSCR_VX
);
478 if ((fpscr_ex
& fpscr_eex
) != 0) {
479 env
->fpscr
|= 1 << FPSCR_FEX
;
480 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
481 /* XXX: we should compute it properly */
482 env
->error_code
= POWERPC_EXCP_FP
;
484 env
->fpscr
&= ~(1 << FPSCR_FEX
);
486 fpscr_set_rounding_mode(env
);
489 void store_fpscr(CPUPPCState
*env
, uint64_t arg
, uint32_t mask
)
491 helper_store_fpscr(env
, arg
, mask
);
494 void helper_float_check_status(CPUPPCState
*env
)
496 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
497 int status
= get_float_exception_flags(&env
->fp_status
);
499 if (status
& float_flag_divbyzero
) {
500 float_zero_divide_excp(env
);
501 } else if (status
& float_flag_overflow
) {
502 float_overflow_excp(env
);
503 } else if (status
& float_flag_underflow
) {
504 float_underflow_excp(env
);
505 } else if (status
& float_flag_inexact
) {
506 float_inexact_excp(env
);
509 if (cs
->exception_index
== POWERPC_EXCP_PROGRAM
&&
510 (env
->error_code
& POWERPC_EXCP_FP
)) {
511 /* Differred floating-point exception after target FPR update */
512 if (msr_fe0
!= 0 || msr_fe1
!= 0) {
513 helper_raise_exception_err(env
, cs
->exception_index
,
519 void helper_reset_fpstatus(CPUPPCState
*env
)
521 set_float_exception_flags(0, &env
->fp_status
);
525 uint64_t helper_fadd(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
)
527 CPU_DoubleU farg1
, farg2
;
532 if (unlikely(float64_is_infinity(farg1
.d
) && float64_is_infinity(farg2
.d
) &&
533 float64_is_neg(farg1
.d
) != float64_is_neg(farg2
.d
))) {
534 /* Magnitude subtraction of infinities */
535 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXISI
, 1);
537 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
538 float64_is_signaling_nan(farg2
.d
))) {
540 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
542 farg1
.d
= float64_add(farg1
.d
, farg2
.d
, &env
->fp_status
);
549 uint64_t helper_fsub(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
)
551 CPU_DoubleU farg1
, farg2
;
556 if (unlikely(float64_is_infinity(farg1
.d
) && float64_is_infinity(farg2
.d
) &&
557 float64_is_neg(farg1
.d
) == float64_is_neg(farg2
.d
))) {
558 /* Magnitude subtraction of infinities */
559 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXISI
, 1);
561 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
562 float64_is_signaling_nan(farg2
.d
))) {
563 /* sNaN subtraction */
564 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
566 farg1
.d
= float64_sub(farg1
.d
, farg2
.d
, &env
->fp_status
);
573 uint64_t helper_fmul(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
)
575 CPU_DoubleU farg1
, farg2
;
580 if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
581 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
582 /* Multiplication of zero by infinity */
583 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXIMZ
, 1);
585 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
586 float64_is_signaling_nan(farg2
.d
))) {
587 /* sNaN multiplication */
588 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
590 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
597 uint64_t helper_fdiv(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
)
599 CPU_DoubleU farg1
, farg2
;
604 if (unlikely(float64_is_infinity(farg1
.d
) &&
605 float64_is_infinity(farg2
.d
))) {
606 /* Division of infinity by infinity */
607 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXIDI
, 1);
608 } else if (unlikely(float64_is_zero(farg1
.d
) && float64_is_zero(farg2
.d
))) {
609 /* Division of zero by zero */
610 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXZDZ
, 1);
612 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
613 float64_is_signaling_nan(farg2
.d
))) {
615 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
617 farg1
.d
= float64_div(farg1
.d
, farg2
.d
, &env
->fp_status
);
624 #define FPU_FCTI(op, cvt, nanval) \
625 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
630 farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \
632 if (unlikely(env->fp_status.float_exception_flags)) { \
633 if (float64_is_any_nan(arg)) { \
634 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
635 if (float64_is_signaling_nan(arg)) { \
636 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
639 } else if (env->fp_status.float_exception_flags & \
640 float_flag_invalid) { \
641 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
643 helper_float_check_status(env); \
648 FPU_FCTI(fctiw
, int32
, 0x80000000U
)
649 FPU_FCTI(fctiwz
, int32_round_to_zero
, 0x80000000U
)
650 FPU_FCTI(fctiwu
, uint32
, 0x00000000U
)
651 FPU_FCTI(fctiwuz
, uint32_round_to_zero
, 0x00000000U
)
652 #if defined(TARGET_PPC64)
653 FPU_FCTI(fctid
, int64
, 0x8000000000000000ULL
)
654 FPU_FCTI(fctidz
, int64_round_to_zero
, 0x8000000000000000ULL
)
655 FPU_FCTI(fctidu
, uint64
, 0x0000000000000000ULL
)
656 FPU_FCTI(fctiduz
, uint64_round_to_zero
, 0x0000000000000000ULL
)
659 #if defined(TARGET_PPC64)
661 #define FPU_FCFI(op, cvtr, is_single) \
662 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
667 float32 tmp = cvtr(arg, &env->fp_status); \
668 farg.d = float32_to_float64(tmp, &env->fp_status); \
670 farg.d = cvtr(arg, &env->fp_status); \
672 helper_float_check_status(env); \
676 FPU_FCFI(fcfid
, int64_to_float64
, 0)
677 FPU_FCFI(fcfids
, int64_to_float32
, 1)
678 FPU_FCFI(fcfidu
, uint64_to_float64
, 0)
679 FPU_FCFI(fcfidus
, uint64_to_float32
, 1)
683 static inline uint64_t do_fri(CPUPPCState
*env
, uint64_t arg
,
690 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
692 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
693 farg
.ll
= arg
| 0x0008000000000000ULL
;
695 int inexact
= get_float_exception_flags(&env
->fp_status
) &
697 set_float_rounding_mode(rounding_mode
, &env
->fp_status
);
698 farg
.ll
= float64_round_to_int(farg
.d
, &env
->fp_status
);
699 /* Restore rounding mode from FPSCR */
700 fpscr_set_rounding_mode(env
);
702 /* fri* does not set FPSCR[XX] */
704 env
->fp_status
.float_exception_flags
&= ~float_flag_inexact
;
707 helper_float_check_status(env
);
711 uint64_t helper_frin(CPUPPCState
*env
, uint64_t arg
)
713 return do_fri(env
, arg
, float_round_ties_away
);
716 uint64_t helper_friz(CPUPPCState
*env
, uint64_t arg
)
718 return do_fri(env
, arg
, float_round_to_zero
);
721 uint64_t helper_frip(CPUPPCState
*env
, uint64_t arg
)
723 return do_fri(env
, arg
, float_round_up
);
726 uint64_t helper_frim(CPUPPCState
*env
, uint64_t arg
)
728 return do_fri(env
, arg
, float_round_down
);
732 uint64_t helper_fmadd(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
735 CPU_DoubleU farg1
, farg2
, farg3
;
741 if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
742 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
743 /* Multiplication of zero by infinity */
744 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXIMZ
, 1);
746 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
747 float64_is_signaling_nan(farg2
.d
) ||
748 float64_is_signaling_nan(farg3
.d
))) {
750 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
752 /* This is the way the PowerPC specification defines it */
753 float128 ft0_128
, ft1_128
;
755 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
756 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
757 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
758 if (unlikely(float128_is_infinity(ft0_128
) &&
759 float64_is_infinity(farg3
.d
) &&
760 float128_is_neg(ft0_128
) != float64_is_neg(farg3
.d
))) {
761 /* Magnitude subtraction of infinities */
762 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXISI
, 1);
764 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
765 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
766 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
774 uint64_t helper_fmsub(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
777 CPU_DoubleU farg1
, farg2
, farg3
;
783 if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
784 (float64_is_zero(farg1
.d
) &&
785 float64_is_infinity(farg2
.d
)))) {
786 /* Multiplication of zero by infinity */
787 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXIMZ
, 1);
789 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
790 float64_is_signaling_nan(farg2
.d
) ||
791 float64_is_signaling_nan(farg3
.d
))) {
793 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
795 /* This is the way the PowerPC specification defines it */
796 float128 ft0_128
, ft1_128
;
798 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
799 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
800 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
801 if (unlikely(float128_is_infinity(ft0_128
) &&
802 float64_is_infinity(farg3
.d
) &&
803 float128_is_neg(ft0_128
) == float64_is_neg(farg3
.d
))) {
804 /* Magnitude subtraction of infinities */
805 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXISI
, 1);
807 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
808 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
809 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
815 /* fnmadd - fnmadd. */
816 uint64_t helper_fnmadd(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
819 CPU_DoubleU farg1
, farg2
, farg3
;
825 if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
826 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
827 /* Multiplication of zero by infinity */
828 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXIMZ
, 1);
830 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
831 float64_is_signaling_nan(farg2
.d
) ||
832 float64_is_signaling_nan(farg3
.d
))) {
834 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
836 /* This is the way the PowerPC specification defines it */
837 float128 ft0_128
, ft1_128
;
839 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
840 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
841 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
842 if (unlikely(float128_is_infinity(ft0_128
) &&
843 float64_is_infinity(farg3
.d
) &&
844 float128_is_neg(ft0_128
) != float64_is_neg(farg3
.d
))) {
845 /* Magnitude subtraction of infinities */
846 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXISI
, 1);
848 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
849 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
850 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
852 if (likely(!float64_is_any_nan(farg1
.d
))) {
853 farg1
.d
= float64_chs(farg1
.d
);
859 /* fnmsub - fnmsub. */
860 uint64_t helper_fnmsub(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
863 CPU_DoubleU farg1
, farg2
, farg3
;
869 if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
870 (float64_is_zero(farg1
.d
) &&
871 float64_is_infinity(farg2
.d
)))) {
872 /* Multiplication of zero by infinity */
873 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXIMZ
, 1);
875 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
876 float64_is_signaling_nan(farg2
.d
) ||
877 float64_is_signaling_nan(farg3
.d
))) {
879 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
881 /* This is the way the PowerPC specification defines it */
882 float128 ft0_128
, ft1_128
;
884 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
885 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
886 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
887 if (unlikely(float128_is_infinity(ft0_128
) &&
888 float64_is_infinity(farg3
.d
) &&
889 float128_is_neg(ft0_128
) == float64_is_neg(farg3
.d
))) {
890 /* Magnitude subtraction of infinities */
891 farg1
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXISI
, 1);
893 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
894 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
895 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
897 if (likely(!float64_is_any_nan(farg1
.d
))) {
898 farg1
.d
= float64_chs(farg1
.d
);
905 uint64_t helper_frsp(CPUPPCState
*env
, uint64_t arg
)
912 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
913 /* sNaN square root */
914 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
916 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
917 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
923 uint64_t helper_fsqrt(CPUPPCState
*env
, uint64_t arg
)
929 if (unlikely(float64_is_neg(farg
.d
) && !float64_is_zero(farg
.d
))) {
930 /* Square root of a negative nonzero number */
931 farg
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSQRT
, 1);
933 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
934 /* sNaN square root */
935 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
937 farg
.d
= float64_sqrt(farg
.d
, &env
->fp_status
);
943 uint64_t helper_fre(CPUPPCState
*env
, uint64_t arg
)
949 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
950 /* sNaN reciprocal */
951 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
953 farg
.d
= float64_div(float64_one
, farg
.d
, &env
->fp_status
);
958 uint64_t helper_fres(CPUPPCState
*env
, uint64_t arg
)
965 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
966 /* sNaN reciprocal */
967 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
969 farg
.d
= float64_div(float64_one
, farg
.d
, &env
->fp_status
);
970 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
971 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
976 /* frsqrte - frsqrte. */
977 uint64_t helper_frsqrte(CPUPPCState
*env
, uint64_t arg
)
984 if (unlikely(float64_is_neg(farg
.d
) && !float64_is_zero(farg
.d
))) {
985 /* Reciprocal square root of a negative nonzero number */
986 farg
.ll
= fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSQRT
, 1);
988 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
989 /* sNaN reciprocal square root */
990 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
992 farg
.d
= float64_sqrt(farg
.d
, &env
->fp_status
);
993 farg
.d
= float64_div(float64_one
, farg
.d
, &env
->fp_status
);
994 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
995 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
1001 uint64_t helper_fsel(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
1008 if ((!float64_is_neg(farg1
.d
) || float64_is_zero(farg1
.d
)) &&
1009 !float64_is_any_nan(farg1
.d
)) {
1016 uint32_t helper_ftdiv(uint64_t fra
, uint64_t frb
)
1021 if (unlikely(float64_is_infinity(fra
) ||
1022 float64_is_infinity(frb
) ||
1023 float64_is_zero(frb
))) {
1027 int e_a
= ppc_float64_get_unbiased_exp(fra
);
1028 int e_b
= ppc_float64_get_unbiased_exp(frb
);
1030 if (unlikely(float64_is_any_nan(fra
) ||
1031 float64_is_any_nan(frb
))) {
1033 } else if ((e_b
<= -1022) || (e_b
>= 1021)) {
1035 } else if (!float64_is_zero(fra
) &&
1036 (((e_a
- e_b
) >= 1023) ||
1037 ((e_a
- e_b
) <= -1021) ||
1042 if (unlikely(float64_is_zero_or_denormal(frb
))) {
1043 /* XB is not zero because of the above check and */
1044 /* so must be denormalized. */
1049 return 0x8 | (fg_flag
? 4 : 0) | (fe_flag
? 2 : 0);
1052 uint32_t helper_ftsqrt(uint64_t frb
)
1057 if (unlikely(float64_is_infinity(frb
) || float64_is_zero(frb
))) {
1061 int e_b
= ppc_float64_get_unbiased_exp(frb
);
1063 if (unlikely(float64_is_any_nan(frb
))) {
1065 } else if (unlikely(float64_is_zero(frb
))) {
1067 } else if (unlikely(float64_is_neg(frb
))) {
1069 } else if (!float64_is_zero(frb
) && (e_b
<= (-1022+52))) {
1073 if (unlikely(float64_is_zero_or_denormal(frb
))) {
1074 /* XB is not zero because of the above check and */
1075 /* therefore must be denormalized. */
1080 return 0x8 | (fg_flag
? 4 : 0) | (fe_flag
? 2 : 0);
1083 void helper_fcmpu(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
1086 CPU_DoubleU farg1
, farg2
;
1092 if (unlikely(float64_is_any_nan(farg1
.d
) ||
1093 float64_is_any_nan(farg2
.d
))) {
1095 } else if (float64_lt(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1097 } else if (!float64_le(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1103 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1104 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1105 env
->crf
[crfD
] = ret
;
1106 if (unlikely(ret
== 0x01UL
1107 && (float64_is_signaling_nan(farg1
.d
) ||
1108 float64_is_signaling_nan(farg2
.d
)))) {
1109 /* sNaN comparison */
1110 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
, 1);
1114 void helper_fcmpo(CPUPPCState
*env
, uint64_t arg1
, uint64_t arg2
,
1117 CPU_DoubleU farg1
, farg2
;
1123 if (unlikely(float64_is_any_nan(farg1
.d
) ||
1124 float64_is_any_nan(farg2
.d
))) {
1126 } else if (float64_lt(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1128 } else if (!float64_le(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1134 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1135 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1136 env
->crf
[crfD
] = ret
;
1137 if (unlikely(ret
== 0x01UL
)) {
1138 if (float64_is_signaling_nan(farg1
.d
) ||
1139 float64_is_signaling_nan(farg2
.d
)) {
1140 /* sNaN comparison */
1141 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXSNAN
|
1142 POWERPC_EXCP_FP_VXVC
, 1);
1144 /* qNaN comparison */
1145 fload_invalid_op_excp(env
, POWERPC_EXCP_FP_VXVC
, 1);
1150 /* Single-precision floating-point conversions */
1151 static inline uint32_t efscfsi(CPUPPCState
*env
, uint32_t val
)
1155 u
.f
= int32_to_float32(val
, &env
->vec_status
);
1160 static inline uint32_t efscfui(CPUPPCState
*env
, uint32_t val
)
1164 u
.f
= uint32_to_float32(val
, &env
->vec_status
);
1169 static inline int32_t efsctsi(CPUPPCState
*env
, uint32_t val
)
1174 /* NaN are not treated the same way IEEE 754 does */
1175 if (unlikely(float32_is_quiet_nan(u
.f
))) {
1179 return float32_to_int32(u
.f
, &env
->vec_status
);
1182 static inline uint32_t efsctui(CPUPPCState
*env
, uint32_t val
)
1187 /* NaN are not treated the same way IEEE 754 does */
1188 if (unlikely(float32_is_quiet_nan(u
.f
))) {
1192 return float32_to_uint32(u
.f
, &env
->vec_status
);
1195 static inline uint32_t efsctsiz(CPUPPCState
*env
, uint32_t val
)
1200 /* NaN are not treated the same way IEEE 754 does */
1201 if (unlikely(float32_is_quiet_nan(u
.f
))) {
1205 return float32_to_int32_round_to_zero(u
.f
, &env
->vec_status
);
1208 static inline uint32_t efsctuiz(CPUPPCState
*env
, uint32_t val
)
1213 /* NaN are not treated the same way IEEE 754 does */
1214 if (unlikely(float32_is_quiet_nan(u
.f
))) {
1218 return float32_to_uint32_round_to_zero(u
.f
, &env
->vec_status
);
1221 static inline uint32_t efscfsf(CPUPPCState
*env
, uint32_t val
)
1226 u
.f
= int32_to_float32(val
, &env
->vec_status
);
1227 tmp
= int64_to_float32(1ULL << 32, &env
->vec_status
);
1228 u
.f
= float32_div(u
.f
, tmp
, &env
->vec_status
);
1233 static inline uint32_t efscfuf(CPUPPCState
*env
, uint32_t val
)
1238 u
.f
= uint32_to_float32(val
, &env
->vec_status
);
1239 tmp
= uint64_to_float32(1ULL << 32, &env
->vec_status
);
1240 u
.f
= float32_div(u
.f
, tmp
, &env
->vec_status
);
1245 static inline uint32_t efsctsf(CPUPPCState
*env
, uint32_t val
)
1251 /* NaN are not treated the same way IEEE 754 does */
1252 if (unlikely(float32_is_quiet_nan(u
.f
))) {
1255 tmp
= uint64_to_float32(1ULL << 32, &env
->vec_status
);
1256 u
.f
= float32_mul(u
.f
, tmp
, &env
->vec_status
);
1258 return float32_to_int32(u
.f
, &env
->vec_status
);
1261 static inline uint32_t efsctuf(CPUPPCState
*env
, uint32_t val
)
1267 /* NaN are not treated the same way IEEE 754 does */
1268 if (unlikely(float32_is_quiet_nan(u
.f
))) {
1271 tmp
= uint64_to_float32(1ULL << 32, &env
->vec_status
);
1272 u
.f
= float32_mul(u
.f
, tmp
, &env
->vec_status
);
1274 return float32_to_uint32(u
.f
, &env
->vec_status
);
1277 #define HELPER_SPE_SINGLE_CONV(name) \
1278 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1280 return e##name(env, val); \
1283 HELPER_SPE_SINGLE_CONV(fscfsi
);
1285 HELPER_SPE_SINGLE_CONV(fscfui
);
1287 HELPER_SPE_SINGLE_CONV(fscfuf
);
1289 HELPER_SPE_SINGLE_CONV(fscfsf
);
1291 HELPER_SPE_SINGLE_CONV(fsctsi
);
1293 HELPER_SPE_SINGLE_CONV(fsctui
);
1295 HELPER_SPE_SINGLE_CONV(fsctsiz
);
1297 HELPER_SPE_SINGLE_CONV(fsctuiz
);
1299 HELPER_SPE_SINGLE_CONV(fsctsf
);
1301 HELPER_SPE_SINGLE_CONV(fsctuf
);
1303 #define HELPER_SPE_VECTOR_CONV(name) \
1304 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1306 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1307 (uint64_t)e##name(env, val); \
1310 HELPER_SPE_VECTOR_CONV(fscfsi
);
1312 HELPER_SPE_VECTOR_CONV(fscfui
);
1314 HELPER_SPE_VECTOR_CONV(fscfuf
);
1316 HELPER_SPE_VECTOR_CONV(fscfsf
);
1318 HELPER_SPE_VECTOR_CONV(fsctsi
);
1320 HELPER_SPE_VECTOR_CONV(fsctui
);
1322 HELPER_SPE_VECTOR_CONV(fsctsiz
);
1324 HELPER_SPE_VECTOR_CONV(fsctuiz
);
1326 HELPER_SPE_VECTOR_CONV(fsctsf
);
1328 HELPER_SPE_VECTOR_CONV(fsctuf
);
1330 /* Single-precision floating-point arithmetic */
1331 static inline uint32_t efsadd(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1337 u1
.f
= float32_add(u1
.f
, u2
.f
, &env
->vec_status
);
1341 static inline uint32_t efssub(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1347 u1
.f
= float32_sub(u1
.f
, u2
.f
, &env
->vec_status
);
1351 static inline uint32_t efsmul(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1357 u1
.f
= float32_mul(u1
.f
, u2
.f
, &env
->vec_status
);
1361 static inline uint32_t efsdiv(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1367 u1
.f
= float32_div(u1
.f
, u2
.f
, &env
->vec_status
);
1371 #define HELPER_SPE_SINGLE_ARITH(name) \
1372 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1374 return e##name(env, op1, op2); \
1377 HELPER_SPE_SINGLE_ARITH(fsadd
);
1379 HELPER_SPE_SINGLE_ARITH(fssub
);
1381 HELPER_SPE_SINGLE_ARITH(fsmul
);
1383 HELPER_SPE_SINGLE_ARITH(fsdiv
);
1385 #define HELPER_SPE_VECTOR_ARITH(name) \
1386 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1388 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1389 (uint64_t)e##name(env, op1, op2); \
1392 HELPER_SPE_VECTOR_ARITH(fsadd
);
1394 HELPER_SPE_VECTOR_ARITH(fssub
);
1396 HELPER_SPE_VECTOR_ARITH(fsmul
);
1398 HELPER_SPE_VECTOR_ARITH(fsdiv
);
1400 /* Single-precision floating-point comparisons */
1401 static inline uint32_t efscmplt(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1407 return float32_lt(u1
.f
, u2
.f
, &env
->vec_status
) ? 4 : 0;
1410 static inline uint32_t efscmpgt(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1416 return float32_le(u1
.f
, u2
.f
, &env
->vec_status
) ? 0 : 4;
1419 static inline uint32_t efscmpeq(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1425 return float32_eq(u1
.f
, u2
.f
, &env
->vec_status
) ? 4 : 0;
1428 static inline uint32_t efststlt(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1430 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1431 return efscmplt(env
, op1
, op2
);
1434 static inline uint32_t efststgt(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1436 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1437 return efscmpgt(env
, op1
, op2
);
1440 static inline uint32_t efststeq(CPUPPCState
*env
, uint32_t op1
, uint32_t op2
)
1442 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1443 return efscmpeq(env
, op1
, op2
);
1446 #define HELPER_SINGLE_SPE_CMP(name) \
1447 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1449 return e##name(env, op1, op2) << 2; \
1452 HELPER_SINGLE_SPE_CMP(fststlt
);
1454 HELPER_SINGLE_SPE_CMP(fststgt
);
1456 HELPER_SINGLE_SPE_CMP(fststeq
);
1458 HELPER_SINGLE_SPE_CMP(fscmplt
);
1460 HELPER_SINGLE_SPE_CMP(fscmpgt
);
1462 HELPER_SINGLE_SPE_CMP(fscmpeq
);
1464 static inline uint32_t evcmp_merge(int t0
, int t1
)
1466 return (t0
<< 3) | (t1
<< 2) | ((t0
| t1
) << 1) | (t0
& t1
);
1469 #define HELPER_VECTOR_SPE_CMP(name) \
1470 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1472 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1473 e##name(env, op1, op2)); \
1476 HELPER_VECTOR_SPE_CMP(fststlt
);
1478 HELPER_VECTOR_SPE_CMP(fststgt
);
1480 HELPER_VECTOR_SPE_CMP(fststeq
);
1482 HELPER_VECTOR_SPE_CMP(fscmplt
);
1484 HELPER_VECTOR_SPE_CMP(fscmpgt
);
1486 HELPER_VECTOR_SPE_CMP(fscmpeq
);
1488 /* Double-precision floating-point conversion */
1489 uint64_t helper_efdcfsi(CPUPPCState
*env
, uint32_t val
)
1493 u
.d
= int32_to_float64(val
, &env
->vec_status
);
1498 uint64_t helper_efdcfsid(CPUPPCState
*env
, uint64_t val
)
1502 u
.d
= int64_to_float64(val
, &env
->vec_status
);
1507 uint64_t helper_efdcfui(CPUPPCState
*env
, uint32_t val
)
1511 u
.d
= uint32_to_float64(val
, &env
->vec_status
);
1516 uint64_t helper_efdcfuid(CPUPPCState
*env
, uint64_t val
)
1520 u
.d
= uint64_to_float64(val
, &env
->vec_status
);
1525 uint32_t helper_efdctsi(CPUPPCState
*env
, uint64_t val
)
1530 /* NaN are not treated the same way IEEE 754 does */
1531 if (unlikely(float64_is_any_nan(u
.d
))) {
1535 return float64_to_int32(u
.d
, &env
->vec_status
);
1538 uint32_t helper_efdctui(CPUPPCState
*env
, uint64_t val
)
1543 /* NaN are not treated the same way IEEE 754 does */
1544 if (unlikely(float64_is_any_nan(u
.d
))) {
1548 return float64_to_uint32(u
.d
, &env
->vec_status
);
1551 uint32_t helper_efdctsiz(CPUPPCState
*env
, uint64_t val
)
1556 /* NaN are not treated the same way IEEE 754 does */
1557 if (unlikely(float64_is_any_nan(u
.d
))) {
1561 return float64_to_int32_round_to_zero(u
.d
, &env
->vec_status
);
1564 uint64_t helper_efdctsidz(CPUPPCState
*env
, uint64_t val
)
1569 /* NaN are not treated the same way IEEE 754 does */
1570 if (unlikely(float64_is_any_nan(u
.d
))) {
1574 return float64_to_int64_round_to_zero(u
.d
, &env
->vec_status
);
1577 uint32_t helper_efdctuiz(CPUPPCState
*env
, uint64_t val
)
1582 /* NaN are not treated the same way IEEE 754 does */
1583 if (unlikely(float64_is_any_nan(u
.d
))) {
1587 return float64_to_uint32_round_to_zero(u
.d
, &env
->vec_status
);
1590 uint64_t helper_efdctuidz(CPUPPCState
*env
, uint64_t val
)
1595 /* NaN are not treated the same way IEEE 754 does */
1596 if (unlikely(float64_is_any_nan(u
.d
))) {
1600 return float64_to_uint64_round_to_zero(u
.d
, &env
->vec_status
);
1603 uint64_t helper_efdcfsf(CPUPPCState
*env
, uint32_t val
)
1608 u
.d
= int32_to_float64(val
, &env
->vec_status
);
1609 tmp
= int64_to_float64(1ULL << 32, &env
->vec_status
);
1610 u
.d
= float64_div(u
.d
, tmp
, &env
->vec_status
);
1615 uint64_t helper_efdcfuf(CPUPPCState
*env
, uint32_t val
)
1620 u
.d
= uint32_to_float64(val
, &env
->vec_status
);
1621 tmp
= int64_to_float64(1ULL << 32, &env
->vec_status
);
1622 u
.d
= float64_div(u
.d
, tmp
, &env
->vec_status
);
1627 uint32_t helper_efdctsf(CPUPPCState
*env
, uint64_t val
)
1633 /* NaN are not treated the same way IEEE 754 does */
1634 if (unlikely(float64_is_any_nan(u
.d
))) {
1637 tmp
= uint64_to_float64(1ULL << 32, &env
->vec_status
);
1638 u
.d
= float64_mul(u
.d
, tmp
, &env
->vec_status
);
1640 return float64_to_int32(u
.d
, &env
->vec_status
);
1643 uint32_t helper_efdctuf(CPUPPCState
*env
, uint64_t val
)
1649 /* NaN are not treated the same way IEEE 754 does */
1650 if (unlikely(float64_is_any_nan(u
.d
))) {
1653 tmp
= uint64_to_float64(1ULL << 32, &env
->vec_status
);
1654 u
.d
= float64_mul(u
.d
, tmp
, &env
->vec_status
);
1656 return float64_to_uint32(u
.d
, &env
->vec_status
);
1659 uint32_t helper_efscfd(CPUPPCState
*env
, uint64_t val
)
1665 u2
.f
= float64_to_float32(u1
.d
, &env
->vec_status
);
1670 uint64_t helper_efdcfs(CPUPPCState
*env
, uint32_t val
)
1676 u2
.d
= float32_to_float64(u1
.f
, &env
->vec_status
);
1681 /* Double precision fixed-point arithmetic */
1682 uint64_t helper_efdadd(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1688 u1
.d
= float64_add(u1
.d
, u2
.d
, &env
->vec_status
);
1692 uint64_t helper_efdsub(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1698 u1
.d
= float64_sub(u1
.d
, u2
.d
, &env
->vec_status
);
1702 uint64_t helper_efdmul(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1708 u1
.d
= float64_mul(u1
.d
, u2
.d
, &env
->vec_status
);
1712 uint64_t helper_efddiv(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1718 u1
.d
= float64_div(u1
.d
, u2
.d
, &env
->vec_status
);
1722 /* Double precision floating point helpers */
1723 uint32_t helper_efdtstlt(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1729 return float64_lt(u1
.d
, u2
.d
, &env
->vec_status
) ? 4 : 0;
1732 uint32_t helper_efdtstgt(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1738 return float64_le(u1
.d
, u2
.d
, &env
->vec_status
) ? 0 : 4;
1741 uint32_t helper_efdtsteq(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1747 return float64_eq_quiet(u1
.d
, u2
.d
, &env
->vec_status
) ? 4 : 0;
1750 uint32_t helper_efdcmplt(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1752 /* XXX: TODO: test special values (NaN, infinites, ...) */
1753 return helper_efdtstlt(env
, op1
, op2
);
1756 uint32_t helper_efdcmpgt(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1758 /* XXX: TODO: test special values (NaN, infinites, ...) */
1759 return helper_efdtstgt(env
, op1
, op2
);
1762 uint32_t helper_efdcmpeq(CPUPPCState
*env
, uint64_t op1
, uint64_t op2
)
1764 /* XXX: TODO: test special values (NaN, infinites, ...) */
1765 return helper_efdtsteq(env
, op1
, op2
);
1768 #define DECODE_SPLIT(opcode, shift1, nb1, shift2, nb2) \
1769 (((((opcode) >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
1770 (((opcode) >> (shift2)) & ((1 << (nb2)) - 1)))
1772 #define xT(opcode) DECODE_SPLIT(opcode, 0, 1, 21, 5)
1773 #define xA(opcode) DECODE_SPLIT(opcode, 2, 1, 16, 5)
1774 #define xB(opcode) DECODE_SPLIT(opcode, 1, 1, 11, 5)
1775 #define xC(opcode) DECODE_SPLIT(opcode, 3, 1, 6, 5)
1776 #define BF(opcode) (((opcode) >> (31-8)) & 7)
1778 typedef union _ppc_vsr_t
{
1785 static void getVSR(int n
, ppc_vsr_t
*vsr
, CPUPPCState
*env
)
1788 vsr
->f64
[0] = env
->fpr
[n
];
1789 vsr
->u64
[1] = env
->vsr
[n
];
1791 vsr
->u64
[0] = env
->avr
[n
-32].u64
[0];
1792 vsr
->u64
[1] = env
->avr
[n
-32].u64
[1];
1796 static void putVSR(int n
, ppc_vsr_t
*vsr
, CPUPPCState
*env
)
1799 env
->fpr
[n
] = vsr
->f64
[0];
1800 env
->vsr
[n
] = vsr
->u64
[1];
1802 env
->avr
[n
-32].u64
[0] = vsr
->u64
[0];
1803 env
->avr
[n
-32].u64
[1] = vsr
->u64
[1];
1807 #define float64_to_float64(x, env) x
1810 /* VSX_ADD_SUB - VSX floating point add/subract
1811 * name - instruction mnemonic
1812 * op - operation (add or sub)
1813 * nels - number of elements (1, 2 or 4)
1814 * tp - type (float32 or float64)
1815 * fld - vsr_t field (f32 or f64)
1818 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
1819 void helper_##name(CPUPPCState *env, uint32_t opcode) \
1821 ppc_vsr_t xt, xa, xb; \
1824 getVSR(xA(opcode), &xa, env); \
1825 getVSR(xB(opcode), &xb, env); \
1826 getVSR(xT(opcode), &xt, env); \
1827 helper_reset_fpstatus(env); \
1829 for (i = 0; i < nels; i++) { \
1830 float_status tstat = env->fp_status; \
1831 set_float_exception_flags(0, &tstat); \
1832 xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &tstat); \
1833 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1835 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1836 if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) {\
1837 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
1838 } else if (tp##_is_signaling_nan(xa.fld[i]) || \
1839 tp##_is_signaling_nan(xb.fld[i])) { \
1840 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1845 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
1849 helper_compute_fprf(env, xt.fld[i], sfprf); \
1852 putVSR(xT(opcode), &xt, env); \
1853 helper_float_check_status(env); \
1856 VSX_ADD_SUB(xsadddp
, add
, 1, float64
, f64
, 1, 0)
1857 VSX_ADD_SUB(xsaddsp
, add
, 1, float64
, f64
, 1, 1)
1858 VSX_ADD_SUB(xvadddp
, add
, 2, float64
, f64
, 0, 0)
1859 VSX_ADD_SUB(xvaddsp
, add
, 4, float32
, f32
, 0, 0)
1860 VSX_ADD_SUB(xssubdp
, sub
, 1, float64
, f64
, 1, 0)
1861 VSX_ADD_SUB(xssubsp
, sub
, 1, float64
, f64
, 1, 1)
1862 VSX_ADD_SUB(xvsubdp
, sub
, 2, float64
, f64
, 0, 0)
1863 VSX_ADD_SUB(xvsubsp
, sub
, 4, float32
, f32
, 0, 0)
1865 /* VSX_MUL - VSX floating point multiply
1866 * op - instruction mnemonic
1867 * nels - number of elements (1, 2 or 4)
1868 * tp - type (float32 or float64)
1869 * fld - vsr_t field (f32 or f64)
1872 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
1873 void helper_##op(CPUPPCState *env, uint32_t opcode) \
1875 ppc_vsr_t xt, xa, xb; \
1878 getVSR(xA(opcode), &xa, env); \
1879 getVSR(xB(opcode), &xb, env); \
1880 getVSR(xT(opcode), &xt, env); \
1881 helper_reset_fpstatus(env); \
1883 for (i = 0; i < nels; i++) { \
1884 float_status tstat = env->fp_status; \
1885 set_float_exception_flags(0, &tstat); \
1886 xt.fld[i] = tp##_mul(xa.fld[i], xb.fld[i], &tstat); \
1887 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1889 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1890 if ((tp##_is_infinity(xa.fld[i]) && tp##_is_zero(xb.fld[i])) || \
1891 (tp##_is_infinity(xb.fld[i]) && tp##_is_zero(xa.fld[i]))) { \
1892 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf); \
1893 } else if (tp##_is_signaling_nan(xa.fld[i]) || \
1894 tp##_is_signaling_nan(xb.fld[i])) { \
1895 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1900 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
1904 helper_compute_fprf(env, xt.fld[i], sfprf); \
1908 putVSR(xT(opcode), &xt, env); \
1909 helper_float_check_status(env); \
1912 VSX_MUL(xsmuldp
, 1, float64
, f64
, 1, 0)
1913 VSX_MUL(xsmulsp
, 1, float64
, f64
, 1, 1)
1914 VSX_MUL(xvmuldp
, 2, float64
, f64
, 0, 0)
1915 VSX_MUL(xvmulsp
, 4, float32
, f32
, 0, 0)
1917 /* VSX_DIV - VSX floating point divide
1918 * op - instruction mnemonic
1919 * nels - number of elements (1, 2 or 4)
1920 * tp - type (float32 or float64)
1921 * fld - vsr_t field (f32 or f64)
1924 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
1925 void helper_##op(CPUPPCState *env, uint32_t opcode) \
1927 ppc_vsr_t xt, xa, xb; \
1930 getVSR(xA(opcode), &xa, env); \
1931 getVSR(xB(opcode), &xb, env); \
1932 getVSR(xT(opcode), &xt, env); \
1933 helper_reset_fpstatus(env); \
1935 for (i = 0; i < nels; i++) { \
1936 float_status tstat = env->fp_status; \
1937 set_float_exception_flags(0, &tstat); \
1938 xt.fld[i] = tp##_div(xa.fld[i], xb.fld[i], &tstat); \
1939 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1941 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1942 if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) { \
1943 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf); \
1944 } else if (tp##_is_zero(xa.fld[i]) && \
1945 tp##_is_zero(xb.fld[i])) { \
1946 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \
1947 } else if (tp##_is_signaling_nan(xa.fld[i]) || \
1948 tp##_is_signaling_nan(xb.fld[i])) { \
1949 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1954 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
1958 helper_compute_fprf(env, xt.fld[i], sfprf); \
1962 putVSR(xT(opcode), &xt, env); \
1963 helper_float_check_status(env); \
1966 VSX_DIV(xsdivdp
, 1, float64
, f64
, 1, 0)
1967 VSX_DIV(xsdivsp
, 1, float64
, f64
, 1, 1)
1968 VSX_DIV(xvdivdp
, 2, float64
, f64
, 0, 0)
1969 VSX_DIV(xvdivsp
, 4, float32
, f32
, 0, 0)
1971 /* VSX_RE - VSX floating point reciprocal estimate
1972 * op - instruction mnemonic
1973 * nels - number of elements (1, 2 or 4)
1974 * tp - type (float32 or float64)
1975 * fld - vsr_t field (f32 or f64)
1978 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
1979 void helper_##op(CPUPPCState *env, uint32_t opcode) \
1984 getVSR(xB(opcode), &xb, env); \
1985 getVSR(xT(opcode), &xt, env); \
1986 helper_reset_fpstatus(env); \
1988 for (i = 0; i < nels; i++) { \
1989 if (unlikely(tp##_is_signaling_nan(xb.fld[i]))) { \
1990 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1992 xt.fld[i] = tp##_div(tp##_one, xb.fld[i], &env->fp_status); \
1995 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
1999 helper_compute_fprf(env, xt.fld[0], sfprf); \
2003 putVSR(xT(opcode), &xt, env); \
2004 helper_float_check_status(env); \
2007 VSX_RE(xsredp
, 1, float64
, f64
, 1, 0)
2008 VSX_RE(xsresp
, 1, float64
, f64
, 1, 1)
2009 VSX_RE(xvredp
, 2, float64
, f64
, 0, 0)
2010 VSX_RE(xvresp
, 4, float32
, f32
, 0, 0)
2012 /* VSX_SQRT - VSX floating point square root
2013 * op - instruction mnemonic
2014 * nels - number of elements (1, 2 or 4)
2015 * tp - type (float32 or float64)
2016 * fld - vsr_t field (f32 or f64)
2019 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
2020 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2025 getVSR(xB(opcode), &xb, env); \
2026 getVSR(xT(opcode), &xt, env); \
2027 helper_reset_fpstatus(env); \
2029 for (i = 0; i < nels; i++) { \
2030 float_status tstat = env->fp_status; \
2031 set_float_exception_flags(0, &tstat); \
2032 xt.fld[i] = tp##_sqrt(xb.fld[i], &tstat); \
2033 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2035 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2036 if (tp##_is_neg(xb.fld[i]) && !tp##_is_zero(xb.fld[i])) { \
2037 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
2038 } else if (tp##_is_signaling_nan(xb.fld[i])) { \
2039 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
2044 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
2048 helper_compute_fprf(env, xt.fld[i], sfprf); \
2052 putVSR(xT(opcode), &xt, env); \
2053 helper_float_check_status(env); \
2056 VSX_SQRT(xssqrtdp
, 1, float64
, f64
, 1, 0)
2057 VSX_SQRT(xssqrtsp
, 1, float64
, f64
, 1, 1)
2058 VSX_SQRT(xvsqrtdp
, 2, float64
, f64
, 0, 0)
2059 VSX_SQRT(xvsqrtsp
, 4, float32
, f32
, 0, 0)
2061 /* VSX_RSQRTE - VSX floating point reciprocal square root estimate
2062 * op - instruction mnemonic
2063 * nels - number of elements (1, 2 or 4)
2064 * tp - type (float32 or float64)
2065 * fld - vsr_t field (f32 or f64)
2068 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
2069 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2074 getVSR(xB(opcode), &xb, env); \
2075 getVSR(xT(opcode), &xt, env); \
2076 helper_reset_fpstatus(env); \
2078 for (i = 0; i < nels; i++) { \
2079 float_status tstat = env->fp_status; \
2080 set_float_exception_flags(0, &tstat); \
2081 xt.fld[i] = tp##_sqrt(xb.fld[i], &tstat); \
2082 xt.fld[i] = tp##_div(tp##_one, xt.fld[i], &tstat); \
2083 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2085 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2086 if (tp##_is_neg(xb.fld[i]) && !tp##_is_zero(xb.fld[i])) { \
2087 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
2088 } else if (tp##_is_signaling_nan(xb.fld[i])) { \
2089 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
2094 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
2098 helper_compute_fprf(env, xt.fld[i], sfprf); \
2102 putVSR(xT(opcode), &xt, env); \
2103 helper_float_check_status(env); \
2106 VSX_RSQRTE(xsrsqrtedp
, 1, float64
, f64
, 1, 0)
2107 VSX_RSQRTE(xsrsqrtesp
, 1, float64
, f64
, 1, 1)
2108 VSX_RSQRTE(xvrsqrtedp
, 2, float64
, f64
, 0, 0)
2109 VSX_RSQRTE(xvrsqrtesp
, 4, float32
, f32
, 0, 0)
2111 /* VSX_TDIV - VSX floating point test for divide
2112 * op - instruction mnemonic
2113 * nels - number of elements (1, 2 or 4)
2114 * tp - type (float32 or float64)
2115 * fld - vsr_t field (f32 or f64)
2116 * emin - minimum unbiased exponent
2117 * emax - maximum unbiased exponent
2118 * nbits - number of fraction bits
2120 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
2121 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2128 getVSR(xA(opcode), &xa, env); \
2129 getVSR(xB(opcode), &xb, env); \
2131 for (i = 0; i < nels; i++) { \
2132 if (unlikely(tp##_is_infinity(xa.fld[i]) || \
2133 tp##_is_infinity(xb.fld[i]) || \
2134 tp##_is_zero(xb.fld[i]))) { \
2138 int e_a = ppc_##tp##_get_unbiased_exp(xa.fld[i]); \
2139 int e_b = ppc_##tp##_get_unbiased_exp(xb.fld[i]); \
2141 if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
2142 tp##_is_any_nan(xb.fld[i]))) { \
2144 } else if ((e_b <= emin) || (e_b >= (emax-2))) { \
2146 } else if (!tp##_is_zero(xa.fld[i]) && \
2147 (((e_a - e_b) >= emax) || \
2148 ((e_a - e_b) <= (emin+1)) || \
2149 (e_a <= (emin+nbits)))) { \
2153 if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) { \
2154 /* XB is not zero because of the above check and */ \
2155 /* so must be denormalized. */ \
2161 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2164 VSX_TDIV(xstdivdp
, 1, float64
, f64
, -1022, 1023, 52)
2165 VSX_TDIV(xvtdivdp
, 2, float64
, f64
, -1022, 1023, 52)
2166 VSX_TDIV(xvtdivsp
, 4, float32
, f32
, -126, 127, 23)
2168 /* VSX_TSQRT - VSX floating point test for square root
2169 * op - instruction mnemonic
2170 * nels - number of elements (1, 2 or 4)
2171 * tp - type (float32 or float64)
2172 * fld - vsr_t field (f32 or f64)
2173 * emin - minimum unbiased exponent
2174 * emax - maximum unbiased exponent
2175 * nbits - number of fraction bits
2177 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
2178 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2185 getVSR(xA(opcode), &xa, env); \
2186 getVSR(xB(opcode), &xb, env); \
2188 for (i = 0; i < nels; i++) { \
2189 if (unlikely(tp##_is_infinity(xb.fld[i]) || \
2190 tp##_is_zero(xb.fld[i]))) { \
2194 int e_b = ppc_##tp##_get_unbiased_exp(xb.fld[i]); \
2196 if (unlikely(tp##_is_any_nan(xb.fld[i]))) { \
2198 } else if (unlikely(tp##_is_zero(xb.fld[i]))) { \
2200 } else if (unlikely(tp##_is_neg(xb.fld[i]))) { \
2202 } else if (!tp##_is_zero(xb.fld[i]) && \
2203 (e_b <= (emin+nbits))) { \
2207 if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) { \
2208 /* XB is not zero because of the above check and */ \
2209 /* therefore must be denormalized. */ \
2215 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2218 VSX_TSQRT(xstsqrtdp
, 1, float64
, f64
, -1022, 52)
2219 VSX_TSQRT(xvtsqrtdp
, 2, float64
, f64
, -1022, 52)
2220 VSX_TSQRT(xvtsqrtsp
, 4, float32
, f32
, -126, 23)
2222 /* VSX_MADD - VSX floating point muliply/add variations
2223 * op - instruction mnemonic
2224 * nels - number of elements (1, 2 or 4)
2225 * tp - type (float32 or float64)
2226 * fld - vsr_t field (f32 or f64)
2227 * maddflgs - flags for the float*muladd routine that control the
2228 * various forms (madd, msub, nmadd, nmsub)
2229 * afrm - A form (1=A, 0=M)
2232 #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp) \
2233 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2235 ppc_vsr_t xt_in, xa, xb, xt_out; \
2239 if (afrm) { /* AxB + T */ \
2242 } else { /* AxT + B */ \
2247 getVSR(xA(opcode), &xa, env); \
2248 getVSR(xB(opcode), &xb, env); \
2249 getVSR(xT(opcode), &xt_in, env); \
2253 helper_reset_fpstatus(env); \
2255 for (i = 0; i < nels; i++) { \
2256 float_status tstat = env->fp_status; \
2257 set_float_exception_flags(0, &tstat); \
2258 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2259 /* Avoid double rounding errors by rounding the intermediate */ \
2260 /* result to odd. */ \
2261 set_float_rounding_mode(float_round_to_zero, &tstat); \
2262 xt_out.fld[i] = tp##_muladd(xa.fld[i], b->fld[i], c->fld[i], \
2263 maddflgs, &tstat); \
2264 xt_out.fld[i] |= (get_float_exception_flags(&tstat) & \
2265 float_flag_inexact) != 0; \
2267 xt_out.fld[i] = tp##_muladd(xa.fld[i], b->fld[i], c->fld[i], \
2268 maddflgs, &tstat); \
2270 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2272 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2273 if (tp##_is_signaling_nan(xa.fld[i]) || \
2274 tp##_is_signaling_nan(b->fld[i]) || \
2275 tp##_is_signaling_nan(c->fld[i])) { \
2276 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
2277 tstat.float_exception_flags &= ~float_flag_invalid; \
2279 if ((tp##_is_infinity(xa.fld[i]) && tp##_is_zero(b->fld[i])) || \
2280 (tp##_is_zero(xa.fld[i]) && tp##_is_infinity(b->fld[i]))) { \
2281 xt_out.fld[i] = float64_to_##tp(fload_invalid_op_excp(env, \
2282 POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status); \
2283 tstat.float_exception_flags &= ~float_flag_invalid; \
2285 if ((tstat.float_exception_flags & float_flag_invalid) && \
2286 ((tp##_is_infinity(xa.fld[i]) || \
2287 tp##_is_infinity(b->fld[i])) && \
2288 tp##_is_infinity(c->fld[i]))) { \
2289 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
2294 xt_out.fld[i] = helper_frsp(env, xt_out.fld[i]); \
2298 helper_compute_fprf(env, xt_out.fld[i], sfprf); \
2301 putVSR(xT(opcode), &xt_out, env); \
2302 helper_float_check_status(env); \
2306 #define MSUB_FLGS float_muladd_negate_c
2307 #define NMADD_FLGS float_muladd_negate_result
2308 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
2310 VSX_MADD(xsmaddadp
, 1, float64
, f64
, MADD_FLGS
, 1, 1, 0)
2311 VSX_MADD(xsmaddmdp
, 1, float64
, f64
, MADD_FLGS
, 0, 1, 0)
2312 VSX_MADD(xsmsubadp
, 1, float64
, f64
, MSUB_FLGS
, 1, 1, 0)
2313 VSX_MADD(xsmsubmdp
, 1, float64
, f64
, MSUB_FLGS
, 0, 1, 0)
2314 VSX_MADD(xsnmaddadp
, 1, float64
, f64
, NMADD_FLGS
, 1, 1, 0)
2315 VSX_MADD(xsnmaddmdp
, 1, float64
, f64
, NMADD_FLGS
, 0, 1, 0)
2316 VSX_MADD(xsnmsubadp
, 1, float64
, f64
, NMSUB_FLGS
, 1, 1, 0)
2317 VSX_MADD(xsnmsubmdp
, 1, float64
, f64
, NMSUB_FLGS
, 0, 1, 0)
2319 VSX_MADD(xsmaddasp
, 1, float64
, f64
, MADD_FLGS
, 1, 1, 1)
2320 VSX_MADD(xsmaddmsp
, 1, float64
, f64
, MADD_FLGS
, 0, 1, 1)
2321 VSX_MADD(xsmsubasp
, 1, float64
, f64
, MSUB_FLGS
, 1, 1, 1)
2322 VSX_MADD(xsmsubmsp
, 1, float64
, f64
, MSUB_FLGS
, 0, 1, 1)
2323 VSX_MADD(xsnmaddasp
, 1, float64
, f64
, NMADD_FLGS
, 1, 1, 1)
2324 VSX_MADD(xsnmaddmsp
, 1, float64
, f64
, NMADD_FLGS
, 0, 1, 1)
2325 VSX_MADD(xsnmsubasp
, 1, float64
, f64
, NMSUB_FLGS
, 1, 1, 1)
2326 VSX_MADD(xsnmsubmsp
, 1, float64
, f64
, NMSUB_FLGS
, 0, 1, 1)
2328 VSX_MADD(xvmaddadp
, 2, float64
, f64
, MADD_FLGS
, 1, 0, 0)
2329 VSX_MADD(xvmaddmdp
, 2, float64
, f64
, MADD_FLGS
, 0, 0, 0)
2330 VSX_MADD(xvmsubadp
, 2, float64
, f64
, MSUB_FLGS
, 1, 0, 0)
2331 VSX_MADD(xvmsubmdp
, 2, float64
, f64
, MSUB_FLGS
, 0, 0, 0)
2332 VSX_MADD(xvnmaddadp
, 2, float64
, f64
, NMADD_FLGS
, 1, 0, 0)
2333 VSX_MADD(xvnmaddmdp
, 2, float64
, f64
, NMADD_FLGS
, 0, 0, 0)
2334 VSX_MADD(xvnmsubadp
, 2, float64
, f64
, NMSUB_FLGS
, 1, 0, 0)
2335 VSX_MADD(xvnmsubmdp
, 2, float64
, f64
, NMSUB_FLGS
, 0, 0, 0)
2337 VSX_MADD(xvmaddasp
, 4, float32
, f32
, MADD_FLGS
, 1, 0, 0)
2338 VSX_MADD(xvmaddmsp
, 4, float32
, f32
, MADD_FLGS
, 0, 0, 0)
2339 VSX_MADD(xvmsubasp
, 4, float32
, f32
, MSUB_FLGS
, 1, 0, 0)
2340 VSX_MADD(xvmsubmsp
, 4, float32
, f32
, MSUB_FLGS
, 0, 0, 0)
2341 VSX_MADD(xvnmaddasp
, 4, float32
, f32
, NMADD_FLGS
, 1, 0, 0)
2342 VSX_MADD(xvnmaddmsp
, 4, float32
, f32
, NMADD_FLGS
, 0, 0, 0)
2343 VSX_MADD(xvnmsubasp
, 4, float32
, f32
, NMSUB_FLGS
, 1, 0, 0)
2344 VSX_MADD(xvnmsubmsp
, 4, float32
, f32
, NMSUB_FLGS
, 0, 0, 0)
2346 #define VSX_SCALAR_CMP(op, ordered) \
2347 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2352 getVSR(xA(opcode), &xa, env); \
2353 getVSR(xB(opcode), &xb, env); \
2355 if (unlikely(float64_is_any_nan(xa.f64[0]) || \
2356 float64_is_any_nan(xb.f64[0]))) { \
2357 if (float64_is_signaling_nan(xa.f64[0]) || \
2358 float64_is_signaling_nan(xb.f64[0])) { \
2359 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2362 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
2366 if (float64_lt(xa.f64[0], xb.f64[0], &env->fp_status)) { \
2368 } else if (!float64_le(xa.f64[0], xb.f64[0], &env->fp_status)) { \
2375 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
2376 env->fpscr |= cc << FPSCR_FPRF; \
2377 env->crf[BF(opcode)] = cc; \
2379 helper_float_check_status(env); \
2382 VSX_SCALAR_CMP(xscmpodp
, 1)
2383 VSX_SCALAR_CMP(xscmpudp
, 0)
2385 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
2386 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
2388 /* VSX_MAX_MIN - VSX floating point maximum/minimum
2389 * name - instruction mnemonic
2390 * op - operation (max or min)
2391 * nels - number of elements (1, 2 or 4)
2392 * tp - type (float32 or float64)
2393 * fld - vsr_t field (f32 or f64)
2395 #define VSX_MAX_MIN(name, op, nels, tp, fld) \
2396 void helper_##name(CPUPPCState *env, uint32_t opcode) \
2398 ppc_vsr_t xt, xa, xb; \
2401 getVSR(xA(opcode), &xa, env); \
2402 getVSR(xB(opcode), &xb, env); \
2403 getVSR(xT(opcode), &xt, env); \
2405 for (i = 0; i < nels; i++) { \
2406 xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &env->fp_status); \
2407 if (unlikely(tp##_is_signaling_nan(xa.fld[i]) || \
2408 tp##_is_signaling_nan(xb.fld[i]))) { \
2409 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2413 putVSR(xT(opcode), &xt, env); \
2414 helper_float_check_status(env); \
2417 VSX_MAX_MIN(xsmaxdp
, maxnum
, 1, float64
, f64
)
2418 VSX_MAX_MIN(xvmaxdp
, maxnum
, 2, float64
, f64
)
2419 VSX_MAX_MIN(xvmaxsp
, maxnum
, 4, float32
, f32
)
2420 VSX_MAX_MIN(xsmindp
, minnum
, 1, float64
, f64
)
2421 VSX_MAX_MIN(xvmindp
, minnum
, 2, float64
, f64
)
2422 VSX_MAX_MIN(xvminsp
, minnum
, 4, float32
, f32
)
2424 /* VSX_CMP - VSX floating point compare
2425 * op - instruction mnemonic
2426 * nels - number of elements (1, 2 or 4)
2427 * tp - type (float32 or float64)
2428 * fld - vsr_t field (f32 or f64)
2429 * cmp - comparison operation
2430 * svxvc - set VXVC bit
2432 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc) \
2433 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2435 ppc_vsr_t xt, xa, xb; \
2438 int all_false = 1; \
2440 getVSR(xA(opcode), &xa, env); \
2441 getVSR(xB(opcode), &xb, env); \
2442 getVSR(xT(opcode), &xt, env); \
2444 for (i = 0; i < nels; i++) { \
2445 if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
2446 tp##_is_any_nan(xb.fld[i]))) { \
2447 if (tp##_is_signaling_nan(xa.fld[i]) || \
2448 tp##_is_signaling_nan(xb.fld[i])) { \
2449 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2452 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
2457 if (tp##_##cmp(xb.fld[i], xa.fld[i], &env->fp_status) == 1) { \
2467 putVSR(xT(opcode), &xt, env); \
2468 if ((opcode >> (31-21)) & 1) { \
2469 env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2471 helper_float_check_status(env); \
2474 VSX_CMP(xvcmpeqdp
, 2, float64
, f64
, eq
, 0)
2475 VSX_CMP(xvcmpgedp
, 2, float64
, f64
, le
, 1)
2476 VSX_CMP(xvcmpgtdp
, 2, float64
, f64
, lt
, 1)
2477 VSX_CMP(xvcmpeqsp
, 4, float32
, f32
, eq
, 0)
2478 VSX_CMP(xvcmpgesp
, 4, float32
, f32
, le
, 1)
2479 VSX_CMP(xvcmpgtsp
, 4, float32
, f32
, lt
, 1)
2481 #if defined(HOST_WORDS_BIGENDIAN)
2487 /* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2488 * op - instruction mnemonic
2489 * nels - number of elements (1, 2 or 4)
2490 * stp - source type (float32 or float64)
2491 * ttp - target type (float32 or float64)
2492 * sfld - source vsr_t field
2493 * tfld - target vsr_t field (f32 or f64)
2496 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2497 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2502 getVSR(xB(opcode), &xb, env); \
2503 getVSR(xT(opcode), &xt, env); \
2505 for (i = 0; i < nels; i++) { \
2506 int j = 2*i + JOFFSET; \
2507 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
2508 if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \
2509 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2510 xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
2513 helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \
2514 &env->fp_status), sfprf); \
2518 putVSR(xT(opcode), &xt, env); \
2519 helper_float_check_status(env); \
2522 VSX_CVT_FP_TO_FP(xscvdpsp
, 1, float64
, float32
, f64
[i
], f32
[j
], 1)
2523 VSX_CVT_FP_TO_FP(xscvspdp
, 1, float32
, float64
, f32
[j
], f64
[i
], 1)
2524 VSX_CVT_FP_TO_FP(xvcvdpsp
, 2, float64
, float32
, f64
[i
], f32
[j
], 0)
2525 VSX_CVT_FP_TO_FP(xvcvspdp
, 2, float32
, float64
, f32
[j
], f64
[i
], 0)
2527 uint64_t helper_xscvdpspn(CPUPPCState
*env
, uint64_t xb
)
2529 float_status tstat
= env
->fp_status
;
2530 set_float_exception_flags(0, &tstat
);
2532 return (uint64_t)float64_to_float32(xb
, &tstat
) << 32;
2535 uint64_t helper_xscvspdpn(CPUPPCState
*env
, uint64_t xb
)
2537 float_status tstat
= env
->fp_status
;
2538 set_float_exception_flags(0, &tstat
);
2540 return float32_to_float64(xb
>> 32, &tstat
);
2543 /* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2544 * op - instruction mnemonic
2545 * nels - number of elements (1, 2 or 4)
2546 * stp - source type (float32 or float64)
2547 * ttp - target type (int32, uint32, int64 or uint64)
2548 * sfld - source vsr_t field
2549 * tfld - target vsr_t field
2550 * jdef - definition of the j index (i or 2*i)
2551 * rnan - resulting NaN
2553 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, jdef, rnan) \
2554 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2559 getVSR(xB(opcode), &xb, env); \
2560 getVSR(xT(opcode), &xt, env); \
2562 for (i = 0; i < nels; i++) { \
2564 if (unlikely(stp##_is_any_nan(xb.sfld))) { \
2565 if (stp##_is_signaling_nan(xb.sfld)) { \
2566 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2568 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
2571 xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \
2573 if (env->fp_status.float_exception_flags & float_flag_invalid) { \
2574 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
2579 putVSR(xT(opcode), &xt, env); \
2580 helper_float_check_status(env); \
2583 VSX_CVT_FP_TO_INT(xscvdpsxds
, 1, float64
, int64
, f64
[j
], u64
[i
], i
, \
2584 0x8000000000000000ULL
)
2585 VSX_CVT_FP_TO_INT(xscvdpsxws
, 1, float64
, int32
, f64
[i
], u32
[j
], \
2586 2*i
+ JOFFSET
, 0x80000000U
)
2587 VSX_CVT_FP_TO_INT(xscvdpuxds
, 1, float64
, uint64
, f64
[j
], u64
[i
], i
, 0ULL)
2588 VSX_CVT_FP_TO_INT(xscvdpuxws
, 1, float64
, uint32
, f64
[i
], u32
[j
], \
2590 VSX_CVT_FP_TO_INT(xvcvdpsxds
, 2, float64
, int64
, f64
[j
], u64
[i
], i
, \
2591 0x8000000000000000ULL
)
2592 VSX_CVT_FP_TO_INT(xvcvdpsxws
, 2, float64
, int32
, f64
[i
], u32
[j
], \
2593 2*i
+ JOFFSET
, 0x80000000U
)
2594 VSX_CVT_FP_TO_INT(xvcvdpuxds
, 2, float64
, uint64
, f64
[j
], u64
[i
], i
, 0ULL)
2595 VSX_CVT_FP_TO_INT(xvcvdpuxws
, 2, float64
, uint32
, f64
[i
], u32
[j
], \
2597 VSX_CVT_FP_TO_INT(xvcvspsxds
, 2, float32
, int64
, f32
[j
], u64
[i
], \
2598 2*i
+ JOFFSET
, 0x8000000000000000ULL
)
2599 VSX_CVT_FP_TO_INT(xvcvspsxws
, 4, float32
, int32
, f32
[j
], u32
[j
], i
, \
2601 VSX_CVT_FP_TO_INT(xvcvspuxds
, 2, float32
, uint64
, f32
[j
], u64
[i
], \
2602 2*i
+ JOFFSET
, 0ULL)
2603 VSX_CVT_FP_TO_INT(xvcvspuxws
, 4, float32
, uint32
, f32
[j
], u32
[i
], i
, 0U)
2605 /* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2606 * op - instruction mnemonic
2607 * nels - number of elements (1, 2 or 4)
2608 * stp - source type (int32, uint32, int64 or uint64)
2609 * ttp - target type (float32 or float64)
2610 * sfld - source vsr_t field
2611 * tfld - target vsr_t field
2612 * jdef - definition of the j index (i or 2*i)
2615 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, jdef, sfprf, r2sp) \
2616 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2621 getVSR(xB(opcode), &xb, env); \
2622 getVSR(xT(opcode), &xt, env); \
2624 for (i = 0; i < nels; i++) { \
2626 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
2628 xt.tfld = helper_frsp(env, xt.tfld); \
2631 helper_compute_fprf(env, xt.tfld, sfprf); \
2635 putVSR(xT(opcode), &xt, env); \
2636 helper_float_check_status(env); \
2639 VSX_CVT_INT_TO_FP(xscvsxddp
, 1, int64
, float64
, u64
[j
], f64
[i
], i
, 1, 0)
2640 VSX_CVT_INT_TO_FP(xscvuxddp
, 1, uint64
, float64
, u64
[j
], f64
[i
], i
, 1, 0)
2641 VSX_CVT_INT_TO_FP(xscvsxdsp
, 1, int64
, float64
, u64
[j
], f64
[i
], i
, 1, 1)
2642 VSX_CVT_INT_TO_FP(xscvuxdsp
, 1, uint64
, float64
, u64
[j
], f64
[i
], i
, 1, 1)
2643 VSX_CVT_INT_TO_FP(xvcvsxddp
, 2, int64
, float64
, u64
[j
], f64
[i
], i
, 0, 0)
2644 VSX_CVT_INT_TO_FP(xvcvuxddp
, 2, uint64
, float64
, u64
[j
], f64
[i
], i
, 0, 0)
2645 VSX_CVT_INT_TO_FP(xvcvsxwdp
, 2, int32
, float64
, u32
[j
], f64
[i
], \
2646 2*i
+ JOFFSET
, 0, 0)
2647 VSX_CVT_INT_TO_FP(xvcvuxwdp
, 2, uint64
, float64
, u32
[j
], f64
[i
], \
2648 2*i
+ JOFFSET
, 0, 0)
2649 VSX_CVT_INT_TO_FP(xvcvsxdsp
, 2, int64
, float32
, u64
[i
], f32
[j
], \
2650 2*i
+ JOFFSET
, 0, 0)
2651 VSX_CVT_INT_TO_FP(xvcvuxdsp
, 2, uint64
, float32
, u64
[i
], f32
[j
], \
2652 2*i
+ JOFFSET
, 0, 0)
2653 VSX_CVT_INT_TO_FP(xvcvsxwsp
, 4, int32
, float32
, u32
[j
], f32
[i
], i
, 0, 0)
2654 VSX_CVT_INT_TO_FP(xvcvuxwsp
, 4, uint32
, float32
, u32
[j
], f32
[i
], i
, 0, 0)
2656 /* For "use current rounding mode", define a value that will not be one of
2657 * the existing rounding model enums.
2659 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
2660 float_round_up + float_round_to_zero)
2662 /* VSX_ROUND - VSX floating point round
2663 * op - instruction mnemonic
2664 * nels - number of elements (1, 2 or 4)
2665 * tp - type (float32 or float64)
2666 * fld - vsr_t field (f32 or f64)
2667 * rmode - rounding mode
2670 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
2671 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2675 getVSR(xB(opcode), &xb, env); \
2676 getVSR(xT(opcode), &xt, env); \
2678 if (rmode != FLOAT_ROUND_CURRENT) { \
2679 set_float_rounding_mode(rmode, &env->fp_status); \
2682 for (i = 0; i < nels; i++) { \
2683 if (unlikely(tp##_is_signaling_nan(xb.fld[i]))) { \
2684 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2685 xt.fld[i] = tp##_snan_to_qnan(xb.fld[i]); \
2687 xt.fld[i] = tp##_round_to_int(xb.fld[i], &env->fp_status); \
2690 helper_compute_fprf(env, xt.fld[i], sfprf); \
2694 /* If this is not a "use current rounding mode" instruction, \
2695 * then inhibit setting of the XX bit and restore rounding \
2696 * mode from FPSCR */ \
2697 if (rmode != FLOAT_ROUND_CURRENT) { \
2698 fpscr_set_rounding_mode(env); \
2699 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
2702 putVSR(xT(opcode), &xt, env); \
2703 helper_float_check_status(env); \
2706 VSX_ROUND(xsrdpi
, 1, float64
, f64
, float_round_nearest_even
, 1)
2707 VSX_ROUND(xsrdpic
, 1, float64
, f64
, FLOAT_ROUND_CURRENT
, 1)
2708 VSX_ROUND(xsrdpim
, 1, float64
, f64
, float_round_down
, 1)
2709 VSX_ROUND(xsrdpip
, 1, float64
, f64
, float_round_up
, 1)
2710 VSX_ROUND(xsrdpiz
, 1, float64
, f64
, float_round_to_zero
, 1)
2712 VSX_ROUND(xvrdpi
, 2, float64
, f64
, float_round_nearest_even
, 0)
2713 VSX_ROUND(xvrdpic
, 2, float64
, f64
, FLOAT_ROUND_CURRENT
, 0)
2714 VSX_ROUND(xvrdpim
, 2, float64
, f64
, float_round_down
, 0)
2715 VSX_ROUND(xvrdpip
, 2, float64
, f64
, float_round_up
, 0)
2716 VSX_ROUND(xvrdpiz
, 2, float64
, f64
, float_round_to_zero
, 0)
2718 VSX_ROUND(xvrspi
, 4, float32
, f32
, float_round_nearest_even
, 0)
2719 VSX_ROUND(xvrspic
, 4, float32
, f32
, FLOAT_ROUND_CURRENT
, 0)
2720 VSX_ROUND(xvrspim
, 4, float32
, f32
, float_round_down
, 0)
2721 VSX_ROUND(xvrspip
, 4, float32
, f32
, float_round_up
, 0)
2722 VSX_ROUND(xvrspiz
, 4, float32
, f32
, float_round_to_zero
, 0)
2724 uint64_t helper_xsrsp(CPUPPCState
*env
, uint64_t xb
)
2726 helper_reset_fpstatus(env
);
2728 uint64_t xt
= helper_frsp(env
, xb
);
2730 helper_compute_fprf(env
, xt
, 1);
2731 helper_float_check_status(env
);