target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     return cs->interrupt_request &
  44         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
  45 }
  46
  47 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  48 {
  49     /* Reset a single ARMCPRegInfo register */
  50     ARMCPRegInfo *ri = value;
  51     ARMCPU *cpu = opaque;
  52
  53     if (ri->type & ARM_CP_SPECIAL) {
  54         return;
  55     }
  56
  57     if (ri->resetfn) {
  58         ri->resetfn(&cpu->env, ri);
  59         return;
  60     }
  61
  62     /* A zero offset is never possible as it would be regs[0]
  63      * so we use it to indicate that reset is being handled elsewhere.
  64      * This is basically only used for fields in non-core coprocessors
  65      * (like the pxa2xx ones).
  66      */
  67     if (!ri->fieldoffset) {
  68         return;
  69     }
  70
  71     if (cpreg_field_is_64bit(ri)) {
  72         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  73     } else {
  74         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  75     }
  76 }
  77
  78 /* CPUClass::reset() */
  79 static void arm_cpu_reset(CPUState *s)
  80 {
  81     ARMCPU *cpu = ARM_CPU(s);
  82     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  83     CPUARMState *env = &cpu->env;
  84
  85     acc->parent_reset(s);
  86
  87     memset(env, 0, offsetof(CPUARMState, features));
  88     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  89     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  90     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  91     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  92     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  93
  94     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  95         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  96     }
  97
  98     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  99         /* 64 bit CPUs always start in 64 bit mode */
 100         env->aarch64 = 1;
 101 #if defined(CONFIG_USER_ONLY)
 102         env->pstate = PSTATE_MODE_EL0t;
 103         /* Userspace expects access to CTL_EL0 and the cache ops */
 104         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 105         /* and to the FP/Neon instructions */
 106         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 107 #else
 108         env->pstate = PSTATE_MODE_EL1h;
 109         env->pc = cpu->rvbar;
 110 #endif
 111     } else {
 112 #if defined(CONFIG_USER_ONLY)
 113         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 115 #endif
 116     }
 117
 118 #if defined(CONFIG_USER_ONLY)
 119     env->uncached_cpsr = ARM_CPU_MODE_USR;
 120     /* For user mode we must enable access to coprocessors */
 121     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 122     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 123         env->cp15.c15_cpar = 3;
 124     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 125         env->cp15.c15_cpar = 1;
 126     }
 127 #else
 128     /* SVC mode with interrupts disabled.  */
 129     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 130     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 131     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 132      * clear at reset. Initial SP and PC are loaded from ROM.
 133      */
 134     if (IS_M(env)) {
 135         uint32_t initial_msp; /* Loaded from 0x0 */
 136         uint32_t initial_pc; /* Loaded from 0x4 */
 137         uint8_t *rom;
 138
 139         env->daif &= ~PSTATE_I;
 140         rom = rom_ptr(0);
 141         if (rom) {
 142             /* Address zero is covered by ROM which hasn't yet been
 143              * copied into physical memory.
 144              */
 145             initial_msp = ldl_p(rom);
 146             initial_pc = ldl_p(rom + 4);
 147         } else {
 148             /* Address zero not covered by a ROM blob, or the ROM blob
 149              * is in non-modifiable memory and this is a second reset after
 150              * it got copied into memory. In the latter case, rom_ptr
 151              * will return a NULL pointer and we should use ldl_phys instead.
 152              */
 153             initial_msp = ldl_phys(s->as, 0);
 154             initial_pc = ldl_phys(s->as, 4);
 155         }
 156
 157         env->regs[13] = initial_msp & 0xFFFFFFFC;
 158         env->regs[15] = initial_pc & ~1;
 159         env->thumb = initial_pc & 1;
 160     }
 161
 162     if (env->cp15.c1_sys & SCTLR_V) {
 163         env->regs[15] = 0xFFFF0000;
 164     }
 165
 166     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 167 #endif
 168     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 169     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 170     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 171     set_float_detect_tininess(float_tininess_before_rounding,
 172                               &env->vfp.fp_status);
 173     set_float_detect_tininess(float_tininess_before_rounding,
 174                               &env->vfp.standard_fp_status);
 175     tlb_flush(s, 1);
 176
 177 #ifndef CONFIG_USER_ONLY
 178     if (kvm_enabled()) {
 179         kvm_arm_reset_vcpu(cpu);
 180     }
 181 #endif
 182
 183     hw_breakpoint_update_all(cpu);
 184     hw_watchpoint_update_all(cpu);
 185 }
 186
 187 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 188 {
 189     CPUClass *cc = CPU_GET_CLASS(cs);
 190     bool ret = false;
 191
 192     if (interrupt_request & CPU_INTERRUPT_FIQ
 193         && arm_excp_unmasked(cs, EXCP_FIQ)) {
 194         cs->exception_index = EXCP_FIQ;
 195         cc->do_interrupt(cs);
 196         ret = true;
 197     }
 198     /* ARMv7-M interrupt return works by loading a magic value
 199        into the PC.  On real hardware the load causes the
 200        return to occur.  The qemu implementation performs the
 201        jump normally, then does the exception return when the
 202        CPU tries to execute code at the magic address.
 203        This will cause the magic PC value to be pushed to
 204        the stack if an interrupt occurred at the wrong time.
 205        We avoid this by disabling interrupts when
 206        pc contains a magic address.  */
 207     if (interrupt_request & CPU_INTERRUPT_HARD
 208         && arm_excp_unmasked(cs, EXCP_IRQ)) {
 209         cs->exception_index = EXCP_IRQ;
 210         cc->do_interrupt(cs);
 211         ret = true;
 212     }
 213
 214     return ret;
 215 }
 216
 217 #ifndef CONFIG_USER_ONLY
 218 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 219 {
 220     ARMCPU *cpu = opaque;
 221     CPUState *cs = CPU(cpu);
 222
 223     switch (irq) {
 224     case ARM_CPU_IRQ:
 225         if (level) {
 226             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 227         } else {
 228             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 229         }
 230         break;
 231     case ARM_CPU_FIQ:
 232         if (level) {
 233             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 234         } else {
 235             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 236         }
 237         break;
 238     default:
 239         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 240     }
 241 }
 242
 243 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 244 {
 245 #ifdef CONFIG_KVM
 246     ARMCPU *cpu = opaque;
 247     CPUState *cs = CPU(cpu);
 248     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 249
 250     switch (irq) {
 251     case ARM_CPU_IRQ:
 252         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 253         break;
 254     case ARM_CPU_FIQ:
 255         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 256         break;
 257     default:
 258         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 259     }
 260     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 261     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 262 #endif
 263 }
 264 #endif
 265
 266 static inline void set_feature(CPUARMState *env, int feature)
 267 {
 268     env->features |= 1ULL << feature;
 269 }
 270
 271 static void arm_cpu_initfn(Object *obj)
 272 {
 273     CPUState *cs = CPU(obj);
 274     ARMCPU *cpu = ARM_CPU(obj);
 275     static bool inited;
 276
 277     cs->env_ptr = &cpu->env;
 278     cpu_exec_init(&cpu->env);
 279     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 280                                          g_free, g_free);
 281
 282 #ifndef CONFIG_USER_ONLY
 283     /* Our inbound IRQ and FIQ lines */
 284     if (kvm_enabled()) {
 285         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 286     } else {
 287         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 288     }
 289
 290     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 291                                                 arm_gt_ptimer_cb, cpu);
 292     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 293                                                 arm_gt_vtimer_cb, cpu);
 294     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 295                        ARRAY_SIZE(cpu->gt_timer_outputs));
 296 #endif
 297
 298     /* DTB consumers generally don't in fact care what the 'compatible'
 299      * string is, so always provide some string and trust that a hypothetical
 300      * picky DTB consumer will also provide a helpful error message.
 301      */
 302     cpu->dtb_compatible = "qemu,unknown";
 303     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 304     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 305
 306     if (tcg_enabled() && !inited) {
 307         inited = true;
 308         arm_translate_init();
 309     }
 310 }
 311
 312 static Property arm_cpu_reset_cbar_property =
 313             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 314
 315 static Property arm_cpu_reset_hivecs_property =
 316             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 317
 318 static Property arm_cpu_rvbar_property =
 319             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 320
 321 static void arm_cpu_post_init(Object *obj)
 322 {
 323     ARMCPU *cpu = ARM_CPU(obj);
 324
 325     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 326         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 327         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 328                                  &error_abort);
 329     }
 330
 331     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 332         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 333                                  &error_abort);
 334     }
 335
 336     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 337         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 338                                  &error_abort);
 339     }
 340 }
 341
 342 static void arm_cpu_finalizefn(Object *obj)
 343 {
 344     ARMCPU *cpu = ARM_CPU(obj);
 345     g_hash_table_destroy(cpu->cp_regs);
 346 }
 347
 348 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 349 {
 350     CPUState *cs = CPU(dev);
 351     ARMCPU *cpu = ARM_CPU(dev);
 352     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 353     CPUARMState *env = &cpu->env;
 354
 355     /* Some features automatically imply others: */
 356     if (arm_feature(env, ARM_FEATURE_V8)) {
 357         set_feature(env, ARM_FEATURE_V7);
 358         set_feature(env, ARM_FEATURE_ARM_DIV);
 359         set_feature(env, ARM_FEATURE_LPAE);
 360     }
 361     if (arm_feature(env, ARM_FEATURE_V7)) {
 362         set_feature(env, ARM_FEATURE_VAPA);
 363         set_feature(env, ARM_FEATURE_THUMB2);
 364         set_feature(env, ARM_FEATURE_MPIDR);
 365         if (!arm_feature(env, ARM_FEATURE_M)) {
 366             set_feature(env, ARM_FEATURE_V6K);
 367         } else {
 368             set_feature(env, ARM_FEATURE_V6);
 369         }
 370     }
 371     if (arm_feature(env, ARM_FEATURE_V6K)) {
 372         set_feature(env, ARM_FEATURE_V6);
 373         set_feature(env, ARM_FEATURE_MVFR);
 374     }
 375     if (arm_feature(env, ARM_FEATURE_V6)) {
 376         set_feature(env, ARM_FEATURE_V5);
 377         if (!arm_feature(env, ARM_FEATURE_M)) {
 378             set_feature(env, ARM_FEATURE_AUXCR);
 379         }
 380     }
 381     if (arm_feature(env, ARM_FEATURE_V5)) {
 382         set_feature(env, ARM_FEATURE_V4T);
 383     }
 384     if (arm_feature(env, ARM_FEATURE_M)) {
 385         set_feature(env, ARM_FEATURE_THUMB_DIV);
 386     }
 387     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 388         set_feature(env, ARM_FEATURE_THUMB_DIV);
 389     }
 390     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 391         set_feature(env, ARM_FEATURE_VFP3);
 392         set_feature(env, ARM_FEATURE_VFP_FP16);
 393     }
 394     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 395         set_feature(env, ARM_FEATURE_VFP);
 396     }
 397     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 398         set_feature(env, ARM_FEATURE_V7MP);
 399         set_feature(env, ARM_FEATURE_PXN);
 400     }
 401     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 402         set_feature(env, ARM_FEATURE_CBAR);
 403     }
 404
 405     if (cpu->reset_hivecs) {
 406             cpu->reset_sctlr |= (1 << 13);
 407     }
 408
 409     register_cp_regs_for_features(cpu);
 410     arm_cpu_register_gdb_regs_for_features(cpu);
 411
 412     init_cpreg_list(cpu);
 413
 414     qemu_init_vcpu(cs);
 415     cpu_reset(cs);
 416
 417     acc->parent_realize(dev, errp);
 418 }
 419
 420 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 421 {
 422     ObjectClass *oc;
 423     char *typename;
 424
 425     if (!cpu_model) {
 426         return NULL;
 427     }
 428
 429     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 430     oc = object_class_by_name(typename);
 431     g_free(typename);
 432     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 433         object_class_is_abstract(oc)) {
 434         return NULL;
 435     }
 436     return oc;
 437 }
 438
 439 /* CPU models. These are not needed for the AArch64 linux-user build. */
 440 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 441
 442 static void arm926_initfn(Object *obj)
 443 {
 444     ARMCPU *cpu = ARM_CPU(obj);
 445
 446     cpu->dtb_compatible = "arm,arm926";
 447     set_feature(&cpu->env, ARM_FEATURE_V5);
 448     set_feature(&cpu->env, ARM_FEATURE_VFP);
 449     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 450     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 451     cpu->midr = 0x41069265;
 452     cpu->reset_fpsid = 0x41011090;
 453     cpu->ctr = 0x1dd20d2;
 454     cpu->reset_sctlr = 0x00090078;
 455 }
 456
 457 static void arm946_initfn(Object *obj)
 458 {
 459     ARMCPU *cpu = ARM_CPU(obj);
 460
 461     cpu->dtb_compatible = "arm,arm946";
 462     set_feature(&cpu->env, ARM_FEATURE_V5);
 463     set_feature(&cpu->env, ARM_FEATURE_MPU);
 464     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 465     cpu->midr = 0x41059461;
 466     cpu->ctr = 0x0f004006;
 467     cpu->reset_sctlr = 0x00000078;
 468 }
 469
 470 static void arm1026_initfn(Object *obj)
 471 {
 472     ARMCPU *cpu = ARM_CPU(obj);
 473
 474     cpu->dtb_compatible = "arm,arm1026";
 475     set_feature(&cpu->env, ARM_FEATURE_V5);
 476     set_feature(&cpu->env, ARM_FEATURE_VFP);
 477     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 478     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 479     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 480     cpu->midr = 0x4106a262;
 481     cpu->reset_fpsid = 0x410110a0;
 482     cpu->ctr = 0x1dd20d2;
 483     cpu->reset_sctlr = 0x00090078;
 484     cpu->reset_auxcr = 1;
 485     {
 486         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 487         ARMCPRegInfo ifar = {
 488             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 489             .access = PL1_RW,
 490             .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 491             .resetvalue = 0
 492         };
 493         define_one_arm_cp_reg(cpu, &ifar);
 494     }
 495 }
 496
 497 static void arm1136_r2_initfn(Object *obj)
 498 {
 499     ARMCPU *cpu = ARM_CPU(obj);
 500     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 501      * older core than plain "arm1136". In particular this does not
 502      * have the v6K features.
 503      * These ID register values are correct for 1136 but may be wrong
 504      * for 1136_r2 (in particular r0p2 does not actually implement most
 505      * of the ID registers).
 506      */
 507
 508     cpu->dtb_compatible = "arm,arm1136";
 509     set_feature(&cpu->env, ARM_FEATURE_V6);
 510     set_feature(&cpu->env, ARM_FEATURE_VFP);
 511     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 512     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 513     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 514     cpu->midr = 0x4107b362;
 515     cpu->reset_fpsid = 0x410120b4;
 516     cpu->mvfr0 = 0x11111111;
 517     cpu->mvfr1 = 0x00000000;
 518     cpu->ctr = 0x1dd20d2;
 519     cpu->reset_sctlr = 0x00050078;
 520     cpu->id_pfr0 = 0x111;
 521     cpu->id_pfr1 = 0x1;
 522     cpu->id_dfr0 = 0x2;
 523     cpu->id_afr0 = 0x3;
 524     cpu->id_mmfr0 = 0x01130003;
 525     cpu->id_mmfr1 = 0x10030302;
 526     cpu->id_mmfr2 = 0x01222110;
 527     cpu->id_isar0 = 0x00140011;
 528     cpu->id_isar1 = 0x12002111;
 529     cpu->id_isar2 = 0x11231111;
 530     cpu->id_isar3 = 0x01102131;
 531     cpu->id_isar4 = 0x141;
 532     cpu->reset_auxcr = 7;
 533 }
 534
 535 static void arm1136_initfn(Object *obj)
 536 {
 537     ARMCPU *cpu = ARM_CPU(obj);
 538
 539     cpu->dtb_compatible = "arm,arm1136";
 540     set_feature(&cpu->env, ARM_FEATURE_V6K);
 541     set_feature(&cpu->env, ARM_FEATURE_V6);
 542     set_feature(&cpu->env, ARM_FEATURE_VFP);
 543     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 544     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 545     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 546     cpu->midr = 0x4117b363;
 547     cpu->reset_fpsid = 0x410120b4;
 548     cpu->mvfr0 = 0x11111111;
 549     cpu->mvfr1 = 0x00000000;
 550     cpu->ctr = 0x1dd20d2;
 551     cpu->reset_sctlr = 0x00050078;
 552     cpu->id_pfr0 = 0x111;
 553     cpu->id_pfr1 = 0x1;
 554     cpu->id_dfr0 = 0x2;
 555     cpu->id_afr0 = 0x3;
 556     cpu->id_mmfr0 = 0x01130003;
 557     cpu->id_mmfr1 = 0x10030302;
 558     cpu->id_mmfr2 = 0x01222110;
 559     cpu->id_isar0 = 0x00140011;
 560     cpu->id_isar1 = 0x12002111;
 561     cpu->id_isar2 = 0x11231111;
 562     cpu->id_isar3 = 0x01102131;
 563     cpu->id_isar4 = 0x141;
 564     cpu->reset_auxcr = 7;
 565 }
 566
 567 static void arm1176_initfn(Object *obj)
 568 {
 569     ARMCPU *cpu = ARM_CPU(obj);
 570
 571     cpu->dtb_compatible = "arm,arm1176";
 572     set_feature(&cpu->env, ARM_FEATURE_V6K);
 573     set_feature(&cpu->env, ARM_FEATURE_VFP);
 574     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 575     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 576     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 577     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 578     cpu->midr = 0x410fb767;
 579     cpu->reset_fpsid = 0x410120b5;
 580     cpu->mvfr0 = 0x11111111;
 581     cpu->mvfr1 = 0x00000000;
 582     cpu->ctr = 0x1dd20d2;
 583     cpu->reset_sctlr = 0x00050078;
 584     cpu->id_pfr0 = 0x111;
 585     cpu->id_pfr1 = 0x11;
 586     cpu->id_dfr0 = 0x33;
 587     cpu->id_afr0 = 0;
 588     cpu->id_mmfr0 = 0x01130003;
 589     cpu->id_mmfr1 = 0x10030302;
 590     cpu->id_mmfr2 = 0x01222100;
 591     cpu->id_isar0 = 0x0140011;
 592     cpu->id_isar1 = 0x12002111;
 593     cpu->id_isar2 = 0x11231121;
 594     cpu->id_isar3 = 0x01102131;
 595     cpu->id_isar4 = 0x01141;
 596     cpu->reset_auxcr = 7;
 597 }
 598
 599 static void arm11mpcore_initfn(Object *obj)
 600 {
 601     ARMCPU *cpu = ARM_CPU(obj);
 602
 603     cpu->dtb_compatible = "arm,arm11mpcore";
 604     set_feature(&cpu->env, ARM_FEATURE_V6K);
 605     set_feature(&cpu->env, ARM_FEATURE_VFP);
 606     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 607     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 608     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 609     cpu->midr = 0x410fb022;
 610     cpu->reset_fpsid = 0x410120b4;
 611     cpu->mvfr0 = 0x11111111;
 612     cpu->mvfr1 = 0x00000000;
 613     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 614     cpu->id_pfr0 = 0x111;
 615     cpu->id_pfr1 = 0x1;
 616     cpu->id_dfr0 = 0;
 617     cpu->id_afr0 = 0x2;
 618     cpu->id_mmfr0 = 0x01100103;
 619     cpu->id_mmfr1 = 0x10020302;
 620     cpu->id_mmfr2 = 0x01222000;
 621     cpu->id_isar0 = 0x00100011;
 622     cpu->id_isar1 = 0x12002111;
 623     cpu->id_isar2 = 0x11221011;
 624     cpu->id_isar3 = 0x01102131;
 625     cpu->id_isar4 = 0x141;
 626     cpu->reset_auxcr = 1;
 627 }
 628
 629 static void cortex_m3_initfn(Object *obj)
 630 {
 631     ARMCPU *cpu = ARM_CPU(obj);
 632     set_feature(&cpu->env, ARM_FEATURE_V7);
 633     set_feature(&cpu->env, ARM_FEATURE_M);
 634     cpu->midr = 0x410fc231;
 635 }
 636
 637 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 638 {
 639 #ifndef CONFIG_USER_ONLY
 640     CPUClass *cc = CPU_CLASS(oc);
 641
 642     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 643 #endif
 644 }
 645
 646 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 647     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 648       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 649     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 650       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 651     REGINFO_SENTINEL
 652 };
 653
 654 static void cortex_a8_initfn(Object *obj)
 655 {
 656     ARMCPU *cpu = ARM_CPU(obj);
 657
 658     cpu->dtb_compatible = "arm,cortex-a8";
 659     set_feature(&cpu->env, ARM_FEATURE_V7);
 660     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 661     set_feature(&cpu->env, ARM_FEATURE_NEON);
 662     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 663     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 664     cpu->midr = 0x410fc080;
 665     cpu->reset_fpsid = 0x410330c0;
 666     cpu->mvfr0 = 0x11110222;
 667     cpu->mvfr1 = 0x00011100;
 668     cpu->ctr = 0x82048004;
 669     cpu->reset_sctlr = 0x00c50078;
 670     cpu->id_pfr0 = 0x1031;
 671     cpu->id_pfr1 = 0x11;
 672     cpu->id_dfr0 = 0x400;
 673     cpu->id_afr0 = 0;
 674     cpu->id_mmfr0 = 0x31100003;
 675     cpu->id_mmfr1 = 0x20000000;
 676     cpu->id_mmfr2 = 0x01202000;
 677     cpu->id_mmfr3 = 0x11;
 678     cpu->id_isar0 = 0x00101111;
 679     cpu->id_isar1 = 0x12112111;
 680     cpu->id_isar2 = 0x21232031;
 681     cpu->id_isar3 = 0x11112131;
 682     cpu->id_isar4 = 0x00111142;
 683     cpu->dbgdidr = 0x15141000;
 684     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 685     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 686     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 687     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 688     cpu->reset_auxcr = 2;
 689     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 690 }
 691
 692 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 693     /* power_control should be set to maximum latency. Again,
 694      * default to 0 and set by private hook
 695      */
 696     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 697       .access = PL1_RW, .resetvalue = 0,
 698       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 699     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 700       .access = PL1_RW, .resetvalue = 0,
 701       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 702     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 703       .access = PL1_RW, .resetvalue = 0,
 704       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 705     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 706       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 707     /* TLB lockdown control */
 708     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 709       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 710     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 711       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 712     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 713       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 714     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 715       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 716     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 717       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 718     REGINFO_SENTINEL
 719 };
 720
 721 static void cortex_a9_initfn(Object *obj)
 722 {
 723     ARMCPU *cpu = ARM_CPU(obj);
 724
 725     cpu->dtb_compatible = "arm,cortex-a9";
 726     set_feature(&cpu->env, ARM_FEATURE_V7);
 727     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 728     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 729     set_feature(&cpu->env, ARM_FEATURE_NEON);
 730     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 731     /* Note that A9 supports the MP extensions even for
 732      * A9UP and single-core A9MP (which are both different
 733      * and valid configurations; we don't model A9UP).
 734      */
 735     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 736     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 737     cpu->midr = 0x410fc090;
 738     cpu->reset_fpsid = 0x41033090;
 739     cpu->mvfr0 = 0x11110222;
 740     cpu->mvfr1 = 0x01111111;
 741     cpu->ctr = 0x80038003;
 742     cpu->reset_sctlr = 0x00c50078;
 743     cpu->id_pfr0 = 0x1031;
 744     cpu->id_pfr1 = 0x11;
 745     cpu->id_dfr0 = 0x000;
 746     cpu->id_afr0 = 0;
 747     cpu->id_mmfr0 = 0x00100103;
 748     cpu->id_mmfr1 = 0x20000000;
 749     cpu->id_mmfr2 = 0x01230000;
 750     cpu->id_mmfr3 = 0x00002111;
 751     cpu->id_isar0 = 0x00101111;
 752     cpu->id_isar1 = 0x13112111;
 753     cpu->id_isar2 = 0x21232041;
 754     cpu->id_isar3 = 0x11112131;
 755     cpu->id_isar4 = 0x00111142;
 756     cpu->dbgdidr = 0x35141000;
 757     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 758     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 759     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 760     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 761 }
 762
 763 #ifndef CONFIG_USER_ONLY
 764 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 765 {
 766     /* Linux wants the number of processors from here.
 767      * Might as well set the interrupt-controller bit too.
 768      */
 769     return ((smp_cpus - 1) << 24) | (1 << 23);
 770 }
 771 #endif
 772
 773 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 774 #ifndef CONFIG_USER_ONLY
 775     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 776       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 777       .writefn = arm_cp_write_ignore, },
 778 #endif
 779     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 780       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 781     REGINFO_SENTINEL
 782 };
 783
 784 static void cortex_a15_initfn(Object *obj)
 785 {
 786     ARMCPU *cpu = ARM_CPU(obj);
 787
 788     cpu->dtb_compatible = "arm,cortex-a15";
 789     set_feature(&cpu->env, ARM_FEATURE_V7);
 790     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 791     set_feature(&cpu->env, ARM_FEATURE_NEON);
 792     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 793     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 794     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 795     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 796     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 797     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 798     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 799     cpu->midr = 0x412fc0f1;
 800     cpu->reset_fpsid = 0x410430f0;
 801     cpu->mvfr0 = 0x10110222;
 802     cpu->mvfr1 = 0x11111111;
 803     cpu->ctr = 0x8444c004;
 804     cpu->reset_sctlr = 0x00c50078;
 805     cpu->id_pfr0 = 0x00001131;
 806     cpu->id_pfr1 = 0x00011011;
 807     cpu->id_dfr0 = 0x02010555;
 808     cpu->id_afr0 = 0x00000000;
 809     cpu->id_mmfr0 = 0x10201105;
 810     cpu->id_mmfr1 = 0x20000000;
 811     cpu->id_mmfr2 = 0x01240000;
 812     cpu->id_mmfr3 = 0x02102211;
 813     cpu->id_isar0 = 0x02101110;
 814     cpu->id_isar1 = 0x13112111;
 815     cpu->id_isar2 = 0x21232041;
 816     cpu->id_isar3 = 0x11112131;
 817     cpu->id_isar4 = 0x10011142;
 818     cpu->dbgdidr = 0x3515f021;
 819     cpu->clidr = 0x0a200023;
 820     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 821     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 822     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 823     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 824 }
 825
 826 static void ti925t_initfn(Object *obj)
 827 {
 828     ARMCPU *cpu = ARM_CPU(obj);
 829     set_feature(&cpu->env, ARM_FEATURE_V4T);
 830     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 831     cpu->midr = ARM_CPUID_TI925T;
 832     cpu->ctr = 0x5109149;
 833     cpu->reset_sctlr = 0x00000070;
 834 }
 835
 836 static void sa1100_initfn(Object *obj)
 837 {
 838     ARMCPU *cpu = ARM_CPU(obj);
 839
 840     cpu->dtb_compatible = "intel,sa1100";
 841     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 842     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 843     cpu->midr = 0x4401A11B;
 844     cpu->reset_sctlr = 0x00000070;
 845 }
 846
 847 static void sa1110_initfn(Object *obj)
 848 {
 849     ARMCPU *cpu = ARM_CPU(obj);
 850     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 851     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 852     cpu->midr = 0x6901B119;
 853     cpu->reset_sctlr = 0x00000070;
 854 }
 855
 856 static void pxa250_initfn(Object *obj)
 857 {
 858     ARMCPU *cpu = ARM_CPU(obj);
 859
 860     cpu->dtb_compatible = "marvell,xscale";
 861     set_feature(&cpu->env, ARM_FEATURE_V5);
 862     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 863     cpu->midr = 0x69052100;
 864     cpu->ctr = 0xd172172;
 865     cpu->reset_sctlr = 0x00000078;
 866 }
 867
 868 static void pxa255_initfn(Object *obj)
 869 {
 870     ARMCPU *cpu = ARM_CPU(obj);
 871
 872     cpu->dtb_compatible = "marvell,xscale";
 873     set_feature(&cpu->env, ARM_FEATURE_V5);
 874     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 875     cpu->midr = 0x69052d00;
 876     cpu->ctr = 0xd172172;
 877     cpu->reset_sctlr = 0x00000078;
 878 }
 879
 880 static void pxa260_initfn(Object *obj)
 881 {
 882     ARMCPU *cpu = ARM_CPU(obj);
 883
 884     cpu->dtb_compatible = "marvell,xscale";
 885     set_feature(&cpu->env, ARM_FEATURE_V5);
 886     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 887     cpu->midr = 0x69052903;
 888     cpu->ctr = 0xd172172;
 889     cpu->reset_sctlr = 0x00000078;
 890 }
 891
 892 static void pxa261_initfn(Object *obj)
 893 {
 894     ARMCPU *cpu = ARM_CPU(obj);
 895
 896     cpu->dtb_compatible = "marvell,xscale";
 897     set_feature(&cpu->env, ARM_FEATURE_V5);
 898     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 899     cpu->midr = 0x69052d05;
 900     cpu->ctr = 0xd172172;
 901     cpu->reset_sctlr = 0x00000078;
 902 }
 903
 904 static void pxa262_initfn(Object *obj)
 905 {
 906     ARMCPU *cpu = ARM_CPU(obj);
 907
 908     cpu->dtb_compatible = "marvell,xscale";
 909     set_feature(&cpu->env, ARM_FEATURE_V5);
 910     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 911     cpu->midr = 0x69052d06;
 912     cpu->ctr = 0xd172172;
 913     cpu->reset_sctlr = 0x00000078;
 914 }
 915
 916 static void pxa270a0_initfn(Object *obj)
 917 {
 918     ARMCPU *cpu = ARM_CPU(obj);
 919
 920     cpu->dtb_compatible = "marvell,xscale";
 921     set_feature(&cpu->env, ARM_FEATURE_V5);
 922     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 923     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 924     cpu->midr = 0x69054110;
 925     cpu->ctr = 0xd172172;
 926     cpu->reset_sctlr = 0x00000078;
 927 }
 928
 929 static void pxa270a1_initfn(Object *obj)
 930 {
 931     ARMCPU *cpu = ARM_CPU(obj);
 932
 933     cpu->dtb_compatible = "marvell,xscale";
 934     set_feature(&cpu->env, ARM_FEATURE_V5);
 935     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 936     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 937     cpu->midr = 0x69054111;
 938     cpu->ctr = 0xd172172;
 939     cpu->reset_sctlr = 0x00000078;
 940 }
 941
 942 static void pxa270b0_initfn(Object *obj)
 943 {
 944     ARMCPU *cpu = ARM_CPU(obj);
 945
 946     cpu->dtb_compatible = "marvell,xscale";
 947     set_feature(&cpu->env, ARM_FEATURE_V5);
 948     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 949     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 950     cpu->midr = 0x69054112;
 951     cpu->ctr = 0xd172172;
 952     cpu->reset_sctlr = 0x00000078;
 953 }
 954
 955 static void pxa270b1_initfn(Object *obj)
 956 {
 957     ARMCPU *cpu = ARM_CPU(obj);
 958
 959     cpu->dtb_compatible = "marvell,xscale";
 960     set_feature(&cpu->env, ARM_FEATURE_V5);
 961     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 962     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 963     cpu->midr = 0x69054113;
 964     cpu->ctr = 0xd172172;
 965     cpu->reset_sctlr = 0x00000078;
 966 }
 967
 968 static void pxa270c0_initfn(Object *obj)
 969 {
 970     ARMCPU *cpu = ARM_CPU(obj);
 971
 972     cpu->dtb_compatible = "marvell,xscale";
 973     set_feature(&cpu->env, ARM_FEATURE_V5);
 974     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 975     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 976     cpu->midr = 0x69054114;
 977     cpu->ctr = 0xd172172;
 978     cpu->reset_sctlr = 0x00000078;
 979 }
 980
 981 static void pxa270c5_initfn(Object *obj)
 982 {
 983     ARMCPU *cpu = ARM_CPU(obj);
 984
 985     cpu->dtb_compatible = "marvell,xscale";
 986     set_feature(&cpu->env, ARM_FEATURE_V5);
 987     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 988     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 989     cpu->midr = 0x69054117;
 990     cpu->ctr = 0xd172172;
 991     cpu->reset_sctlr = 0x00000078;
 992 }
 993
 994 #ifdef CONFIG_USER_ONLY
 995 static void arm_any_initfn(Object *obj)
 996 {
 997     ARMCPU *cpu = ARM_CPU(obj);
 998     set_feature(&cpu->env, ARM_FEATURE_V8);
 999     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1000     set_feature(&cpu->env, ARM_FEATURE_NEON);
1001     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1002     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1003     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1004     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1005     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1006     set_feature(&cpu->env, ARM_FEATURE_CRC);
1007     cpu->midr = 0xffffffff;
1008 }
1009 #endif
1010
1011 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1012
1013 typedef struct ARMCPUInfo {
1014     const char *name;
1015     void (*initfn)(Object *obj);
1016     void (*class_init)(ObjectClass *oc, void *data);
1017 } ARMCPUInfo;
1018
1019 static const ARMCPUInfo arm_cpus[] = {
1020 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1021     { .name = "arm926",      .initfn = arm926_initfn },
1022     { .name = "arm946",      .initfn = arm946_initfn },
1023     { .name = "arm1026",     .initfn = arm1026_initfn },
1024     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1025      * older core than plain "arm1136". In particular this does not
1026      * have the v6K features.
1027      */
1028     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1029     { .name = "arm1136",     .initfn = arm1136_initfn },
1030     { .name = "arm1176",     .initfn = arm1176_initfn },
1031     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1032     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1033                              .class_init = arm_v7m_class_init },
1034     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1035     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1036     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1037     { .name = "ti925t",      .initfn = ti925t_initfn },
1038     { .name = "sa1100",      .initfn = sa1100_initfn },
1039     { .name = "sa1110",      .initfn = sa1110_initfn },
1040     { .name = "pxa250",      .initfn = pxa250_initfn },
1041     { .name = "pxa255",      .initfn = pxa255_initfn },
1042     { .name = "pxa260",      .initfn = pxa260_initfn },
1043     { .name = "pxa261",      .initfn = pxa261_initfn },
1044     { .name = "pxa262",      .initfn = pxa262_initfn },
1045     /* "pxa270" is an alias for "pxa270-a0" */
1046     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1047     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1048     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1049     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1050     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1051     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1052     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1053 #ifdef CONFIG_USER_ONLY
1054     { .name = "any",         .initfn = arm_any_initfn },
1055 #endif
1056 #endif
1057     { .name = NULL }
1058 };
1059
1060 static Property arm_cpu_properties[] = {
1061     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1062     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1063     DEFINE_PROP_END_OF_LIST()
1064 };
1065
1066 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1067 {
1068     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1069     CPUClass *cc = CPU_CLASS(acc);
1070     DeviceClass *dc = DEVICE_CLASS(oc);
1071
1072     acc->parent_realize = dc->realize;
1073     dc->realize = arm_cpu_realizefn;
1074     dc->props = arm_cpu_properties;
1075
1076     acc->parent_reset = cc->reset;
1077     cc->reset = arm_cpu_reset;
1078
1079     cc->class_by_name = arm_cpu_class_by_name;
1080     cc->has_work = arm_cpu_has_work;
1081     cc->do_interrupt = arm_cpu_do_interrupt;
1082     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1083     cc->dump_state = arm_cpu_dump_state;
1084     cc->set_pc = arm_cpu_set_pc;
1085     cc->gdb_read_register = arm_cpu_gdb_read_register;
1086     cc->gdb_write_register = arm_cpu_gdb_write_register;
1087 #ifdef CONFIG_USER_ONLY
1088     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1089 #else
1090     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1091     cc->vmsd = &vmstate_arm_cpu;
1092 #endif
1093     cc->gdb_num_core_regs = 26;
1094     cc->gdb_core_xml_file = "arm-core.xml";
1095     cc->debug_excp_handler = arm_debug_excp_handler;
1096 }
1097
1098 static void cpu_register(const ARMCPUInfo *info)
1099 {
1100     TypeInfo type_info = {
1101         .parent = TYPE_ARM_CPU,
1102         .instance_size = sizeof(ARMCPU),
1103         .instance_init = info->initfn,
1104         .class_size = sizeof(ARMCPUClass),
1105         .class_init = info->class_init,
1106     };
1107
1108     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1109     type_register(&type_info);
1110     g_free((void *)type_info.name);
1111 }
1112
1113 static const TypeInfo arm_cpu_type_info = {
1114     .name = TYPE_ARM_CPU,
1115     .parent = TYPE_CPU,
1116     .instance_size = sizeof(ARMCPU),
1117     .instance_init = arm_cpu_initfn,
1118     .instance_post_init = arm_cpu_post_init,
1119     .instance_finalize = arm_cpu_finalizefn,
1120     .abstract = true,
1121     .class_size = sizeof(ARMCPUClass),
1122     .class_init = arm_cpu_class_init,
1123 };
1124
1125 static void arm_cpu_register_types(void)
1126 {
1127     const ARMCPUInfo *info = arm_cpus;
1128
1129     type_register_static(&arm_cpu_type_info);
1130
1131     while (info->name) {
1132         cpu_register(info);
1133         info++;
1134     }
1135 }
1136
1137 type_init(arm_cpu_register_types)