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s390x/kvm: Rework cmma management
[qemu/ar7.git] / target / s390x / cpu.h
blob8ab75c0d43eb6d8b5ed765fde5160893c1aeae4d
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #ifndef S390X_CPU_H
24 #define S390X_CPU_H
25
26 #include "qemu-common.h"
27 #include "cpu-qom.h"
28
29 #define TARGET_LONG_BITS 64
30
31 #define ELF_MACHINE_UNAME "S390X"
32
33 #define CPUArchState struct CPUS390XState
34
35 #include "exec/cpu-defs.h"
36 #define TARGET_PAGE_BITS 12
37
38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
40
41 #include "exec/cpu-all.h"
42
43 #include "fpu/softfloat.h"
44
45 #define NB_MMU_MODES 3
46 #define TARGET_INSN_START_EXTRA_WORDS 1
47
48 #define MMU_MODE0_SUFFIX _primary
49 #define MMU_MODE1_SUFFIX _secondary
50 #define MMU_MODE2_SUFFIX _home
51
52 #define MMU_USER_IDX 0
53
54 #define MAX_EXT_QUEUE 16
55 #define MAX_IO_QUEUE 16
56 #define MAX_MCHK_QUEUE 16
57
58 #define PSW_MCHK_MASK 0x0004000000000000
59 #define PSW_IO_MASK 0x0200000000000000
60
61 typedef struct PSW {
62 uint64_t mask;
63 uint64_t addr;
64 } PSW;
65
66 typedef struct ExtQueue {
67 uint32_t code;
68 uint32_t param;
69 uint32_t param64;
70 } ExtQueue;
71
72 typedef struct IOIntQueue {
73 uint16_t id;
74 uint16_t nr;
75 uint32_t parm;
76 uint32_t word;
77 } IOIntQueue;
78
79 typedef struct MchkQueue {
80 uint16_t type;
81 } MchkQueue;
82
83 typedef struct CPUS390XState {
84 uint64_t regs[16]; /* GP registers */
85 /*
86 * The floating point registers are part of the vector registers.
87 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
88 */
89 CPU_DoubleU vregs[32][2]; /* vector registers */
90 uint32_t aregs[16]; /* access registers */
91 uint8_t riccb[64]; /* runtime instrumentation control */
92
93 /* Fields up to this point are not cleared by initial CPU reset */
94 struct {} start_initial_reset_fields;
95
96 uint32_t fpc; /* floating-point control register */
97 uint32_t cc_op;
98
99 float_status fpu_status; /* passed to softfloat lib */
100
101 /* The low part of a 128-bit return, or remainder of a divide. */
102 uint64_t retxl;
103
104 PSW psw;
105
106 uint64_t cc_src;
107 uint64_t cc_dst;
108 uint64_t cc_vr;
109
110 uint64_t ex_value;
111
112 uint64_t __excp_addr;
113 uint64_t psa;
114
115 uint32_t int_pgm_code;
116 uint32_t int_pgm_ilen;
117
118 uint32_t int_svc_code;
119 uint32_t int_svc_ilen;
120
121 uint64_t per_address;
122 uint16_t per_perc_atmid;
123
124 uint64_t cregs[16]; /* control registers */
125
126 ExtQueue ext_queue[MAX_EXT_QUEUE];
127 IOIntQueue io_queue[MAX_IO_QUEUE][8];
128 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
129
130 int pending_int;
131 int ext_index;
132 int io_index[8];
133 int mchk_index;
134
135 uint64_t ckc;
136 uint64_t cputm;
137 uint32_t todpr;
138
139 uint64_t pfault_token;
140 uint64_t pfault_compare;
141 uint64_t pfault_select;
142
143 uint64_t gbea;
144 uint64_t pp;
145
146 /* Fields up to this point are cleared by a CPU reset */
147 struct {} end_reset_fields;
148
149 CPU_COMMON
150
151 uint32_t cpu_num;
152 uint64_t cpuid;
153
154 uint64_t tod_offset;
155 uint64_t tod_basetime;
156 QEMUTimer *tod_timer;
157
158 QEMUTimer *cpu_timer;
159
160 /*
161 * The cpu state represents the logical state of a cpu. In contrast to other
162 * architectures, there is a difference between a halt and a stop on s390.
163 * If all cpus are either stopped (including check stop) or in the disabled
164 * wait state, the vm can be shut down.
165 */
166 #define CPU_STATE_UNINITIALIZED 0x00
167 #define CPU_STATE_STOPPED 0x01
168 #define CPU_STATE_CHECK_STOP 0x02
169 #define CPU_STATE_OPERATING 0x03
170 #define CPU_STATE_LOAD 0x04
171 uint8_t cpu_state;
172
173 /* currently processed sigp order */
174 uint8_t sigp_order;
175
176 } CPUS390XState;
177
178 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
179 {
180 return &cs->vregs[nr][0];
181 }
182
183 /**
184 * S390CPU:
185 * @env: #CPUS390XState.
186 *
187 * An S/390 CPU.
188 */
189 struct S390CPU {
190 /*< private >*/
191 CPUState parent_obj;
192 /*< public >*/
193
194 CPUS390XState env;
195 int64_t id;
196 S390CPUModel *model;
197 /* needed for live migration */
198 void *irqstate;
199 uint32_t irqstate_saved_size;
200 };
201
202 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
203 {
204 return container_of(env, S390CPU, env);
205 }
206
207 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
208
209 #define ENV_OFFSET offsetof(S390CPU, env)
210
211 #ifndef CONFIG_USER_ONLY
212 extern const struct VMStateDescription vmstate_s390_cpu;
213 #endif
214
215 void s390_cpu_do_interrupt(CPUState *cpu);
216 bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
217 void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
218 int flags);
219 int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
220 int cpuid, void *opaque);
221
222 hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
223 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
224 int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
225 int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
226 void s390_cpu_gdb_init(CPUState *cs);
227 void s390x_cpu_debug_excp_handler(CPUState *cs);
228
229 #include "sysemu/kvm.h"
230
231 /* distinguish between 24 bit and 31 bit addressing */
232 #define HIGH_ORDER_BIT 0x80000000
233
234 /* Interrupt Codes */
235 /* Program Interrupts */
236 #define PGM_OPERATION 0x0001
237 #define PGM_PRIVILEGED 0x0002
238 #define PGM_EXECUTE 0x0003
239 #define PGM_PROTECTION 0x0004
240 #define PGM_ADDRESSING 0x0005
241 #define PGM_SPECIFICATION 0x0006
242 #define PGM_DATA 0x0007
243 #define PGM_FIXPT_OVERFLOW 0x0008
244 #define PGM_FIXPT_DIVIDE 0x0009
245 #define PGM_DEC_OVERFLOW 0x000a
246 #define PGM_DEC_DIVIDE 0x000b
247 #define PGM_HFP_EXP_OVERFLOW 0x000c
248 #define PGM_HFP_EXP_UNDERFLOW 0x000d
249 #define PGM_HFP_SIGNIFICANCE 0x000e
250 #define PGM_HFP_DIVIDE 0x000f
251 #define PGM_SEGMENT_TRANS 0x0010
252 #define PGM_PAGE_TRANS 0x0011
253 #define PGM_TRANS_SPEC 0x0012
254 #define PGM_SPECIAL_OP 0x0013
255 #define PGM_OPERAND 0x0015
256 #define PGM_TRACE_TABLE 0x0016
257 #define PGM_SPACE_SWITCH 0x001c
258 #define PGM_HFP_SQRT 0x001d
259 #define PGM_PC_TRANS_SPEC 0x001f
260 #define PGM_AFX_TRANS 0x0020
261 #define PGM_ASX_TRANS 0x0021
262 #define PGM_LX_TRANS 0x0022
263 #define PGM_EX_TRANS 0x0023
264 #define PGM_PRIM_AUTH 0x0024
265 #define PGM_SEC_AUTH 0x0025
266 #define PGM_ALET_SPEC 0x0028
267 #define PGM_ALEN_SPEC 0x0029
268 #define PGM_ALE_SEQ 0x002a
269 #define PGM_ASTE_VALID 0x002b
270 #define PGM_ASTE_SEQ 0x002c
271 #define PGM_EXT_AUTH 0x002d
272 #define PGM_STACK_FULL 0x0030
273 #define PGM_STACK_EMPTY 0x0031
274 #define PGM_STACK_SPEC 0x0032
275 #define PGM_STACK_TYPE 0x0033
276 #define PGM_STACK_OP 0x0034
277 #define PGM_ASCE_TYPE 0x0038
278 #define PGM_REG_FIRST_TRANS 0x0039
279 #define PGM_REG_SEC_TRANS 0x003a
280 #define PGM_REG_THIRD_TRANS 0x003b
281 #define PGM_MONITOR 0x0040
282 #define PGM_PER 0x0080
283 #define PGM_CRYPTO 0x0119
284
285 /* External Interrupts */
286 #define EXT_INTERRUPT_KEY 0x0040
287 #define EXT_CLOCK_COMP 0x1004
288 #define EXT_CPU_TIMER 0x1005
289 #define EXT_MALFUNCTION 0x1200
290 #define EXT_EMERGENCY 0x1201
291 #define EXT_EXTERNAL_CALL 0x1202
292 #define EXT_ETR 0x1406
293 #define EXT_SERVICE 0x2401
294 #define EXT_VIRTIO 0x2603
295
296 /* PSW defines */
297 #undef PSW_MASK_PER
298 #undef PSW_MASK_DAT
299 #undef PSW_MASK_IO
300 #undef PSW_MASK_EXT
301 #undef PSW_MASK_KEY
302 #undef PSW_SHIFT_KEY
303 #undef PSW_MASK_MCHECK
304 #undef PSW_MASK_WAIT
305 #undef PSW_MASK_PSTATE
306 #undef PSW_MASK_ASC
307 #undef PSW_SHIFT_ASC
308 #undef PSW_MASK_CC
309 #undef PSW_MASK_PM
310 #undef PSW_MASK_64
311 #undef PSW_MASK_32
312 #undef PSW_MASK_ESA_ADDR
313
314 #define PSW_MASK_PER 0x4000000000000000ULL
315 #define PSW_MASK_DAT 0x0400000000000000ULL
316 #define PSW_MASK_IO 0x0200000000000000ULL
317 #define PSW_MASK_EXT 0x0100000000000000ULL
318 #define PSW_MASK_KEY 0x00F0000000000000ULL
319 #define PSW_SHIFT_KEY 52
320 #define PSW_MASK_MCHECK 0x0004000000000000ULL
321 #define PSW_MASK_WAIT 0x0002000000000000ULL
322 #define PSW_MASK_PSTATE 0x0001000000000000ULL
323 #define PSW_MASK_ASC 0x0000C00000000000ULL
324 #define PSW_SHIFT_ASC 46
325 #define PSW_MASK_CC 0x0000300000000000ULL
326 #define PSW_MASK_PM 0x00000F0000000000ULL
327 #define PSW_MASK_64 0x0000000100000000ULL
328 #define PSW_MASK_32 0x0000000080000000ULL
329 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
330
331 #undef PSW_ASC_PRIMARY
332 #undef PSW_ASC_ACCREG
333 #undef PSW_ASC_SECONDARY
334 #undef PSW_ASC_HOME
335
336 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
337 #define PSW_ASC_ACCREG 0x0000400000000000ULL
338 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
339 #define PSW_ASC_HOME 0x0000C00000000000ULL
340
341 /* the address space values shifted */
342 #define AS_PRIMARY 0
343 #define AS_ACCREG 1
344 #define AS_SECONDARY 2
345 #define AS_HOME 3
346
347 /* tb flags */
348
349 #define FLAG_MASK_PSW_SHIFT 31
350 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
351 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
352 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
353 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
354 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
355 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
356 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
357
358 /* Control register 0 bits */
359 #define CR0_LOWPROT 0x0000000010000000ULL
360 #define CR0_SECONDARY 0x0000000004000000ULL
361 #define CR0_EDAT 0x0000000000800000ULL
362
363 /* MMU */
364 #define MMU_PRIMARY_IDX 0
365 #define MMU_SECONDARY_IDX 1
366 #define MMU_HOME_IDX 2
367
368 static inline bool psw_key_valid(CPUS390XState *env, uint8_t psw_key)
369 {
370 uint16_t pkm = env->cregs[3] >> 16;
371
372 if (env->psw.mask & PSW_MASK_PSTATE) {
373 /* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */
374 return pkm & (0x80 >> psw_key);
375 }
376 return true;
377 }
378
379 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
380 {
381 switch (env->psw.mask & PSW_MASK_ASC) {
382 case PSW_ASC_PRIMARY:
383 return MMU_PRIMARY_IDX;
384 case PSW_ASC_SECONDARY:
385 return MMU_SECONDARY_IDX;
386 case PSW_ASC_HOME:
387 return MMU_HOME_IDX;
388 case PSW_ASC_ACCREG:
389 /* Fallthrough: access register mode is not yet supported */
390 default:
391 abort();
392 }
393 }
394
395 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
396 {
397 switch (mmu_idx) {
398 case MMU_PRIMARY_IDX:
399 return PSW_ASC_PRIMARY;
400 case MMU_SECONDARY_IDX:
401 return PSW_ASC_SECONDARY;
402 case MMU_HOME_IDX:
403 return PSW_ASC_HOME;
404 default:
405 abort();
406 }
407 }
408
409 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
410 target_ulong *cs_base, uint32_t *flags)
411 {
412 *pc = env->psw.addr;
413 *cs_base = env->ex_value;
414 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
415 }
416
417 #define MAX_ILEN 6
418
419 /* While the PoO talks about ILC (a number between 1-3) what is actually
420 stored in LowCore is shifted left one bit (an even between 2-6). As
421 this is the actual length of the insn and therefore more useful, that
422 is what we want to pass around and manipulate. To make sure that we
423 have applied this distinction universally, rename the "ILC" to "ILEN". */
424 static inline int get_ilen(uint8_t opc)
425 {
426 switch (opc >> 6) {
427 case 0:
428 return 2;
429 case 1:
430 case 2:
431 return 4;
432 default:
433 return 6;
434 }
435 }
436
437 /* PER bits from control register 9 */
438 #define PER_CR9_EVENT_BRANCH 0x80000000
439 #define PER_CR9_EVENT_IFETCH 0x40000000
440 #define PER_CR9_EVENT_STORE 0x20000000
441 #define PER_CR9_EVENT_STORE_REAL 0x08000000
442 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
443 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
444 #define PER_CR9_CONTROL_ALTERATION 0x00200000
445
446 /* PER bits from the PER CODE/ATMID/AI in lowcore */
447 #define PER_CODE_EVENT_BRANCH 0x8000
448 #define PER_CODE_EVENT_IFETCH 0x4000
449 #define PER_CODE_EVENT_STORE 0x2000
450 #define PER_CODE_EVENT_STORE_REAL 0x0800
451 #define PER_CODE_EVENT_NULLIFICATION 0x0100
452
453 /* Compute the ATMID field that is stored in the per_perc_atmid lowcore
454 entry when a PER exception is triggered. */
455 static inline uint8_t get_per_atmid(CPUS390XState *env)
456 {
457 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
458 ( (1 << 6) ) |
459 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
460 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
461 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
462 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
463 }
464
465 /* Check if an address is within the PER starting address and the PER
466 ending address. The address range might loop. */
467 static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
468 {
469 if (env->cregs[10] <= env->cregs[11]) {
470 return env->cregs[10] <= addr && addr <= env->cregs[11];
471 } else {
472 return env->cregs[10] <= addr || addr <= env->cregs[11];
473 }
474 }
475
476 #ifndef CONFIG_USER_ONLY
477 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
478 #endif
479
480 S390CPU *cpu_s390x_init(const char *cpu_model);
481 S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
482 S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
483 void s390x_translate_init(void);
484
485 /* you can call this signal handler from your SIGBUS and SIGSEGV
486 signal handlers to inform the virtual CPU of exceptions. non zero
487 is returned if the signal was handled by the virtual CPU. */
488 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
489 void *puc);
490 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
491 int mmu_idx);
492
493
494 #ifndef CONFIG_USER_ONLY
495 void do_restart_interrupt(CPUS390XState *env);
496 void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
497 MMUAccessType access_type,
498 int mmu_idx, uintptr_t retaddr);
499
500 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
501 uint8_t *ar)
502 {
503 hwaddr addr = 0;
504 uint8_t reg;
505
506 reg = ipb >> 28;
507 if (reg > 0) {
508 addr = env->regs[reg];
509 }
510 addr += (ipb >> 16) & 0xfff;
511 if (ar) {
512 *ar = reg;
513 }
514
515 return addr;
516 }
517
518 /* Base/displacement are at the same locations. */
519 #define decode_basedisp_rs decode_basedisp_s
520
521 /* helper functions for run_on_cpu() */
522 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
523 {
524 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
525
526 scc->cpu_reset(cs);
527 }
528 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
529 {
530 cpu_reset(cs);
531 }
532
533 void s390x_tod_timer(void *opaque);
534 void s390x_cpu_timer(void *opaque);
535
536 int s390_virtio_hypercall(CPUS390XState *env);
537
538 #ifdef CONFIG_KVM
539 void kvm_s390_service_interrupt(uint32_t parm);
540 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
541 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
542 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
543 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
544 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
545 int len, bool is_write);
546 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
547 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
548 #else
549 static inline void kvm_s390_service_interrupt(uint32_t parm)
550 {
551 }
552 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
553 {
554 return -ENOSYS;
555 }
556 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
557 {
558 return -ENOSYS;
559 }
560 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
561 void *hostbuf, int len, bool is_write)
562 {
563 return -ENOSYS;
564 }
565 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
566 uint64_t te_code)
567 {
568 }
569 #endif
570
571 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
572 {
573 if (kvm_enabled()) {
574 return kvm_s390_get_clock(tod_high, tod_low);
575 }
576 /* Fixme TCG */
577 *tod_high = 0;
578 *tod_low = 0;
579 return 0;
580 }
581
582 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
583 {
584 if (kvm_enabled()) {
585 return kvm_s390_set_clock(tod_high, tod_low);
586 }
587 /* Fixme TCG */
588 return 0;
589 }
590
591 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
592 unsigned int s390_cpu_halt(S390CPU *cpu);
593 void s390_cpu_unhalt(S390CPU *cpu);
594 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
595 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
596 {
597 return cpu->env.cpu_state;
598 }
599
600 void gtod_save(QEMUFile *f, void *opaque);
601 int gtod_load(QEMUFile *f, void *opaque, int version_id);
602
603 void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
604 uint64_t param64);
605
606 /* ioinst.c */
607 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1);
608 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1);
609 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1);
610 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
611 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
612 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb);
613 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
614 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
615 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb);
616 int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb);
617 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
618 uint32_t ipb);
619 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1);
620 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1);
621 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1);
622
623 /* service interrupts are floating therefore we must not pass an cpustate */
624 void s390_sclp_extint(uint32_t parm);
625
626 #else
627 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
628 {
629 return 0;
630 }
631
632 static inline void s390_cpu_unhalt(S390CPU *cpu)
633 {
634 }
635
636 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
637 {
638 return 0;
639 }
640 #endif
641
642 extern void subsystem_reset(void);
643
644 #define cpu_init(model) CPU(cpu_s390x_init(model))
645 #define cpu_signal_handler cpu_s390x_signal_handler
646
647 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
648 #define cpu_list s390_cpu_list
649 void s390_cpu_model_register_props(Object *obj);
650 void s390_cpu_model_class_register_props(ObjectClass *oc);
651 void s390_realize_cpu_model(CPUState *cs, Error **errp);
652 ObjectClass *s390_cpu_class_by_name(const char *name);
653
654 #define EXCP_EXT 1 /* external interrupt */
655 #define EXCP_SVC 2 /* supervisor call (syscall) */
656 #define EXCP_PGM 3 /* program interruption */
657 #define EXCP_IO 7 /* I/O interrupt */
658 #define EXCP_MCHK 8 /* machine check */
659
660 #define INTERRUPT_EXT (1 << 0)
661 #define INTERRUPT_TOD (1 << 1)
662 #define INTERRUPT_CPUTIMER (1 << 2)
663 #define INTERRUPT_IO (1 << 3)
664 #define INTERRUPT_MCHK (1 << 4)
665
666 /* Program Status Word. */
667 #define S390_PSWM_REGNUM 0
668 #define S390_PSWA_REGNUM 1
669 /* General Purpose Registers. */
670 #define S390_R0_REGNUM 2
671 #define S390_R1_REGNUM 3
672 #define S390_R2_REGNUM 4
673 #define S390_R3_REGNUM 5
674 #define S390_R4_REGNUM 6
675 #define S390_R5_REGNUM 7
676 #define S390_R6_REGNUM 8
677 #define S390_R7_REGNUM 9
678 #define S390_R8_REGNUM 10
679 #define S390_R9_REGNUM 11
680 #define S390_R10_REGNUM 12
681 #define S390_R11_REGNUM 13
682 #define S390_R12_REGNUM 14
683 #define S390_R13_REGNUM 15
684 #define S390_R14_REGNUM 16
685 #define S390_R15_REGNUM 17
686 /* Total Core Registers. */
687 #define S390_NUM_CORE_REGS 18
688
689 /* CC optimization */
690
691 /* Instead of computing the condition codes after each x86 instruction,
692 * QEMU just stores the result (called CC_DST), the type of operation
693 * (called CC_OP) and whatever operands are needed (CC_SRC and possibly
694 * CC_VR). When the condition codes are needed, the condition codes can
695 * be calculated using this information. Condition codes are not generated
696 * if they are only needed for conditional branches.
697 */
698 enum cc_op {
699 CC_OP_CONST0 = 0, /* CC is 0 */
700 CC_OP_CONST1, /* CC is 1 */
701 CC_OP_CONST2, /* CC is 2 */
702 CC_OP_CONST3, /* CC is 3 */
703
704 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
705 CC_OP_STATIC, /* CC value is env->cc_op */
706
707 CC_OP_NZ, /* env->cc_dst != 0 */
708 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
709 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
710 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
711 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
712 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
713 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
714
715 CC_OP_ADD_64, /* overflow on add (64bit) */
716 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
717 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
718 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
719 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
720 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
721 CC_OP_ABS_64, /* sign eval on abs (64bit) */
722 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
723
724 CC_OP_ADD_32, /* overflow on add (32bit) */
725 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
726 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
727 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
728 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
729 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
730 CC_OP_ABS_32, /* sign eval on abs (64bit) */
731 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
732
733 CC_OP_COMP_32, /* complement */
734 CC_OP_COMP_64, /* complement */
735
736 CC_OP_TM_32, /* test under mask (32bit) */
737 CC_OP_TM_64, /* test under mask (64bit) */
738
739 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
740 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
741 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
742
743 CC_OP_ICM, /* insert characters under mask */
744 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
745 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
746 CC_OP_FLOGR, /* find leftmost one */
747 CC_OP_MAX
748 };
749
750 static const char *cc_names[] = {
751 [CC_OP_CONST0] = "CC_OP_CONST0",
752 [CC_OP_CONST1] = "CC_OP_CONST1",
753 [CC_OP_CONST2] = "CC_OP_CONST2",
754 [CC_OP_CONST3] = "CC_OP_CONST3",
755 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
756 [CC_OP_STATIC] = "CC_OP_STATIC",
757 [CC_OP_NZ] = "CC_OP_NZ",
758 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
759 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
760 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
761 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
762 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
763 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
764 [CC_OP_ADD_64] = "CC_OP_ADD_64",
765 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
766 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
767 [CC_OP_SUB_64] = "CC_OP_SUB_64",
768 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
769 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
770 [CC_OP_ABS_64] = "CC_OP_ABS_64",
771 [CC_OP_NABS_64] = "CC_OP_NABS_64",
772 [CC_OP_ADD_32] = "CC_OP_ADD_32",
773 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
774 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
775 [CC_OP_SUB_32] = "CC_OP_SUB_32",
776 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
777 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
778 [CC_OP_ABS_32] = "CC_OP_ABS_32",
779 [CC_OP_NABS_32] = "CC_OP_NABS_32",
780 [CC_OP_COMP_32] = "CC_OP_COMP_32",
781 [CC_OP_COMP_64] = "CC_OP_COMP_64",
782 [CC_OP_TM_32] = "CC_OP_TM_32",
783 [CC_OP_TM_64] = "CC_OP_TM_64",
784 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
785 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
786 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
787 [CC_OP_ICM] = "CC_OP_ICM",
788 [CC_OP_SLA_32] = "CC_OP_SLA_32",
789 [CC_OP_SLA_64] = "CC_OP_SLA_64",
790 [CC_OP_FLOGR] = "CC_OP_FLOGR",
791 };
792
793 static inline const char *cc_name(int cc_op)
794 {
795 return cc_names[cc_op];
796 }
797
798 static inline void setcc(S390CPU *cpu, uint64_t cc)
799 {
800 CPUS390XState *env = &cpu->env;
801
802 env->psw.mask &= ~(3ull << 44);
803 env->psw.mask |= (cc & 3) << 44;
804 env->cc_op = cc;
805 }
806
807 typedef struct LowCore
808 {
809 /* prefix area: defined by architecture */
810 uint32_t ccw1[2]; /* 0x000 */
811 uint32_t ccw2[4]; /* 0x008 */
812 uint8_t pad1[0x80-0x18]; /* 0x018 */
813 uint32_t ext_params; /* 0x080 */
814 uint16_t cpu_addr; /* 0x084 */
815 uint16_t ext_int_code; /* 0x086 */
816 uint16_t svc_ilen; /* 0x088 */
817 uint16_t svc_code; /* 0x08a */
818 uint16_t pgm_ilen; /* 0x08c */
819 uint16_t pgm_code; /* 0x08e */
820 uint32_t data_exc_code; /* 0x090 */
821 uint16_t mon_class_num; /* 0x094 */
822 uint16_t per_perc_atmid; /* 0x096 */
823 uint64_t per_address; /* 0x098 */
824 uint8_t exc_access_id; /* 0x0a0 */
825 uint8_t per_access_id; /* 0x0a1 */
826 uint8_t op_access_id; /* 0x0a2 */
827 uint8_t ar_access_id; /* 0x0a3 */
828 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
829 uint64_t trans_exc_code; /* 0x0a8 */
830 uint64_t monitor_code; /* 0x0b0 */
831 uint16_t subchannel_id; /* 0x0b8 */
832 uint16_t subchannel_nr; /* 0x0ba */
833 uint32_t io_int_parm; /* 0x0bc */
834 uint32_t io_int_word; /* 0x0c0 */
835 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
836 uint32_t stfl_fac_list; /* 0x0c8 */
837 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
838 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
839 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
840 uint32_t external_damage_code; /* 0x0f4 */
841 uint64_t failing_storage_address; /* 0x0f8 */
842 uint8_t pad6[0x110-0x100]; /* 0x100 */
843 uint64_t per_breaking_event_addr; /* 0x110 */
844 uint8_t pad7[0x120-0x118]; /* 0x118 */
845 PSW restart_old_psw; /* 0x120 */
846 PSW external_old_psw; /* 0x130 */
847 PSW svc_old_psw; /* 0x140 */
848 PSW program_old_psw; /* 0x150 */
849 PSW mcck_old_psw; /* 0x160 */
850 PSW io_old_psw; /* 0x170 */
851 uint8_t pad8[0x1a0-0x180]; /* 0x180 */
852 PSW restart_new_psw; /* 0x1a0 */
853 PSW external_new_psw; /* 0x1b0 */
854 PSW svc_new_psw; /* 0x1c0 */
855 PSW program_new_psw; /* 0x1d0 */
856 PSW mcck_new_psw; /* 0x1e0 */
857 PSW io_new_psw; /* 0x1f0 */
858 PSW return_psw; /* 0x200 */
859 uint8_t irb[64]; /* 0x210 */
860 uint64_t sync_enter_timer; /* 0x250 */
861 uint64_t async_enter_timer; /* 0x258 */
862 uint64_t exit_timer; /* 0x260 */
863 uint64_t last_update_timer; /* 0x268 */
864 uint64_t user_timer; /* 0x270 */
865 uint64_t system_timer; /* 0x278 */
866 uint64_t last_update_clock; /* 0x280 */
867 uint64_t steal_clock; /* 0x288 */
868 PSW return_mcck_psw; /* 0x290 */
869 uint8_t pad9[0xc00-0x2a0]; /* 0x2a0 */
870 /* System info area */
871 uint64_t save_area[16]; /* 0xc00 */
872 uint8_t pad10[0xd40-0xc80]; /* 0xc80 */
873 uint64_t kernel_stack; /* 0xd40 */
874 uint64_t thread_info; /* 0xd48 */
875 uint64_t async_stack; /* 0xd50 */
876 uint64_t kernel_asce; /* 0xd58 */
877 uint64_t user_asce; /* 0xd60 */
878 uint64_t panic_stack; /* 0xd68 */
879 uint64_t user_exec_asce; /* 0xd70 */
880 uint8_t pad11[0xdc0-0xd78]; /* 0xd78 */
881
882 /* SMP info area: defined by DJB */
883 uint64_t clock_comparator; /* 0xdc0 */
884 uint64_t ext_call_fast; /* 0xdc8 */
885 uint64_t percpu_offset; /* 0xdd0 */
886 uint64_t current_task; /* 0xdd8 */
887 uint32_t softirq_pending; /* 0xde0 */
888 uint32_t pad_0x0de4; /* 0xde4 */
889 uint64_t int_clock; /* 0xde8 */
890 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
891
892 /* 0xe00 is used as indicator for dump tools */
893 /* whether the kernel died with panic() or not */
894 uint32_t panic_magic; /* 0xe00 */
895
896 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
897
898 /* 64 bit extparam used for pfault, diag 250 etc */
899 uint64_t ext_params2; /* 0x11B8 */
900
901 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
902
903 /* System info area */
904
905 uint64_t floating_pt_save_area[16]; /* 0x1200 */
906 uint64_t gpregs_save_area[16]; /* 0x1280 */
907 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
908 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
909 uint32_t prefixreg_save_area; /* 0x1318 */
910 uint32_t fpt_creg_save_area; /* 0x131c */
911 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
912 uint32_t tod_progreg_save_area; /* 0x1324 */
913 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
914 uint32_t clock_comp_save_area[2]; /* 0x1330 */
915 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
916 uint32_t access_regs_save_area[16]; /* 0x1340 */
917 uint64_t cregs_save_area[16]; /* 0x1380 */
918
919 /* align to the top of the prefix area */
920
921 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
922 } QEMU_PACKED LowCore;
923
924 /* STSI */
925 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
926 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
927 #define STSI_LEVEL_1 0x0000000010000000ULL
928 #define STSI_LEVEL_2 0x0000000020000000ULL
929 #define STSI_LEVEL_3 0x0000000030000000ULL
930 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
931 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
932 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
933 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
934
935 /* Basic Machine Configuration */
936 struct sysib_111 {
937 uint32_t res1[8];
938 uint8_t manuf[16];
939 uint8_t type[4];
940 uint8_t res2[12];
941 uint8_t model[16];
942 uint8_t sequence[16];
943 uint8_t plant[4];
944 uint8_t res3[156];
945 };
946
947 /* Basic Machine CPU */
948 struct sysib_121 {
949 uint32_t res1[80];
950 uint8_t sequence[16];
951 uint8_t plant[4];
952 uint8_t res2[2];
953 uint16_t cpu_addr;
954 uint8_t res3[152];
955 };
956
957 /* Basic Machine CPUs */
958 struct sysib_122 {
959 uint8_t res1[32];
960 uint32_t capability;
961 uint16_t total_cpus;
962 uint16_t active_cpus;
963 uint16_t standby_cpus;
964 uint16_t reserved_cpus;
965 uint16_t adjustments[2026];
966 };
967
968 /* LPAR CPU */
969 struct sysib_221 {
970 uint32_t res1[80];
971 uint8_t sequence[16];
972 uint8_t plant[4];
973 uint16_t cpu_id;
974 uint16_t cpu_addr;
975 uint8_t res3[152];
976 };
977
978 /* LPAR CPUs */
979 struct sysib_222 {
980 uint32_t res1[32];
981 uint16_t lpar_num;
982 uint8_t res2;
983 uint8_t lcpuc;
984 uint16_t total_cpus;
985 uint16_t conf_cpus;
986 uint16_t standby_cpus;
987 uint16_t reserved_cpus;
988 uint8_t name[8];
989 uint32_t caf;
990 uint8_t res3[16];
991 uint16_t dedicated_cpus;
992 uint16_t shared_cpus;
993 uint8_t res4[180];
994 };
995
996 /* VM CPUs */
997 struct sysib_322 {
998 uint8_t res1[31];
999 uint8_t count;
1000 struct {
1001 uint8_t res2[4];
1002 uint16_t total_cpus;
1003 uint16_t conf_cpus;
1004 uint16_t standby_cpus;
1005 uint16_t reserved_cpus;
1006 uint8_t name[8];
1007 uint32_t caf;
1008 uint8_t cpi[16];
1009 uint8_t res5[3];
1010 uint8_t ext_name_encoding;
1011 uint32_t res3;
1012 uint8_t uuid[16];
1013 } vm[8];
1014 uint8_t res4[1504];
1015 uint8_t ext_names[8][256];
1016 };
1017
1018 /* MMU defines */
1019 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
1020 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
1021 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
1022 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
1023 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
1024 #define _ASCE_REAL_SPACE 0x20 /* real space control */
1025 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
1026 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
1027 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
1028 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
1029 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
1030 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
1031
1032 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
1033 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
1034 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
1035 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
1036 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
1037 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
1038 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
1039 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
1040 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
1041
1042 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
1043 #define _SEGMENT_ENTRY_FC 0x400 /* format control */
1044 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
1045 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1046
1047 #define VADDR_PX 0xff000 /* page index bits */
1048
1049 #define _PAGE_RO 0x200 /* HW read-only bit */
1050 #define _PAGE_INVALID 0x400 /* HW invalid bit */
1051 #define _PAGE_RES0 0x800 /* bit must be zero */
1052
1053 #define SK_C (0x1 << 1)
1054 #define SK_R (0x1 << 2)
1055 #define SK_F (0x1 << 3)
1056 #define SK_ACC_MASK (0xf << 4)
1057
1058 /* SIGP order codes */
1059 #define SIGP_SENSE 0x01
1060 #define SIGP_EXTERNAL_CALL 0x02
1061 #define SIGP_EMERGENCY 0x03
1062 #define SIGP_START 0x04
1063 #define SIGP_STOP 0x05
1064 #define SIGP_RESTART 0x06
1065 #define SIGP_STOP_STORE_STATUS 0x09
1066 #define SIGP_INITIAL_CPU_RESET 0x0b
1067 #define SIGP_CPU_RESET 0x0c
1068 #define SIGP_SET_PREFIX 0x0d
1069 #define SIGP_STORE_STATUS_ADDR 0x0e
1070 #define SIGP_SET_ARCH 0x12
1071 #define SIGP_STORE_ADTL_STATUS 0x17
1072
1073 /* SIGP condition codes */
1074 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
1075 #define SIGP_CC_STATUS_STORED 1
1076 #define SIGP_CC_BUSY 2
1077 #define SIGP_CC_NOT_OPERATIONAL 3
1078
1079 /* SIGP status bits */
1080 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1081 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1082 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1083 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1084 #define SIGP_STAT_STOPPED 0x00000040UL
1085 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1086 #define SIGP_STAT_CHECK_STOP 0x00000010UL
1087 #define SIGP_STAT_INOPERATIVE 0x00000004UL
1088 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
1089 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1090
1091 /* SIGP SET ARCHITECTURE modes */
1092 #define SIGP_MODE_ESA_S390 0
1093 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1094 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1095
1096 /* SIGP order code mask corresponding to bit positions 56-63 */
1097 #define SIGP_ORDER_MASK 0x000000ff
1098
1099 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1100 target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr);
1101 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1102 target_ulong *raddr, int *flags, bool exc);
1103 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1104 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1105 uint64_t vr);
1106 void s390_cpu_recompute_watchpoints(CPUState *cs);
1107
1108 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1109 int len, bool is_write);
1110
1111 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1112 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1113 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1114 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1115 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1116 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1117
1118 /* The value of the TOD clock for 1.1.1970. */
1119 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1120
1121 /* Converts ns to s390's clock format */
1122 static inline uint64_t time2tod(uint64_t ns) {
1123 return (ns << 9) / 125;
1124 }
1125
1126 /* Converts s390's clock format to ns */
1127 static inline uint64_t tod2time(uint64_t t) {
1128 return (t * 125) >> 9;
1129 }
1130
1131 /* from s390-virtio-ccw */
1132 #define MEM_SECTION_SIZE 0x10000000UL
1133 #define MAX_AVAIL_SLOTS 32
1134
1135 /* fpu_helper.c */
1136 uint32_t set_cc_nz_f32(float32 v);
1137 uint32_t set_cc_nz_f64(float64 v);
1138 uint32_t set_cc_nz_f128(float128 v);
1139
1140 /* misc_helper.c */
1141 #ifndef CONFIG_USER_ONLY
1142 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1143 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1144 #endif
1145 /* automatically detect the instruction length */
1146 #define ILEN_AUTO 0xff
1147 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1148 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1149 uintptr_t retaddr);
1150
1151 #ifdef CONFIG_KVM
1152 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1153 uint16_t subchannel_nr, uint32_t io_int_parm,
1154 uint32_t io_int_word);
1155 void kvm_s390_crw_mchk(void);
1156 void kvm_s390_enable_css_support(S390CPU *cpu);
1157 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1158 int vq, bool assign);
1159 int kvm_s390_cpu_restart(S390CPU *cpu);
1160 int kvm_s390_get_memslot_count(KVMState *s);
1161 int kvm_s390_cmma_active(void);
1162 void kvm_s390_cmma_reset(void);
1163 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1164 void kvm_s390_reset_vcpu(S390CPU *cpu);
1165 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1166 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1167 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1168 int kvm_s390_get_ri(void);
1169 void kvm_s390_crypto_reset(void);
1170 #else
1171 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1172 uint16_t subchannel_nr,
1173 uint32_t io_int_parm,
1174 uint32_t io_int_word)
1175 {
1176 }
1177 static inline void kvm_s390_crw_mchk(void)
1178 {
1179 }
1180 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1181 {
1182 }
1183 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1184 uint32_t sch, int vq,
1185 bool assign)
1186 {
1187 return -ENOSYS;
1188 }
1189 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1190 {
1191 return -ENOSYS;
1192 }
1193 static inline void kvm_s390_cmma_reset(void)
1194 {
1195 }
1196 static inline int kvm_s390_get_memslot_count(KVMState *s)
1197 {
1198 return MAX_AVAIL_SLOTS;
1199 }
1200 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1201 {
1202 return -ENOSYS;
1203 }
1204 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1205 {
1206 }
1207 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1208 uint64_t *hw_limit)
1209 {
1210 return 0;
1211 }
1212 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1213 {
1214 }
1215 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1216 {
1217 return 0;
1218 }
1219 static inline int kvm_s390_get_ri(void)
1220 {
1221 return 0;
1222 }
1223 static inline void kvm_s390_crypto_reset(void)
1224 {
1225 }
1226 #endif
1227
1228 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1229 {
1230 if (kvm_enabled()) {
1231 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1232 }
1233 return 0;
1234 }
1235
1236 static inline void s390_cmma_reset(void)
1237 {
1238 if (kvm_enabled()) {
1239 kvm_s390_cmma_reset();
1240 }
1241 }
1242
1243 static inline int s390_cpu_restart(S390CPU *cpu)
1244 {
1245 if (kvm_enabled()) {
1246 return kvm_s390_cpu_restart(cpu);
1247 }
1248 return -ENOSYS;
1249 }
1250
1251 static inline int s390_get_memslot_count(KVMState *s)
1252 {
1253 if (kvm_enabled()) {
1254 return kvm_s390_get_memslot_count(s);
1255 } else {
1256 return MAX_AVAIL_SLOTS;
1257 }
1258 }
1259
1260 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1261 uint32_t io_int_parm, uint32_t io_int_word);
1262 void s390_crw_mchk(void);
1263
1264 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1265 uint32_t sch_id, int vq,
1266 bool assign)
1267 {
1268 if (kvm_enabled()) {
1269 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1270 } else {
1271 return 0;
1272 }
1273 }
1274
1275 static inline void s390_crypto_reset(void)
1276 {
1277 if (kvm_enabled()) {
1278 kvm_s390_crypto_reset();
1279 }
1280 }
1281
1282 static inline bool s390_get_squash_mcss(void)
1283 {
1284 if (object_property_get_bool(OBJECT(qdev_get_machine()), "s390-squash-mcss",
1285 NULL)) {
1286 return true;
1287 }
1288
1289 return false;
1290 }
1291
1292 /* machine check interruption code */
1293
1294 /* subclasses */
1295 #define MCIC_SC_SD 0x8000000000000000ULL
1296 #define MCIC_SC_PD 0x4000000000000000ULL
1297 #define MCIC_SC_SR 0x2000000000000000ULL
1298 #define MCIC_SC_CD 0x0800000000000000ULL
1299 #define MCIC_SC_ED 0x0400000000000000ULL
1300 #define MCIC_SC_DG 0x0100000000000000ULL
1301 #define MCIC_SC_W 0x0080000000000000ULL
1302 #define MCIC_SC_CP 0x0040000000000000ULL
1303 #define MCIC_SC_SP 0x0020000000000000ULL
1304 #define MCIC_SC_CK 0x0010000000000000ULL
1305
1306 /* subclass modifiers */
1307 #define MCIC_SCM_B 0x0002000000000000ULL
1308 #define MCIC_SCM_DA 0x0000000020000000ULL
1309 #define MCIC_SCM_AP 0x0000000000080000ULL
1310
1311 /* storage errors */
1312 #define MCIC_SE_SE 0x0000800000000000ULL
1313 #define MCIC_SE_SC 0x0000400000000000ULL
1314 #define MCIC_SE_KE 0x0000200000000000ULL
1315 #define MCIC_SE_DS 0x0000100000000000ULL
1316 #define MCIC_SE_IE 0x0000000080000000ULL
1317
1318 /* validity bits */
1319 #define MCIC_VB_WP 0x0000080000000000ULL
1320 #define MCIC_VB_MS 0x0000040000000000ULL
1321 #define MCIC_VB_PM 0x0000020000000000ULL
1322 #define MCIC_VB_IA 0x0000010000000000ULL
1323 #define MCIC_VB_FA 0x0000008000000000ULL
1324 #define MCIC_VB_VR 0x0000004000000000ULL
1325 #define MCIC_VB_EC 0x0000002000000000ULL
1326 #define MCIC_VB_FP 0x0000001000000000ULL
1327 #define MCIC_VB_GR 0x0000000800000000ULL
1328 #define MCIC_VB_CR 0x0000000400000000ULL
1329 #define MCIC_VB_ST 0x0000000100000000ULL
1330 #define MCIC_VB_AR 0x0000000040000000ULL
1331 #define MCIC_VB_PR 0x0000000000200000ULL
1332 #define MCIC_VB_FC 0x0000000000100000ULL
1333 #define MCIC_VB_CT 0x0000000000020000ULL
1334 #define MCIC_VB_CC 0x0000000000010000ULL
1335
1336 #endif
AR7 emulation for QEMU