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hw: explicitly include qemu/log.h
[qemu/ar7.git] / hw / ppc / spapr.c
blobde1de1d06746f4aa8ebdcf4684297b2835dba1f4
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/device_tree.h"
41 #include "kvm_ppc.h"
42 #include "migration/migration.h"
43 #include "mmu-hash64.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/spapr.h"
51 #include "hw/ppc/spapr_vio.h"
52 #include "hw/pci-host/spapr.h"
53 #include "hw/ppc/xics.h"
54 #include "hw/pci/msi.h"
55
56 #include "hw/pci/pci.h"
57 #include "hw/scsi/scsi.h"
58 #include "hw/virtio/virtio-scsi.h"
59
60 #include "exec/address-spaces.h"
61 #include "hw/usb.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "trace.h"
65 #include "hw/nmi.h"
66
67 #include "hw/compat.h"
68 #include "qemu/cutils.h"
69
70 #include <libfdt.h>
71
72 /* SLOF memory layout:
73 *
74 * SLOF raw image loaded at 0, copies its romfs right below the flat
75 * device-tree, then position SLOF itself 31M below that
76 *
77 * So we set FW_OVERHEAD to 40MB which should account for all of that
78 * and more
79 *
80 * We load our kernel at 4M, leaving space for SLOF initial image
81 */
82 #define FDT_MAX_SIZE 0x100000
83 #define RTAS_MAX_SIZE 0x10000
84 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
85 #define FW_MAX_SIZE 0x400000
86 #define FW_FILE_NAME "slof.bin"
87 #define FW_OVERHEAD 0x2800000
88 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
89
90 #define MIN_RMA_SLOF 128UL
91
92 #define TIMEBASE_FREQ 512000000ULL
93
94 #define PHANDLE_XICP 0x00001111
95
96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
97
98 static XICSState *try_create_xics(const char *type, int nr_servers,
99 int nr_irqs, Error **errp)
100 {
101 Error *err = NULL;
102 DeviceState *dev;
103
104 dev = qdev_create(NULL, type);
105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
107 object_property_set_bool(OBJECT(dev), true, "realized", &err);
108 if (err) {
109 error_propagate(errp, err);
110 object_unparent(OBJECT(dev));
111 return NULL;
112 }
113 return XICS_COMMON(dev);
114 }
115
116 static XICSState *xics_system_init(MachineState *machine,
117 int nr_servers, int nr_irqs, Error **errp)
118 {
119 XICSState *icp = NULL;
120
121 if (kvm_enabled()) {
122 Error *err = NULL;
123
124 if (machine_kernel_irqchip_allowed(machine)) {
125 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
126 }
127 if (machine_kernel_irqchip_required(machine) && !icp) {
128 error_reportf_err(err,
129 "kernel_irqchip requested but unavailable: ");
130 } else {
131 error_free(err);
132 }
133 }
134
135 if (!icp) {
136 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
137 }
138
139 return icp;
140 }
141
142 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
143 int smt_threads)
144 {
145 int i, ret = 0;
146 uint32_t servers_prop[smt_threads];
147 uint32_t gservers_prop[smt_threads * 2];
148 int index = ppc_get_vcpu_dt_id(cpu);
149
150 if (cpu->cpu_version) {
151 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
152 if (ret < 0) {
153 return ret;
154 }
155 }
156
157 /* Build interrupt servers and gservers properties */
158 for (i = 0; i < smt_threads; i++) {
159 servers_prop[i] = cpu_to_be32(index + i);
160 /* Hack, direct the group queues back to cpu 0 */
161 gservers_prop[i*2] = cpu_to_be32(index + i);
162 gservers_prop[i*2 + 1] = 0;
163 }
164 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
165 servers_prop, sizeof(servers_prop));
166 if (ret < 0) {
167 return ret;
168 }
169 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
170 gservers_prop, sizeof(gservers_prop));
171
172 return ret;
173 }
174
175 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
176 {
177 int ret = 0;
178 PowerPCCPU *cpu = POWERPC_CPU(cs);
179 int index = ppc_get_vcpu_dt_id(cpu);
180 uint32_t associativity[] = {cpu_to_be32(0x5),
181 cpu_to_be32(0x0),
182 cpu_to_be32(0x0),
183 cpu_to_be32(0x0),
184 cpu_to_be32(cs->numa_node),
185 cpu_to_be32(index)};
186
187 /* Advertise NUMA via ibm,associativity */
188 if (nb_numa_nodes > 1) {
189 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
190 sizeof(associativity));
191 }
192
193 return ret;
194 }
195
196 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
197 {
198 int ret = 0, offset, cpus_offset;
199 CPUState *cs;
200 char cpu_model[32];
201 int smt = kvmppc_smt_threads();
202 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
203
204 CPU_FOREACH(cs) {
205 PowerPCCPU *cpu = POWERPC_CPU(cs);
206 DeviceClass *dc = DEVICE_GET_CLASS(cs);
207 int index = ppc_get_vcpu_dt_id(cpu);
208
209 if ((index % smt) != 0) {
210 continue;
211 }
212
213 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
214
215 cpus_offset = fdt_path_offset(fdt, "/cpus");
216 if (cpus_offset < 0) {
217 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
218 "cpus");
219 if (cpus_offset < 0) {
220 return cpus_offset;
221 }
222 }
223 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
224 if (offset < 0) {
225 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 return offset;
228 }
229 }
230
231 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
232 pft_size_prop, sizeof(pft_size_prop));
233 if (ret < 0) {
234 return ret;
235 }
236
237 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
238 if (ret < 0) {
239 return ret;
240 }
241
242 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
243 ppc_get_compat_smt_threads(cpu));
244 if (ret < 0) {
245 return ret;
246 }
247 }
248 return ret;
249 }
250
251
252 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
253 size_t maxsize)
254 {
255 size_t maxcells = maxsize / sizeof(uint32_t);
256 int i, j, count;
257 uint32_t *p = prop;
258
259 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
260 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
261
262 if (!sps->page_shift) {
263 break;
264 }
265 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
266 if (sps->enc[count].page_shift == 0) {
267 break;
268 }
269 }
270 if ((p - prop) >= (maxcells - 3 - count * 2)) {
271 break;
272 }
273 *(p++) = cpu_to_be32(sps->page_shift);
274 *(p++) = cpu_to_be32(sps->slb_enc);
275 *(p++) = cpu_to_be32(count);
276 for (j = 0; j < count; j++) {
277 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
278 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
279 }
280 }
281
282 return (p - prop) * sizeof(uint32_t);
283 }
284
285 static hwaddr spapr_node0_size(void)
286 {
287 MachineState *machine = MACHINE(qdev_get_machine());
288
289 if (nb_numa_nodes) {
290 int i;
291 for (i = 0; i < nb_numa_nodes; ++i) {
292 if (numa_info[i].node_mem) {
293 return MIN(pow2floor(numa_info[i].node_mem),
294 machine->ram_size);
295 }
296 }
297 }
298 return machine->ram_size;
299 }
300
301 #define _FDT(exp) \
302 do { \
303 int ret = (exp); \
304 if (ret < 0) { \
305 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
306 #exp, fdt_strerror(ret)); \
307 exit(1); \
308 } \
309 } while (0)
310
311 static void add_str(GString *s, const gchar *s1)
312 {
313 g_string_append_len(s, s1, strlen(s1) + 1);
314 }
315
316 static void *spapr_create_fdt_skel(hwaddr initrd_base,
317 hwaddr initrd_size,
318 hwaddr kernel_size,
319 bool little_endian,
320 const char *kernel_cmdline,
321 uint32_t epow_irq)
322 {
323 void *fdt;
324 uint32_t start_prop = cpu_to_be32(initrd_base);
325 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
326 GString *hypertas = g_string_sized_new(256);
327 GString *qemu_hypertas = g_string_sized_new(256);
328 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
329 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
330 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
331 char *buf;
332
333 add_str(hypertas, "hcall-pft");
334 add_str(hypertas, "hcall-term");
335 add_str(hypertas, "hcall-dabr");
336 add_str(hypertas, "hcall-interrupt");
337 add_str(hypertas, "hcall-tce");
338 add_str(hypertas, "hcall-vio");
339 add_str(hypertas, "hcall-splpar");
340 add_str(hypertas, "hcall-bulk");
341 add_str(hypertas, "hcall-set-mode");
342 add_str(qemu_hypertas, "hcall-memop1");
343
344 fdt = g_malloc0(FDT_MAX_SIZE);
345 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
346
347 if (kernel_size) {
348 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
349 }
350 if (initrd_size) {
351 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
352 }
353 _FDT((fdt_finish_reservemap(fdt)));
354
355 /* Root node */
356 _FDT((fdt_begin_node(fdt, "")));
357 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
358 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
359 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
360
361 /*
362 * Add info to guest to indentify which host is it being run on
363 * and what is the uuid of the guest
364 */
365 if (kvmppc_get_host_model(&buf)) {
366 _FDT((fdt_property_string(fdt, "host-model", buf)));
367 g_free(buf);
368 }
369 if (kvmppc_get_host_serial(&buf)) {
370 _FDT((fdt_property_string(fdt, "host-serial", buf)));
371 g_free(buf);
372 }
373
374 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
375 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
376 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
377 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
378 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
379 qemu_uuid[14], qemu_uuid[15]);
380
381 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
382 if (qemu_uuid_set) {
383 _FDT((fdt_property_string(fdt, "system-id", buf)));
384 }
385 g_free(buf);
386
387 if (qemu_get_vm_name()) {
388 _FDT((fdt_property_string(fdt, "ibm,partition-name",
389 qemu_get_vm_name())));
390 }
391
392 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
393 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
394
395 /* /chosen */
396 _FDT((fdt_begin_node(fdt, "chosen")));
397
398 /* Set Form1_affinity */
399 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
400
401 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
402 _FDT((fdt_property(fdt, "linux,initrd-start",
403 &start_prop, sizeof(start_prop))));
404 _FDT((fdt_property(fdt, "linux,initrd-end",
405 &end_prop, sizeof(end_prop))));
406 if (kernel_size) {
407 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
408 cpu_to_be64(kernel_size) };
409
410 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
411 if (little_endian) {
412 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
413 }
414 }
415 if (boot_menu) {
416 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
417 }
418 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
419 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
420 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
421
422 _FDT((fdt_end_node(fdt)));
423
424 /* RTAS */
425 _FDT((fdt_begin_node(fdt, "rtas")));
426
427 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
428 add_str(hypertas, "hcall-multi-tce");
429 }
430 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
431 hypertas->len)));
432 g_string_free(hypertas, TRUE);
433 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
434 qemu_hypertas->len)));
435 g_string_free(qemu_hypertas, TRUE);
436
437 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
438 refpoints, sizeof(refpoints))));
439
440 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
441 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
442 RTAS_EVENT_SCAN_RATE)));
443
444 if (msi_nonbroken) {
445 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
446 }
447
448 /*
449 * According to PAPR, rtas ibm,os-term does not guarantee a return
450 * back to the guest cpu.
451 *
452 * While an additional ibm,extended-os-term property indicates that
453 * rtas call return will always occur. Set this property.
454 */
455 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
456
457 _FDT((fdt_end_node(fdt)));
458
459 /* interrupt controller */
460 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
461
462 _FDT((fdt_property_string(fdt, "device_type",
463 "PowerPC-External-Interrupt-Presentation")));
464 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
465 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
466 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
467 interrupt_server_ranges_prop,
468 sizeof(interrupt_server_ranges_prop))));
469 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
470 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
471 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
472
473 _FDT((fdt_end_node(fdt)));
474
475 /* vdevice */
476 _FDT((fdt_begin_node(fdt, "vdevice")));
477
478 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
479 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
480 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
481 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
482 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
483 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
484
485 _FDT((fdt_end_node(fdt)));
486
487 /* event-sources */
488 spapr_events_fdt_skel(fdt, epow_irq);
489
490 /* /hypervisor node */
491 if (kvm_enabled()) {
492 uint8_t hypercall[16];
493
494 /* indicate KVM hypercall interface */
495 _FDT((fdt_begin_node(fdt, "hypervisor")));
496 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
497 if (kvmppc_has_cap_fixup_hcalls()) {
498 /*
499 * Older KVM versions with older guest kernels were broken with the
500 * magic page, don't allow the guest to map it.
501 */
502 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
503 sizeof(hypercall))) {
504 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
505 sizeof(hypercall))));
506 }
507 }
508 _FDT((fdt_end_node(fdt)));
509 }
510
511 _FDT((fdt_end_node(fdt))); /* close root node */
512 _FDT((fdt_finish(fdt)));
513
514 return fdt;
515 }
516
517 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
518 hwaddr size)
519 {
520 uint32_t associativity[] = {
521 cpu_to_be32(0x4), /* length */
522 cpu_to_be32(0x0), cpu_to_be32(0x0),
523 cpu_to_be32(0x0), cpu_to_be32(nodeid)
524 };
525 char mem_name[32];
526 uint64_t mem_reg_property[2];
527 int off;
528
529 mem_reg_property[0] = cpu_to_be64(start);
530 mem_reg_property[1] = cpu_to_be64(size);
531
532 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
533 off = fdt_add_subnode(fdt, 0, mem_name);
534 _FDT(off);
535 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
536 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
537 sizeof(mem_reg_property))));
538 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
539 sizeof(associativity))));
540 return off;
541 }
542
543 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
544 {
545 MachineState *machine = MACHINE(spapr);
546 hwaddr mem_start, node_size;
547 int i, nb_nodes = nb_numa_nodes;
548 NodeInfo *nodes = numa_info;
549 NodeInfo ramnode;
550
551 /* No NUMA nodes, assume there is just one node with whole RAM */
552 if (!nb_numa_nodes) {
553 nb_nodes = 1;
554 ramnode.node_mem = machine->ram_size;
555 nodes = &ramnode;
556 }
557
558 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
559 if (!nodes[i].node_mem) {
560 continue;
561 }
562 if (mem_start >= machine->ram_size) {
563 node_size = 0;
564 } else {
565 node_size = nodes[i].node_mem;
566 if (node_size > machine->ram_size - mem_start) {
567 node_size = machine->ram_size - mem_start;
568 }
569 }
570 if (!mem_start) {
571 /* ppc_spapr_init() checks for rma_size <= node0_size already */
572 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
573 mem_start += spapr->rma_size;
574 node_size -= spapr->rma_size;
575 }
576 for ( ; node_size; ) {
577 hwaddr sizetmp = pow2floor(node_size);
578
579 /* mem_start != 0 here */
580 if (ctzl(mem_start) < ctzl(sizetmp)) {
581 sizetmp = 1ULL << ctzl(mem_start);
582 }
583
584 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
585 node_size -= sizetmp;
586 mem_start += sizetmp;
587 }
588 }
589
590 return 0;
591 }
592
593 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
594 sPAPRMachineState *spapr)
595 {
596 PowerPCCPU *cpu = POWERPC_CPU(cs);
597 CPUPPCState *env = &cpu->env;
598 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
599 int index = ppc_get_vcpu_dt_id(cpu);
600 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
601 0xffffffff, 0xffffffff};
602 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
603 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
604 uint32_t page_sizes_prop[64];
605 size_t page_sizes_prop_size;
606 uint32_t vcpus_per_socket = smp_threads * smp_cores;
607 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
608
609 /* Note: we keep CI large pages off for now because a 64K capable guest
610 * provisioned with large pages might otherwise try to map a qemu
611 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
612 * even if that qemu runs on a 4k host.
613 *
614 * We can later add this bit back when we are confident this is not
615 * an issue (!HV KVM or 64K host)
616 */
617 uint8_t pa_features_206[] = { 6, 0,
618 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
619 uint8_t pa_features_207[] = { 24, 0,
620 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
621 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
622 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
623 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
624 uint8_t *pa_features;
625 size_t pa_size;
626
627 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
628 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
629
630 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
631 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
632 env->dcache_line_size)));
633 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
634 env->dcache_line_size)));
635 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
636 env->icache_line_size)));
637 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
638 env->icache_line_size)));
639
640 if (pcc->l1_dcache_size) {
641 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
642 pcc->l1_dcache_size)));
643 } else {
644 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
645 }
646 if (pcc->l1_icache_size) {
647 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
648 pcc->l1_icache_size)));
649 } else {
650 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
651 }
652
653 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
654 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
655 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
656 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
657 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
658 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
659
660 if (env->spr_cb[SPR_PURR].oea_read) {
661 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
662 }
663
664 if (env->mmu_model & POWERPC_MMU_1TSEG) {
665 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
666 segs, sizeof(segs))));
667 }
668
669 /* Advertise VMX/VSX (vector extensions) if available
670 * 0 / no property == no vector extensions
671 * 1 == VMX / Altivec available
672 * 2 == VSX available */
673 if (env->insns_flags & PPC_ALTIVEC) {
674 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
675
676 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
677 }
678
679 /* Advertise DFP (Decimal Floating Point) if available
680 * 0 / no property == no DFP
681 * 1 == DFP available */
682 if (env->insns_flags2 & PPC2_DFP) {
683 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
684 }
685
686 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
687 sizeof(page_sizes_prop));
688 if (page_sizes_prop_size) {
689 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
690 page_sizes_prop, page_sizes_prop_size)));
691 }
692
693 /* Do the ibm,pa-features property, adjust it for ci-large-pages */
694 if (env->mmu_model == POWERPC_MMU_2_06) {
695 pa_features = pa_features_206;
696 pa_size = sizeof(pa_features_206);
697 } else /* env->mmu_model == POWERPC_MMU_2_07 */ {
698 pa_features = pa_features_207;
699 pa_size = sizeof(pa_features_207);
700 }
701 if (env->ci_large_pages) {
702 pa_features[3] |= 0x20;
703 }
704 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
705
706 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
707 cs->cpu_index / vcpus_per_socket)));
708
709 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
710 pft_size_prop, sizeof(pft_size_prop))));
711
712 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
713
714 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
715 ppc_get_compat_smt_threads(cpu)));
716 }
717
718 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
719 {
720 CPUState *cs;
721 int cpus_offset;
722 char *nodename;
723 int smt = kvmppc_smt_threads();
724
725 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
726 _FDT(cpus_offset);
727 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
728 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
729
730 /*
731 * We walk the CPUs in reverse order to ensure that CPU DT nodes
732 * created by fdt_add_subnode() end up in the right order in FDT
733 * for the guest kernel the enumerate the CPUs correctly.
734 */
735 CPU_FOREACH_REVERSE(cs) {
736 PowerPCCPU *cpu = POWERPC_CPU(cs);
737 int index = ppc_get_vcpu_dt_id(cpu);
738 DeviceClass *dc = DEVICE_GET_CLASS(cs);
739 int offset;
740
741 if ((index % smt) != 0) {
742 continue;
743 }
744
745 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
746 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
747 g_free(nodename);
748 _FDT(offset);
749 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
750 }
751
752 }
753
754 /*
755 * Adds ibm,dynamic-reconfiguration-memory node.
756 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
757 * of this device tree node.
758 */
759 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
760 {
761 MachineState *machine = MACHINE(spapr);
762 int ret, i, offset;
763 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
764 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
765 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
766 uint32_t *int_buf, *cur_index, buf_len;
767 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
768
769 /*
770 * Don't create the node if there are no DR LMBs.
771 */
772 if (!nr_lmbs) {
773 return 0;
774 }
775
776 /*
777 * Allocate enough buffer size to fit in ibm,dynamic-memory
778 * or ibm,associativity-lookup-arrays
779 */
780 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
781 * sizeof(uint32_t);
782 cur_index = int_buf = g_malloc0(buf_len);
783
784 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
785
786 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
787 sizeof(prop_lmb_size));
788 if (ret < 0) {
789 goto out;
790 }
791
792 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
793 if (ret < 0) {
794 goto out;
795 }
796
797 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
798 if (ret < 0) {
799 goto out;
800 }
801
802 /* ibm,dynamic-memory */
803 int_buf[0] = cpu_to_be32(nr_lmbs);
804 cur_index++;
805 for (i = 0; i < nr_lmbs; i++) {
806 sPAPRDRConnector *drc;
807 sPAPRDRConnectorClass *drck;
808 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;;
809 uint32_t *dynamic_memory = cur_index;
810
811 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
812 addr/lmb_size);
813 g_assert(drc);
814 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
815
816 dynamic_memory[0] = cpu_to_be32(addr >> 32);
817 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
818 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
819 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
820 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
821 if (addr < machine->ram_size ||
822 memory_region_present(get_system_memory(), addr)) {
823 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
824 } else {
825 dynamic_memory[5] = cpu_to_be32(0);
826 }
827
828 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
829 }
830 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
831 if (ret < 0) {
832 goto out;
833 }
834
835 /* ibm,associativity-lookup-arrays */
836 cur_index = int_buf;
837 int_buf[0] = cpu_to_be32(nr_nodes);
838 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
839 cur_index += 2;
840 for (i = 0; i < nr_nodes; i++) {
841 uint32_t associativity[] = {
842 cpu_to_be32(0x0),
843 cpu_to_be32(0x0),
844 cpu_to_be32(0x0),
845 cpu_to_be32(i)
846 };
847 memcpy(cur_index, associativity, sizeof(associativity));
848 cur_index += 4;
849 }
850 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
851 (cur_index - int_buf) * sizeof(uint32_t));
852 out:
853 g_free(int_buf);
854 return ret;
855 }
856
857 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
858 target_ulong addr, target_ulong size,
859 bool cpu_update, bool memory_update)
860 {
861 void *fdt, *fdt_skel;
862 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
863 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
864
865 size -= sizeof(hdr);
866
867 /* Create sceleton */
868 fdt_skel = g_malloc0(size);
869 _FDT((fdt_create(fdt_skel, size)));
870 _FDT((fdt_begin_node(fdt_skel, "")));
871 _FDT((fdt_end_node(fdt_skel)));
872 _FDT((fdt_finish(fdt_skel)));
873 fdt = g_malloc0(size);
874 _FDT((fdt_open_into(fdt_skel, fdt, size)));
875 g_free(fdt_skel);
876
877 /* Fixup cpu nodes */
878 if (cpu_update) {
879 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
880 }
881
882 /* Generate ibm,dynamic-reconfiguration-memory node if required */
883 if (memory_update && smc->dr_lmb_enabled) {
884 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
885 }
886
887 /* Pack resulting tree */
888 _FDT((fdt_pack(fdt)));
889
890 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
891 trace_spapr_cas_failed(size);
892 return -1;
893 }
894
895 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
896 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
897 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
898 g_free(fdt);
899
900 return 0;
901 }
902
903 static void spapr_finalize_fdt(sPAPRMachineState *spapr,
904 hwaddr fdt_addr,
905 hwaddr rtas_addr,
906 hwaddr rtas_size)
907 {
908 MachineState *machine = MACHINE(qdev_get_machine());
909 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
910 const char *boot_device = machine->boot_order;
911 int ret, i;
912 size_t cb = 0;
913 char *bootlist;
914 void *fdt;
915 sPAPRPHBState *phb;
916
917 fdt = g_malloc(FDT_MAX_SIZE);
918
919 /* open out the base tree into a temp buffer for the final tweaks */
920 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
921
922 ret = spapr_populate_memory(spapr, fdt);
923 if (ret < 0) {
924 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
925 exit(1);
926 }
927
928 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
929 if (ret < 0) {
930 fprintf(stderr, "couldn't setup vio devices in fdt\n");
931 exit(1);
932 }
933
934 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
935 ret = spapr_rng_populate_dt(fdt);
936 if (ret < 0) {
937 fprintf(stderr, "could not set up rng device in the fdt\n");
938 exit(1);
939 }
940 }
941
942 QLIST_FOREACH(phb, &spapr->phbs, list) {
943 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
944 if (ret < 0) {
945 error_report("couldn't setup PCI devices in fdt");
946 exit(1);
947 }
948 }
949
950 /* RTAS */
951 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
952 if (ret < 0) {
953 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
954 }
955
956 /* cpus */
957 spapr_populate_cpus_dt_node(fdt, spapr);
958
959 bootlist = get_boot_devices_list(&cb, true);
960 if (cb && bootlist) {
961 int offset = fdt_path_offset(fdt, "/chosen");
962 if (offset < 0) {
963 exit(1);
964 }
965 for (i = 0; i < cb; i++) {
966 if (bootlist[i] == '\n') {
967 bootlist[i] = ' ';
968 }
969
970 }
971 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
972 }
973
974 if (boot_device && strlen(boot_device)) {
975 int offset = fdt_path_offset(fdt, "/chosen");
976
977 if (offset < 0) {
978 exit(1);
979 }
980 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
981 }
982
983 if (!spapr->has_graphics) {
984 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
985 }
986
987 if (smc->dr_lmb_enabled) {
988 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
989 }
990
991 _FDT((fdt_pack(fdt)));
992
993 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
994 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
995 fdt_totalsize(fdt), FDT_MAX_SIZE);
996 exit(1);
997 }
998
999 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1000 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1001
1002 g_free(bootlist);
1003 g_free(fdt);
1004 }
1005
1006 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1007 {
1008 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1009 }
1010
1011 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1012 {
1013 CPUPPCState *env = &cpu->env;
1014
1015 if (msr_pr) {
1016 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1017 env->gpr[3] = H_PRIVILEGE;
1018 } else {
1019 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1020 }
1021 }
1022
1023 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1024 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1025 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1026 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1027 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1028
1029 /*
1030 * Get the fd to access the kernel htab, re-opening it if necessary
1031 */
1032 static int get_htab_fd(sPAPRMachineState *spapr)
1033 {
1034 if (spapr->htab_fd >= 0) {
1035 return spapr->htab_fd;
1036 }
1037
1038 spapr->htab_fd = kvmppc_get_htab_fd(false);
1039 if (spapr->htab_fd < 0) {
1040 error_report("Unable to open fd for reading hash table from KVM: %s",
1041 strerror(errno));
1042 }
1043
1044 return spapr->htab_fd;
1045 }
1046
1047 static void close_htab_fd(sPAPRMachineState *spapr)
1048 {
1049 if (spapr->htab_fd >= 0) {
1050 close(spapr->htab_fd);
1051 }
1052 spapr->htab_fd = -1;
1053 }
1054
1055 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1056 {
1057 int shift;
1058
1059 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1060 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1061 * that's much more than is needed for Linux guests */
1062 shift = ctz64(pow2ceil(ramsize)) - 7;
1063 shift = MAX(shift, 18); /* Minimum architected size */
1064 shift = MIN(shift, 46); /* Maximum architected size */
1065 return shift;
1066 }
1067
1068 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1069 Error **errp)
1070 {
1071 long rc;
1072
1073 /* Clean up any HPT info from a previous boot */
1074 g_free(spapr->htab);
1075 spapr->htab = NULL;
1076 spapr->htab_shift = 0;
1077 close_htab_fd(spapr);
1078
1079 rc = kvmppc_reset_htab(shift);
1080 if (rc < 0) {
1081 /* kernel-side HPT needed, but couldn't allocate one */
1082 error_setg_errno(errp, errno,
1083 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1084 shift);
1085 /* This is almost certainly fatal, but if the caller really
1086 * wants to carry on with shift == 0, it's welcome to try */
1087 } else if (rc > 0) {
1088 /* kernel-side HPT allocated */
1089 if (rc != shift) {
1090 error_setg(errp,
1091 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1092 shift, rc);
1093 }
1094
1095 spapr->htab_shift = shift;
1096 spapr->htab = NULL;
1097 } else {
1098 /* kernel-side HPT not needed, allocate in userspace instead */
1099 size_t size = 1ULL << shift;
1100 int i;
1101
1102 spapr->htab = qemu_memalign(size, size);
1103 if (!spapr->htab) {
1104 error_setg_errno(errp, errno,
1105 "Could not allocate HPT of order %d", shift);
1106 return;
1107 }
1108
1109 memset(spapr->htab, 0, size);
1110 spapr->htab_shift = shift;
1111
1112 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1113 DIRTY_HPTE(HPTE(spapr->htab, i));
1114 }
1115 }
1116 }
1117
1118 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1119 {
1120 bool matched = false;
1121
1122 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1123 matched = true;
1124 }
1125
1126 if (!matched) {
1127 error_report("Device %s is not supported by this machine yet.",
1128 qdev_fw_name(DEVICE(sbdev)));
1129 exit(1);
1130 }
1131
1132 return 0;
1133 }
1134
1135 static void ppc_spapr_reset(void)
1136 {
1137 MachineState *machine = MACHINE(qdev_get_machine());
1138 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1139 PowerPCCPU *first_ppc_cpu;
1140 uint32_t rtas_limit;
1141
1142 /* Check for unknown sysbus devices */
1143 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1144
1145 /* Allocate and/or reset the hash page table */
1146 spapr_reallocate_hpt(spapr,
1147 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1148 &error_fatal);
1149
1150 /* Update the RMA size if necessary */
1151 if (spapr->vrma_adjust) {
1152 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1153 spapr->htab_shift);
1154 }
1155
1156 qemu_devices_reset();
1157
1158 /*
1159 * We place the device tree and RTAS just below either the top of the RMA,
1160 * or just below 2GB, whichever is lowere, so that it can be
1161 * processed with 32-bit real mode code if necessary
1162 */
1163 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1164 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1165 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1166
1167 /* Load the fdt */
1168 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1169 spapr->rtas_size);
1170
1171 /* Copy RTAS over */
1172 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1173 spapr->rtas_size);
1174
1175 /* Set up the entry state */
1176 first_ppc_cpu = POWERPC_CPU(first_cpu);
1177 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1178 first_ppc_cpu->env.gpr[5] = 0;
1179 first_cpu->halted = 0;
1180 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1181
1182 }
1183
1184 static void spapr_cpu_reset(void *opaque)
1185 {
1186 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1187 PowerPCCPU *cpu = opaque;
1188 CPUState *cs = CPU(cpu);
1189 CPUPPCState *env = &cpu->env;
1190
1191 cpu_reset(cs);
1192
1193 /* All CPUs start halted. CPU0 is unhalted from the machine level
1194 * reset code and the rest are explicitly started up by the guest
1195 * using an RTAS call */
1196 cs->halted = 1;
1197
1198 env->spr[SPR_HIOR] = 0;
1199
1200 ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
1201 &error_fatal);
1202 }
1203
1204 static void spapr_create_nvram(sPAPRMachineState *spapr)
1205 {
1206 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1207 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1208
1209 if (dinfo) {
1210 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1211 &error_fatal);
1212 }
1213
1214 qdev_init_nofail(dev);
1215
1216 spapr->nvram = (struct sPAPRNVRAM *)dev;
1217 }
1218
1219 static void spapr_rtc_create(sPAPRMachineState *spapr)
1220 {
1221 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1222
1223 qdev_init_nofail(dev);
1224 spapr->rtc = dev;
1225
1226 object_property_add_alias(qdev_get_machine(), "rtc-time",
1227 OBJECT(spapr->rtc), "date", NULL);
1228 }
1229
1230 /* Returns whether we want to use VGA or not */
1231 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1232 {
1233 switch (vga_interface_type) {
1234 case VGA_NONE:
1235 return false;
1236 case VGA_DEVICE:
1237 return true;
1238 case VGA_STD:
1239 case VGA_VIRTIO:
1240 return pci_vga_init(pci_bus) != NULL;
1241 default:
1242 error_setg(errp,
1243 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1244 return false;
1245 }
1246 }
1247
1248 static int spapr_post_load(void *opaque, int version_id)
1249 {
1250 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1251 int err = 0;
1252
1253 /* In earlier versions, there was no separate qdev for the PAPR
1254 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1255 * So when migrating from those versions, poke the incoming offset
1256 * value into the RTC device */
1257 if (version_id < 3) {
1258 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1259 }
1260
1261 return err;
1262 }
1263
1264 static bool version_before_3(void *opaque, int version_id)
1265 {
1266 return version_id < 3;
1267 }
1268
1269 static const VMStateDescription vmstate_spapr = {
1270 .name = "spapr",
1271 .version_id = 3,
1272 .minimum_version_id = 1,
1273 .post_load = spapr_post_load,
1274 .fields = (VMStateField[]) {
1275 /* used to be @next_irq */
1276 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1277
1278 /* RTC offset */
1279 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1280
1281 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1282 VMSTATE_END_OF_LIST()
1283 },
1284 };
1285
1286 static int htab_save_setup(QEMUFile *f, void *opaque)
1287 {
1288 sPAPRMachineState *spapr = opaque;
1289
1290 /* "Iteration" header */
1291 qemu_put_be32(f, spapr->htab_shift);
1292
1293 if (spapr->htab) {
1294 spapr->htab_save_index = 0;
1295 spapr->htab_first_pass = true;
1296 } else {
1297 assert(kvm_enabled());
1298 }
1299
1300
1301 return 0;
1302 }
1303
1304 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1305 int64_t max_ns)
1306 {
1307 bool has_timeout = max_ns != -1;
1308 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1309 int index = spapr->htab_save_index;
1310 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1311
1312 assert(spapr->htab_first_pass);
1313
1314 do {
1315 int chunkstart;
1316
1317 /* Consume invalid HPTEs */
1318 while ((index < htabslots)
1319 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1320 index++;
1321 CLEAN_HPTE(HPTE(spapr->htab, index));
1322 }
1323
1324 /* Consume valid HPTEs */
1325 chunkstart = index;
1326 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1327 && HPTE_VALID(HPTE(spapr->htab, index))) {
1328 index++;
1329 CLEAN_HPTE(HPTE(spapr->htab, index));
1330 }
1331
1332 if (index > chunkstart) {
1333 int n_valid = index - chunkstart;
1334
1335 qemu_put_be32(f, chunkstart);
1336 qemu_put_be16(f, n_valid);
1337 qemu_put_be16(f, 0);
1338 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1339 HASH_PTE_SIZE_64 * n_valid);
1340
1341 if (has_timeout &&
1342 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1343 break;
1344 }
1345 }
1346 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1347
1348 if (index >= htabslots) {
1349 assert(index == htabslots);
1350 index = 0;
1351 spapr->htab_first_pass = false;
1352 }
1353 spapr->htab_save_index = index;
1354 }
1355
1356 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1357 int64_t max_ns)
1358 {
1359 bool final = max_ns < 0;
1360 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1361 int examined = 0, sent = 0;
1362 int index = spapr->htab_save_index;
1363 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1364
1365 assert(!spapr->htab_first_pass);
1366
1367 do {
1368 int chunkstart, invalidstart;
1369
1370 /* Consume non-dirty HPTEs */
1371 while ((index < htabslots)
1372 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1373 index++;
1374 examined++;
1375 }
1376
1377 chunkstart = index;
1378 /* Consume valid dirty HPTEs */
1379 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1380 && HPTE_DIRTY(HPTE(spapr->htab, index))
1381 && HPTE_VALID(HPTE(spapr->htab, index))) {
1382 CLEAN_HPTE(HPTE(spapr->htab, index));
1383 index++;
1384 examined++;
1385 }
1386
1387 invalidstart = index;
1388 /* Consume invalid dirty HPTEs */
1389 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1390 && HPTE_DIRTY(HPTE(spapr->htab, index))
1391 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1392 CLEAN_HPTE(HPTE(spapr->htab, index));
1393 index++;
1394 examined++;
1395 }
1396
1397 if (index > chunkstart) {
1398 int n_valid = invalidstart - chunkstart;
1399 int n_invalid = index - invalidstart;
1400
1401 qemu_put_be32(f, chunkstart);
1402 qemu_put_be16(f, n_valid);
1403 qemu_put_be16(f, n_invalid);
1404 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1405 HASH_PTE_SIZE_64 * n_valid);
1406 sent += index - chunkstart;
1407
1408 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1409 break;
1410 }
1411 }
1412
1413 if (examined >= htabslots) {
1414 break;
1415 }
1416
1417 if (index >= htabslots) {
1418 assert(index == htabslots);
1419 index = 0;
1420 }
1421 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1422
1423 if (index >= htabslots) {
1424 assert(index == htabslots);
1425 index = 0;
1426 }
1427
1428 spapr->htab_save_index = index;
1429
1430 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1431 }
1432
1433 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1434 #define MAX_KVM_BUF_SIZE 2048
1435
1436 static int htab_save_iterate(QEMUFile *f, void *opaque)
1437 {
1438 sPAPRMachineState *spapr = opaque;
1439 int fd;
1440 int rc = 0;
1441
1442 /* Iteration header */
1443 qemu_put_be32(f, 0);
1444
1445 if (!spapr->htab) {
1446 assert(kvm_enabled());
1447
1448 fd = get_htab_fd(spapr);
1449 if (fd < 0) {
1450 return fd;
1451 }
1452
1453 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1454 if (rc < 0) {
1455 return rc;
1456 }
1457 } else if (spapr->htab_first_pass) {
1458 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1459 } else {
1460 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1461 }
1462
1463 /* End marker */
1464 qemu_put_be32(f, 0);
1465 qemu_put_be16(f, 0);
1466 qemu_put_be16(f, 0);
1467
1468 return rc;
1469 }
1470
1471 static int htab_save_complete(QEMUFile *f, void *opaque)
1472 {
1473 sPAPRMachineState *spapr = opaque;
1474 int fd;
1475
1476 /* Iteration header */
1477 qemu_put_be32(f, 0);
1478
1479 if (!spapr->htab) {
1480 int rc;
1481
1482 assert(kvm_enabled());
1483
1484 fd = get_htab_fd(spapr);
1485 if (fd < 0) {
1486 return fd;
1487 }
1488
1489 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1490 if (rc < 0) {
1491 return rc;
1492 }
1493 close_htab_fd(spapr);
1494 } else {
1495 if (spapr->htab_first_pass) {
1496 htab_save_first_pass(f, spapr, -1);
1497 }
1498 htab_save_later_pass(f, spapr, -1);
1499 }
1500
1501 /* End marker */
1502 qemu_put_be32(f, 0);
1503 qemu_put_be16(f, 0);
1504 qemu_put_be16(f, 0);
1505
1506 return 0;
1507 }
1508
1509 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1510 {
1511 sPAPRMachineState *spapr = opaque;
1512 uint32_t section_hdr;
1513 int fd = -1;
1514
1515 if (version_id < 1 || version_id > 1) {
1516 error_report("htab_load() bad version");
1517 return -EINVAL;
1518 }
1519
1520 section_hdr = qemu_get_be32(f);
1521
1522 if (section_hdr) {
1523 Error *local_err = NULL;
1524
1525 /* First section gives the htab size */
1526 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1527 if (local_err) {
1528 error_report_err(local_err);
1529 return -EINVAL;
1530 }
1531 return 0;
1532 }
1533
1534 if (!spapr->htab) {
1535 assert(kvm_enabled());
1536
1537 fd = kvmppc_get_htab_fd(true);
1538 if (fd < 0) {
1539 error_report("Unable to open fd to restore KVM hash table: %s",
1540 strerror(errno));
1541 }
1542 }
1543
1544 while (true) {
1545 uint32_t index;
1546 uint16_t n_valid, n_invalid;
1547
1548 index = qemu_get_be32(f);
1549 n_valid = qemu_get_be16(f);
1550 n_invalid = qemu_get_be16(f);
1551
1552 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1553 /* End of Stream */
1554 break;
1555 }
1556
1557 if ((index + n_valid + n_invalid) >
1558 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1559 /* Bad index in stream */
1560 error_report(
1561 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1562 index, n_valid, n_invalid, spapr->htab_shift);
1563 return -EINVAL;
1564 }
1565
1566 if (spapr->htab) {
1567 if (n_valid) {
1568 qemu_get_buffer(f, HPTE(spapr->htab, index),
1569 HASH_PTE_SIZE_64 * n_valid);
1570 }
1571 if (n_invalid) {
1572 memset(HPTE(spapr->htab, index + n_valid), 0,
1573 HASH_PTE_SIZE_64 * n_invalid);
1574 }
1575 } else {
1576 int rc;
1577
1578 assert(fd >= 0);
1579
1580 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1581 if (rc < 0) {
1582 return rc;
1583 }
1584 }
1585 }
1586
1587 if (!spapr->htab) {
1588 assert(fd >= 0);
1589 close(fd);
1590 }
1591
1592 return 0;
1593 }
1594
1595 static SaveVMHandlers savevm_htab_handlers = {
1596 .save_live_setup = htab_save_setup,
1597 .save_live_iterate = htab_save_iterate,
1598 .save_live_complete_precopy = htab_save_complete,
1599 .load_state = htab_load,
1600 };
1601
1602 static void spapr_boot_set(void *opaque, const char *boot_device,
1603 Error **errp)
1604 {
1605 MachineState *machine = MACHINE(qdev_get_machine());
1606 machine->boot_order = g_strdup(boot_device);
1607 }
1608
1609 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
1610 Error **errp)
1611 {
1612 CPUPPCState *env = &cpu->env;
1613
1614 /* Set time-base frequency to 512 MHz */
1615 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
1616
1617 /* Enable PAPR mode in TCG or KVM */
1618 cpu_ppc_set_papr(cpu);
1619
1620 if (cpu->max_compat) {
1621 Error *local_err = NULL;
1622
1623 ppc_set_compat(cpu, cpu->max_compat, &local_err);
1624 if (local_err) {
1625 error_propagate(errp, local_err);
1626 return;
1627 }
1628 }
1629
1630 xics_cpu_setup(spapr->icp, cpu);
1631
1632 qemu_register_reset(spapr_cpu_reset, cpu);
1633 }
1634
1635 /*
1636 * Reset routine for LMB DR devices.
1637 *
1638 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1639 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1640 * when it walks all its children devices. LMB devices reset occurs
1641 * as part of spapr_ppc_reset().
1642 */
1643 static void spapr_drc_reset(void *opaque)
1644 {
1645 sPAPRDRConnector *drc = opaque;
1646 DeviceState *d = DEVICE(drc);
1647
1648 if (d) {
1649 device_reset(d);
1650 }
1651 }
1652
1653 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1654 {
1655 MachineState *machine = MACHINE(spapr);
1656 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1657 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1658 int i;
1659
1660 for (i = 0; i < nr_lmbs; i++) {
1661 sPAPRDRConnector *drc;
1662 uint64_t addr;
1663
1664 addr = i * lmb_size + spapr->hotplug_memory.base;
1665 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1666 addr/lmb_size);
1667 qemu_register_reset(spapr_drc_reset, drc);
1668 }
1669 }
1670
1671 /*
1672 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1673 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1674 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1675 */
1676 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1677 {
1678 int i;
1679
1680 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1681 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1682 " is not aligned to %llu MiB",
1683 machine->ram_size,
1684 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1685 return;
1686 }
1687
1688 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1689 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1690 " is not aligned to %llu MiB",
1691 machine->ram_size,
1692 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1693 return;
1694 }
1695
1696 for (i = 0; i < nb_numa_nodes; i++) {
1697 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1698 error_setg(errp,
1699 "Node %d memory size 0x%" PRIx64
1700 " is not aligned to %llu MiB",
1701 i, numa_info[i].node_mem,
1702 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1703 return;
1704 }
1705 }
1706 }
1707
1708 /* pSeries LPAR / sPAPR hardware init */
1709 static void ppc_spapr_init(MachineState *machine)
1710 {
1711 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1712 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1713 const char *kernel_filename = machine->kernel_filename;
1714 const char *kernel_cmdline = machine->kernel_cmdline;
1715 const char *initrd_filename = machine->initrd_filename;
1716 PowerPCCPU *cpu;
1717 PCIHostState *phb;
1718 int i;
1719 MemoryRegion *sysmem = get_system_memory();
1720 MemoryRegion *ram = g_new(MemoryRegion, 1);
1721 MemoryRegion *rma_region;
1722 void *rma = NULL;
1723 hwaddr rma_alloc_size;
1724 hwaddr node0_size = spapr_node0_size();
1725 uint32_t initrd_base = 0;
1726 long kernel_size = 0, initrd_size = 0;
1727 long load_limit, fw_size;
1728 bool kernel_le = false;
1729 char *filename;
1730
1731 msi_nonbroken = true;
1732
1733 QLIST_INIT(&spapr->phbs);
1734
1735 cpu_ppc_hypercall = emulate_spapr_hypercall;
1736
1737 /* Allocate RMA if necessary */
1738 rma_alloc_size = kvmppc_alloc_rma(&rma);
1739
1740 if (rma_alloc_size == -1) {
1741 error_report("Unable to create RMA");
1742 exit(1);
1743 }
1744
1745 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1746 spapr->rma_size = rma_alloc_size;
1747 } else {
1748 spapr->rma_size = node0_size;
1749
1750 /* With KVM, we don't actually know whether KVM supports an
1751 * unbounded RMA (PR KVM) or is limited by the hash table size
1752 * (HV KVM using VRMA), so we always assume the latter
1753 *
1754 * In that case, we also limit the initial allocations for RTAS
1755 * etc... to 256M since we have no way to know what the VRMA size
1756 * is going to be as it depends on the size of the hash table
1757 * isn't determined yet.
1758 */
1759 if (kvm_enabled()) {
1760 spapr->vrma_adjust = 1;
1761 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1762 }
1763 }
1764
1765 if (spapr->rma_size > node0_size) {
1766 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1767 spapr->rma_size);
1768 exit(1);
1769 }
1770
1771 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1772 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1773
1774 /* Set up Interrupt Controller before we create the VCPUs */
1775 spapr->icp = xics_system_init(machine,
1776 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
1777 smp_threads),
1778 XICS_IRQS, &error_fatal);
1779
1780 if (smc->dr_lmb_enabled) {
1781 spapr_validate_node_memory(machine, &error_fatal);
1782 }
1783
1784 /* init CPUs */
1785 if (machine->cpu_model == NULL) {
1786 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
1787 }
1788 for (i = 0; i < smp_cpus; i++) {
1789 cpu = cpu_ppc_init(machine->cpu_model);
1790 if (cpu == NULL) {
1791 error_report("Unable to find PowerPC CPU definition");
1792 exit(1);
1793 }
1794 spapr_cpu_init(spapr, cpu, &error_fatal);
1795 }
1796
1797 if (kvm_enabled()) {
1798 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1799 kvmppc_enable_logical_ci_hcalls();
1800 kvmppc_enable_set_mode_hcall();
1801 }
1802
1803 /* allocate RAM */
1804 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1805 machine->ram_size);
1806 memory_region_add_subregion(sysmem, 0, ram);
1807
1808 if (rma_alloc_size && rma) {
1809 rma_region = g_new(MemoryRegion, 1);
1810 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1811 rma_alloc_size, rma);
1812 vmstate_register_ram_global(rma_region);
1813 memory_region_add_subregion(sysmem, 0, rma_region);
1814 }
1815
1816 /* initialize hotplug memory address space */
1817 if (machine->ram_size < machine->maxram_size) {
1818 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1819
1820 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) {
1821 error_report("Specified number of memory slots %"
1822 PRIu64" exceeds max supported %d",
1823 machine->ram_slots, SPAPR_MAX_RAM_SLOTS);
1824 exit(1);
1825 }
1826
1827 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1828 SPAPR_HOTPLUG_MEM_ALIGN);
1829 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1830 "hotplug-memory", hotplug_mem_size);
1831 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1832 &spapr->hotplug_memory.mr);
1833 }
1834
1835 if (smc->dr_lmb_enabled) {
1836 spapr_create_lmb_dr_connectors(spapr);
1837 }
1838
1839 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1840 if (!filename) {
1841 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1842 exit(1);
1843 }
1844 spapr->rtas_size = get_image_size(filename);
1845 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1846 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1847 error_report("Could not load LPAR rtas '%s'", filename);
1848 exit(1);
1849 }
1850 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1851 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1852 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1853 exit(1);
1854 }
1855 g_free(filename);
1856
1857 /* Set up EPOW events infrastructure */
1858 spapr_events_init(spapr);
1859
1860 /* Set up the RTC RTAS interfaces */
1861 spapr_rtc_create(spapr);
1862
1863 /* Set up VIO bus */
1864 spapr->vio_bus = spapr_vio_bus_init();
1865
1866 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1867 if (serial_hds[i]) {
1868 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1869 }
1870 }
1871
1872 /* We always have at least the nvram device on VIO */
1873 spapr_create_nvram(spapr);
1874
1875 /* Set up PCI */
1876 spapr_pci_rtas_init();
1877
1878 phb = spapr_create_phb(spapr, 0);
1879
1880 for (i = 0; i < nb_nics; i++) {
1881 NICInfo *nd = &nd_table[i];
1882
1883 if (!nd->model) {
1884 nd->model = g_strdup("ibmveth");
1885 }
1886
1887 if (strcmp(nd->model, "ibmveth") == 0) {
1888 spapr_vlan_create(spapr->vio_bus, nd);
1889 } else {
1890 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1891 }
1892 }
1893
1894 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1895 spapr_vscsi_create(spapr->vio_bus);
1896 }
1897
1898 /* Graphics */
1899 if (spapr_vga_init(phb->bus, &error_fatal)) {
1900 spapr->has_graphics = true;
1901 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1902 }
1903
1904 if (machine->usb) {
1905 if (smc->use_ohci_by_default) {
1906 pci_create_simple(phb->bus, -1, "pci-ohci");
1907 } else {
1908 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1909 }
1910
1911 if (spapr->has_graphics) {
1912 USBBus *usb_bus = usb_bus_find(-1);
1913
1914 usb_create_simple(usb_bus, "usb-kbd");
1915 usb_create_simple(usb_bus, "usb-mouse");
1916 }
1917 }
1918
1919 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1920 error_report(
1921 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1922 MIN_RMA_SLOF);
1923 exit(1);
1924 }
1925
1926 if (kernel_filename) {
1927 uint64_t lowaddr = 0;
1928
1929 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1930 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1931 0, 0);
1932 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1933 kernel_size = load_elf(kernel_filename,
1934 translate_kernel_address, NULL,
1935 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1936 0, 0);
1937 kernel_le = kernel_size > 0;
1938 }
1939 if (kernel_size < 0) {
1940 error_report("error loading %s: %s",
1941 kernel_filename, load_elf_strerror(kernel_size));
1942 exit(1);
1943 }
1944
1945 /* load initrd */
1946 if (initrd_filename) {
1947 /* Try to locate the initrd in the gap between the kernel
1948 * and the firmware. Add a bit of space just in case
1949 */
1950 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1951 initrd_size = load_image_targphys(initrd_filename, initrd_base,
1952 load_limit - initrd_base);
1953 if (initrd_size < 0) {
1954 error_report("could not load initial ram disk '%s'",
1955 initrd_filename);
1956 exit(1);
1957 }
1958 } else {
1959 initrd_base = 0;
1960 initrd_size = 0;
1961 }
1962 }
1963
1964 if (bios_name == NULL) {
1965 bios_name = FW_FILE_NAME;
1966 }
1967 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1968 if (!filename) {
1969 error_report("Could not find LPAR firmware '%s'", bios_name);
1970 exit(1);
1971 }
1972 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
1973 if (fw_size <= 0) {
1974 error_report("Could not load LPAR firmware '%s'", filename);
1975 exit(1);
1976 }
1977 g_free(filename);
1978
1979 /* FIXME: Should register things through the MachineState's qdev
1980 * interface, this is a legacy from the sPAPREnvironment structure
1981 * which predated MachineState but had a similar function */
1982 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
1983 register_savevm_live(NULL, "spapr/htab", -1, 1,
1984 &savevm_htab_handlers, spapr);
1985
1986 /* Prepare the device tree */
1987 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
1988 kernel_size, kernel_le,
1989 kernel_cmdline,
1990 spapr->check_exception_irq);
1991 assert(spapr->fdt_skel != NULL);
1992
1993 /* used by RTAS */
1994 QTAILQ_INIT(&spapr->ccs_list);
1995 qemu_register_reset(spapr_ccs_reset_hook, spapr);
1996
1997 qemu_register_boot_set(spapr_boot_set, spapr);
1998 }
1999
2000 static int spapr_kvm_type(const char *vm_type)
2001 {
2002 if (!vm_type) {
2003 return 0;
2004 }
2005
2006 if (!strcmp(vm_type, "HV")) {
2007 return 1;
2008 }
2009
2010 if (!strcmp(vm_type, "PR")) {
2011 return 2;
2012 }
2013
2014 error_report("Unknown kvm-type specified '%s'", vm_type);
2015 exit(1);
2016 }
2017
2018 /*
2019 * Implementation of an interface to adjust firmware path
2020 * for the bootindex property handling.
2021 */
2022 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2023 DeviceState *dev)
2024 {
2025 #define CAST(type, obj, name) \
2026 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2027 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2028 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2029
2030 if (d) {
2031 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2032 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2033 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2034
2035 if (spapr) {
2036 /*
2037 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2038 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2039 * in the top 16 bits of the 64-bit LUN
2040 */
2041 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2042 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2043 (uint64_t)id << 48);
2044 } else if (virtio) {
2045 /*
2046 * We use SRP luns of the form 01000000 | (target << 8) | lun
2047 * in the top 32 bits of the 64-bit LUN
2048 * Note: the quote above is from SLOF and it is wrong,
2049 * the actual binding is:
2050 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2051 */
2052 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2053 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2054 (uint64_t)id << 32);
2055 } else if (usb) {
2056 /*
2057 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2058 * in the top 32 bits of the 64-bit LUN
2059 */
2060 unsigned usb_port = atoi(usb->port->path);
2061 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2062 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2063 (uint64_t)id << 32);
2064 }
2065 }
2066
2067 if (phb) {
2068 /* Replace "pci" with "pci@800000020000000" */
2069 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2070 }
2071
2072 return NULL;
2073 }
2074
2075 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2076 {
2077 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2078
2079 return g_strdup(spapr->kvm_type);
2080 }
2081
2082 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2083 {
2084 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2085
2086 g_free(spapr->kvm_type);
2087 spapr->kvm_type = g_strdup(value);
2088 }
2089
2090 static void spapr_machine_initfn(Object *obj)
2091 {
2092 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2093
2094 spapr->htab_fd = -1;
2095 object_property_add_str(obj, "kvm-type",
2096 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2097 object_property_set_description(obj, "kvm-type",
2098 "Specifies the KVM virtualization mode (HV, PR)",
2099 NULL);
2100 }
2101
2102 static void spapr_machine_finalizefn(Object *obj)
2103 {
2104 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2105
2106 g_free(spapr->kvm_type);
2107 }
2108
2109 static void ppc_cpu_do_nmi_on_cpu(void *arg)
2110 {
2111 CPUState *cs = arg;
2112
2113 cpu_synchronize_state(cs);
2114 ppc_cpu_do_system_reset(cs);
2115 }
2116
2117 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2118 {
2119 CPUState *cs;
2120
2121 CPU_FOREACH(cs) {
2122 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2123 }
2124 }
2125
2126 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2127 uint32_t node, Error **errp)
2128 {
2129 sPAPRDRConnector *drc;
2130 sPAPRDRConnectorClass *drck;
2131 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2132 int i, fdt_offset, fdt_size;
2133 void *fdt;
2134
2135 /*
2136 * Check for DRC connectors and send hotplug notification to the
2137 * guest only in case of hotplugged memory. This allows cold plugged
2138 * memory to be specified at boot time.
2139 */
2140 if (!dev->hotplugged) {
2141 return;
2142 }
2143
2144 for (i = 0; i < nr_lmbs; i++) {
2145 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2146 addr/SPAPR_MEMORY_BLOCK_SIZE);
2147 g_assert(drc);
2148
2149 fdt = create_device_tree(&fdt_size);
2150 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2151 SPAPR_MEMORY_BLOCK_SIZE);
2152
2153 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2154 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2155 addr += SPAPR_MEMORY_BLOCK_SIZE;
2156 }
2157 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2158 }
2159
2160 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2161 uint32_t node, Error **errp)
2162 {
2163 Error *local_err = NULL;
2164 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2165 PCDIMMDevice *dimm = PC_DIMM(dev);
2166 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2167 MemoryRegion *mr = ddc->get_memory_region(dimm);
2168 uint64_t align = memory_region_get_alignment(mr);
2169 uint64_t size = memory_region_size(mr);
2170 uint64_t addr;
2171
2172 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2173 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2174 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2175 goto out;
2176 }
2177
2178 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2179 if (local_err) {
2180 goto out;
2181 }
2182
2183 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2184 if (local_err) {
2185 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2186 goto out;
2187 }
2188
2189 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2190
2191 out:
2192 error_propagate(errp, local_err);
2193 }
2194
2195 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2196 DeviceState *dev, Error **errp)
2197 {
2198 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2199
2200 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2201 int node;
2202
2203 if (!smc->dr_lmb_enabled) {
2204 error_setg(errp, "Memory hotplug not supported for this machine");
2205 return;
2206 }
2207 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2208 if (*errp) {
2209 return;
2210 }
2211 if (node < 0 || node >= MAX_NODES) {
2212 error_setg(errp, "Invaild node %d", node);
2213 return;
2214 }
2215
2216 /*
2217 * Currently PowerPC kernel doesn't allow hot-adding memory to
2218 * memory-less node, but instead will silently add the memory
2219 * to the first node that has some memory. This causes two
2220 * unexpected behaviours for the user.
2221 *
2222 * - Memory gets hotplugged to a different node than what the user
2223 * specified.
2224 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2225 * to memory-less node, a reboot will set things accordingly
2226 * and the previously hotplugged memory now ends in the right node.
2227 * This appears as if some memory moved from one node to another.
2228 *
2229 * So until kernel starts supporting memory hotplug to memory-less
2230 * nodes, just prevent such attempts upfront in QEMU.
2231 */
2232 if (nb_numa_nodes && !numa_info[node].node_mem) {
2233 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2234 node);
2235 return;
2236 }
2237
2238 spapr_memory_plug(hotplug_dev, dev, node, errp);
2239 }
2240 }
2241
2242 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2243 DeviceState *dev, Error **errp)
2244 {
2245 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2246 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2247 }
2248 }
2249
2250 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2251 DeviceState *dev)
2252 {
2253 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2254 return HOTPLUG_HANDLER(machine);
2255 }
2256 return NULL;
2257 }
2258
2259 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2260 {
2261 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2262 * socket means much for the paravirtualized PAPR platform) */
2263 return cpu_index / smp_threads / smp_cores;
2264 }
2265
2266 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2267 {
2268 MachineClass *mc = MACHINE_CLASS(oc);
2269 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2270 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2271 NMIClass *nc = NMI_CLASS(oc);
2272 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2273
2274 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2275
2276 /*
2277 * We set up the default / latest behaviour here. The class_init
2278 * functions for the specific versioned machine types can override
2279 * these details for backwards compatibility
2280 */
2281 mc->init = ppc_spapr_init;
2282 mc->reset = ppc_spapr_reset;
2283 mc->block_default_type = IF_SCSI;
2284 mc->max_cpus = MAX_CPUMASK_BITS;
2285 mc->no_parallel = 1;
2286 mc->default_boot_order = "";
2287 mc->default_ram_size = 512 * M_BYTE;
2288 mc->kvm_type = spapr_kvm_type;
2289 mc->has_dynamic_sysbus = true;
2290 mc->pci_allow_0_address = true;
2291 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2292 hc->plug = spapr_machine_device_plug;
2293 hc->unplug = spapr_machine_device_unplug;
2294 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2295
2296 smc->dr_lmb_enabled = true;
2297 fwc->get_dev_path = spapr_get_fw_dev_path;
2298 nc->nmi_monitor_handler = spapr_nmi;
2299 }
2300
2301 static const TypeInfo spapr_machine_info = {
2302 .name = TYPE_SPAPR_MACHINE,
2303 .parent = TYPE_MACHINE,
2304 .abstract = true,
2305 .instance_size = sizeof(sPAPRMachineState),
2306 .instance_init = spapr_machine_initfn,
2307 .instance_finalize = spapr_machine_finalizefn,
2308 .class_size = sizeof(sPAPRMachineClass),
2309 .class_init = spapr_machine_class_init,
2310 .interfaces = (InterfaceInfo[]) {
2311 { TYPE_FW_PATH_PROVIDER },
2312 { TYPE_NMI },
2313 { TYPE_HOTPLUG_HANDLER },
2314 { }
2315 },
2316 };
2317
2318 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2319 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2320 void *data) \
2321 { \
2322 MachineClass *mc = MACHINE_CLASS(oc); \
2323 spapr_machine_##suffix##_class_options(mc); \
2324 if (latest) { \
2325 mc->alias = "pseries"; \
2326 mc->is_default = 1; \
2327 } \
2328 } \
2329 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2330 { \
2331 MachineState *machine = MACHINE(obj); \
2332 spapr_machine_##suffix##_instance_options(machine); \
2333 } \
2334 static const TypeInfo spapr_machine_##suffix##_info = { \
2335 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2336 .parent = TYPE_SPAPR_MACHINE, \
2337 .class_init = spapr_machine_##suffix##_class_init, \
2338 .instance_init = spapr_machine_##suffix##_instance_init, \
2339 }; \
2340 static void spapr_machine_register_##suffix(void) \
2341 { \
2342 type_register(&spapr_machine_##suffix##_info); \
2343 } \
2344 type_init(spapr_machine_register_##suffix)
2345
2346 /*
2347 * pseries-2.6
2348 */
2349 static void spapr_machine_2_6_instance_options(MachineState *machine)
2350 {
2351 }
2352
2353 static void spapr_machine_2_6_class_options(MachineClass *mc)
2354 {
2355 /* Defaults for the latest behaviour inherited from the base class */
2356 }
2357
2358 DEFINE_SPAPR_MACHINE(2_6, "2.6", true);
2359
2360 /*
2361 * pseries-2.5
2362 */
2363 #define SPAPR_COMPAT_2_5 \
2364 HW_COMPAT_2_5 \
2365 { \
2366 .driver = "spapr-vlan", \
2367 .property = "use-rx-buffer-pools", \
2368 .value = "off", \
2369 },
2370
2371 static void spapr_machine_2_5_instance_options(MachineState *machine)
2372 {
2373 }
2374
2375 static void spapr_machine_2_5_class_options(MachineClass *mc)
2376 {
2377 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2378
2379 spapr_machine_2_6_class_options(mc);
2380 smc->use_ohci_by_default = true;
2381 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2382 }
2383
2384 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2385
2386 /*
2387 * pseries-2.4
2388 */
2389 #define SPAPR_COMPAT_2_4 \
2390 SPAPR_COMPAT_2_5 \
2391 HW_COMPAT_2_4
2392
2393 static void spapr_machine_2_4_instance_options(MachineState *machine)
2394 {
2395 spapr_machine_2_5_instance_options(machine);
2396 }
2397
2398 static void spapr_machine_2_4_class_options(MachineClass *mc)
2399 {
2400 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2401
2402 spapr_machine_2_5_class_options(mc);
2403 smc->dr_lmb_enabled = false;
2404 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2405 }
2406
2407 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2408
2409 /*
2410 * pseries-2.3
2411 */
2412 #define SPAPR_COMPAT_2_3 \
2413 SPAPR_COMPAT_2_4 \
2414 HW_COMPAT_2_3 \
2415 {\
2416 .driver = "spapr-pci-host-bridge",\
2417 .property = "dynamic-reconfiguration",\
2418 .value = "off",\
2419 },
2420
2421 static void spapr_machine_2_3_instance_options(MachineState *machine)
2422 {
2423 spapr_machine_2_4_instance_options(machine);
2424 savevm_skip_section_footers();
2425 global_state_set_optional();
2426 savevm_skip_configuration();
2427 }
2428
2429 static void spapr_machine_2_3_class_options(MachineClass *mc)
2430 {
2431 spapr_machine_2_4_class_options(mc);
2432 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2433 }
2434 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2435
2436 /*
2437 * pseries-2.2
2438 */
2439
2440 #define SPAPR_COMPAT_2_2 \
2441 SPAPR_COMPAT_2_3 \
2442 HW_COMPAT_2_2 \
2443 {\
2444 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2445 .property = "mem_win_size",\
2446 .value = "0x20000000",\
2447 },
2448
2449 static void spapr_machine_2_2_instance_options(MachineState *machine)
2450 {
2451 spapr_machine_2_3_instance_options(machine);
2452 machine->suppress_vmdesc = true;
2453 }
2454
2455 static void spapr_machine_2_2_class_options(MachineClass *mc)
2456 {
2457 spapr_machine_2_3_class_options(mc);
2458 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2459 }
2460 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2461
2462 /*
2463 * pseries-2.1
2464 */
2465 #define SPAPR_COMPAT_2_1 \
2466 SPAPR_COMPAT_2_2 \
2467 HW_COMPAT_2_1
2468
2469 static void spapr_machine_2_1_instance_options(MachineState *machine)
2470 {
2471 spapr_machine_2_2_instance_options(machine);
2472 }
2473
2474 static void spapr_machine_2_1_class_options(MachineClass *mc)
2475 {
2476 spapr_machine_2_2_class_options(mc);
2477 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2478 }
2479 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2480
2481 static void spapr_machine_register_types(void)
2482 {
2483 type_register_static(&spapr_machine_info);
2484 }
2485
2486 type_init(spapr_machine_register_types)
AR7 emulation for QEMU