hw/arm/ast2400.c

   1 /*
   2  * AST2400 SoC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/arm/ast2400.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21
  22 #define AST2400_UART_5_BASE      0x00184000
  23 #define AST2400_IOMEM_SIZE       0x00200000
  24 #define AST2400_IOMEM_BASE       0x1E600000
  25 #define AST2400_VIC_BASE         0x1E6C0000
  26 #define AST2400_TIMER_BASE       0x1E782000
  27
  28 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
  29 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
  30
  31 /*
  32  * IO handlers: simply catch any reads/writes to IO addresses that aren't
  33  * handled by a device mapping.
  34  */
  35
  36 static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size)
  37 {
  38     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
  39                   __func__, offset, size);
  40     return 0;
  41 }
  42
  43 static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value,
  44                 unsigned size)
  45 {
  46     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
  47                   __func__, offset, value, size);
  48 }
  49
  50 static const MemoryRegionOps ast2400_io_ops = {
  51     .read = ast2400_io_read,
  52     .write = ast2400_io_write,
  53     .endianness = DEVICE_LITTLE_ENDIAN,
  54 };
  55
  56 static void ast2400_init(Object *obj)
  57 {
  58     AST2400State *s = AST2400(obj);
  59
  60     s->cpu = cpu_arm_init("arm926");
  61
  62     object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
  63     object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
  64     qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
  65
  66     object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
  67     object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
  68     qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
  69 }
  70
  71 static void ast2400_realize(DeviceState *dev, Error **errp)
  72 {
  73     int i;
  74     AST2400State *s = AST2400(dev);
  75     Error *err = NULL;
  76
  77     /* IO space */
  78     memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,
  79             "ast2400.io", AST2400_IOMEM_SIZE);
  80     memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE,
  81             &s->iomem, -1);
  82
  83     /* VIC */
  84     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
  85     if (err) {
  86         error_propagate(errp, err);
  87         return;
  88     }
  89     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE);
  90     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
  91                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
  92     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
  93                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
  94
  95     /* Timer */
  96     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
  97     if (err) {
  98         error_propagate(errp, err);
  99         return;
 100     }
 101     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE);
 102     for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
 103         qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
 104         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 105     }
 106
 107     /* UART - attach an 8250 to the IO space as our UART5 */
 108     if (serial_hds[0]) {
 109         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
 110         serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,
 111                        uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
 112     }
 113 }
 114
 115 static void ast2400_class_init(ObjectClass *oc, void *data)
 116 {
 117     DeviceClass *dc = DEVICE_CLASS(oc);
 118
 119     dc->realize = ast2400_realize;
 120
 121     /*
 122      * Reason: creates an ARM CPU, thus use after free(), see
 123      * arm_cpu_class_init()
 124      */
 125     dc->cannot_destroy_with_object_finalize_yet = true;
 126 }
 127
 128 static const TypeInfo ast2400_type_info = {
 129     .name = TYPE_AST2400,
 130     .parent = TYPE_SYS_BUS_DEVICE,
 131     .instance_size = sizeof(AST2400State),
 132     .instance_init = ast2400_init,
 133     .class_init = ast2400_class_init,
 134 };
 135
 136 static void ast2400_register_types(void)
 137 {
 138     type_register_static(&ast2400_type_info);
 139 }
 140
 141 type_init(ast2400_register_types)