target-arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 /* internal defines */
   5 typedef struct DisasContext {
   6     target_ulong pc;
   7     uint32_t insn;
   8     int is_jmp;
   9     /* Nonzero if this instruction has been conditionally skipped.  */
  10     int condjmp;
  11     /* The label that will be jumped to when the instruction is skipped.  */
  12     int condlabel;
  13     /* Thumb-2 conditional execution bits.  */
  14     int condexec_mask;
  15     int condexec_cond;
  16     struct TranslationBlock *tb;
  17     int singlestep_enabled;
  18     int thumb;
  19     int bswap_code;
  20 #if !defined(CONFIG_USER_ONLY)
  21     int user;
  22 #endif
  23     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  24     bool ns;        /* Use non-secure CPREG bank on access */
  25     bool cpacr_fpen; /* FP enabled via CPACR.FPEN */
  26     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  27     int vec_len;
  28     int vec_stride;
  29     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  30      * so that top level loop can generate correct syndrome information.
  31      */
  32     uint32_t svc_imm;
  33     int aarch64;
  34     int current_el;
  35     GHashTable *cp_regs;
  36     uint64_t features; /* CPU features bits */
  37     /* Because unallocated encodings generate different exception syndrome
  38      * information from traps due to FP being disabled, we can't do a single
  39      * "is fp access disabled" check at a high level in the decode tree.
  40      * To help in catching bugs where the access check was forgotten in some
  41      * code path, we set this flag when the access check is done, and assert
  42      * that it is set at the point where we actually touch the FP regs.
  43      */
  44     bool fp_access_checked;
  45     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  46      * single-step support).
  47      */
  48     bool ss_active;
  49     bool pstate_ss;
  50     /* True if the insn just emitted was a load-exclusive instruction
  51      * (necessary for syndrome information for single step exceptions),
  52      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  53      */
  54     bool is_ldex;
  55     /* True if a single-step exception will be taken to the current EL */
  56     bool ss_same_el;
  57     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  58     int c15_cpar;
  59 #define TMP_A64_MAX 16
  60     int tmp_a64_count;
  61     TCGv_i64 tmp_a64[TMP_A64_MAX];
  62 } DisasContext;
  63
  64 extern TCGv_ptr cpu_env;
  65
  66 static inline int arm_dc_feature(DisasContext *dc, int feature)
  67 {
  68     return (dc->features & (1ULL << feature)) != 0;
  69 }
  70
  71 static inline int get_mem_index(DisasContext *s)
  72 {
  73     return s->mmu_idx;
  74 }
  75
  76 /* target-specific extra values for is_jmp */
  77 /* These instructions trap after executing, so the A32/T32 decoder must
  78  * defer them until after the conditional execution state has been updated.
  79  * WFI also needs special handling when single-stepping.
  80  */
  81 #define DISAS_WFI 4
  82 #define DISAS_SWI 5
  83 /* For instructions which unconditionally cause an exception we can skip
  84  * emitting unreachable code at the end of the TB in the A64 decoder
  85  */
  86 #define DISAS_EXC 6
  87 /* WFE */
  88 #define DISAS_WFE 7
  89 #define DISAS_HVC 8
  90 #define DISAS_SMC 9
  91
  92 #ifdef TARGET_AARCH64
  93 void a64_translate_init(void);
  94 void gen_intermediate_code_internal_a64(ARMCPU *cpu,
  95                                         TranslationBlock *tb,
  96                                         bool search_pc);
  97 void gen_a64_set_pc_im(uint64_t val);
  98 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
  99                             fprintf_function cpu_fprintf, int flags);
 100 #else
 101 static inline void a64_translate_init(void)
 102 {
 103 }
 104
 105 static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
 106                                                       TranslationBlock *tb,
 107                                                       bool search_pc)
 108 {
 109 }
 110
 111 static inline void gen_a64_set_pc_im(uint64_t val)
 112 {
 113 }
 114
 115 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 116                                           fprintf_function cpu_fprintf,
 117                                           int flags)
 118 {
 119 }
 120 #endif
 121
 122 void arm_gen_test_cc(int cc, int label);
 123
 124 #endif /* TARGET_ARM_TRANSLATE_H */