target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13
  14 #ifndef CONFIG_USER_ONLY
  15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
  16                                 int access_type, ARMMMUIdx mmu_idx,
  17                                 hwaddr *phys_ptr, int *prot,
  18                                 target_ulong *page_size);
  19
  20 /* Definitions for the PMCCNTR and PMCR registers */
  21 #define PMCRD   0x8
  22 #define PMCRC   0x4
  23 #define PMCRE   0x1
  24 #endif
  25
  26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  27 {
  28     int nregs;
  29
  30     /* VFP data registers are always little-endian.  */
  31     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  32     if (reg < nregs) {
  33         stfq_le_p(buf, env->vfp.regs[reg]);
  34         return 8;
  35     }
  36     if (arm_feature(env, ARM_FEATURE_NEON)) {
  37         /* Aliases for Q regs.  */
  38         nregs += 16;
  39         if (reg < nregs) {
  40             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  41             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  42             return 16;
  43         }
  44     }
  45     switch (reg - nregs) {
  46     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  47     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  48     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  49     }
  50     return 0;
  51 }
  52
  53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  54 {
  55     int nregs;
  56
  57     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  58     if (reg < nregs) {
  59         env->vfp.regs[reg] = ldfq_le_p(buf);
  60         return 8;
  61     }
  62     if (arm_feature(env, ARM_FEATURE_NEON)) {
  63         nregs += 16;
  64         if (reg < nregs) {
  65             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  66             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  67             return 16;
  68         }
  69     }
  70     switch (reg - nregs) {
  71     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  72     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  73     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  74     }
  75     return 0;
  76 }
  77
  78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  79 {
  80     switch (reg) {
  81     case 0 ... 31:
  82         /* 128 bit FP register */
  83         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  84         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  85         return 16;
  86     case 32:
  87         /* FPSR */
  88         stl_p(buf, vfp_get_fpsr(env));
  89         return 4;
  90     case 33:
  91         /* FPCR */
  92         stl_p(buf, vfp_get_fpcr(env));
  93         return 4;
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 100 {
 101     switch (reg) {
 102     case 0 ... 31:
 103         /* 128 bit FP register */
 104         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 105         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 106         return 16;
 107     case 32:
 108         /* FPSR */
 109         vfp_set_fpsr(env, ldl_p(buf));
 110         return 4;
 111     case 33:
 112         /* FPCR */
 113         vfp_set_fpcr(env, ldl_p(buf));
 114         return 4;
 115     default:
 116         return 0;
 117     }
 118 }
 119
 120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 121 {
 122     assert(ri->fieldoffset);
 123     if (cpreg_field_is_64bit(ri)) {
 124         return CPREG_FIELD64(env, ri);
 125     } else {
 126         return CPREG_FIELD32(env, ri);
 127     }
 128 }
 129
 130 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 131                       uint64_t value)
 132 {
 133     assert(ri->fieldoffset);
 134     if (cpreg_field_is_64bit(ri)) {
 135         CPREG_FIELD64(env, ri) = value;
 136     } else {
 137         CPREG_FIELD32(env, ri) = value;
 138     }
 139 }
 140
 141 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 142 {
 143     return (char *)env + ri->fieldoffset;
 144 }
 145
 146 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 147 {
 148     /* Raw read of a coprocessor register (as needed for migration, etc). */
 149     if (ri->type & ARM_CP_CONST) {
 150         return ri->resetvalue;
 151     } else if (ri->raw_readfn) {
 152         return ri->raw_readfn(env, ri);
 153     } else if (ri->readfn) {
 154         return ri->readfn(env, ri);
 155     } else {
 156         return raw_read(env, ri);
 157     }
 158 }
 159
 160 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 161                              uint64_t v)
 162 {
 163     /* Raw write of a coprocessor register (as needed for migration, etc).
 164      * Note that constant registers are treated as write-ignored; the
 165      * caller should check for success by whether a readback gives the
 166      * value written.
 167      */
 168     if (ri->type & ARM_CP_CONST) {
 169         return;
 170     } else if (ri->raw_writefn) {
 171         ri->raw_writefn(env, ri, v);
 172     } else if (ri->writefn) {
 173         ri->writefn(env, ri, v);
 174     } else {
 175         raw_write(env, ri, v);
 176     }
 177 }
 178
 179 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 180 {
 181    /* Return true if the regdef would cause an assertion if you called
 182     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 183     * program bug for it not to have the NO_RAW flag).
 184     * NB that returning false here doesn't necessarily mean that calling
 185     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 186     * read/write access functions which are safe for raw use" from "has
 187     * read/write access functions which have side effects but has forgotten
 188     * to provide raw access functions".
 189     * The tests here line up with the conditions in read/write_raw_cp_reg()
 190     * and assertions in raw_read()/raw_write().
 191     */
 192     if ((ri->type & ARM_CP_CONST) ||
 193         ri->fieldoffset ||
 194         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 195         return false;
 196     }
 197     return true;
 198 }
 199
 200 bool write_cpustate_to_list(ARMCPU *cpu)
 201 {
 202     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 203     int i;
 204     bool ok = true;
 205
 206     for (i = 0; i < cpu->cpreg_array_len; i++) {
 207         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 208         const ARMCPRegInfo *ri;
 209
 210         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 211         if (!ri) {
 212             ok = false;
 213             continue;
 214         }
 215         if (ri->type & ARM_CP_NO_RAW) {
 216             continue;
 217         }
 218         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 219     }
 220     return ok;
 221 }
 222
 223 bool write_list_to_cpustate(ARMCPU *cpu)
 224 {
 225     int i;
 226     bool ok = true;
 227
 228     for (i = 0; i < cpu->cpreg_array_len; i++) {
 229         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 230         uint64_t v = cpu->cpreg_values[i];
 231         const ARMCPRegInfo *ri;
 232
 233         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 234         if (!ri) {
 235             ok = false;
 236             continue;
 237         }
 238         if (ri->type & ARM_CP_NO_RAW) {
 239             continue;
 240         }
 241         /* Write value and confirm it reads back as written
 242          * (to catch read-only registers and partially read-only
 243          * registers where the incoming migration value doesn't match)
 244          */
 245         write_raw_cp_reg(&cpu->env, ri, v);
 246         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 247             ok = false;
 248         }
 249     }
 250     return ok;
 251 }
 252
 253 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 254 {
 255     ARMCPU *cpu = opaque;
 256     uint64_t regidx;
 257     const ARMCPRegInfo *ri;
 258
 259     regidx = *(uint32_t *)key;
 260     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 261
 262     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 263         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 264         /* The value array need not be initialized at this point */
 265         cpu->cpreg_array_len++;
 266     }
 267 }
 268
 269 static void count_cpreg(gpointer key, gpointer opaque)
 270 {
 271     ARMCPU *cpu = opaque;
 272     uint64_t regidx;
 273     const ARMCPRegInfo *ri;
 274
 275     regidx = *(uint32_t *)key;
 276     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 277
 278     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 279         cpu->cpreg_array_len++;
 280     }
 281 }
 282
 283 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 284 {
 285     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 286     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 287
 288     if (aidx > bidx) {
 289         return 1;
 290     }
 291     if (aidx < bidx) {
 292         return -1;
 293     }
 294     return 0;
 295 }
 296
 297 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 298 {
 299     GList **plist = udata;
 300
 301     *plist = g_list_prepend(*plist, key);
 302 }
 303
 304 void init_cpreg_list(ARMCPU *cpu)
 305 {
 306     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 307      * Note that we require cpreg_tuples[] to be sorted by key ID.
 308      */
 309     GList *keys = NULL;
 310     int arraylen;
 311
 312     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 313
 314     keys = g_list_sort(keys, cpreg_key_compare);
 315
 316     cpu->cpreg_array_len = 0;
 317
 318     g_list_foreach(keys, count_cpreg, cpu);
 319
 320     arraylen = cpu->cpreg_array_len;
 321     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 322     cpu->cpreg_values = g_new(uint64_t, arraylen);
 323     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 324     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 325     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 326     cpu->cpreg_array_len = 0;
 327
 328     g_list_foreach(keys, add_cpreg_to_list, cpu);
 329
 330     assert(cpu->cpreg_array_len == arraylen);
 331
 332     g_list_free(keys);
 333 }
 334
 335 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 336 {
 337     ARMCPU *cpu = arm_env_get_cpu(env);
 338
 339     raw_write(env, ri, value);
 340     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 341 }
 342
 343 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 344 {
 345     ARMCPU *cpu = arm_env_get_cpu(env);
 346
 347     if (raw_read(env, ri) != value) {
 348         /* Unlike real hardware the qemu TLB uses virtual addresses,
 349          * not modified virtual addresses, so this causes a TLB flush.
 350          */
 351         tlb_flush(CPU(cpu), 1);
 352         raw_write(env, ri, value);
 353     }
 354 }
 355
 356 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 357                              uint64_t value)
 358 {
 359     ARMCPU *cpu = arm_env_get_cpu(env);
 360
 361     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 362         && !extended_addresses_enabled(env)) {
 363         /* For VMSA (when not using the LPAE long descriptor page table
 364          * format) this register includes the ASID, so do a TLB flush.
 365          * For PMSA it is purely a process ID and no action is needed.
 366          */
 367         tlb_flush(CPU(cpu), 1);
 368     }
 369     raw_write(env, ri, value);
 370 }
 371
 372 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 373                           uint64_t value)
 374 {
 375     /* Invalidate all (TLBIALL) */
 376     ARMCPU *cpu = arm_env_get_cpu(env);
 377
 378     tlb_flush(CPU(cpu), 1);
 379 }
 380
 381 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 382                           uint64_t value)
 383 {
 384     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 385     ARMCPU *cpu = arm_env_get_cpu(env);
 386
 387     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 388 }
 389
 390 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 391                            uint64_t value)
 392 {
 393     /* Invalidate by ASID (TLBIASID) */
 394     ARMCPU *cpu = arm_env_get_cpu(env);
 395
 396     tlb_flush(CPU(cpu), value == 0);
 397 }
 398
 399 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 400                            uint64_t value)
 401 {
 402     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 403     ARMCPU *cpu = arm_env_get_cpu(env);
 404
 405     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 406 }
 407
 408 /* IS variants of TLB operations must affect all cores */
 409 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 410                              uint64_t value)
 411 {
 412     CPUState *other_cs;
 413
 414     CPU_FOREACH(other_cs) {
 415         tlb_flush(other_cs, 1);
 416     }
 417 }
 418
 419 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 420                              uint64_t value)
 421 {
 422     CPUState *other_cs;
 423
 424     CPU_FOREACH(other_cs) {
 425         tlb_flush(other_cs, value == 0);
 426     }
 427 }
 428
 429 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 430                              uint64_t value)
 431 {
 432     CPUState *other_cs;
 433
 434     CPU_FOREACH(other_cs) {
 435         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 436     }
 437 }
 438
 439 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 440                              uint64_t value)
 441 {
 442     CPUState *other_cs;
 443
 444     CPU_FOREACH(other_cs) {
 445         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 446     }
 447 }
 448
 449 static const ARMCPRegInfo cp_reginfo[] = {
 450     /* Define the secure and non-secure FCSE identifier CP registers
 451      * separately because there is no secure bank in V8 (no _EL3).  This allows
 452      * the secure register to be properly reset and migrated. There is also no
 453      * v8 EL1 version of the register so the non-secure instance stands alone.
 454      */
 455     { .name = "FCSEIDR(NS)",
 456       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 457       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 458       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 459       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 460     { .name = "FCSEIDR(S)",
 461       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 462       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 463       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 464       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 465     /* Define the secure and non-secure context identifier CP registers
 466      * separately because there is no secure bank in V8 (no _EL3).  This allows
 467      * the secure register to be properly reset and migrated.  In the
 468      * non-secure case, the 32-bit register will have reset and migration
 469      * disabled during registration as it is handled by the 64-bit instance.
 470      */
 471     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 472       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 473       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 474       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 475       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 476     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 477       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 478       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 479       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 480       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 481     REGINFO_SENTINEL
 482 };
 483
 484 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 485     /* NB: Some of these registers exist in v8 but with more precise
 486      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 487      */
 488     /* MMU Domain access control / MPU write buffer control */
 489     { .name = "DACR",
 490       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 491       .access = PL1_RW, .resetvalue = 0,
 492       .writefn = dacr_write, .raw_writefn = raw_write,
 493       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 494                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 495     /* ??? This covers not just the impdef TLB lockdown registers but also
 496      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 497      */
 498     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 499       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 500     /* Cache maintenance ops; some of this space may be overridden later. */
 501     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 502       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 503       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 504     REGINFO_SENTINEL
 505 };
 506
 507 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 508     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 509      * over-broad.
 510      */
 511     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 512       .access = PL1_W, .type = ARM_CP_WFI },
 513     REGINFO_SENTINEL
 514 };
 515
 516 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 517     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 518      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 519      */
 520     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 521       .access = PL1_W, .type = ARM_CP_WFI },
 522     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 523      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 524      * OMAPCP will override this space.
 525      */
 526     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 527       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 528       .resetvalue = 0 },
 529     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 530       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 531       .resetvalue = 0 },
 532     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 533     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 534       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 535       .resetvalue = 0 },
 536     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 537      * implementing it as RAZ means the "debug architecture version" bits
 538      * will read as a reserved value, which should cause Linux to not try
 539      * to use the debug hardware.
 540      */
 541     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 542       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 543     /* MMU TLB control. Note that the wildcarding means we cover not just
 544      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 545      */
 546     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 547       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 548       .type = ARM_CP_NO_RAW },
 549     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 550       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 551       .type = ARM_CP_NO_RAW },
 552     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 553       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 554       .type = ARM_CP_NO_RAW },
 555     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 556       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 557       .type = ARM_CP_NO_RAW },
 558     REGINFO_SENTINEL
 559 };
 560
 561 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 562                         uint64_t value)
 563 {
 564     uint32_t mask = 0;
 565
 566     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 567     if (!arm_feature(env, ARM_FEATURE_V8)) {
 568         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 569          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 570          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 571          */
 572         if (arm_feature(env, ARM_FEATURE_VFP)) {
 573             /* VFP coprocessor: cp10 & cp11 [23:20] */
 574             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 575
 576             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 577                 /* ASEDIS [31] bit is RAO/WI */
 578                 value |= (1 << 31);
 579             }
 580
 581             /* VFPv3 and upwards with NEON implement 32 double precision
 582              * registers (D0-D31).
 583              */
 584             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 585                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 586                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 587                 value |= (1 << 30);
 588             }
 589         }
 590         value &= mask;
 591     }
 592     env->cp15.c1_coproc = value;
 593 }
 594
 595 static const ARMCPRegInfo v6_cp_reginfo[] = {
 596     /* prefetch by MVA in v6, NOP in v7 */
 597     { .name = "MVA_prefetch",
 598       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 599       .access = PL1_W, .type = ARM_CP_NOP },
 600     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 601       .access = PL0_W, .type = ARM_CP_NOP },
 602     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 603       .access = PL0_W, .type = ARM_CP_NOP },
 604     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 605       .access = PL0_W, .type = ARM_CP_NOP },
 606     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 607       .access = PL1_RW,
 608       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 609                              offsetof(CPUARMState, cp15.ifar_ns) },
 610       .resetvalue = 0, },
 611     /* Watchpoint Fault Address Register : should actually only be present
 612      * for 1136, 1176, 11MPCore.
 613      */
 614     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 615       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 616     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 617       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 618       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 619       .resetvalue = 0, .writefn = cpacr_write },
 620     REGINFO_SENTINEL
 621 };
 622
 623 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 624 {
 625     /* Performance monitor registers user accessibility is controlled
 626      * by PMUSERENR.
 627      */
 628     if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
 629         return CP_ACCESS_TRAP;
 630     }
 631     return CP_ACCESS_OK;
 632 }
 633
 634 #ifndef CONFIG_USER_ONLY
 635
 636 static inline bool arm_ccnt_enabled(CPUARMState *env)
 637 {
 638     /* This does not support checking PMCCFILTR_EL0 register */
 639
 640     if (!(env->cp15.c9_pmcr & PMCRE)) {
 641         return false;
 642     }
 643
 644     return true;
 645 }
 646
 647 void pmccntr_sync(CPUARMState *env)
 648 {
 649     uint64_t temp_ticks;
 650
 651     temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 652                           get_ticks_per_sec(), 1000000);
 653
 654     if (env->cp15.c9_pmcr & PMCRD) {
 655         /* Increment once every 64 processor clock cycles */
 656         temp_ticks /= 64;
 657     }
 658
 659     if (arm_ccnt_enabled(env)) {
 660         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 661     }
 662 }
 663
 664 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 665                        uint64_t value)
 666 {
 667     pmccntr_sync(env);
 668
 669     if (value & PMCRC) {
 670         /* The counter has been reset */
 671         env->cp15.c15_ccnt = 0;
 672     }
 673
 674     /* only the DP, X, D and E bits are writable */
 675     env->cp15.c9_pmcr &= ~0x39;
 676     env->cp15.c9_pmcr |= (value & 0x39);
 677
 678     pmccntr_sync(env);
 679 }
 680
 681 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 682 {
 683     uint64_t total_ticks;
 684
 685     if (!arm_ccnt_enabled(env)) {
 686         /* Counter is disabled, do not change value */
 687         return env->cp15.c15_ccnt;
 688     }
 689
 690     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 691                            get_ticks_per_sec(), 1000000);
 692
 693     if (env->cp15.c9_pmcr & PMCRD) {
 694         /* Increment once every 64 processor clock cycles */
 695         total_ticks /= 64;
 696     }
 697     return total_ticks - env->cp15.c15_ccnt;
 698 }
 699
 700 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 701                         uint64_t value)
 702 {
 703     uint64_t total_ticks;
 704
 705     if (!arm_ccnt_enabled(env)) {
 706         /* Counter is disabled, set the absolute value */
 707         env->cp15.c15_ccnt = value;
 708         return;
 709     }
 710
 711     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 712                            get_ticks_per_sec(), 1000000);
 713
 714     if (env->cp15.c9_pmcr & PMCRD) {
 715         /* Increment once every 64 processor clock cycles */
 716         total_ticks /= 64;
 717     }
 718     env->cp15.c15_ccnt = total_ticks - value;
 719 }
 720
 721 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 722                             uint64_t value)
 723 {
 724     uint64_t cur_val = pmccntr_read(env, NULL);
 725
 726     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 727 }
 728
 729 #else /* CONFIG_USER_ONLY */
 730
 731 void pmccntr_sync(CPUARMState *env)
 732 {
 733 }
 734
 735 #endif
 736
 737 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 738                             uint64_t value)
 739 {
 740     pmccntr_sync(env);
 741     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 742     pmccntr_sync(env);
 743 }
 744
 745 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 746                             uint64_t value)
 747 {
 748     value &= (1 << 31);
 749     env->cp15.c9_pmcnten |= value;
 750 }
 751
 752 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 753                              uint64_t value)
 754 {
 755     value &= (1 << 31);
 756     env->cp15.c9_pmcnten &= ~value;
 757 }
 758
 759 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 760                          uint64_t value)
 761 {
 762     env->cp15.c9_pmovsr &= ~value;
 763 }
 764
 765 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 766                              uint64_t value)
 767 {
 768     env->cp15.c9_pmxevtyper = value & 0xff;
 769 }
 770
 771 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 772                             uint64_t value)
 773 {
 774     env->cp15.c9_pmuserenr = value & 1;
 775 }
 776
 777 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 778                              uint64_t value)
 779 {
 780     /* We have no event counters so only the C bit can be changed */
 781     value &= (1 << 31);
 782     env->cp15.c9_pminten |= value;
 783 }
 784
 785 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 786                              uint64_t value)
 787 {
 788     value &= (1 << 31);
 789     env->cp15.c9_pminten &= ~value;
 790 }
 791
 792 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 793                        uint64_t value)
 794 {
 795     /* Note that even though the AArch64 view of this register has bits
 796      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 797      * architectural requirements for bits which are RES0 only in some
 798      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 799      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 800      */
 801     raw_write(env, ri, value & ~0x1FULL);
 802 }
 803
 804 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 805 {
 806     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 807      * For bits that vary between AArch32/64, code needs to check the
 808      * current execution mode before directly using the feature bit.
 809      */
 810     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 811
 812     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 813         valid_mask &= ~SCR_HCE;
 814
 815         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 816          * supported if EL2 exists. The bit is UNK/SBZP when
 817          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 818          * when EL2 is unavailable.
 819          */
 820         if (arm_feature(env, ARM_FEATURE_V7)) {
 821             valid_mask &= ~SCR_SMD;
 822         }
 823     }
 824
 825     /* Clear all-context RES0 bits.  */
 826     value &= valid_mask;
 827     raw_write(env, ri, value);
 828 }
 829
 830 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 831 {
 832     ARMCPU *cpu = arm_env_get_cpu(env);
 833
 834     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
 835      * bank
 836      */
 837     uint32_t index = A32_BANKED_REG_GET(env, csselr,
 838                                         ri->secure & ARM_CP_SECSTATE_S);
 839
 840     return cpu->ccsidr[index];
 841 }
 842
 843 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 844                          uint64_t value)
 845 {
 846     raw_write(env, ri, value & 0xf);
 847 }
 848
 849 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 850 {
 851     CPUState *cs = ENV_GET_CPU(env);
 852     uint64_t ret = 0;
 853
 854     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 855         ret |= CPSR_I;
 856     }
 857     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 858         ret |= CPSR_F;
 859     }
 860     /* External aborts are not possible in QEMU so A bit is always clear */
 861     return ret;
 862 }
 863
 864 static const ARMCPRegInfo v7_cp_reginfo[] = {
 865     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 866     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 867       .access = PL1_W, .type = ARM_CP_NOP },
 868     /* Performance monitors are implementation defined in v7,
 869      * but with an ARM recommended set of registers, which we
 870      * follow (although we don't actually implement any counters)
 871      *
 872      * Performance registers fall into three categories:
 873      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 874      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 875      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 876      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 877      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 878      */
 879     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 880       .access = PL0_RW, .type = ARM_CP_ALIAS,
 881       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 882       .writefn = pmcntenset_write,
 883       .accessfn = pmreg_access,
 884       .raw_writefn = raw_write },
 885     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 886       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 887       .access = PL0_RW, .accessfn = pmreg_access,
 888       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 889       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 890     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 891       .access = PL0_RW,
 892       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 893       .accessfn = pmreg_access,
 894       .writefn = pmcntenclr_write,
 895       .type = ARM_CP_ALIAS },
 896     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 897       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 898       .access = PL0_RW, .accessfn = pmreg_access,
 899       .type = ARM_CP_ALIAS,
 900       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 901       .writefn = pmcntenclr_write },
 902     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 903       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 904       .accessfn = pmreg_access,
 905       .writefn = pmovsr_write,
 906       .raw_writefn = raw_write },
 907     /* Unimplemented so WI. */
 908     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 909       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 910     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 911      * We choose to RAZ/WI.
 912      */
 913     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 914       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 915       .accessfn = pmreg_access },
 916 #ifndef CONFIG_USER_ONLY
 917     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 918       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 919       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 920       .accessfn = pmreg_access },
 921     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 922       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 923       .access = PL0_RW, .accessfn = pmreg_access,
 924       .type = ARM_CP_IO,
 925       .readfn = pmccntr_read, .writefn = pmccntr_write, },
 926 #endif
 927     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
 928       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
 929       .writefn = pmccfiltr_write,
 930       .access = PL0_RW, .accessfn = pmreg_access,
 931       .type = ARM_CP_IO,
 932       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
 933       .resetvalue = 0, },
 934     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 935       .access = PL0_RW,
 936       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 937       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 938       .raw_writefn = raw_write },
 939     /* Unimplemented, RAZ/WI. */
 940     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 941       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 942       .accessfn = pmreg_access },
 943     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 944       .access = PL0_R | PL1_RW,
 945       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 946       .resetvalue = 0,
 947       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 948     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 949       .access = PL1_RW,
 950       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 951       .resetvalue = 0,
 952       .writefn = pmintenset_write, .raw_writefn = raw_write },
 953     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 954       .access = PL1_RW, .type = ARM_CP_ALIAS,
 955       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 956       .resetvalue = 0, .writefn = pmintenclr_write, },
 957     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 958       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 959       .access = PL1_RW, .writefn = vbar_write,
 960       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
 961                              offsetof(CPUARMState, cp15.vbar_ns) },
 962       .resetvalue = 0 },
 963     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 964       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 965       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
 966     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 967       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 968       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
 969       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
 970                              offsetof(CPUARMState, cp15.csselr_ns) } },
 971     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 972      * just RAZ for all cores:
 973      */
 974     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
 975       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
 976       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 977     /* Auxiliary fault status registers: these also are IMPDEF, and we
 978      * choose to RAZ/WI for all cores.
 979      */
 980     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
 981       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
 982       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 983     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
 984       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
 985       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 986     /* MAIR can just read-as-written because we don't implement caches
 987      * and so don't need to care about memory attributes.
 988      */
 989     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
 990       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
 991       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
 992       .resetvalue = 0 },
 993     /* For non-long-descriptor page tables these are PRRR and NMRR;
 994      * regardless they still act as reads-as-written for QEMU.
 995      * The override is necessary because of the overly-broad TLB_LOCKDOWN
 996      * definition.
 997      */
 998      /* MAIR0/1 are defined separately from their 64-bit counterpart which
 999       * allows them to assign the correct fieldoffset based on the endianness
1000       * handled in the field definitions.
1001       */
1002     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
1003       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1004       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1005                              offsetof(CPUARMState, cp15.mair0_ns) },
1006       .resetfn = arm_cp_reset_ignore },
1007     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
1008       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1009       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1010                              offsetof(CPUARMState, cp15.mair1_ns) },
1011       .resetfn = arm_cp_reset_ignore },
1012     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1013       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1014       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1015     /* 32 bit ITLB invalidates */
1016     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1017       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1018     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1019       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1020     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1021       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1022     /* 32 bit DTLB invalidates */
1023     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1024       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1025     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1026       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1027     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1028       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1029     /* 32 bit TLB invalidates */
1030     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1031       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1032     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1033       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1034     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1035       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1036     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1037       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1038     REGINFO_SENTINEL
1039 };
1040
1041 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1042     /* 32 bit TLB invalidates, Inner Shareable */
1043     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1044       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1045     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1046       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1047     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1048       .type = ARM_CP_NO_RAW, .access = PL1_W,
1049       .writefn = tlbiasid_is_write },
1050     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1051       .type = ARM_CP_NO_RAW, .access = PL1_W,
1052       .writefn = tlbimvaa_is_write },
1053     REGINFO_SENTINEL
1054 };
1055
1056 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1057                         uint64_t value)
1058 {
1059     value &= 1;
1060     env->teecr = value;
1061 }
1062
1063 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1064 {
1065     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1066         return CP_ACCESS_TRAP;
1067     }
1068     return CP_ACCESS_OK;
1069 }
1070
1071 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1072     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1073       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1074       .resetvalue = 0,
1075       .writefn = teecr_write },
1076     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1077       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1078       .accessfn = teehbr_access, .resetvalue = 0 },
1079     REGINFO_SENTINEL
1080 };
1081
1082 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1083     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1084       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1085       .access = PL0_RW,
1086       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1087     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1088       .access = PL0_RW,
1089       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1090                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1091       .resetfn = arm_cp_reset_ignore },
1092     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1093       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1094       .access = PL0_R|PL1_W,
1095       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1096       .resetvalue = 0},
1097     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1098       .access = PL0_R|PL1_W,
1099       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1100                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1101       .resetfn = arm_cp_reset_ignore },
1102     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1103       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1104       .access = PL1_RW,
1105       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1106     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1107       .access = PL1_RW,
1108       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1109                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1110       .resetvalue = 0 },
1111     REGINFO_SENTINEL
1112 };
1113
1114 #ifndef CONFIG_USER_ONLY
1115
1116 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1117 {
1118     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1119     if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1120         return CP_ACCESS_TRAP;
1121     }
1122     return CP_ACCESS_OK;
1123 }
1124
1125 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1126 {
1127     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1128     if (arm_current_el(env) == 0 &&
1129         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1130         return CP_ACCESS_TRAP;
1131     }
1132     return CP_ACCESS_OK;
1133 }
1134
1135 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1136 {
1137     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1138      * EL0[PV]TEN is zero.
1139      */
1140     if (arm_current_el(env) == 0 &&
1141         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1142         return CP_ACCESS_TRAP;
1143     }
1144     return CP_ACCESS_OK;
1145 }
1146
1147 static CPAccessResult gt_pct_access(CPUARMState *env,
1148                                          const ARMCPRegInfo *ri)
1149 {
1150     return gt_counter_access(env, GTIMER_PHYS);
1151 }
1152
1153 static CPAccessResult gt_vct_access(CPUARMState *env,
1154                                          const ARMCPRegInfo *ri)
1155 {
1156     return gt_counter_access(env, GTIMER_VIRT);
1157 }
1158
1159 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1160 {
1161     return gt_timer_access(env, GTIMER_PHYS);
1162 }
1163
1164 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1165 {
1166     return gt_timer_access(env, GTIMER_VIRT);
1167 }
1168
1169 static uint64_t gt_get_countervalue(CPUARMState *env)
1170 {
1171     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1172 }
1173
1174 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1175 {
1176     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1177
1178     if (gt->ctl & 1) {
1179         /* Timer enabled: calculate and set current ISTATUS, irq, and
1180          * reset timer to when ISTATUS next has to change
1181          */
1182         uint64_t count = gt_get_countervalue(&cpu->env);
1183         /* Note that this must be unsigned 64 bit arithmetic: */
1184         int istatus = count >= gt->cval;
1185         uint64_t nexttick;
1186
1187         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1188         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1189                      (istatus && !(gt->ctl & 2)));
1190         if (istatus) {
1191             /* Next transition is when count rolls back over to zero */
1192             nexttick = UINT64_MAX;
1193         } else {
1194             /* Next transition is when we hit cval */
1195             nexttick = gt->cval;
1196         }
1197         /* Note that the desired next expiry time might be beyond the
1198          * signed-64-bit range of a QEMUTimer -- in this case we just
1199          * set the timer for as far in the future as possible. When the
1200          * timer expires we will reset the timer for any remaining period.
1201          */
1202         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1203             nexttick = INT64_MAX / GTIMER_SCALE;
1204         }
1205         timer_mod(cpu->gt_timer[timeridx], nexttick);
1206     } else {
1207         /* Timer disabled: ISTATUS and timer output always clear */
1208         gt->ctl &= ~4;
1209         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1210         timer_del(cpu->gt_timer[timeridx]);
1211     }
1212 }
1213
1214 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1215 {
1216     ARMCPU *cpu = arm_env_get_cpu(env);
1217     int timeridx = ri->opc1 & 1;
1218
1219     timer_del(cpu->gt_timer[timeridx]);
1220 }
1221
1222 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1223 {
1224     return gt_get_countervalue(env);
1225 }
1226
1227 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1228                           uint64_t value)
1229 {
1230     int timeridx = ri->opc1 & 1;
1231
1232     env->cp15.c14_timer[timeridx].cval = value;
1233     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1234 }
1235
1236 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1237 {
1238     int timeridx = ri->crm & 1;
1239
1240     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1241                       gt_get_countervalue(env));
1242 }
1243
1244 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1245                           uint64_t value)
1246 {
1247     int timeridx = ri->crm & 1;
1248
1249     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1250         + sextract64(value, 0, 32);
1251     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1252 }
1253
1254 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1255                          uint64_t value)
1256 {
1257     ARMCPU *cpu = arm_env_get_cpu(env);
1258     int timeridx = ri->crm & 1;
1259     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1260
1261     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1262     if ((oldval ^ value) & 1) {
1263         /* Enable toggled */
1264         gt_recalc_timer(cpu, timeridx);
1265     } else if ((oldval ^ value) & 2) {
1266         /* IMASK toggled: don't need to recalculate,
1267          * just set the interrupt line based on ISTATUS
1268          */
1269         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1270                      (oldval & 4) && !(value & 2));
1271     }
1272 }
1273
1274 void arm_gt_ptimer_cb(void *opaque)
1275 {
1276     ARMCPU *cpu = opaque;
1277
1278     gt_recalc_timer(cpu, GTIMER_PHYS);
1279 }
1280
1281 void arm_gt_vtimer_cb(void *opaque)
1282 {
1283     ARMCPU *cpu = opaque;
1284
1285     gt_recalc_timer(cpu, GTIMER_VIRT);
1286 }
1287
1288 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1289     /* Note that CNTFRQ is purely reads-as-written for the benefit
1290      * of software; writing it doesn't actually change the timer frequency.
1291      * Our reset value matches the fixed frequency we implement the timer at.
1292      */
1293     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1294       .type = ARM_CP_ALIAS,
1295       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1296       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1297       .resetfn = arm_cp_reset_ignore,
1298     },
1299     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1300       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1301       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1302       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1303       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1304     },
1305     /* overall control: mostly access permissions */
1306     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1307       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1308       .access = PL1_RW,
1309       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1310       .resetvalue = 0,
1311     },
1312     /* per-timer control */
1313     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1314       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1315       .accessfn = gt_ptimer_access,
1316       .fieldoffset = offsetoflow32(CPUARMState,
1317                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1318       .resetfn = arm_cp_reset_ignore,
1319       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1320     },
1321     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1322       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1323       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1324       .accessfn = gt_ptimer_access,
1325       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1326       .resetvalue = 0,
1327       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1328     },
1329     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1330       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1331       .accessfn = gt_vtimer_access,
1332       .fieldoffset = offsetoflow32(CPUARMState,
1333                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1334       .resetfn = arm_cp_reset_ignore,
1335       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1336     },
1337     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1338       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1339       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1340       .accessfn = gt_vtimer_access,
1341       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1342       .resetvalue = 0,
1343       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1344     },
1345     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1346     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1347       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1348       .accessfn = gt_ptimer_access,
1349       .readfn = gt_tval_read, .writefn = gt_tval_write,
1350     },
1351     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1352       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1353       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1354       .readfn = gt_tval_read, .writefn = gt_tval_write,
1355     },
1356     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1357       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1358       .accessfn = gt_vtimer_access,
1359       .readfn = gt_tval_read, .writefn = gt_tval_write,
1360     },
1361     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1362       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1363       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1364       .readfn = gt_tval_read, .writefn = gt_tval_write,
1365     },
1366     /* The counter itself */
1367     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1368       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1369       .accessfn = gt_pct_access,
1370       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1371     },
1372     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1373       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1374       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1375       .accessfn = gt_pct_access,
1376       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1377     },
1378     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1379       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1380       .accessfn = gt_vct_access,
1381       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1382     },
1383     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1384       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1385       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1386       .accessfn = gt_vct_access,
1387       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1388     },
1389     /* Comparison value, indicating when the timer goes off */
1390     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1391       .access = PL1_RW | PL0_R,
1392       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1393       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1394       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1395       .writefn = gt_cval_write, .raw_writefn = raw_write,
1396     },
1397     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1398       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1399       .access = PL1_RW | PL0_R,
1400       .type = ARM_CP_IO,
1401       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1402       .resetvalue = 0, .accessfn = gt_vtimer_access,
1403       .writefn = gt_cval_write, .raw_writefn = raw_write,
1404     },
1405     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1406       .access = PL1_RW | PL0_R,
1407       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1408       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1409       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1410       .writefn = gt_cval_write, .raw_writefn = raw_write,
1411     },
1412     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1413       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1414       .access = PL1_RW | PL0_R,
1415       .type = ARM_CP_IO,
1416       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1417       .resetvalue = 0, .accessfn = gt_vtimer_access,
1418       .writefn = gt_cval_write, .raw_writefn = raw_write,
1419     },
1420     REGINFO_SENTINEL
1421 };
1422
1423 #else
1424 /* In user-mode none of the generic timer registers are accessible,
1425  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1426  * so instead just don't register any of them.
1427  */
1428 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1429     REGINFO_SENTINEL
1430 };
1431
1432 #endif
1433
1434 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1435 {
1436     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1437         raw_write(env, ri, value);
1438     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1439         raw_write(env, ri, value & 0xfffff6ff);
1440     } else {
1441         raw_write(env, ri, value & 0xfffff1ff);
1442     }
1443 }
1444
1445 #ifndef CONFIG_USER_ONLY
1446 /* get_phys_addr() isn't present for user-mode-only targets */
1447
1448 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1449 {
1450     if (ri->opc2 & 4) {
1451         /* Other states are only available with TrustZone; in
1452          * a non-TZ implementation these registers don't exist
1453          * at all, which is an Uncategorized trap. This underdecoding
1454          * is safe because the reginfo is NO_RAW.
1455          */
1456         return CP_ACCESS_TRAP_UNCATEGORIZED;
1457     }
1458     return CP_ACCESS_OK;
1459 }
1460
1461 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1462                              int access_type, ARMMMUIdx mmu_idx)
1463 {
1464     hwaddr phys_addr;
1465     target_ulong page_size;
1466     int prot;
1467     int ret;
1468     uint64_t par64;
1469
1470     ret = get_phys_addr(env, value, access_type, mmu_idx,
1471                         &phys_addr, &prot, &page_size);
1472     if (extended_addresses_enabled(env)) {
1473         /* ret is a DFSR/IFSR value for the long descriptor
1474          * translation table format, but with WnR always clear.
1475          * Convert it to a 64-bit PAR.
1476          */
1477         par64 = (1 << 11); /* LPAE bit always set */
1478         if (ret == 0) {
1479             par64 |= phys_addr & ~0xfffULL;
1480             /* We don't set the ATTR or SH fields in the PAR. */
1481         } else {
1482             par64 |= 1; /* F */
1483             par64 |= (ret & 0x3f) << 1; /* FS */
1484             /* Note that S2WLK and FSTAGE are always zero, because we don't
1485              * implement virtualization and therefore there can't be a stage 2
1486              * fault.
1487              */
1488         }
1489     } else {
1490         /* ret is a DFSR/IFSR value for the short descriptor
1491          * translation table format (with WnR always clear).
1492          * Convert it to a 32-bit PAR.
1493          */
1494         if (ret == 0) {
1495             /* We do not set any attribute bits in the PAR */
1496             if (page_size == (1 << 24)
1497                 && arm_feature(env, ARM_FEATURE_V7)) {
1498                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1499             } else {
1500                 par64 = phys_addr & 0xfffff000;
1501             }
1502         } else {
1503             par64 = ((ret & (1 << 10)) >> 5) | ((ret & (1 << 12)) >> 6) |
1504                     ((ret & 0xf) << 1) | 1;
1505         }
1506     }
1507     return par64;
1508 }
1509
1510 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1511 {
1512     int access_type = ri->opc2 & 1;
1513     uint64_t par64;
1514     ARMMMUIdx mmu_idx;
1515     int el = arm_current_el(env);
1516     bool secure = arm_is_secure_below_el3(env);
1517
1518     switch (ri->opc2 & 6) {
1519     case 0:
1520         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1521         switch (el) {
1522         case 3:
1523             mmu_idx = ARMMMUIdx_S1E3;
1524             break;
1525         case 2:
1526             mmu_idx = ARMMMUIdx_S1NSE1;
1527             break;
1528         case 1:
1529             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1530             break;
1531         default:
1532             g_assert_not_reached();
1533         }
1534         break;
1535     case 2:
1536         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1537         switch (el) {
1538         case 3:
1539             mmu_idx = ARMMMUIdx_S1SE0;
1540             break;
1541         case 2:
1542             mmu_idx = ARMMMUIdx_S1NSE0;
1543             break;
1544         case 1:
1545             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1546             break;
1547         default:
1548             g_assert_not_reached();
1549         }
1550         break;
1551     case 4:
1552         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1553         mmu_idx = ARMMMUIdx_S12NSE1;
1554         break;
1555     case 6:
1556         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1557         mmu_idx = ARMMMUIdx_S12NSE0;
1558         break;
1559     default:
1560         g_assert_not_reached();
1561     }
1562
1563     par64 = do_ats_write(env, value, access_type, mmu_idx);
1564
1565     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1566 }
1567
1568 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1569                         uint64_t value)
1570 {
1571     int access_type = ri->opc2 & 1;
1572     ARMMMUIdx mmu_idx;
1573     int secure = arm_is_secure_below_el3(env);
1574
1575     switch (ri->opc2 & 6) {
1576     case 0:
1577         switch (ri->opc1) {
1578         case 0: /* AT S1E1R, AT S1E1W */
1579             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1580             break;
1581         case 4: /* AT S1E2R, AT S1E2W */
1582             mmu_idx = ARMMMUIdx_S1E2;
1583             break;
1584         case 6: /* AT S1E3R, AT S1E3W */
1585             mmu_idx = ARMMMUIdx_S1E3;
1586             break;
1587         default:
1588             g_assert_not_reached();
1589         }
1590         break;
1591     case 2: /* AT S1E0R, AT S1E0W */
1592         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1593         break;
1594     case 4: /* AT S12E1R, AT S12E1W */
1595         mmu_idx = ARMMMUIdx_S12NSE1;
1596         break;
1597     case 6: /* AT S12E0R, AT S12E0W */
1598         mmu_idx = ARMMMUIdx_S12NSE0;
1599         break;
1600     default:
1601         g_assert_not_reached();
1602     }
1603
1604     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1605 }
1606 #endif
1607
1608 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1609     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1610       .access = PL1_RW, .resetvalue = 0,
1611       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1612                              offsetoflow32(CPUARMState, cp15.par_ns) },
1613       .writefn = par_write },
1614 #ifndef CONFIG_USER_ONLY
1615     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1616       .access = PL1_W, .accessfn = ats_access,
1617       .writefn = ats_write, .type = ARM_CP_NO_RAW },
1618 #endif
1619     REGINFO_SENTINEL
1620 };
1621
1622 /* Return basic MPU access permission bits.  */
1623 static uint32_t simple_mpu_ap_bits(uint32_t val)
1624 {
1625     uint32_t ret;
1626     uint32_t mask;
1627     int i;
1628     ret = 0;
1629     mask = 3;
1630     for (i = 0; i < 16; i += 2) {
1631         ret |= (val >> i) & mask;
1632         mask <<= 2;
1633     }
1634     return ret;
1635 }
1636
1637 /* Pad basic MPU access permission bits to extended format.  */
1638 static uint32_t extended_mpu_ap_bits(uint32_t val)
1639 {
1640     uint32_t ret;
1641     uint32_t mask;
1642     int i;
1643     ret = 0;
1644     mask = 3;
1645     for (i = 0; i < 16; i += 2) {
1646         ret |= (val & mask) << i;
1647         mask <<= 2;
1648     }
1649     return ret;
1650 }
1651
1652 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1653                                  uint64_t value)
1654 {
1655     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1656 }
1657
1658 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1659 {
1660     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1661 }
1662
1663 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1664                                  uint64_t value)
1665 {
1666     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1667 }
1668
1669 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1670 {
1671     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1672 }
1673
1674 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1675     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1676       .access = PL1_RW, .type = ARM_CP_ALIAS,
1677       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1678       .resetvalue = 0,
1679       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1680     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1681       .access = PL1_RW, .type = ARM_CP_ALIAS,
1682       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1683       .resetvalue = 0,
1684       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1685     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1686       .access = PL1_RW,
1687       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1688       .resetvalue = 0, },
1689     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1690       .access = PL1_RW,
1691       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1692       .resetvalue = 0, },
1693     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1694       .access = PL1_RW,
1695       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1696     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1697       .access = PL1_RW,
1698       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1699     /* Protection region base and size registers */
1700     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1701       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1702       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1703     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1704       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1705       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1706     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1707       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1708       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1709     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1710       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1711       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1712     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1713       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1714       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1715     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1716       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1717       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1718     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1719       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1720       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1721     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1722       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1723       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1724     REGINFO_SENTINEL
1725 };
1726
1727 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1728                                  uint64_t value)
1729 {
1730     TCR *tcr = raw_ptr(env, ri);
1731     int maskshift = extract32(value, 0, 3);
1732
1733     if (!arm_feature(env, ARM_FEATURE_V8)) {
1734         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1735             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1736              * using Long-desciptor translation table format */
1737             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1738         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1739             /* In an implementation that includes the Security Extensions
1740              * TTBCR has additional fields PD0 [4] and PD1 [5] for
1741              * Short-descriptor translation table format.
1742              */
1743             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1744         } else {
1745             value &= TTBCR_N;
1746         }
1747     }
1748
1749     /* Update the masks corresponding to the the TCR bank being written
1750      * Note that we always calculate mask and base_mask, but
1751      * they are only used for short-descriptor tables (ie if EAE is 0);
1752      * for long-descriptor tables the TCR fields are used differently
1753      * and the mask and base_mask values are meaningless.
1754      */
1755     tcr->raw_tcr = value;
1756     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1757     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
1758 }
1759
1760 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1761                              uint64_t value)
1762 {
1763     ARMCPU *cpu = arm_env_get_cpu(env);
1764
1765     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1766         /* With LPAE the TTBCR could result in a change of ASID
1767          * via the TTBCR.A1 bit, so do a TLB flush.
1768          */
1769         tlb_flush(CPU(cpu), 1);
1770     }
1771     vmsa_ttbcr_raw_write(env, ri, value);
1772 }
1773
1774 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1775 {
1776     TCR *tcr = raw_ptr(env, ri);
1777
1778     /* Reset both the TCR as well as the masks corresponding to the bank of
1779      * the TCR being reset.
1780      */
1781     tcr->raw_tcr = 0;
1782     tcr->mask = 0;
1783     tcr->base_mask = 0xffffc000u;
1784 }
1785
1786 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1787                                uint64_t value)
1788 {
1789     ARMCPU *cpu = arm_env_get_cpu(env);
1790     TCR *tcr = raw_ptr(env, ri);
1791
1792     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1793     tlb_flush(CPU(cpu), 1);
1794     tcr->raw_tcr = value;
1795 }
1796
1797 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1798                             uint64_t value)
1799 {
1800     /* 64 bit accesses to the TTBRs can change the ASID and so we
1801      * must flush the TLB.
1802      */
1803     if (cpreg_field_is_64bit(ri)) {
1804         ARMCPU *cpu = arm_env_get_cpu(env);
1805
1806         tlb_flush(CPU(cpu), 1);
1807     }
1808     raw_write(env, ri, value);
1809 }
1810
1811 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1812     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1813       .access = PL1_RW, .type = ARM_CP_ALIAS,
1814       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
1815                              offsetoflow32(CPUARMState, cp15.dfsr_ns) },
1816       .resetfn = arm_cp_reset_ignore, },
1817     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1818       .access = PL1_RW, .resetvalue = 0,
1819       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
1820                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
1821     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1822       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1823       .access = PL1_RW,
1824       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1825     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1826       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
1827       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
1828       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
1829                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
1830     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1831       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
1832       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
1833       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
1834                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
1835     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1836       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1837       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1838       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1839       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
1840     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1841       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
1842       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1843       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
1844                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
1845     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
1846       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1847       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1848       .resetvalue = 0, },
1849     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
1850       .access = PL1_RW, .resetvalue = 0,
1851       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
1852                              offsetof(CPUARMState, cp15.dfar_ns) } },
1853     REGINFO_SENTINEL
1854 };
1855
1856 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1857                                 uint64_t value)
1858 {
1859     env->cp15.c15_ticonfig = value & 0xe7;
1860     /* The OS_TYPE bit in this register changes the reported CPUID! */
1861     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1862         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1863 }
1864
1865 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1866                                 uint64_t value)
1867 {
1868     env->cp15.c15_threadid = value & 0xffff;
1869 }
1870
1871 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1872                            uint64_t value)
1873 {
1874     /* Wait-for-interrupt (deprecated) */
1875     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1876 }
1877
1878 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1879                                   uint64_t value)
1880 {
1881     /* On OMAP there are registers indicating the max/min index of dcache lines
1882      * containing a dirty line; cache flush operations have to reset these.
1883      */
1884     env->cp15.c15_i_max = 0x000;
1885     env->cp15.c15_i_min = 0xff0;
1886 }
1887
1888 static const ARMCPRegInfo omap_cp_reginfo[] = {
1889     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1890       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1891       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1892       .resetvalue = 0, },
1893     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1894       .access = PL1_RW, .type = ARM_CP_NOP },
1895     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1896       .access = PL1_RW,
1897       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1898       .writefn = omap_ticonfig_write },
1899     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1900       .access = PL1_RW,
1901       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1902     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1903       .access = PL1_RW, .resetvalue = 0xff0,
1904       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1905     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1906       .access = PL1_RW,
1907       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1908       .writefn = omap_threadid_write },
1909     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1910       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1911       .type = ARM_CP_NO_RAW,
1912       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1913     /* TODO: Peripheral port remap register:
1914      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1915      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1916      * when MMU is off.
1917      */
1918     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1919       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1920       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
1921       .writefn = omap_cachemaint_write },
1922     { .name = "C9", .cp = 15, .crn = 9,
1923       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1924       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1925     REGINFO_SENTINEL
1926 };
1927
1928 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1929                               uint64_t value)
1930 {
1931     env->cp15.c15_cpar = value & 0x3fff;
1932 }
1933
1934 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1935     { .name = "XSCALE_CPAR",
1936       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1937       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1938       .writefn = xscale_cpar_write, },
1939     { .name = "XSCALE_AUXCR",
1940       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1941       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1942       .resetvalue = 0, },
1943     /* XScale specific cache-lockdown: since we have no cache we NOP these
1944      * and hope the guest does not really rely on cache behaviour.
1945      */
1946     { .name = "XSCALE_LOCK_ICACHE_LINE",
1947       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1948       .access = PL1_W, .type = ARM_CP_NOP },
1949     { .name = "XSCALE_UNLOCK_ICACHE",
1950       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1951       .access = PL1_W, .type = ARM_CP_NOP },
1952     { .name = "XSCALE_DCACHE_LOCK",
1953       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1954       .access = PL1_RW, .type = ARM_CP_NOP },
1955     { .name = "XSCALE_UNLOCK_DCACHE",
1956       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1957       .access = PL1_W, .type = ARM_CP_NOP },
1958     REGINFO_SENTINEL
1959 };
1960
1961 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1962     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1963      * implementation of this implementation-defined space.
1964      * Ideally this should eventually disappear in favour of actually
1965      * implementing the correct behaviour for all cores.
1966      */
1967     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1968       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1969       .access = PL1_RW,
1970       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
1971       .resetvalue = 0 },
1972     REGINFO_SENTINEL
1973 };
1974
1975 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1976     /* Cache status: RAZ because we have no cache so it's always clean */
1977     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1978       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
1979       .resetvalue = 0 },
1980     REGINFO_SENTINEL
1981 };
1982
1983 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1984     /* We never have a a block transfer operation in progress */
1985     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1986       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
1987       .resetvalue = 0 },
1988     /* The cache ops themselves: these all NOP for QEMU */
1989     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1990       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1991     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1992       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1993     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1994       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1995     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1996       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1997     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1998       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1999     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2000       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2001     REGINFO_SENTINEL
2002 };
2003
2004 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2005     /* The cache test-and-clean instructions always return (1 << 30)
2006      * to indicate that there are no dirty cache lines.
2007      */
2008     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2009       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2010       .resetvalue = (1 << 30) },
2011     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2012       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2013       .resetvalue = (1 << 30) },
2014     REGINFO_SENTINEL
2015 };
2016
2017 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2018     /* Ignore ReadBuffer accesses */
2019     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2020       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2021       .access = PL1_RW, .resetvalue = 0,
2022       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2023     REGINFO_SENTINEL
2024 };
2025
2026 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2027 {
2028     CPUState *cs = CPU(arm_env_get_cpu(env));
2029     uint32_t mpidr = cs->cpu_index;
2030     /* We don't support setting cluster ID ([8..11]) (known as Aff1
2031      * in later ARM ARM versions), or any of the higher affinity level fields,
2032      * so these bits always RAZ.
2033      */
2034     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2035         mpidr |= (1U << 31);
2036         /* Cores which are uniprocessor (non-coherent)
2037          * but still implement the MP extensions set
2038          * bit 30. (For instance, A9UP.) However we do
2039          * not currently model any of those cores.
2040          */
2041     }
2042     return mpidr;
2043 }
2044
2045 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2046     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2047       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2048       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2049     REGINFO_SENTINEL
2050 };
2051
2052 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2053     /* NOP AMAIR0/1: the override is because these clash with the rather
2054      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
2055      */
2056     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2057       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2058       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
2059       .resetvalue = 0 },
2060     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2061     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2062       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
2063       .resetvalue = 0 },
2064     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2065       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2066       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2067                              offsetof(CPUARMState, cp15.par_ns)} },
2068     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2069       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2070       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2071                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2072       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
2073     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2074       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2075       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2076                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2077       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
2078     REGINFO_SENTINEL
2079 };
2080
2081 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2082 {
2083     return vfp_get_fpcr(env);
2084 }
2085
2086 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2087                             uint64_t value)
2088 {
2089     vfp_set_fpcr(env, value);
2090 }
2091
2092 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2093 {
2094     return vfp_get_fpsr(env);
2095 }
2096
2097 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2098                             uint64_t value)
2099 {
2100     vfp_set_fpsr(env, value);
2101 }
2102
2103 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
2104 {
2105     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2106         return CP_ACCESS_TRAP;
2107     }
2108     return CP_ACCESS_OK;
2109 }
2110
2111 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2112                             uint64_t value)
2113 {
2114     env->daif = value & PSTATE_DAIF;
2115 }
2116
2117 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2118                                           const ARMCPRegInfo *ri)
2119 {
2120     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2121      * SCTLR_EL1.UCI is set.
2122      */
2123     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2124         return CP_ACCESS_TRAP;
2125     }
2126     return CP_ACCESS_OK;
2127 }
2128
2129 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2130  * Page D4-1736 (DDI0487A.b)
2131  */
2132
2133 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
2134                                uint64_t value)
2135 {
2136     /* Invalidate by VA (AArch64 version) */
2137     ARMCPU *cpu = arm_env_get_cpu(env);
2138     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2139
2140     tlb_flush_page(CPU(cpu), pageaddr);
2141 }
2142
2143 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
2144                                 uint64_t value)
2145 {
2146     /* Invalidate by VA, all ASIDs (AArch64 version) */
2147     ARMCPU *cpu = arm_env_get_cpu(env);
2148     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2149
2150     tlb_flush_page(CPU(cpu), pageaddr);
2151 }
2152
2153 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2154                                  uint64_t value)
2155 {
2156     /* Invalidate by ASID (AArch64 version) */
2157     ARMCPU *cpu = arm_env_get_cpu(env);
2158     int asid = extract64(value, 48, 16);
2159     tlb_flush(CPU(cpu), asid == 0);
2160 }
2161
2162 static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2163                                   uint64_t value)
2164 {
2165     CPUState *other_cs;
2166     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2167
2168     CPU_FOREACH(other_cs) {
2169         tlb_flush_page(other_cs, pageaddr);
2170     }
2171 }
2172
2173 static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2174                                   uint64_t value)
2175 {
2176     CPUState *other_cs;
2177     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2178
2179     CPU_FOREACH(other_cs) {
2180         tlb_flush_page(other_cs, pageaddr);
2181     }
2182 }
2183
2184 static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2185                                   uint64_t value)
2186 {
2187     CPUState *other_cs;
2188     int asid = extract64(value, 48, 16);
2189
2190     CPU_FOREACH(other_cs) {
2191         tlb_flush(other_cs, asid == 0);
2192     }
2193 }
2194
2195 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2196 {
2197     /* We don't implement EL2, so the only control on DC ZVA is the
2198      * bit in the SCTLR which can prohibit access for EL0.
2199      */
2200     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2201         return CP_ACCESS_TRAP;
2202     }
2203     return CP_ACCESS_OK;
2204 }
2205
2206 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2207 {
2208     ARMCPU *cpu = arm_env_get_cpu(env);
2209     int dzp_bit = 1 << 4;
2210
2211     /* DZP indicates whether DC ZVA access is allowed */
2212     if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2213         dzp_bit = 0;
2214     }
2215     return cpu->dcz_blocksize | dzp_bit;
2216 }
2217
2218 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2219 {
2220     if (!(env->pstate & PSTATE_SP)) {
2221         /* Access to SP_EL0 is undefined if it's being used as
2222          * the stack pointer.
2223          */
2224         return CP_ACCESS_TRAP_UNCATEGORIZED;
2225     }
2226     return CP_ACCESS_OK;
2227 }
2228
2229 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2230 {
2231     return env->pstate & PSTATE_SP;
2232 }
2233
2234 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2235 {
2236     update_spsel(env, val);
2237 }
2238
2239 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2240                         uint64_t value)
2241 {
2242     ARMCPU *cpu = arm_env_get_cpu(env);
2243
2244     if (raw_read(env, ri) == value) {
2245         /* Skip the TLB flush if nothing actually changed; Linux likes
2246          * to do a lot of pointless SCTLR writes.
2247          */
2248         return;
2249     }
2250
2251     raw_write(env, ri, value);
2252     /* ??? Lots of these bits are not implemented.  */
2253     /* This may enable/disable the MMU, so do a TLB flush.  */
2254     tlb_flush(CPU(cpu), 1);
2255 }
2256
2257 static const ARMCPRegInfo v8_cp_reginfo[] = {
2258     /* Minimal set of EL0-visible registers. This will need to be expanded
2259      * significantly for system emulation of AArch64 CPUs.
2260      */
2261     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2262       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2263       .access = PL0_RW, .type = ARM_CP_NZCV },
2264     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2265       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2266       .type = ARM_CP_NO_RAW,
2267       .access = PL0_RW, .accessfn = aa64_daif_access,
2268       .fieldoffset = offsetof(CPUARMState, daif),
2269       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2270     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2271       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2272       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2273     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2274       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2275       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2276     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2277       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2278       .access = PL0_R, .type = ARM_CP_NO_RAW,
2279       .readfn = aa64_dczid_read },
2280     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2281       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2282       .access = PL0_W, .type = ARM_CP_DC_ZVA,
2283 #ifndef CONFIG_USER_ONLY
2284       /* Avoid overhead of an access check that always passes in user-mode */
2285       .accessfn = aa64_zva_access,
2286 #endif
2287     },
2288     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2289       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2290       .access = PL1_R, .type = ARM_CP_CURRENTEL },
2291     /* Cache ops: all NOPs since we don't emulate caches */
2292     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2293       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2294       .access = PL1_W, .type = ARM_CP_NOP },
2295     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2296       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2297       .access = PL1_W, .type = ARM_CP_NOP },
2298     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2299       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2300       .access = PL0_W, .type = ARM_CP_NOP,
2301       .accessfn = aa64_cacheop_access },
2302     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2303       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2304       .access = PL1_W, .type = ARM_CP_NOP },
2305     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2306       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2307       .access = PL1_W, .type = ARM_CP_NOP },
2308     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2309       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2310       .access = PL0_W, .type = ARM_CP_NOP,
2311       .accessfn = aa64_cacheop_access },
2312     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2313       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2314       .access = PL1_W, .type = ARM_CP_NOP },
2315     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2316       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2317       .access = PL0_W, .type = ARM_CP_NOP,
2318       .accessfn = aa64_cacheop_access },
2319     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2320       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2321       .access = PL0_W, .type = ARM_CP_NOP,
2322       .accessfn = aa64_cacheop_access },
2323     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2324       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2325       .access = PL1_W, .type = ARM_CP_NOP },
2326     /* TLBI operations */
2327     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2328       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2329       .access = PL1_W, .type = ARM_CP_NO_RAW,
2330       .writefn = tlbiall_is_write },
2331     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2332       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2333       .access = PL1_W, .type = ARM_CP_NO_RAW,
2334       .writefn = tlbi_aa64_va_is_write },
2335     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2336       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2337       .access = PL1_W, .type = ARM_CP_NO_RAW,
2338       .writefn = tlbi_aa64_asid_is_write },
2339     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2340       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2341       .access = PL1_W, .type = ARM_CP_NO_RAW,
2342       .writefn = tlbi_aa64_vaa_is_write },
2343     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2344       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2345       .access = PL1_W, .type = ARM_CP_NO_RAW,
2346       .writefn = tlbi_aa64_va_is_write },
2347     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2348       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2349       .access = PL1_W, .type = ARM_CP_NO_RAW,
2350       .writefn = tlbi_aa64_vaa_is_write },
2351     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2352       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2353       .access = PL1_W, .type = ARM_CP_NO_RAW,
2354       .writefn = tlbiall_write },
2355     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2356       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2357       .access = PL1_W, .type = ARM_CP_NO_RAW,
2358       .writefn = tlbi_aa64_va_write },
2359     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2360       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2361       .access = PL1_W, .type = ARM_CP_NO_RAW,
2362       .writefn = tlbi_aa64_asid_write },
2363     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2364       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2365       .access = PL1_W, .type = ARM_CP_NO_RAW,
2366       .writefn = tlbi_aa64_vaa_write },
2367     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2368       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2369       .access = PL1_W, .type = ARM_CP_NO_RAW,
2370       .writefn = tlbi_aa64_va_write },
2371     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2372       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2373       .access = PL1_W, .type = ARM_CP_NO_RAW,
2374       .writefn = tlbi_aa64_vaa_write },
2375 #ifndef CONFIG_USER_ONLY
2376     /* 64 bit address translation operations */
2377     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2378       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2379       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2380     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2381       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2382       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2383     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2384       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2385       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2386     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2387       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2388       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2389 #endif
2390     /* TLB invalidate last level of translation table walk */
2391     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2392       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
2393     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2394       .type = ARM_CP_NO_RAW, .access = PL1_W,
2395       .writefn = tlbimvaa_is_write },
2396     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2397       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
2398     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2399       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
2400     /* 32 bit cache operations */
2401     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2402       .type = ARM_CP_NOP, .access = PL1_W },
2403     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2404       .type = ARM_CP_NOP, .access = PL1_W },
2405     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2406       .type = ARM_CP_NOP, .access = PL1_W },
2407     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2408       .type = ARM_CP_NOP, .access = PL1_W },
2409     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2410       .type = ARM_CP_NOP, .access = PL1_W },
2411     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2412       .type = ARM_CP_NOP, .access = PL1_W },
2413     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2414       .type = ARM_CP_NOP, .access = PL1_W },
2415     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2416       .type = ARM_CP_NOP, .access = PL1_W },
2417     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2418       .type = ARM_CP_NOP, .access = PL1_W },
2419     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2420       .type = ARM_CP_NOP, .access = PL1_W },
2421     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2422       .type = ARM_CP_NOP, .access = PL1_W },
2423     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2424       .type = ARM_CP_NOP, .access = PL1_W },
2425     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2426       .type = ARM_CP_NOP, .access = PL1_W },
2427     /* MMU Domain access control / MPU write buffer control */
2428     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2429       .access = PL1_RW, .resetvalue = 0,
2430       .writefn = dacr_write, .raw_writefn = raw_write,
2431       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
2432                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
2433     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2434       .type = ARM_CP_ALIAS,
2435       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2436       .access = PL1_RW,
2437       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2438     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2439       .type = ARM_CP_ALIAS,
2440       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2441       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2442     /* We rely on the access checks not allowing the guest to write to the
2443      * state field when SPSel indicates that it's being used as the stack
2444      * pointer.
2445      */
2446     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2447       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2448       .access = PL1_RW, .accessfn = sp_el0_access,
2449       .type = ARM_CP_ALIAS,
2450       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2451     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
2452       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
2453       .access = PL2_RW, .type = ARM_CP_ALIAS,
2454       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
2455     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2456       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2457       .type = ARM_CP_NO_RAW,
2458       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2459     REGINFO_SENTINEL
2460 };
2461
2462 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
2463 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2464     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2465       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2466       .access = PL2_RW,
2467       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2468     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2469       .type = ARM_CP_NO_RAW,
2470       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2471       .access = PL2_RW,
2472       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2473     REGINFO_SENTINEL
2474 };
2475
2476 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2477 {
2478     ARMCPU *cpu = arm_env_get_cpu(env);
2479     uint64_t valid_mask = HCR_MASK;
2480
2481     if (arm_feature(env, ARM_FEATURE_EL3)) {
2482         valid_mask &= ~HCR_HCD;
2483     } else {
2484         valid_mask &= ~HCR_TSC;
2485     }
2486
2487     /* Clear RES0 bits.  */
2488     value &= valid_mask;
2489
2490     /* These bits change the MMU setup:
2491      * HCR_VM enables stage 2 translation
2492      * HCR_PTW forbids certain page-table setups
2493      * HCR_DC Disables stage1 and enables stage2 translation
2494      */
2495     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
2496         tlb_flush(CPU(cpu), 1);
2497     }
2498     raw_write(env, ri, value);
2499 }
2500
2501 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2502     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2503       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2504       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
2505       .writefn = hcr_write },
2506     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
2507       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
2508       .access = PL2_RW, .resetvalue = 0,
2509       .writefn = dacr_write, .raw_writefn = raw_write,
2510       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
2511     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2512       .type = ARM_CP_ALIAS,
2513       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2514       .access = PL2_RW,
2515       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2516     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2517       .type = ARM_CP_ALIAS,
2518       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2519       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2520     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
2521       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
2522       .access = PL2_RW, .resetvalue = 0,
2523       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
2524     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2525       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2526       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2527     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2528       .type = ARM_CP_ALIAS,
2529       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2530       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2531     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2532       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2533       .access = PL2_RW, .writefn = vbar_write,
2534       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2535       .resetvalue = 0 },
2536     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
2537       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
2538       .access = PL3_RW, .type = ARM_CP_ALIAS,
2539       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
2540     REGINFO_SENTINEL
2541 };
2542
2543 static const ARMCPRegInfo el3_cp_reginfo[] = {
2544     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
2545       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
2546       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
2547       .resetvalue = 0, .writefn = scr_write },
2548     { .name = "SCR",  .type = ARM_CP_ALIAS,
2549       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
2550       .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
2551       .resetfn = arm_cp_reset_ignore, .writefn = scr_write },
2552     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
2553       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
2554       .access = PL3_RW, .resetvalue = 0,
2555       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
2556     { .name = "SDER",
2557       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
2558       .access = PL3_RW, .resetvalue = 0,
2559       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
2560       /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
2561     { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
2562       .access = PL3_W | PL1_R, .resetvalue = 0,
2563       .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
2564     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
2565       .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
2566       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
2567     { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
2568       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
2569       .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
2570       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
2571     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
2572       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
2573       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2574       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
2575     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
2576       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
2577       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
2578       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2579       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
2580     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2581       .type = ARM_CP_ALIAS,
2582       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2583       .access = PL3_RW,
2584       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2585     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2586       .type = ARM_CP_ALIAS,
2587       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2588       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2589     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2590       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2591       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2592     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2593       .type = ARM_CP_ALIAS,
2594       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2595       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2596     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2597       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2598       .access = PL3_RW, .writefn = vbar_write,
2599       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2600       .resetvalue = 0 },
2601     REGINFO_SENTINEL
2602 };
2603
2604 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2605 {
2606     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2607      * but the AArch32 CTR has its own reginfo struct)
2608      */
2609     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
2610         return CP_ACCESS_TRAP;
2611     }
2612     return CP_ACCESS_OK;
2613 }
2614
2615 static const ARMCPRegInfo debug_cp_reginfo[] = {
2616     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2617      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2618      * unlike DBGDRAR it is never accessible from EL0.
2619      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2620      * accessor.
2621      */
2622     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2623       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2624     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2625       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2626       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2627     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2628       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2629     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
2630     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2631       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2632       .access = PL1_RW,
2633       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2634       .resetvalue = 0 },
2635     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
2636      * We don't implement the configurable EL0 access.
2637      */
2638     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
2639       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2640       .type = ARM_CP_ALIAS,
2641       .access = PL1_R,
2642       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2643       .resetfn = arm_cp_reset_ignore },
2644     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2645     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2646       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2647       .access = PL1_W, .type = ARM_CP_NOP },
2648     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
2649     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
2650       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
2651       .access = PL1_RW, .type = ARM_CP_NOP },
2652     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
2653      * implement vector catch debug events yet.
2654      */
2655     { .name = "DBGVCR",
2656       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2657       .access = PL1_RW, .type = ARM_CP_NOP },
2658     REGINFO_SENTINEL
2659 };
2660
2661 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2662     /* 64 bit access versions of the (dummy) debug registers */
2663     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2664       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2665     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2666       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2667     REGINFO_SENTINEL
2668 };
2669
2670 void hw_watchpoint_update(ARMCPU *cpu, int n)
2671 {
2672     CPUARMState *env = &cpu->env;
2673     vaddr len = 0;
2674     vaddr wvr = env->cp15.dbgwvr[n];
2675     uint64_t wcr = env->cp15.dbgwcr[n];
2676     int mask;
2677     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
2678
2679     if (env->cpu_watchpoint[n]) {
2680         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
2681         env->cpu_watchpoint[n] = NULL;
2682     }
2683
2684     if (!extract64(wcr, 0, 1)) {
2685         /* E bit clear : watchpoint disabled */
2686         return;
2687     }
2688
2689     switch (extract64(wcr, 3, 2)) {
2690     case 0:
2691         /* LSC 00 is reserved and must behave as if the wp is disabled */
2692         return;
2693     case 1:
2694         flags |= BP_MEM_READ;
2695         break;
2696     case 2:
2697         flags |= BP_MEM_WRITE;
2698         break;
2699     case 3:
2700         flags |= BP_MEM_ACCESS;
2701         break;
2702     }
2703
2704     /* Attempts to use both MASK and BAS fields simultaneously are
2705      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
2706      * thus generating a watchpoint for every byte in the masked region.
2707      */
2708     mask = extract64(wcr, 24, 4);
2709     if (mask == 1 || mask == 2) {
2710         /* Reserved values of MASK; we must act as if the mask value was
2711          * some non-reserved value, or as if the watchpoint were disabled.
2712          * We choose the latter.
2713          */
2714         return;
2715     } else if (mask) {
2716         /* Watchpoint covers an aligned area up to 2GB in size */
2717         len = 1ULL << mask;
2718         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
2719          * whether the watchpoint fires when the unmasked bits match; we opt
2720          * to generate the exceptions.
2721          */
2722         wvr &= ~(len - 1);
2723     } else {
2724         /* Watchpoint covers bytes defined by the byte address select bits */
2725         int bas = extract64(wcr, 5, 8);
2726         int basstart;
2727
2728         if (bas == 0) {
2729             /* This must act as if the watchpoint is disabled */
2730             return;
2731         }
2732
2733         if (extract64(wvr, 2, 1)) {
2734             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
2735              * ignored, and BAS[3:0] define which bytes to watch.
2736              */
2737             bas &= 0xf;
2738         }
2739         /* The BAS bits are supposed to be programmed to indicate a contiguous
2740          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
2741          * we fire for each byte in the word/doubleword addressed by the WVR.
2742          * We choose to ignore any non-zero bits after the first range of 1s.
2743          */
2744         basstart = ctz32(bas);
2745         len = cto32(bas >> basstart);
2746         wvr += basstart;
2747     }
2748
2749     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
2750                           &env->cpu_watchpoint[n]);
2751 }
2752
2753 void hw_watchpoint_update_all(ARMCPU *cpu)
2754 {
2755     int i;
2756     CPUARMState *env = &cpu->env;
2757
2758     /* Completely clear out existing QEMU watchpoints and our array, to
2759      * avoid possible stale entries following migration load.
2760      */
2761     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
2762     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
2763
2764     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
2765         hw_watchpoint_update(cpu, i);
2766     }
2767 }
2768
2769 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2770                          uint64_t value)
2771 {
2772     ARMCPU *cpu = arm_env_get_cpu(env);
2773     int i = ri->crm;
2774
2775     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
2776      * register reads and behaves as if values written are sign extended.
2777      * Bits [1:0] are RES0.
2778      */
2779     value = sextract64(value, 0, 49) & ~3ULL;
2780
2781     raw_write(env, ri, value);
2782     hw_watchpoint_update(cpu, i);
2783 }
2784
2785 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2786                          uint64_t value)
2787 {
2788     ARMCPU *cpu = arm_env_get_cpu(env);
2789     int i = ri->crm;
2790
2791     raw_write(env, ri, value);
2792     hw_watchpoint_update(cpu, i);
2793 }
2794
2795 void hw_breakpoint_update(ARMCPU *cpu, int n)
2796 {
2797     CPUARMState *env = &cpu->env;
2798     uint64_t bvr = env->cp15.dbgbvr[n];
2799     uint64_t bcr = env->cp15.dbgbcr[n];
2800     vaddr addr;
2801     int bt;
2802     int flags = BP_CPU;
2803
2804     if (env->cpu_breakpoint[n]) {
2805         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
2806         env->cpu_breakpoint[n] = NULL;
2807     }
2808
2809     if (!extract64(bcr, 0, 1)) {
2810         /* E bit clear : watchpoint disabled */
2811         return;
2812     }
2813
2814     bt = extract64(bcr, 20, 4);
2815
2816     switch (bt) {
2817     case 4: /* unlinked address mismatch (reserved if AArch64) */
2818     case 5: /* linked address mismatch (reserved if AArch64) */
2819         qemu_log_mask(LOG_UNIMP,
2820                       "arm: address mismatch breakpoint types not implemented");
2821         return;
2822     case 0: /* unlinked address match */
2823     case 1: /* linked address match */
2824     {
2825         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
2826          * we behave as if the register was sign extended. Bits [1:0] are
2827          * RES0. The BAS field is used to allow setting breakpoints on 16
2828          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
2829          * a bp will fire if the addresses covered by the bp and the addresses
2830          * covered by the insn overlap but the insn doesn't start at the
2831          * start of the bp address range. We choose to require the insn and
2832          * the bp to have the same address. The constraints on writing to
2833          * BAS enforced in dbgbcr_write mean we have only four cases:
2834          *  0b0000  => no breakpoint
2835          *  0b0011  => breakpoint on addr
2836          *  0b1100  => breakpoint on addr + 2
2837          *  0b1111  => breakpoint on addr
2838          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
2839          */
2840         int bas = extract64(bcr, 5, 4);
2841         addr = sextract64(bvr, 0, 49) & ~3ULL;
2842         if (bas == 0) {
2843             return;
2844         }
2845         if (bas == 0xc) {
2846             addr += 2;
2847         }
2848         break;
2849     }
2850     case 2: /* unlinked context ID match */
2851     case 8: /* unlinked VMID match (reserved if no EL2) */
2852     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
2853         qemu_log_mask(LOG_UNIMP,
2854                       "arm: unlinked context breakpoint types not implemented");
2855         return;
2856     case 9: /* linked VMID match (reserved if no EL2) */
2857     case 11: /* linked context ID and VMID match (reserved if no EL2) */
2858     case 3: /* linked context ID match */
2859     default:
2860         /* We must generate no events for Linked context matches (unless
2861          * they are linked to by some other bp/wp, which is handled in
2862          * updates for the linking bp/wp). We choose to also generate no events
2863          * for reserved values.
2864          */
2865         return;
2866     }
2867
2868     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
2869 }
2870
2871 void hw_breakpoint_update_all(ARMCPU *cpu)
2872 {
2873     int i;
2874     CPUARMState *env = &cpu->env;
2875
2876     /* Completely clear out existing QEMU breakpoints and our array, to
2877      * avoid possible stale entries following migration load.
2878      */
2879     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
2880     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
2881
2882     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
2883         hw_breakpoint_update(cpu, i);
2884     }
2885 }
2886
2887 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2888                          uint64_t value)
2889 {
2890     ARMCPU *cpu = arm_env_get_cpu(env);
2891     int i = ri->crm;
2892
2893     raw_write(env, ri, value);
2894     hw_breakpoint_update(cpu, i);
2895 }
2896
2897 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2898                          uint64_t value)
2899 {
2900     ARMCPU *cpu = arm_env_get_cpu(env);
2901     int i = ri->crm;
2902
2903     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
2904      * copy of BAS[0].
2905      */
2906     value = deposit64(value, 6, 1, extract64(value, 5, 1));
2907     value = deposit64(value, 8, 1, extract64(value, 7, 1));
2908
2909     raw_write(env, ri, value);
2910     hw_breakpoint_update(cpu, i);
2911 }
2912
2913 static void define_debug_regs(ARMCPU *cpu)
2914 {
2915     /* Define v7 and v8 architectural debug registers.
2916      * These are just dummy implementations for now.
2917      */
2918     int i;
2919     int wrps, brps, ctx_cmps;
2920     ARMCPRegInfo dbgdidr = {
2921         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
2922         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
2923     };
2924
2925     /* Note that all these register fields hold "number of Xs minus 1". */
2926     brps = extract32(cpu->dbgdidr, 24, 4);
2927     wrps = extract32(cpu->dbgdidr, 28, 4);
2928     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
2929
2930     assert(ctx_cmps <= brps);
2931
2932     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
2933      * of the debug registers such as number of breakpoints;
2934      * check that if they both exist then they agree.
2935      */
2936     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2937         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
2938         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
2939         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
2940     }
2941
2942     define_one_arm_cp_reg(cpu, &dbgdidr);
2943     define_arm_cp_regs(cpu, debug_cp_reginfo);
2944
2945     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
2946         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
2947     }
2948
2949     for (i = 0; i < brps + 1; i++) {
2950         ARMCPRegInfo dbgregs[] = {
2951             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
2952               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2953               .access = PL1_RW,
2954               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
2955               .writefn = dbgbvr_write, .raw_writefn = raw_write
2956             },
2957             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
2958               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2959               .access = PL1_RW,
2960               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
2961               .writefn = dbgbcr_write, .raw_writefn = raw_write
2962             },
2963             REGINFO_SENTINEL
2964         };
2965         define_arm_cp_regs(cpu, dbgregs);
2966     }
2967
2968     for (i = 0; i < wrps + 1; i++) {
2969         ARMCPRegInfo dbgregs[] = {
2970             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
2971               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2972               .access = PL1_RW,
2973               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
2974               .writefn = dbgwvr_write, .raw_writefn = raw_write
2975             },
2976             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
2977               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2978               .access = PL1_RW,
2979               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
2980               .writefn = dbgwcr_write, .raw_writefn = raw_write
2981             },
2982             REGINFO_SENTINEL
2983         };
2984         define_arm_cp_regs(cpu, dbgregs);
2985     }
2986 }
2987
2988 void register_cp_regs_for_features(ARMCPU *cpu)
2989 {
2990     /* Register all the coprocessor registers based on feature bits */
2991     CPUARMState *env = &cpu->env;
2992     if (arm_feature(env, ARM_FEATURE_M)) {
2993         /* M profile has no coprocessor registers */
2994         return;
2995     }
2996
2997     define_arm_cp_regs(cpu, cp_reginfo);
2998     if (!arm_feature(env, ARM_FEATURE_V8)) {
2999         /* Must go early as it is full of wildcards that may be
3000          * overridden by later definitions.
3001          */
3002         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
3003     }
3004
3005     if (arm_feature(env, ARM_FEATURE_V6)) {
3006         /* The ID registers all have impdef reset values */
3007         ARMCPRegInfo v6_idregs[] = {
3008             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
3009               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3010               .access = PL1_R, .type = ARM_CP_CONST,
3011               .resetvalue = cpu->id_pfr0 },
3012             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
3013               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
3014               .access = PL1_R, .type = ARM_CP_CONST,
3015               .resetvalue = cpu->id_pfr1 },
3016             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
3017               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
3018               .access = PL1_R, .type = ARM_CP_CONST,
3019               .resetvalue = cpu->id_dfr0 },
3020             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
3021               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
3022               .access = PL1_R, .type = ARM_CP_CONST,
3023               .resetvalue = cpu->id_afr0 },
3024             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
3025               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
3026               .access = PL1_R, .type = ARM_CP_CONST,
3027               .resetvalue = cpu->id_mmfr0 },
3028             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
3029               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
3030               .access = PL1_R, .type = ARM_CP_CONST,
3031               .resetvalue = cpu->id_mmfr1 },
3032             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
3033               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
3034               .access = PL1_R, .type = ARM_CP_CONST,
3035               .resetvalue = cpu->id_mmfr2 },
3036             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
3037               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
3038               .access = PL1_R, .type = ARM_CP_CONST,
3039               .resetvalue = cpu->id_mmfr3 },
3040             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
3041               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
3042               .access = PL1_R, .type = ARM_CP_CONST,
3043               .resetvalue = cpu->id_isar0 },
3044             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
3045               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
3046               .access = PL1_R, .type = ARM_CP_CONST,
3047               .resetvalue = cpu->id_isar1 },
3048             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
3049               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3050               .access = PL1_R, .type = ARM_CP_CONST,
3051               .resetvalue = cpu->id_isar2 },
3052             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
3053               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
3054               .access = PL1_R, .type = ARM_CP_CONST,
3055               .resetvalue = cpu->id_isar3 },
3056             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
3057               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
3058               .access = PL1_R, .type = ARM_CP_CONST,
3059               .resetvalue = cpu->id_isar4 },
3060             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
3061               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
3062               .access = PL1_R, .type = ARM_CP_CONST,
3063               .resetvalue = cpu->id_isar5 },
3064             /* 6..7 are as yet unallocated and must RAZ */
3065             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
3066               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
3067               .resetvalue = 0 },
3068             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
3069               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
3070               .resetvalue = 0 },
3071             REGINFO_SENTINEL
3072         };
3073         define_arm_cp_regs(cpu, v6_idregs);
3074         define_arm_cp_regs(cpu, v6_cp_reginfo);
3075     } else {
3076         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
3077     }
3078     if (arm_feature(env, ARM_FEATURE_V6K)) {
3079         define_arm_cp_regs(cpu, v6k_cp_reginfo);
3080     }
3081     if (arm_feature(env, ARM_FEATURE_V7MP)) {
3082         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
3083     }
3084     if (arm_feature(env, ARM_FEATURE_V7)) {
3085         /* v7 performance monitor control register: same implementor
3086          * field as main ID register, and we implement only the cycle
3087          * count register.
3088          */
3089 #ifndef CONFIG_USER_ONLY
3090         ARMCPRegInfo pmcr = {
3091             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
3092             .access = PL0_RW,
3093             .type = ARM_CP_IO | ARM_CP_ALIAS,
3094             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
3095             .accessfn = pmreg_access, .writefn = pmcr_write,
3096             .raw_writefn = raw_write,
3097         };
3098         ARMCPRegInfo pmcr64 = {
3099             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
3100             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
3101             .access = PL0_RW, .accessfn = pmreg_access,
3102             .type = ARM_CP_IO,
3103             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
3104             .resetvalue = cpu->midr & 0xff000000,
3105             .writefn = pmcr_write, .raw_writefn = raw_write,
3106         };
3107         define_one_arm_cp_reg(cpu, &pmcr);
3108         define_one_arm_cp_reg(cpu, &pmcr64);
3109 #endif
3110         ARMCPRegInfo clidr = {
3111             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
3112             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
3113             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
3114         };
3115         define_one_arm_cp_reg(cpu, &clidr);
3116         define_arm_cp_regs(cpu, v7_cp_reginfo);
3117         define_debug_regs(cpu);
3118     } else {
3119         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
3120     }
3121     if (arm_feature(env, ARM_FEATURE_V8)) {
3122         /* AArch64 ID registers, which all have impdef reset values */
3123         ARMCPRegInfo v8_idregs[] = {
3124             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
3125               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
3126               .access = PL1_R, .type = ARM_CP_CONST,
3127               .resetvalue = cpu->id_aa64pfr0 },
3128             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
3129               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
3130               .access = PL1_R, .type = ARM_CP_CONST,
3131               .resetvalue = cpu->id_aa64pfr1},
3132             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
3133               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
3134               .access = PL1_R, .type = ARM_CP_CONST,
3135               /* We mask out the PMUVer field, because we don't currently
3136                * implement the PMU. Not advertising it prevents the guest
3137                * from trying to use it and getting UNDEFs on registers we
3138                * don't implement.
3139                */
3140               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
3141             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
3142               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
3143               .access = PL1_R, .type = ARM_CP_CONST,
3144               .resetvalue = cpu->id_aa64dfr1 },
3145             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
3146               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
3147               .access = PL1_R, .type = ARM_CP_CONST,
3148               .resetvalue = cpu->id_aa64afr0 },
3149             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
3150               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
3151               .access = PL1_R, .type = ARM_CP_CONST,
3152               .resetvalue = cpu->id_aa64afr1 },
3153             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
3154               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
3155               .access = PL1_R, .type = ARM_CP_CONST,
3156               .resetvalue = cpu->id_aa64isar0 },
3157             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
3158               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
3159               .access = PL1_R, .type = ARM_CP_CONST,
3160               .resetvalue = cpu->id_aa64isar1 },
3161             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
3162               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3163               .access = PL1_R, .type = ARM_CP_CONST,
3164               .resetvalue = cpu->id_aa64mmfr0 },
3165             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
3166               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
3167               .access = PL1_R, .type = ARM_CP_CONST,
3168               .resetvalue = cpu->id_aa64mmfr1 },
3169             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
3170               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
3171               .access = PL1_R, .type = ARM_CP_CONST,
3172               .resetvalue = cpu->mvfr0 },
3173             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
3174               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
3175               .access = PL1_R, .type = ARM_CP_CONST,
3176               .resetvalue = cpu->mvfr1 },
3177             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
3178               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
3179               .access = PL1_R, .type = ARM_CP_CONST,
3180               .resetvalue = cpu->mvfr2 },
3181             REGINFO_SENTINEL
3182         };
3183         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
3184         if (!arm_feature(env, ARM_FEATURE_EL3) &&
3185             !arm_feature(env, ARM_FEATURE_EL2)) {
3186             ARMCPRegInfo rvbar = {
3187                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
3188                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3189                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
3190             };
3191             define_one_arm_cp_reg(cpu, &rvbar);
3192         }
3193         define_arm_cp_regs(cpu, v8_idregs);
3194         define_arm_cp_regs(cpu, v8_cp_reginfo);
3195     }
3196     if (arm_feature(env, ARM_FEATURE_EL2)) {
3197         define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
3198         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
3199         if (!arm_feature(env, ARM_FEATURE_EL3)) {
3200             ARMCPRegInfo rvbar = {
3201                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
3202                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
3203                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
3204             };
3205             define_one_arm_cp_reg(cpu, &rvbar);
3206         }
3207     } else {
3208         /* If EL2 is missing but higher ELs are enabled, we need to
3209          * register the no_el2 reginfos.
3210          */
3211         if (arm_feature(env, ARM_FEATURE_EL3)) {
3212             define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
3213         }
3214     }
3215     if (arm_feature(env, ARM_FEATURE_EL3)) {
3216         define_arm_cp_regs(cpu, el3_cp_reginfo);
3217         ARMCPRegInfo rvbar = {
3218             .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
3219             .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
3220             .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
3221         };
3222         define_one_arm_cp_reg(cpu, &rvbar);
3223     }
3224     if (arm_feature(env, ARM_FEATURE_MPU)) {
3225         /* These are the MPU registers prior to PMSAv6. Any new
3226          * PMSA core later than the ARM946 will require that we
3227          * implement the PMSAv6 or PMSAv7 registers, which are
3228          * completely different.
3229          */
3230         assert(!arm_feature(env, ARM_FEATURE_V6));
3231         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
3232     } else {
3233         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
3234     }
3235     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
3236         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
3237     }
3238     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
3239         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
3240     }
3241     if (arm_feature(env, ARM_FEATURE_VAPA)) {
3242         define_arm_cp_regs(cpu, vapa_cp_reginfo);
3243     }
3244     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
3245         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
3246     }
3247     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
3248         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
3249     }
3250     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
3251         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
3252     }
3253     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
3254         define_arm_cp_regs(cpu, omap_cp_reginfo);
3255     }
3256     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
3257         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
3258     }
3259     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3260         define_arm_cp_regs(cpu, xscale_cp_reginfo);
3261     }
3262     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
3263         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
3264     }
3265     if (arm_feature(env, ARM_FEATURE_LPAE)) {
3266         define_arm_cp_regs(cpu, lpae_cp_reginfo);
3267     }
3268     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
3269      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
3270      * be read-only (ie write causes UNDEF exception).
3271      */
3272     {
3273         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
3274             /* Pre-v8 MIDR space.
3275              * Note that the MIDR isn't a simple constant register because
3276              * of the TI925 behaviour where writes to another register can
3277              * cause the MIDR value to change.
3278              *
3279              * Unimplemented registers in the c15 0 0 0 space default to
3280              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
3281              * and friends override accordingly.
3282              */
3283             { .name = "MIDR",
3284               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
3285               .access = PL1_R, .resetvalue = cpu->midr,
3286               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
3287               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
3288               .type = ARM_CP_OVERRIDE },
3289             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
3290             { .name = "DUMMY",
3291               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
3292               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3293             { .name = "DUMMY",
3294               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
3295               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3296             { .name = "DUMMY",
3297               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
3298               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3299             { .name = "DUMMY",
3300               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
3301               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3302             { .name = "DUMMY",
3303               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
3304               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3305             REGINFO_SENTINEL
3306         };
3307         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
3308             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
3309              * variable-MIDR TI925 behaviour. Instead we have a single
3310              * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
3311              */
3312             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
3313               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
3314               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
3315             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
3316               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
3317               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
3318             REGINFO_SENTINEL
3319         };
3320         ARMCPRegInfo id_cp_reginfo[] = {
3321             /* These are common to v8 and pre-v8 */
3322             { .name = "CTR",
3323               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
3324               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3325             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
3326               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
3327               .access = PL0_R, .accessfn = ctr_el0_access,
3328               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3329             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
3330             { .name = "TCMTR",
3331               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
3332               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3333             { .name = "TLBTR",
3334               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
3335               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3336             REGINFO_SENTINEL
3337         };
3338         ARMCPRegInfo crn0_wi_reginfo = {
3339             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
3340             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
3341             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
3342         };
3343         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
3344             arm_feature(env, ARM_FEATURE_STRONGARM)) {
3345             ARMCPRegInfo *r;
3346             /* Register the blanket "writes ignored" value first to cover the
3347              * whole space. Then update the specific ID registers to allow write
3348              * access, so that they ignore writes rather than causing them to
3349              * UNDEF.
3350              */
3351             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
3352             for (r = id_pre_v8_midr_cp_reginfo;
3353                  r->type != ARM_CP_SENTINEL; r++) {
3354                 r->access = PL1_RW;
3355             }
3356             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
3357                 r->access = PL1_RW;
3358             }
3359         }
3360         if (arm_feature(env, ARM_FEATURE_V8)) {
3361             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
3362         } else {
3363             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
3364         }
3365         define_arm_cp_regs(cpu, id_cp_reginfo);
3366     }
3367
3368     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
3369         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
3370     }
3371
3372     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
3373         ARMCPRegInfo auxcr = {
3374             .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
3375             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
3376             .access = PL1_RW, .type = ARM_CP_CONST,
3377             .resetvalue = cpu->reset_auxcr
3378         };
3379         define_one_arm_cp_reg(cpu, &auxcr);
3380     }
3381
3382     if (arm_feature(env, ARM_FEATURE_CBAR)) {
3383         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3384             /* 32 bit view is [31:18] 0...0 [43:32]. */
3385             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
3386                 | extract64(cpu->reset_cbar, 32, 12);
3387             ARMCPRegInfo cbar_reginfo[] = {
3388                 { .name = "CBAR",
3389                   .type = ARM_CP_CONST,
3390                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3391                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
3392                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
3393                   .type = ARM_CP_CONST,
3394                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
3395                   .access = PL1_R, .resetvalue = cbar32 },
3396                 REGINFO_SENTINEL
3397             };
3398             /* We don't implement a r/w 64 bit CBAR currently */
3399             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
3400             define_arm_cp_regs(cpu, cbar_reginfo);
3401         } else {
3402             ARMCPRegInfo cbar = {
3403                 .name = "CBAR",
3404                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3405                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
3406                 .fieldoffset = offsetof(CPUARMState,
3407                                         cp15.c15_config_base_address)
3408             };
3409             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
3410                 cbar.access = PL1_R;
3411                 cbar.fieldoffset = 0;
3412                 cbar.type = ARM_CP_CONST;
3413             }
3414             define_one_arm_cp_reg(cpu, &cbar);
3415         }
3416     }
3417
3418     /* Generic registers whose values depend on the implementation */
3419     {
3420         ARMCPRegInfo sctlr = {
3421             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
3422             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3423             .access = PL1_RW,
3424             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
3425                                    offsetof(CPUARMState, cp15.sctlr_ns) },
3426             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
3427             .raw_writefn = raw_write,
3428         };
3429         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3430             /* Normally we would always end the TB on an SCTLR write, but Linux
3431              * arch/arm/mach-pxa/sleep.S expects two instructions following
3432              * an MMU enable to execute from cache.  Imitate this behaviour.
3433              */
3434             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
3435         }
3436         define_one_arm_cp_reg(cpu, &sctlr);
3437     }
3438 }
3439
3440 ARMCPU *cpu_arm_init(const char *cpu_model)
3441 {
3442     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
3443 }
3444
3445 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
3446 {
3447     CPUState *cs = CPU(cpu);
3448     CPUARMState *env = &cpu->env;
3449
3450     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3451         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
3452                                  aarch64_fpu_gdb_set_reg,
3453                                  34, "aarch64-fpu.xml", 0);
3454     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
3455         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3456                                  51, "arm-neon.xml", 0);
3457     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
3458         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3459                                  35, "arm-vfp3.xml", 0);
3460     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
3461         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3462                                  19, "arm-vfp.xml", 0);
3463     }
3464 }
3465
3466 /* Sort alphabetically by type name, except for "any". */
3467 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
3468 {
3469     ObjectClass *class_a = (ObjectClass *)a;
3470     ObjectClass *class_b = (ObjectClass *)b;
3471     const char *name_a, *name_b;
3472
3473     name_a = object_class_get_name(class_a);
3474     name_b = object_class_get_name(class_b);
3475     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
3476         return 1;
3477     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
3478         return -1;
3479     } else {
3480         return strcmp(name_a, name_b);
3481     }
3482 }
3483
3484 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
3485 {
3486     ObjectClass *oc = data;
3487     CPUListState *s = user_data;
3488     const char *typename;
3489     char *name;
3490
3491     typename = object_class_get_name(oc);
3492     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
3493     (*s->cpu_fprintf)(s->file, "  %s\n",
3494                       name);
3495     g_free(name);
3496 }
3497
3498 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3499 {
3500     CPUListState s = {
3501         .file = f,
3502         .cpu_fprintf = cpu_fprintf,
3503     };
3504     GSList *list;
3505
3506     list = object_class_get_list(TYPE_ARM_CPU, false);
3507     list = g_slist_sort(list, arm_cpu_list_compare);
3508     (*cpu_fprintf)(f, "Available CPUs:\n");
3509     g_slist_foreach(list, arm_cpu_list_entry, &s);
3510     g_slist_free(list);
3511 #ifdef CONFIG_KVM
3512     /* The 'host' CPU type is dynamically registered only if KVM is
3513      * enabled, so we have to special-case it here:
3514      */
3515     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
3516 #endif
3517 }
3518
3519 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
3520 {
3521     ObjectClass *oc = data;
3522     CpuDefinitionInfoList **cpu_list = user_data;
3523     CpuDefinitionInfoList *entry;
3524     CpuDefinitionInfo *info;
3525     const char *typename;
3526
3527     typename = object_class_get_name(oc);
3528     info = g_malloc0(sizeof(*info));
3529     info->name = g_strndup(typename,
3530                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
3531
3532     entry = g_malloc0(sizeof(*entry));
3533     entry->value = info;
3534     entry->next = *cpu_list;
3535     *cpu_list = entry;
3536 }
3537
3538 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
3539 {
3540     CpuDefinitionInfoList *cpu_list = NULL;
3541     GSList *list;
3542
3543     list = object_class_get_list(TYPE_ARM_CPU, false);
3544     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
3545     g_slist_free(list);
3546
3547     return cpu_list;
3548 }
3549
3550 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
3551                                    void *opaque, int state, int secstate,
3552                                    int crm, int opc1, int opc2)
3553 {
3554     /* Private utility function for define_one_arm_cp_reg_with_opaque():
3555      * add a single reginfo struct to the hash table.
3556      */
3557     uint32_t *key = g_new(uint32_t, 1);
3558     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
3559     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
3560     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
3561
3562     /* Reset the secure state to the specific incoming state.  This is
3563      * necessary as the register may have been defined with both states.
3564      */
3565     r2->secure = secstate;
3566
3567     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
3568         /* Register is banked (using both entries in array).
3569          * Overwriting fieldoffset as the array is only used to define
3570          * banked registers but later only fieldoffset is used.
3571          */
3572         r2->fieldoffset = r->bank_fieldoffsets[ns];
3573     }
3574
3575     if (state == ARM_CP_STATE_AA32) {
3576         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
3577             /* If the register is banked then we don't need to migrate or
3578              * reset the 32-bit instance in certain cases:
3579              *
3580              * 1) If the register has both 32-bit and 64-bit instances then we
3581              *    can count on the 64-bit instance taking care of the
3582              *    non-secure bank.
3583              * 2) If ARMv8 is enabled then we can count on a 64-bit version
3584              *    taking care of the secure bank.  This requires that separate
3585              *    32 and 64-bit definitions are provided.
3586              */
3587             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
3588                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
3589                 r2->type |= ARM_CP_ALIAS;
3590                 r2->resetfn = arm_cp_reset_ignore;
3591             }
3592         } else if ((secstate != r->secure) && !ns) {
3593             /* The register is not banked so we only want to allow migration of
3594              * the non-secure instance.
3595              */
3596             r2->type |= ARM_CP_ALIAS;
3597             r2->resetfn = arm_cp_reset_ignore;
3598         }
3599
3600         if (r->state == ARM_CP_STATE_BOTH) {
3601             /* We assume it is a cp15 register if the .cp field is left unset.
3602              */
3603             if (r2->cp == 0) {
3604                 r2->cp = 15;
3605             }
3606
3607 #ifdef HOST_WORDS_BIGENDIAN
3608             if (r2->fieldoffset) {
3609                 r2->fieldoffset += sizeof(uint32_t);
3610             }
3611 #endif
3612         }
3613     }
3614     if (state == ARM_CP_STATE_AA64) {
3615         /* To allow abbreviation of ARMCPRegInfo
3616          * definitions, we treat cp == 0 as equivalent to
3617          * the value for "standard guest-visible sysreg".
3618          * STATE_BOTH definitions are also always "standard
3619          * sysreg" in their AArch64 view (the .cp value may
3620          * be non-zero for the benefit of the AArch32 view).
3621          */
3622         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
3623             r2->cp = CP_REG_ARM64_SYSREG_CP;
3624         }
3625         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
3626                                   r2->opc0, opc1, opc2);
3627     } else {
3628         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
3629     }
3630     if (opaque) {
3631         r2->opaque = opaque;
3632     }
3633     /* reginfo passed to helpers is correct for the actual access,
3634      * and is never ARM_CP_STATE_BOTH:
3635      */
3636     r2->state = state;
3637     /* Make sure reginfo passed to helpers for wildcarded regs
3638      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
3639      */
3640     r2->crm = crm;
3641     r2->opc1 = opc1;
3642     r2->opc2 = opc2;
3643     /* By convention, for wildcarded registers only the first
3644      * entry is used for migration; the others are marked as
3645      * ALIAS so we don't try to transfer the register
3646      * multiple times. Special registers (ie NOP/WFI) are
3647      * never migratable and not even raw-accessible.
3648      */
3649     if ((r->type & ARM_CP_SPECIAL)) {
3650         r2->type |= ARM_CP_NO_RAW;
3651     }
3652     if (((r->crm == CP_ANY) && crm != 0) ||
3653         ((r->opc1 == CP_ANY) && opc1 != 0) ||
3654         ((r->opc2 == CP_ANY) && opc2 != 0)) {
3655         r2->type |= ARM_CP_ALIAS;
3656     }
3657
3658     /* Check that raw accesses are either forbidden or handled. Note that
3659      * we can't assert this earlier because the setup of fieldoffset for
3660      * banked registers has to be done first.
3661      */
3662     if (!(r2->type & ARM_CP_NO_RAW)) {
3663         assert(!raw_accessors_invalid(r2));
3664     }
3665
3666     /* Overriding of an existing definition must be explicitly
3667      * requested.
3668      */
3669     if (!(r->type & ARM_CP_OVERRIDE)) {
3670         ARMCPRegInfo *oldreg;
3671         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
3672         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
3673             fprintf(stderr, "Register redefined: cp=%d %d bit "
3674                     "crn=%d crm=%d opc1=%d opc2=%d, "
3675                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
3676                     r2->crn, r2->crm, r2->opc1, r2->opc2,
3677                     oldreg->name, r2->name);
3678             g_assert_not_reached();
3679         }
3680     }
3681     g_hash_table_insert(cpu->cp_regs, key, r2);
3682 }
3683
3684
3685 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
3686                                        const ARMCPRegInfo *r, void *opaque)
3687 {
3688     /* Define implementations of coprocessor registers.
3689      * We store these in a hashtable because typically
3690      * there are less than 150 registers in a space which
3691      * is 16*16*16*8*8 = 262144 in size.
3692      * Wildcarding is supported for the crm, opc1 and opc2 fields.
3693      * If a register is defined twice then the second definition is
3694      * used, so this can be used to define some generic registers and
3695      * then override them with implementation specific variations.
3696      * At least one of the original and the second definition should
3697      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
3698      * against accidental use.
3699      *
3700      * The state field defines whether the register is to be
3701      * visible in the AArch32 or AArch64 execution state. If the
3702      * state is set to ARM_CP_STATE_BOTH then we synthesise a
3703      * reginfo structure for the AArch32 view, which sees the lower
3704      * 32 bits of the 64 bit register.
3705      *
3706      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
3707      * be wildcarded. AArch64 registers are always considered to be 64
3708      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
3709      * the register, if any.
3710      */
3711     int crm, opc1, opc2, state;
3712     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
3713     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
3714     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
3715     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
3716     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
3717     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
3718     /* 64 bit registers have only CRm and Opc1 fields */
3719     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
3720     /* op0 only exists in the AArch64 encodings */
3721     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
3722     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
3723     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
3724     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
3725      * encodes a minimum access level for the register. We roll this
3726      * runtime check into our general permission check code, so check
3727      * here that the reginfo's specified permissions are strict enough
3728      * to encompass the generic architectural permission check.
3729      */
3730     if (r->state != ARM_CP_STATE_AA32) {
3731         int mask = 0;
3732         switch (r->opc1) {
3733         case 0: case 1: case 2:
3734             /* min_EL EL1 */
3735             mask = PL1_RW;
3736             break;
3737         case 3:
3738             /* min_EL EL0 */
3739             mask = PL0_RW;
3740             break;
3741         case 4:
3742             /* min_EL EL2 */
3743             mask = PL2_RW;
3744             break;
3745         case 5:
3746             /* unallocated encoding, so not possible */
3747             assert(false);
3748             break;
3749         case 6:
3750             /* min_EL EL3 */
3751             mask = PL3_RW;
3752             break;
3753         case 7:
3754             /* min_EL EL1, secure mode only (we don't check the latter) */
3755             mask = PL1_RW;
3756             break;
3757         default:
3758             /* broken reginfo with out-of-range opc1 */
3759             assert(false);
3760             break;
3761         }
3762         /* assert our permissions are not too lax (stricter is fine) */
3763         assert((r->access & ~mask) == 0);
3764     }
3765
3766     /* Check that the register definition has enough info to handle
3767      * reads and writes if they are permitted.
3768      */
3769     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
3770         if (r->access & PL3_R) {
3771             assert((r->fieldoffset ||
3772                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
3773                    r->readfn);
3774         }
3775         if (r->access & PL3_W) {
3776             assert((r->fieldoffset ||
3777                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
3778                    r->writefn);
3779         }
3780     }
3781     /* Bad type field probably means missing sentinel at end of reg list */
3782     assert(cptype_valid(r->type));
3783     for (crm = crmmin; crm <= crmmax; crm++) {
3784         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
3785             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
3786                 for (state = ARM_CP_STATE_AA32;
3787                      state <= ARM_CP_STATE_AA64; state++) {
3788                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
3789                         continue;
3790                     }
3791                     if (state == ARM_CP_STATE_AA32) {
3792                         /* Under AArch32 CP registers can be common
3793                          * (same for secure and non-secure world) or banked.
3794                          */
3795                         switch (r->secure) {
3796                         case ARM_CP_SECSTATE_S:
3797                         case ARM_CP_SECSTATE_NS:
3798                             add_cpreg_to_hashtable(cpu, r, opaque, state,
3799                                                    r->secure, crm, opc1, opc2);
3800                             break;
3801                         default:
3802                             add_cpreg_to_hashtable(cpu, r, opaque, state,
3803                                                    ARM_CP_SECSTATE_S,
3804                                                    crm, opc1, opc2);
3805                             add_cpreg_to_hashtable(cpu, r, opaque, state,
3806                                                    ARM_CP_SECSTATE_NS,
3807                                                    crm, opc1, opc2);
3808                             break;
3809                         }
3810                     } else {
3811                         /* AArch64 registers get mapped to non-secure instance
3812                          * of AArch32 */
3813                         add_cpreg_to_hashtable(cpu, r, opaque, state,
3814                                                ARM_CP_SECSTATE_NS,
3815                                                crm, opc1, opc2);
3816                     }
3817                 }
3818             }
3819         }
3820     }
3821 }
3822
3823 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
3824                                     const ARMCPRegInfo *regs, void *opaque)
3825 {
3826     /* Define a whole list of registers */
3827     const ARMCPRegInfo *r;
3828     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
3829         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
3830     }
3831 }
3832
3833 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
3834 {
3835     return g_hash_table_lookup(cpregs, &encoded_cp);
3836 }
3837
3838 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
3839                          uint64_t value)
3840 {
3841     /* Helper coprocessor write function for write-ignore registers */
3842 }
3843
3844 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
3845 {
3846     /* Helper coprocessor write function for read-as-zero registers */
3847     return 0;
3848 }
3849
3850 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
3851 {
3852     /* Helper coprocessor reset function for do-nothing-on-reset registers */
3853 }
3854
3855 static int bad_mode_switch(CPUARMState *env, int mode)
3856 {
3857     /* Return true if it is not valid for us to switch to
3858      * this CPU mode (ie all the UNPREDICTABLE cases in
3859      * the ARM ARM CPSRWriteByInstr pseudocode).
3860      */
3861     switch (mode) {
3862     case ARM_CPU_MODE_USR:
3863     case ARM_CPU_MODE_SYS:
3864     case ARM_CPU_MODE_SVC:
3865     case ARM_CPU_MODE_ABT:
3866     case ARM_CPU_MODE_UND:
3867     case ARM_CPU_MODE_IRQ:
3868     case ARM_CPU_MODE_FIQ:
3869         return 0;
3870     case ARM_CPU_MODE_MON:
3871         return !arm_is_secure(env);
3872     default:
3873         return 1;
3874     }
3875 }
3876
3877 uint32_t cpsr_read(CPUARMState *env)
3878 {
3879     int ZF;
3880     ZF = (env->ZF == 0);
3881     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
3882         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
3883         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
3884         | ((env->condexec_bits & 0xfc) << 8)
3885         | (env->GE << 16) | (env->daif & CPSR_AIF);
3886 }
3887
3888 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
3889 {
3890     uint32_t changed_daif;
3891
3892     if (mask & CPSR_NZCV) {
3893         env->ZF = (~val) & CPSR_Z;
3894         env->NF = val;
3895         env->CF = (val >> 29) & 1;
3896         env->VF = (val << 3) & 0x80000000;
3897     }
3898     if (mask & CPSR_Q)
3899         env->QF = ((val & CPSR_Q) != 0);
3900     if (mask & CPSR_T)
3901         env->thumb = ((val & CPSR_T) != 0);
3902     if (mask & CPSR_IT_0_1) {
3903         env->condexec_bits &= ~3;
3904         env->condexec_bits |= (val >> 25) & 3;
3905     }
3906     if (mask & CPSR_IT_2_7) {
3907         env->condexec_bits &= 3;
3908         env->condexec_bits |= (val >> 8) & 0xfc;
3909     }
3910     if (mask & CPSR_GE) {
3911         env->GE = (val >> 16) & 0xf;
3912     }
3913
3914     /* In a V7 implementation that includes the security extensions but does
3915      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
3916      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
3917      * bits respectively.
3918      *
3919      * In a V8 implementation, it is permitted for privileged software to
3920      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
3921      */
3922     if (!arm_feature(env, ARM_FEATURE_V8) &&
3923         arm_feature(env, ARM_FEATURE_EL3) &&
3924         !arm_feature(env, ARM_FEATURE_EL2) &&
3925         !arm_is_secure(env)) {
3926
3927         changed_daif = (env->daif ^ val) & mask;
3928
3929         if (changed_daif & CPSR_A) {
3930             /* Check to see if we are allowed to change the masking of async
3931              * abort exceptions from a non-secure state.
3932              */
3933             if (!(env->cp15.scr_el3 & SCR_AW)) {
3934                 qemu_log_mask(LOG_GUEST_ERROR,
3935                               "Ignoring attempt to switch CPSR_A flag from "
3936                               "non-secure world with SCR.AW bit clear\n");
3937                 mask &= ~CPSR_A;
3938             }
3939         }
3940
3941         if (changed_daif & CPSR_F) {
3942             /* Check to see if we are allowed to change the masking of FIQ
3943              * exceptions from a non-secure state.
3944              */
3945             if (!(env->cp15.scr_el3 & SCR_FW)) {
3946                 qemu_log_mask(LOG_GUEST_ERROR,
3947                               "Ignoring attempt to switch CPSR_F flag from "
3948                               "non-secure world with SCR.FW bit clear\n");
3949                 mask &= ~CPSR_F;
3950             }
3951
3952             /* Check whether non-maskable FIQ (NMFI) support is enabled.
3953              * If this bit is set software is not allowed to mask
3954              * FIQs, but is allowed to set CPSR_F to 0.
3955              */
3956             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
3957                 (val & CPSR_F)) {
3958                 qemu_log_mask(LOG_GUEST_ERROR,
3959                               "Ignoring attempt to enable CPSR_F flag "
3960                               "(non-maskable FIQ [NMFI] support enabled)\n");
3961                 mask &= ~CPSR_F;
3962             }
3963         }
3964     }
3965
3966     env->daif &= ~(CPSR_AIF & mask);
3967     env->daif |= val & CPSR_AIF & mask;
3968
3969     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
3970         if (bad_mode_switch(env, val & CPSR_M)) {
3971             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3972              * We choose to ignore the attempt and leave the CPSR M field
3973              * untouched.
3974              */
3975             mask &= ~CPSR_M;
3976         } else {
3977             switch_mode(env, val & CPSR_M);
3978         }
3979     }
3980     mask &= ~CACHED_CPSR_BITS;
3981     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
3982 }
3983
3984 /* Sign/zero extend */
3985 uint32_t HELPER(sxtb16)(uint32_t x)
3986 {
3987     uint32_t res;
3988     res = (uint16_t)(int8_t)x;
3989     res |= (uint32_t)(int8_t)(x >> 16) << 16;
3990     return res;
3991 }
3992
3993 uint32_t HELPER(uxtb16)(uint32_t x)
3994 {
3995     uint32_t res;
3996     res = (uint16_t)(uint8_t)x;
3997     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
3998     return res;
3999 }
4000
4001 uint32_t HELPER(clz)(uint32_t x)
4002 {
4003     return clz32(x);
4004 }
4005
4006 int32_t HELPER(sdiv)(int32_t num, int32_t den)
4007 {
4008     if (den == 0)
4009       return 0;
4010     if (num == INT_MIN && den == -1)
4011       return INT_MIN;
4012     return num / den;
4013 }
4014
4015 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
4016 {
4017     if (den == 0)
4018       return 0;
4019     return num / den;
4020 }
4021
4022 uint32_t HELPER(rbit)(uint32_t x)
4023 {
4024     x =  ((x & 0xff000000) >> 24)
4025        | ((x & 0x00ff0000) >> 8)
4026        | ((x & 0x0000ff00) << 8)
4027        | ((x & 0x000000ff) << 24);
4028     x =  ((x & 0xf0f0f0f0) >> 4)
4029        | ((x & 0x0f0f0f0f) << 4);
4030     x =  ((x & 0x88888888) >> 3)
4031        | ((x & 0x44444444) >> 1)
4032        | ((x & 0x22222222) << 1)
4033        | ((x & 0x11111111) << 3);
4034     return x;
4035 }
4036
4037 #if defined(CONFIG_USER_ONLY)
4038
4039 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
4040                              int mmu_idx)
4041 {
4042     ARMCPU *cpu = ARM_CPU(cs);
4043     CPUARMState *env = &cpu->env;
4044
4045     env->exception.vaddress = address;
4046     if (rw == 2) {
4047         cs->exception_index = EXCP_PREFETCH_ABORT;
4048     } else {
4049         cs->exception_index = EXCP_DATA_ABORT;
4050     }
4051     return 1;
4052 }
4053
4054 /* These should probably raise undefined insn exceptions.  */
4055 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4056 {
4057     ARMCPU *cpu = arm_env_get_cpu(env);
4058
4059     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
4060 }
4061
4062 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4063 {
4064     ARMCPU *cpu = arm_env_get_cpu(env);
4065
4066     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
4067     return 0;
4068 }
4069
4070 void switch_mode(CPUARMState *env, int mode)
4071 {
4072     ARMCPU *cpu = arm_env_get_cpu(env);
4073
4074     if (mode != ARM_CPU_MODE_USR) {
4075         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
4076     }
4077 }
4078
4079 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4080 {
4081     ARMCPU *cpu = arm_env_get_cpu(env);
4082
4083     cpu_abort(CPU(cpu), "banked r13 write\n");
4084 }
4085
4086 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4087 {
4088     ARMCPU *cpu = arm_env_get_cpu(env);
4089
4090     cpu_abort(CPU(cpu), "banked r13 read\n");
4091     return 0;
4092 }
4093
4094 unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
4095 {
4096     return 1;
4097 }
4098
4099 void aarch64_sync_64_to_32(CPUARMState *env)
4100 {
4101     g_assert_not_reached();
4102 }
4103
4104 #else
4105
4106 /* Map CPU modes onto saved register banks.  */
4107 int bank_number(int mode)
4108 {
4109     switch (mode) {
4110     case ARM_CPU_MODE_USR:
4111     case ARM_CPU_MODE_SYS:
4112         return 0;
4113     case ARM_CPU_MODE_SVC:
4114         return 1;
4115     case ARM_CPU_MODE_ABT:
4116         return 2;
4117     case ARM_CPU_MODE_UND:
4118         return 3;
4119     case ARM_CPU_MODE_IRQ:
4120         return 4;
4121     case ARM_CPU_MODE_FIQ:
4122         return 5;
4123     case ARM_CPU_MODE_HYP:
4124         return 6;
4125     case ARM_CPU_MODE_MON:
4126         return 7;
4127     }
4128     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
4129 }
4130
4131 void switch_mode(CPUARMState *env, int mode)
4132 {
4133     int old_mode;
4134     int i;
4135
4136     old_mode = env->uncached_cpsr & CPSR_M;
4137     if (mode == old_mode)
4138         return;
4139
4140     if (old_mode == ARM_CPU_MODE_FIQ) {
4141         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
4142         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
4143     } else if (mode == ARM_CPU_MODE_FIQ) {
4144         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
4145         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
4146     }
4147
4148     i = bank_number(old_mode);
4149     env->banked_r13[i] = env->regs[13];
4150     env->banked_r14[i] = env->regs[14];
4151     env->banked_spsr[i] = env->spsr;
4152
4153     i = bank_number(mode);
4154     env->regs[13] = env->banked_r13[i];
4155     env->regs[14] = env->banked_r14[i];
4156     env->spsr = env->banked_spsr[i];
4157 }
4158
4159 /* Physical Interrupt Target EL Lookup Table
4160  *
4161  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
4162  *
4163  * The below multi-dimensional table is used for looking up the target
4164  * exception level given numerous condition criteria.  Specifically, the
4165  * target EL is based on SCR and HCR routing controls as well as the
4166  * currently executing EL and secure state.
4167  *
4168  *    Dimensions:
4169  *    target_el_table[2][2][2][2][2][4]
4170  *                    |  |  |  |  |  +--- Current EL
4171  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
4172  *                    |  |  |  +--------- HCR mask override
4173  *                    |  |  +------------ SCR exec state control
4174  *                    |  +--------------- SCR mask override
4175  *                    +------------------ 32-bit(0)/64-bit(1) EL3
4176  *
4177  *    The table values are as such:
4178  *    0-3 = EL0-EL3
4179  *     -1 = Cannot occur
4180  *
4181  * The ARM ARM target EL table includes entries indicating that an "exception
4182  * is not taken".  The two cases where this is applicable are:
4183  *    1) An exception is taken from EL3 but the SCR does not have the exception
4184  *    routed to EL3.
4185  *    2) An exception is taken from EL2 but the HCR does not have the exception
4186  *    routed to EL2.
4187  * In these two cases, the below table contain a target of EL1.  This value is
4188  * returned as it is expected that the consumer of the table data will check
4189  * for "target EL >= current EL" to ensure the exception is not taken.
4190  *
4191  *            SCR     HCR
4192  *         64  EA     AMO                 From
4193  *        BIT IRQ     IMO      Non-secure         Secure
4194  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
4195  */
4196 const int8_t target_el_table[2][2][2][2][2][4] = {
4197     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
4198        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
4199       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
4200        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
4201      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
4202        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
4203       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
4204        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
4205     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
4206        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
4207       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
4208        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
4209      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
4210        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
4211       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
4212        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
4213 };
4214
4215 /*
4216  * Determine the target EL for physical exceptions
4217  */
4218 static inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
4219                                         uint32_t cur_el, bool secure)
4220 {
4221     CPUARMState *env = cs->env_ptr;
4222     int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
4223     int scr;
4224     int hcr;
4225     int target_el;
4226     int is64 = arm_el_is_aa64(env, 3);
4227
4228     switch (excp_idx) {
4229     case EXCP_IRQ:
4230         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
4231         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
4232         break;
4233     case EXCP_FIQ:
4234         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
4235         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
4236         break;
4237     default:
4238         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
4239         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
4240         break;
4241     };
4242
4243     /* If HCR.TGE is set then HCR is treated as being 1 */
4244     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
4245
4246     /* Perform a table-lookup for the target EL given the current state */
4247     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
4248
4249     assert(target_el > 0);
4250
4251     return target_el;
4252 }
4253
4254 /*
4255  * Determine the target EL for a given exception type.
4256  */
4257 unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
4258 {
4259     ARMCPU *cpu = ARM_CPU(cs);
4260     CPUARMState *env = &cpu->env;
4261     unsigned int cur_el = arm_current_el(env);
4262     unsigned int target_el;
4263     bool secure = arm_is_secure(env);
4264
4265     switch (excp_idx) {
4266     case EXCP_HVC:
4267     case EXCP_HYP_TRAP:
4268         target_el = 2;
4269         break;
4270     case EXCP_SMC:
4271         target_el = 3;
4272         break;
4273     case EXCP_FIQ:
4274     case EXCP_IRQ:
4275         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
4276         break;
4277     case EXCP_VIRQ:
4278     case EXCP_VFIQ:
4279         target_el = 1;
4280         break;
4281     default:
4282         target_el = MAX(cur_el, 1);
4283         break;
4284     }
4285     return target_el;
4286 }
4287
4288 static void v7m_push(CPUARMState *env, uint32_t val)
4289 {
4290     CPUState *cs = CPU(arm_env_get_cpu(env));
4291
4292     env->regs[13] -= 4;
4293     stl_phys(cs->as, env->regs[13], val);
4294 }
4295
4296 static uint32_t v7m_pop(CPUARMState *env)
4297 {
4298     CPUState *cs = CPU(arm_env_get_cpu(env));
4299     uint32_t val;
4300
4301     val = ldl_phys(cs->as, env->regs[13]);
4302     env->regs[13] += 4;
4303     return val;
4304 }
4305
4306 /* Switch to V7M main or process stack pointer.  */
4307 static void switch_v7m_sp(CPUARMState *env, int process)
4308 {
4309     uint32_t tmp;
4310     if (env->v7m.current_sp != process) {
4311         tmp = env->v7m.other_sp;
4312         env->v7m.other_sp = env->regs[13];
4313         env->regs[13] = tmp;
4314         env->v7m.current_sp = process;
4315     }
4316 }
4317
4318 static void do_v7m_exception_exit(CPUARMState *env)
4319 {
4320     uint32_t type;
4321     uint32_t xpsr;
4322
4323     type = env->regs[15];
4324     if (env->v7m.exception != 0)
4325         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
4326
4327     /* Switch to the target stack.  */
4328     switch_v7m_sp(env, (type & 4) != 0);
4329     /* Pop registers.  */
4330     env->regs[0] = v7m_pop(env);
4331     env->regs[1] = v7m_pop(env);
4332     env->regs[2] = v7m_pop(env);
4333     env->regs[3] = v7m_pop(env);
4334     env->regs[12] = v7m_pop(env);
4335     env->regs[14] = v7m_pop(env);
4336     env->regs[15] = v7m_pop(env);
4337     xpsr = v7m_pop(env);
4338     xpsr_write(env, xpsr, 0xfffffdff);
4339     /* Undo stack alignment.  */
4340     if (xpsr & 0x200)
4341         env->regs[13] |= 4;
4342     /* ??? The exception return type specifies Thread/Handler mode.  However
4343        this is also implied by the xPSR value. Not sure what to do
4344        if there is a mismatch.  */
4345     /* ??? Likewise for mismatches between the CONTROL register and the stack
4346        pointer.  */
4347 }
4348
4349 void arm_v7m_cpu_do_interrupt(CPUState *cs)
4350 {
4351     ARMCPU *cpu = ARM_CPU(cs);
4352     CPUARMState *env = &cpu->env;
4353     uint32_t xpsr = xpsr_read(env);
4354     uint32_t lr;
4355     uint32_t addr;
4356
4357     arm_log_exception(cs->exception_index);
4358
4359     lr = 0xfffffff1;
4360     if (env->v7m.current_sp)
4361         lr |= 4;
4362     if (env->v7m.exception == 0)
4363         lr |= 8;
4364
4365     /* For exceptions we just mark as pending on the NVIC, and let that
4366        handle it.  */
4367     /* TODO: Need to escalate if the current priority is higher than the
4368        one we're raising.  */
4369     switch (cs->exception_index) {
4370     case EXCP_UDEF:
4371         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
4372         return;
4373     case EXCP_SWI:
4374         /* The PC already points to the next instruction.  */
4375         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
4376         return;
4377     case EXCP_PREFETCH_ABORT:
4378     case EXCP_DATA_ABORT:
4379         /* TODO: if we implemented the MPU registers, this is where we
4380          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
4381          */
4382         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
4383         return;
4384     case EXCP_BKPT:
4385         if (semihosting_enabled) {
4386             int nr;
4387             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
4388             if (nr == 0xab) {
4389                 env->regs[15] += 2;
4390                 env->regs[0] = do_arm_semihosting(env);
4391                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4392                 return;
4393             }
4394         }
4395         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
4396         return;
4397     case EXCP_IRQ:
4398         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
4399         break;
4400     case EXCP_EXCEPTION_EXIT:
4401         do_v7m_exception_exit(env);
4402         return;
4403     default:
4404         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
4405         return; /* Never happens.  Keep compiler happy.  */
4406     }
4407
4408     /* Align stack pointer.  */
4409     /* ??? Should only do this if Configuration Control Register
4410        STACKALIGN bit is set.  */
4411     if (env->regs[13] & 4) {
4412         env->regs[13] -= 4;
4413         xpsr |= 0x200;
4414     }
4415     /* Switch to the handler mode.  */
4416     v7m_push(env, xpsr);
4417     v7m_push(env, env->regs[15]);
4418     v7m_push(env, env->regs[14]);
4419     v7m_push(env, env->regs[12]);
4420     v7m_push(env, env->regs[3]);
4421     v7m_push(env, env->regs[2]);
4422     v7m_push(env, env->regs[1]);
4423     v7m_push(env, env->regs[0]);
4424     switch_v7m_sp(env, 0);
4425     /* Clear IT bits */
4426     env->condexec_bits = 0;
4427     env->regs[14] = lr;
4428     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
4429     env->regs[15] = addr & 0xfffffffe;
4430     env->thumb = addr & 1;
4431 }
4432
4433 /* Function used to synchronize QEMU's AArch64 register set with AArch32
4434  * register set.  This is necessary when switching between AArch32 and AArch64
4435  * execution state.
4436  */
4437 void aarch64_sync_32_to_64(CPUARMState *env)
4438 {
4439     int i;
4440     uint32_t mode = env->uncached_cpsr & CPSR_M;
4441
4442     /* We can blanket copy R[0:7] to X[0:7] */
4443     for (i = 0; i < 8; i++) {
4444         env->xregs[i] = env->regs[i];
4445     }
4446
4447     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
4448      * Otherwise, they come from the banked user regs.
4449      */
4450     if (mode == ARM_CPU_MODE_FIQ) {
4451         for (i = 8; i < 13; i++) {
4452             env->xregs[i] = env->usr_regs[i - 8];
4453         }
4454     } else {
4455         for (i = 8; i < 13; i++) {
4456             env->xregs[i] = env->regs[i];
4457         }
4458     }
4459
4460     /* Registers x13-x23 are the various mode SP and FP registers. Registers
4461      * r13 and r14 are only copied if we are in that mode, otherwise we copy
4462      * from the mode banked register.
4463      */
4464     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
4465         env->xregs[13] = env->regs[13];
4466         env->xregs[14] = env->regs[14];
4467     } else {
4468         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
4469         /* HYP is an exception in that it is copied from r14 */
4470         if (mode == ARM_CPU_MODE_HYP) {
4471             env->xregs[14] = env->regs[14];
4472         } else {
4473             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
4474         }
4475     }
4476
4477     if (mode == ARM_CPU_MODE_HYP) {
4478         env->xregs[15] = env->regs[13];
4479     } else {
4480         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
4481     }
4482
4483     if (mode == ARM_CPU_MODE_IRQ) {
4484         env->xregs[16] = env->regs[13];
4485         env->xregs[17] = env->regs[14];
4486     } else {
4487         env->xregs[16] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
4488         env->xregs[17] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
4489     }
4490
4491     if (mode == ARM_CPU_MODE_SVC) {
4492         env->xregs[18] = env->regs[13];
4493         env->xregs[19] = env->regs[14];
4494     } else {
4495         env->xregs[18] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
4496         env->xregs[19] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
4497     }
4498
4499     if (mode == ARM_CPU_MODE_ABT) {
4500         env->xregs[20] = env->regs[13];
4501         env->xregs[21] = env->regs[14];
4502     } else {
4503         env->xregs[20] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
4504         env->xregs[21] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
4505     }
4506
4507     if (mode == ARM_CPU_MODE_UND) {
4508         env->xregs[22] = env->regs[13];
4509         env->xregs[23] = env->regs[14];
4510     } else {
4511         env->xregs[22] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
4512         env->xregs[23] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
4513     }
4514
4515     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
4516      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
4517      * FIQ bank for r8-r14.
4518      */
4519     if (mode == ARM_CPU_MODE_FIQ) {
4520         for (i = 24; i < 31; i++) {
4521             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
4522         }
4523     } else {
4524         for (i = 24; i < 29; i++) {
4525             env->xregs[i] = env->fiq_regs[i - 24];
4526         }
4527         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
4528         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
4529     }
4530
4531     env->pc = env->regs[15];
4532 }
4533
4534 /* Function used to synchronize QEMU's AArch32 register set with AArch64
4535  * register set.  This is necessary when switching between AArch32 and AArch64
4536  * execution state.
4537  */
4538 void aarch64_sync_64_to_32(CPUARMState *env)
4539 {
4540     int i;
4541     uint32_t mode = env->uncached_cpsr & CPSR_M;
4542
4543     /* We can blanket copy X[0:7] to R[0:7] */
4544     for (i = 0; i < 8; i++) {
4545         env->regs[i] = env->xregs[i];
4546     }
4547
4548     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
4549      * Otherwise, we copy x8-x12 into the banked user regs.
4550      */
4551     if (mode == ARM_CPU_MODE_FIQ) {
4552         for (i = 8; i < 13; i++) {
4553             env->usr_regs[i - 8] = env->xregs[i];
4554         }
4555     } else {
4556         for (i = 8; i < 13; i++) {
4557             env->regs[i] = env->xregs[i];
4558         }
4559     }
4560
4561     /* Registers r13 & r14 depend on the current mode.
4562      * If we are in a given mode, we copy the corresponding x registers to r13
4563      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
4564      * for the mode.
4565      */
4566     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
4567         env->regs[13] = env->xregs[13];
4568         env->regs[14] = env->xregs[14];
4569     } else {
4570         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
4571
4572         /* HYP is an exception in that it does not have its own banked r14 but
4573          * shares the USR r14
4574          */
4575         if (mode == ARM_CPU_MODE_HYP) {
4576             env->regs[14] = env->xregs[14];
4577         } else {
4578             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
4579         }
4580     }
4581
4582     if (mode == ARM_CPU_MODE_HYP) {
4583         env->regs[13] = env->xregs[15];
4584     } else {
4585         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
4586     }
4587
4588     if (mode == ARM_CPU_MODE_IRQ) {
4589         env->regs[13] = env->xregs[16];
4590         env->regs[14] = env->xregs[17];
4591     } else {
4592         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
4593         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
4594     }
4595
4596     if (mode == ARM_CPU_MODE_SVC) {
4597         env->regs[13] = env->xregs[18];
4598         env->regs[14] = env->xregs[19];
4599     } else {
4600         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
4601         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
4602     }
4603
4604     if (mode == ARM_CPU_MODE_ABT) {
4605         env->regs[13] = env->xregs[20];
4606         env->regs[14] = env->xregs[21];
4607     } else {
4608         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
4609         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
4610     }
4611
4612     if (mode == ARM_CPU_MODE_UND) {
4613         env->regs[13] = env->xregs[22];
4614         env->regs[14] = env->xregs[23];
4615     } else {
4616         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
4617         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
4618     }
4619
4620     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
4621      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
4622      * FIQ bank for r8-r14.
4623      */
4624     if (mode == ARM_CPU_MODE_FIQ) {
4625         for (i = 24; i < 31; i++) {
4626             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
4627         }
4628     } else {
4629         for (i = 24; i < 29; i++) {
4630             env->fiq_regs[i - 24] = env->xregs[i];
4631         }
4632         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
4633         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
4634     }
4635
4636     env->regs[15] = env->pc;
4637 }
4638
4639 /* Handle a CPU exception.  */
4640 void arm_cpu_do_interrupt(CPUState *cs)
4641 {
4642     ARMCPU *cpu = ARM_CPU(cs);
4643     CPUARMState *env = &cpu->env;
4644     uint32_t addr;
4645     uint32_t mask;
4646     int new_mode;
4647     uint32_t offset;
4648     uint32_t moe;
4649
4650     assert(!IS_M(env));
4651
4652     arm_log_exception(cs->exception_index);
4653
4654     if (arm_is_psci_call(cpu, cs->exception_index)) {
4655         arm_handle_psci_call(cpu);
4656         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
4657         return;
4658     }
4659
4660     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
4661     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
4662     case EC_BREAKPOINT:
4663     case EC_BREAKPOINT_SAME_EL:
4664         moe = 1;
4665         break;
4666     case EC_WATCHPOINT:
4667     case EC_WATCHPOINT_SAME_EL:
4668         moe = 10;
4669         break;
4670     case EC_AA32_BKPT:
4671         moe = 3;
4672         break;
4673     case EC_VECTORCATCH:
4674         moe = 5;
4675         break;
4676     default:
4677         moe = 0;
4678         break;
4679     }
4680
4681     if (moe) {
4682         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
4683     }
4684
4685     /* TODO: Vectored interrupt controller.  */
4686     switch (cs->exception_index) {
4687     case EXCP_UDEF:
4688         new_mode = ARM_CPU_MODE_UND;
4689         addr = 0x04;
4690         mask = CPSR_I;
4691         if (env->thumb)
4692             offset = 2;
4693         else
4694             offset = 4;
4695         break;
4696     case EXCP_SWI:
4697         if (semihosting_enabled) {
4698             /* Check for semihosting interrupt.  */
4699             if (env->thumb) {
4700                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
4701                     & 0xff;
4702             } else {
4703                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
4704                     & 0xffffff;
4705             }
4706             /* Only intercept calls from privileged modes, to provide some
4707                semblance of security.  */
4708             if (((mask == 0x123456 && !env->thumb)
4709                     || (mask == 0xab && env->thumb))
4710                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4711                 env->regs[0] = do_arm_semihosting(env);
4712                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4713                 return;
4714             }
4715         }
4716         new_mode = ARM_CPU_MODE_SVC;
4717         addr = 0x08;
4718         mask = CPSR_I;
4719         /* The PC already points to the next instruction.  */
4720         offset = 0;
4721         break;
4722     case EXCP_BKPT:
4723         /* See if this is a semihosting syscall.  */
4724         if (env->thumb && semihosting_enabled) {
4725             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
4726             if (mask == 0xab
4727                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4728                 env->regs[15] += 2;
4729                 env->regs[0] = do_arm_semihosting(env);
4730                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4731                 return;
4732             }
4733         }
4734         env->exception.fsr = 2;
4735         /* Fall through to prefetch abort.  */
4736     case EXCP_PREFETCH_ABORT:
4737         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
4738         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
4739         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
4740                       env->exception.fsr, (uint32_t)env->exception.vaddress);
4741         new_mode = ARM_CPU_MODE_ABT;
4742         addr = 0x0c;
4743         mask = CPSR_A | CPSR_I;
4744         offset = 4;
4745         break;
4746     case EXCP_DATA_ABORT:
4747         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
4748         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
4749         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
4750                       env->exception.fsr,
4751                       (uint32_t)env->exception.vaddress);
4752         new_mode = ARM_CPU_MODE_ABT;
4753         addr = 0x10;
4754         mask = CPSR_A | CPSR_I;
4755         offset = 8;
4756         break;
4757     case EXCP_IRQ:
4758         new_mode = ARM_CPU_MODE_IRQ;
4759         addr = 0x18;
4760         /* Disable IRQ and imprecise data aborts.  */
4761         mask = CPSR_A | CPSR_I;
4762         offset = 4;
4763         if (env->cp15.scr_el3 & SCR_IRQ) {
4764             /* IRQ routed to monitor mode */
4765             new_mode = ARM_CPU_MODE_MON;
4766             mask |= CPSR_F;
4767         }
4768         break;
4769     case EXCP_FIQ:
4770         new_mode = ARM_CPU_MODE_FIQ;
4771         addr = 0x1c;
4772         /* Disable FIQ, IRQ and imprecise data aborts.  */
4773         mask = CPSR_A | CPSR_I | CPSR_F;
4774         if (env->cp15.scr_el3 & SCR_FIQ) {
4775             /* FIQ routed to monitor mode */
4776             new_mode = ARM_CPU_MODE_MON;
4777         }
4778         offset = 4;
4779         break;
4780     case EXCP_SMC:
4781         new_mode = ARM_CPU_MODE_MON;
4782         addr = 0x08;
4783         mask = CPSR_A | CPSR_I | CPSR_F;
4784         offset = 0;
4785         break;
4786     default:
4787         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
4788         return; /* Never happens.  Keep compiler happy.  */
4789     }
4790
4791     if (new_mode == ARM_CPU_MODE_MON) {
4792         addr += env->cp15.mvbar;
4793     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
4794         /* High vectors. When enabled, base address cannot be remapped. */
4795         addr += 0xffff0000;
4796     } else {
4797         /* ARM v7 architectures provide a vector base address register to remap
4798          * the interrupt vector table.
4799          * This register is only followed in non-monitor mode, and is banked.
4800          * Note: only bits 31:5 are valid.
4801          */
4802         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
4803     }
4804
4805     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
4806         env->cp15.scr_el3 &= ~SCR_NS;
4807     }
4808
4809     switch_mode (env, new_mode);
4810     /* For exceptions taken to AArch32 we must clear the SS bit in both
4811      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
4812      */
4813     env->uncached_cpsr &= ~PSTATE_SS;
4814     env->spsr = cpsr_read(env);
4815     /* Clear IT bits.  */
4816     env->condexec_bits = 0;
4817     /* Switch to the new mode, and to the correct instruction set.  */
4818     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
4819     env->daif |= mask;
4820     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
4821      * and we should just guard the thumb mode on V4 */
4822     if (arm_feature(env, ARM_FEATURE_V4T)) {
4823         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
4824     }
4825     env->regs[14] = env->regs[15] + offset;
4826     env->regs[15] = addr;
4827     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
4828 }
4829
4830
4831 /* Return the exception level which controls this address translation regime */
4832 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
4833 {
4834     switch (mmu_idx) {
4835     case ARMMMUIdx_S2NS:
4836     case ARMMMUIdx_S1E2:
4837         return 2;
4838     case ARMMMUIdx_S1E3:
4839         return 3;
4840     case ARMMMUIdx_S1SE0:
4841         return arm_el_is_aa64(env, 3) ? 1 : 3;
4842     case ARMMMUIdx_S1SE1:
4843     case ARMMMUIdx_S1NSE0:
4844     case ARMMMUIdx_S1NSE1:
4845         return 1;
4846     default:
4847         g_assert_not_reached();
4848     }
4849 }
4850
4851 /* Return the SCTLR value which controls this address translation regime */
4852 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
4853 {
4854     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
4855 }
4856
4857 /* Return true if the specified stage of address translation is disabled */
4858 static inline bool regime_translation_disabled(CPUARMState *env,
4859                                                ARMMMUIdx mmu_idx)
4860 {
4861     if (mmu_idx == ARMMMUIdx_S2NS) {
4862         return (env->cp15.hcr_el2 & HCR_VM) == 0;
4863     }
4864     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
4865 }
4866
4867 /* Return the TCR controlling this translation regime */
4868 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
4869 {
4870     if (mmu_idx == ARMMMUIdx_S2NS) {
4871         /* TODO: return VTCR_EL2 */
4872         g_assert_not_reached();
4873     }
4874     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
4875 }
4876
4877 /* Return true if the translation regime is using LPAE format page tables */
4878 static inline bool regime_using_lpae_format(CPUARMState *env,
4879                                             ARMMMUIdx mmu_idx)
4880 {
4881     int el = regime_el(env, mmu_idx);
4882     if (el == 2 || arm_el_is_aa64(env, el)) {
4883         return true;
4884     }
4885     if (arm_feature(env, ARM_FEATURE_LPAE)
4886         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
4887         return true;
4888     }
4889     return false;
4890 }
4891
4892 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
4893 {
4894     switch (mmu_idx) {
4895     case ARMMMUIdx_S1SE0:
4896     case ARMMMUIdx_S1NSE0:
4897         return true;
4898     default:
4899         return false;
4900     case ARMMMUIdx_S12NSE0:
4901     case ARMMMUIdx_S12NSE1:
4902         g_assert_not_reached();
4903     }
4904 }
4905
4906 /* Check section/page access permissions.
4907    Returns the page protection flags, or zero if the access is not
4908    permitted.  */
4909 static inline int check_ap(CPUARMState *env, ARMMMUIdx mmu_idx,
4910                            int ap, int domain_prot,
4911                            int access_type)
4912 {
4913     int prot_ro;
4914     bool is_user = regime_is_user(env, mmu_idx);
4915
4916     if (domain_prot == 3) {
4917         return PAGE_READ | PAGE_WRITE;
4918     }
4919
4920     if (access_type == 1) {
4921         prot_ro = 0;
4922     } else {
4923         prot_ro = PAGE_READ;
4924     }
4925
4926     switch (ap) {
4927     case 0:
4928         if (arm_feature(env, ARM_FEATURE_V7)) {
4929             return 0;
4930         }
4931         if (access_type == 1) {
4932             return 0;
4933         }
4934         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
4935         case SCTLR_S:
4936             return is_user ? 0 : PAGE_READ;
4937         case SCTLR_R:
4938             return PAGE_READ;
4939         default:
4940             return 0;
4941         }
4942     case 1:
4943         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
4944     case 2:
4945         if (is_user) {
4946             return prot_ro;
4947         } else {
4948             return PAGE_READ | PAGE_WRITE;
4949         }
4950     case 3:
4951         return PAGE_READ | PAGE_WRITE;
4952     case 4: /* Reserved.  */
4953         return 0;
4954     case 5:
4955         return is_user ? 0 : prot_ro;
4956     case 6:
4957         return prot_ro;
4958     case 7:
4959         if (!arm_feature(env, ARM_FEATURE_V6K)) {
4960             return 0;
4961         }
4962         return prot_ro;
4963     default:
4964         abort();
4965     }
4966 }
4967
4968 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
4969                                      uint32_t *table, uint32_t address)
4970 {
4971     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
4972     int el = regime_el(env, mmu_idx);
4973     TCR *tcr = regime_tcr(env, mmu_idx);
4974
4975     if (address & tcr->mask) {
4976         if (tcr->raw_tcr & TTBCR_PD1) {
4977             /* Translation table walk disabled for TTBR1 */
4978             return false;
4979         }
4980         *table = env->cp15.ttbr1_el[el] & 0xffffc000;
4981     } else {
4982         if (tcr->raw_tcr & TTBCR_PD0) {
4983             /* Translation table walk disabled for TTBR0 */
4984             return false;
4985         }
4986         *table = env->cp15.ttbr0_el[el] & tcr->base_mask;
4987     }
4988     *table |= (address >> 18) & 0x3ffc;
4989     return true;
4990 }
4991
4992 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
4993                             ARMMMUIdx mmu_idx, hwaddr *phys_ptr,
4994                             int *prot, target_ulong *page_size)
4995 {
4996     CPUState *cs = CPU(arm_env_get_cpu(env));
4997     int code;
4998     uint32_t table;
4999     uint32_t desc;
5000     int type;
5001     int ap;
5002     int domain = 0;
5003     int domain_prot;
5004     hwaddr phys_addr;
5005     uint32_t dacr;
5006
5007     /* Pagetable walk.  */
5008     /* Lookup l1 descriptor.  */
5009     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
5010         /* Section translation fault if page walk is disabled by PD0 or PD1 */
5011         code = 5;
5012         goto do_fault;
5013     }
5014     desc = ldl_phys(cs->as, table);
5015     type = (desc & 3);
5016     domain = (desc >> 5) & 0x0f;
5017     if (regime_el(env, mmu_idx) == 1) {
5018         dacr = env->cp15.dacr_ns;
5019     } else {
5020         dacr = env->cp15.dacr_s;
5021     }
5022     domain_prot = (dacr >> (domain * 2)) & 3;
5023     if (type == 0) {
5024         /* Section translation fault.  */
5025         code = 5;
5026         goto do_fault;
5027     }
5028     if (domain_prot == 0 || domain_prot == 2) {
5029         if (type == 2)
5030             code = 9; /* Section domain fault.  */
5031         else
5032             code = 11; /* Page domain fault.  */
5033         goto do_fault;
5034     }
5035     if (type == 2) {
5036         /* 1Mb section.  */
5037         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
5038         ap = (desc >> 10) & 3;
5039         code = 13;
5040         *page_size = 1024 * 1024;
5041     } else {
5042         /* Lookup l2 entry.  */
5043         if (type == 1) {
5044             /* Coarse pagetable.  */
5045             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
5046         } else {
5047             /* Fine pagetable.  */
5048             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
5049         }
5050         desc = ldl_phys(cs->as, table);
5051         switch (desc & 3) {
5052         case 0: /* Page translation fault.  */
5053             code = 7;
5054             goto do_fault;
5055         case 1: /* 64k page.  */
5056             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
5057             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
5058             *page_size = 0x10000;
5059             break;
5060         case 2: /* 4k page.  */
5061             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
5062             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
5063             *page_size = 0x1000;
5064             break;
5065         case 3: /* 1k page.  */
5066             if (type == 1) {
5067                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5068                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
5069                 } else {
5070                     /* Page translation fault.  */
5071                     code = 7;
5072                     goto do_fault;
5073                 }
5074             } else {
5075                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
5076             }
5077             ap = (desc >> 4) & 3;
5078             *page_size = 0x400;
5079             break;
5080         default:
5081             /* Never happens, but compiler isn't smart enough to tell.  */
5082             abort();
5083         }
5084         code = 15;
5085     }
5086     *prot = check_ap(env, mmu_idx, ap, domain_prot, access_type);
5087     if (!*prot) {
5088         /* Access permission fault.  */
5089         goto do_fault;
5090     }
5091     *prot |= PAGE_EXEC;
5092     *phys_ptr = phys_addr;
5093     return 0;
5094 do_fault:
5095     return code | (domain << 4);
5096 }
5097
5098 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
5099                             ARMMMUIdx mmu_idx, hwaddr *phys_ptr,
5100                             int *prot, target_ulong *page_size)
5101 {
5102     CPUState *cs = CPU(arm_env_get_cpu(env));
5103     int code;
5104     uint32_t table;
5105     uint32_t desc;
5106     uint32_t xn;
5107     uint32_t pxn = 0;
5108     int type;
5109     int ap;
5110     int domain = 0;
5111     int domain_prot;
5112     hwaddr phys_addr;
5113     uint32_t dacr;
5114
5115     /* Pagetable walk.  */
5116     /* Lookup l1 descriptor.  */
5117     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
5118         /* Section translation fault if page walk is disabled by PD0 or PD1 */
5119         code = 5;
5120         goto do_fault;
5121     }
5122     desc = ldl_phys(cs->as, table);
5123     type = (desc & 3);
5124     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
5125         /* Section translation fault, or attempt to use the encoding
5126          * which is Reserved on implementations without PXN.
5127          */
5128         code = 5;
5129         goto do_fault;
5130     }
5131     if ((type == 1) || !(desc & (1 << 18))) {
5132         /* Page or Section.  */
5133         domain = (desc >> 5) & 0x0f;
5134     }
5135     if (regime_el(env, mmu_idx) == 1) {
5136         dacr = env->cp15.dacr_ns;
5137     } else {
5138         dacr = env->cp15.dacr_s;
5139     }
5140     domain_prot = (dacr >> (domain * 2)) & 3;
5141     if (domain_prot == 0 || domain_prot == 2) {
5142         if (type != 1) {
5143             code = 9; /* Section domain fault.  */
5144         } else {
5145             code = 11; /* Page domain fault.  */
5146         }
5147         goto do_fault;
5148     }
5149     if (type != 1) {
5150         if (desc & (1 << 18)) {
5151             /* Supersection.  */
5152             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
5153             *page_size = 0x1000000;
5154         } else {
5155             /* Section.  */
5156             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
5157             *page_size = 0x100000;
5158         }
5159         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
5160         xn = desc & (1 << 4);
5161         pxn = desc & 1;
5162         code = 13;
5163     } else {
5164         if (arm_feature(env, ARM_FEATURE_PXN)) {
5165             pxn = (desc >> 2) & 1;
5166         }
5167         /* Lookup l2 entry.  */
5168         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
5169         desc = ldl_phys(cs->as, table);
5170         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
5171         switch (desc & 3) {
5172         case 0: /* Page translation fault.  */
5173             code = 7;
5174             goto do_fault;
5175         case 1: /* 64k page.  */
5176             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
5177             xn = desc & (1 << 15);
5178             *page_size = 0x10000;
5179             break;
5180         case 2: case 3: /* 4k page.  */
5181             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
5182             xn = desc & 1;
5183             *page_size = 0x1000;
5184             break;
5185         default:
5186             /* Never happens, but compiler isn't smart enough to tell.  */
5187             abort();
5188         }
5189         code = 15;
5190     }
5191     if (domain_prot == 3) {
5192         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
5193     } else {
5194         if (pxn && !regime_is_user(env, mmu_idx)) {
5195             xn = 1;
5196         }
5197         if (xn && access_type == 2)
5198             goto do_fault;
5199
5200         /* The simplified model uses AP[0] as an access control bit.  */
5201         if ((regime_sctlr(env, mmu_idx) & SCTLR_AFE)
5202                 && (ap & 1) == 0) {
5203             /* Access flag fault.  */
5204             code = (code == 15) ? 6 : 3;
5205             goto do_fault;
5206         }
5207         *prot = check_ap(env, mmu_idx, ap, domain_prot, access_type);
5208         if (!*prot) {
5209             /* Access permission fault.  */
5210             goto do_fault;
5211         }
5212         if (!xn) {
5213             *prot |= PAGE_EXEC;
5214         }
5215     }
5216     *phys_ptr = phys_addr;
5217     return 0;
5218 do_fault:
5219     return code | (domain << 4);
5220 }
5221
5222 /* Fault type for long-descriptor MMU fault reporting; this corresponds
5223  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
5224  */
5225 typedef enum {
5226     translation_fault = 1,
5227     access_fault = 2,
5228     permission_fault = 3,
5229 } MMUFaultType;
5230
5231 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
5232                               int access_type, ARMMMUIdx mmu_idx,
5233                               hwaddr *phys_ptr, int *prot,
5234                               target_ulong *page_size_ptr)
5235 {
5236     CPUState *cs = CPU(arm_env_get_cpu(env));
5237     /* Read an LPAE long-descriptor translation table. */
5238     MMUFaultType fault_type = translation_fault;
5239     uint32_t level = 1;
5240     uint32_t epd;
5241     int32_t tsz;
5242     uint32_t tg;
5243     uint64_t ttbr;
5244     int ttbr_select;
5245     hwaddr descaddr, descmask;
5246     uint32_t tableattrs;
5247     target_ulong page_size;
5248     uint32_t attrs;
5249     int32_t granule_sz = 9;
5250     int32_t va_size = 32;
5251     int32_t tbi = 0;
5252     bool is_user;
5253     TCR *tcr = regime_tcr(env, mmu_idx);
5254
5255     /* TODO:
5256      * This code assumes we're either a 64-bit EL1 or a 32-bit PL1;
5257      * it doesn't handle the different format TCR for TCR_EL2, TCR_EL3,
5258      * and VTCR_EL2, or the fact that those regimes don't have a split
5259      * TTBR0/TTBR1. Attribute and permission bit handling should also
5260      * be checked when adding support for those page table walks.
5261      */
5262     if (arm_el_is_aa64(env, regime_el(env, mmu_idx))) {
5263         va_size = 64;
5264         if (extract64(address, 55, 1))
5265             tbi = extract64(tcr->raw_tcr, 38, 1);
5266         else
5267             tbi = extract64(tcr->raw_tcr, 37, 1);
5268         tbi *= 8;
5269     }
5270
5271     /* Determine whether this address is in the region controlled by
5272      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
5273      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
5274      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
5275      */
5276     uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
5277     if (va_size == 64) {
5278         t0sz = MIN(t0sz, 39);
5279         t0sz = MAX(t0sz, 16);
5280     }
5281     uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
5282     if (va_size == 64) {
5283         t1sz = MIN(t1sz, 39);
5284         t1sz = MAX(t1sz, 16);
5285     }
5286     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
5287         /* there is a ttbr0 region and we are in it (high bits all zero) */
5288         ttbr_select = 0;
5289     } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
5290         /* there is a ttbr1 region and we are in it (high bits all one) */
5291         ttbr_select = 1;
5292     } else if (!t0sz) {
5293         /* ttbr0 region is "everything not in the ttbr1 region" */
5294         ttbr_select = 0;
5295     } else if (!t1sz) {
5296         /* ttbr1 region is "everything not in the ttbr0 region" */
5297         ttbr_select = 1;
5298     } else {
5299         /* in the gap between the two regions, this is a Translation fault */
5300         fault_type = translation_fault;
5301         goto do_fault;
5302     }
5303
5304     /* Note that QEMU ignores shareability and cacheability attributes,
5305      * so we don't need to do anything with the SH, ORGN, IRGN fields
5306      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
5307      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
5308      * implement any ASID-like capability so we can ignore it (instead
5309      * we will always flush the TLB any time the ASID is changed).
5310      */
5311     if (ttbr_select == 0) {
5312         ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0);
5313         epd = extract32(tcr->raw_tcr, 7, 1);
5314         tsz = t0sz;
5315
5316         tg = extract32(tcr->raw_tcr, 14, 2);
5317         if (tg == 1) { /* 64KB pages */
5318             granule_sz = 13;
5319         }
5320         if (tg == 2) { /* 16KB pages */
5321             granule_sz = 11;
5322         }
5323     } else {
5324         ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1);
5325         epd = extract32(tcr->raw_tcr, 23, 1);
5326         tsz = t1sz;
5327
5328         tg = extract32(tcr->raw_tcr, 30, 2);
5329         if (tg == 3)  { /* 64KB pages */
5330             granule_sz = 13;
5331         }
5332         if (tg == 1) { /* 16KB pages */
5333             granule_sz = 11;
5334         }
5335     }
5336
5337     /* Here we should have set up all the parameters for the translation:
5338      * va_size, ttbr, epd, tsz, granule_sz, tbi
5339      */
5340
5341     if (epd) {
5342         /* Translation table walk disabled => Translation fault on TLB miss */
5343         goto do_fault;
5344     }
5345
5346     /* The starting level depends on the virtual address size (which can be
5347      * up to 48 bits) and the translation granule size. It indicates the number
5348      * of strides (granule_sz bits at a time) needed to consume the bits
5349      * of the input address. In the pseudocode this is:
5350      *  level = 4 - RoundUp((inputsize - grainsize) / stride)
5351      * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
5352      * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
5353      * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
5354      *     = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
5355      *     = 4 - (va_size - tsz - 4) / granule_sz;
5356      */
5357     level = 4 - (va_size - tsz - 4) / granule_sz;
5358
5359     /* Clear the vaddr bits which aren't part of the within-region address,
5360      * so that we don't have to special case things when calculating the
5361      * first descriptor address.
5362      */
5363     if (tsz) {
5364         address &= (1ULL << (va_size - tsz)) - 1;
5365     }
5366
5367     descmask = (1ULL << (granule_sz + 3)) - 1;
5368
5369     /* Now we can extract the actual base address from the TTBR */
5370     descaddr = extract64(ttbr, 0, 48);
5371     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
5372
5373     tableattrs = 0;
5374     for (;;) {
5375         uint64_t descriptor;
5376
5377         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
5378         descaddr &= ~7ULL;
5379         descriptor = ldq_phys(cs->as, descaddr);
5380         if (!(descriptor & 1) ||
5381             (!(descriptor & 2) && (level == 3))) {
5382             /* Invalid, or the Reserved level 3 encoding */
5383             goto do_fault;
5384         }
5385         descaddr = descriptor & 0xfffffff000ULL;
5386
5387         if ((descriptor & 2) && (level < 3)) {
5388             /* Table entry. The top five bits are attributes which  may
5389              * propagate down through lower levels of the table (and
5390              * which are all arranged so that 0 means "no effect", so
5391              * we can gather them up by ORing in the bits at each level).
5392              */
5393             tableattrs |= extract64(descriptor, 59, 5);
5394             level++;
5395             continue;
5396         }
5397         /* Block entry at level 1 or 2, or page entry at level 3.
5398          * These are basically the same thing, although the number
5399          * of bits we pull in from the vaddr varies.
5400          */
5401         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
5402         descaddr |= (address & (page_size - 1));
5403         /* Extract attributes from the descriptor and merge with table attrs */
5404         attrs = extract64(descriptor, 2, 10)
5405             | (extract64(descriptor, 52, 12) << 10);
5406         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
5407         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
5408         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
5409          * means "force PL1 access only", which means forcing AP[1] to 0.
5410          */
5411         if (extract32(tableattrs, 2, 1)) {
5412             attrs &= ~(1 << 4);
5413         }
5414         /* Since we're always in the Non-secure state, NSTable is ignored. */
5415         break;
5416     }
5417     /* Here descaddr is the final physical address, and attributes
5418      * are all in attrs.
5419      */
5420     fault_type = access_fault;
5421     if ((attrs & (1 << 8)) == 0) {
5422         /* Access flag */
5423         goto do_fault;
5424     }
5425     fault_type = permission_fault;
5426     is_user = regime_is_user(env, mmu_idx);
5427     if (is_user && !(attrs & (1 << 4))) {
5428         /* Unprivileged access not enabled */
5429         goto do_fault;
5430     }
5431     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
5432     if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) ||
5433         (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) ||
5434         (!is_user && (attrs & (1 << 11)))) {
5435         /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
5436          * treat XN/UXN as UXN for v8.
5437          */
5438         if (access_type == 2) {
5439             goto do_fault;
5440         }
5441         *prot &= ~PAGE_EXEC;
5442     }
5443     if (attrs & (1 << 5)) {
5444         /* Write access forbidden */
5445         if (access_type == 1) {
5446             goto do_fault;
5447         }
5448         *prot &= ~PAGE_WRITE;
5449     }
5450
5451     *phys_ptr = descaddr;
5452     *page_size_ptr = page_size;
5453     return 0;
5454
5455 do_fault:
5456     /* Long-descriptor format IFSR/DFSR value */
5457     return (1 << 9) | (fault_type << 2) | level;
5458 }
5459
5460 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
5461                              int access_type, ARMMMUIdx mmu_idx,
5462                              hwaddr *phys_ptr, int *prot)
5463 {
5464     int n;
5465     uint32_t mask;
5466     uint32_t base;
5467     bool is_user = regime_is_user(env, mmu_idx);
5468
5469     *phys_ptr = address;
5470     for (n = 7; n >= 0; n--) {
5471         base = env->cp15.c6_region[n];
5472         if ((base & 1) == 0) {
5473             continue;
5474         }
5475         mask = 1 << ((base >> 1) & 0x1f);
5476         /* Keep this shift separate from the above to avoid an
5477            (undefined) << 32.  */
5478         mask = (mask << 1) - 1;
5479         if (((base ^ address) & ~mask) == 0) {
5480             break;
5481         }
5482     }
5483     if (n < 0) {
5484         return 2;
5485     }
5486
5487     if (access_type == 2) {
5488         mask = env->cp15.pmsav5_insn_ap;
5489     } else {
5490         mask = env->cp15.pmsav5_data_ap;
5491     }
5492     mask = (mask >> (n * 4)) & 0xf;
5493     switch (mask) {
5494     case 0:
5495         return 1;
5496     case 1:
5497         if (is_user) {
5498             return 1;
5499         }
5500         *prot = PAGE_READ | PAGE_WRITE;
5501         break;
5502     case 2:
5503         *prot = PAGE_READ;
5504         if (!is_user) {
5505             *prot |= PAGE_WRITE;
5506         }
5507         break;
5508     case 3:
5509         *prot = PAGE_READ | PAGE_WRITE;
5510         break;
5511     case 5:
5512         if (is_user) {
5513             return 1;
5514         }
5515         *prot = PAGE_READ;
5516         break;
5517     case 6:
5518         *prot = PAGE_READ;
5519         break;
5520     default:
5521         /* Bad permission.  */
5522         return 1;
5523     }
5524     *prot |= PAGE_EXEC;
5525     return 0;
5526 }
5527
5528 /* get_phys_addr - get the physical address for this virtual address
5529  *
5530  * Find the physical address corresponding to the given virtual address,
5531  * by doing a translation table walk on MMU based systems or using the
5532  * MPU state on MPU based systems.
5533  *
5534  * Returns 0 if the translation was successful. Otherwise, phys_ptr,
5535  * prot and page_size are not filled in, and the return value provides
5536  * information on why the translation aborted, in the format of a
5537  * DFSR/IFSR fault register, with the following caveats:
5538  *  * we honour the short vs long DFSR format differences.
5539  *  * the WnR bit is never set (the caller must do this).
5540  *  * for MPU based systems we don't bother to return a full FSR format
5541  *    value.
5542  *
5543  * @env: CPUARMState
5544  * @address: virtual address to get physical address for
5545  * @access_type: 0 for read, 1 for write, 2 for execute
5546  * @mmu_idx: MMU index indicating required translation regime
5547  * @phys_ptr: set to the physical address corresponding to the virtual address
5548  * @prot: set to the permissions for the page containing phys_ptr
5549  * @page_size: set to the size of the page containing phys_ptr
5550  */
5551 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
5552                                 int access_type, ARMMMUIdx mmu_idx,
5553                                 hwaddr *phys_ptr, int *prot,
5554                                 target_ulong *page_size)
5555 {
5556     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
5557         /* TODO: when we support EL2 we should here call ourselves recursively
5558          * to do the stage 1 and then stage 2 translations. The ldl_phys
5559          * calls for stage 1 will also need changing.
5560          * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
5561          */
5562         assert(!arm_feature(env, ARM_FEATURE_EL2));
5563         mmu_idx += ARMMMUIdx_S1NSE0;
5564     }
5565
5566     /* Fast Context Switch Extension. This doesn't exist at all in v8.
5567      * In v7 and earlier it affects all stage 1 translations.
5568      */
5569     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
5570         && !arm_feature(env, ARM_FEATURE_V8)) {
5571         if (regime_el(env, mmu_idx) == 3) {
5572             address += env->cp15.fcseidr_s;
5573         } else {
5574             address += env->cp15.fcseidr_ns;
5575         }
5576     }
5577
5578     if (regime_translation_disabled(env, mmu_idx)) {
5579         /* MMU/MPU disabled.  */
5580         *phys_ptr = address;
5581         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
5582         *page_size = TARGET_PAGE_SIZE;
5583         return 0;
5584     }
5585
5586     if (arm_feature(env, ARM_FEATURE_MPU)) {
5587         *page_size = TARGET_PAGE_SIZE;
5588         return get_phys_addr_mpu(env, address, access_type, mmu_idx, phys_ptr,
5589                                  prot);
5590     }
5591
5592     if (regime_using_lpae_format(env, mmu_idx)) {
5593         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
5594                                   prot, page_size);
5595     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
5596         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
5597                                 prot, page_size);
5598     } else {
5599         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
5600                                 prot, page_size);
5601     }
5602 }
5603
5604 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
5605                              int access_type, int mmu_idx)
5606 {
5607     ARMCPU *cpu = ARM_CPU(cs);
5608     CPUARMState *env = &cpu->env;
5609     hwaddr phys_addr;
5610     target_ulong page_size;
5611     int prot;
5612     int ret;
5613     uint32_t syn;
5614     bool same_el = (arm_current_el(env) != 0);
5615
5616     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr, &prot,
5617                         &page_size);
5618     if (ret == 0) {
5619         /* Map a single [sub]page.  */
5620         phys_addr &= TARGET_PAGE_MASK;
5621         address &= TARGET_PAGE_MASK;
5622         tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
5623         return 0;
5624     }
5625
5626     /* AArch64 syndrome does not have an LPAE bit */
5627     syn = ret & ~(1 << 9);
5628
5629     /* For insn and data aborts we assume there is no instruction syndrome
5630      * information; this is always true for exceptions reported to EL1.
5631      */
5632     if (access_type == 2) {
5633         syn = syn_insn_abort(same_el, 0, 0, syn);
5634         cs->exception_index = EXCP_PREFETCH_ABORT;
5635     } else {
5636         syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
5637         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
5638             ret |= (1 << 11);
5639         }
5640         cs->exception_index = EXCP_DATA_ABORT;
5641     }
5642
5643     env->exception.syndrome = syn;
5644     env->exception.vaddress = address;
5645     env->exception.fsr = ret;
5646     return 1;
5647 }
5648
5649 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
5650 {
5651     ARMCPU *cpu = ARM_CPU(cs);
5652     CPUARMState *env = &cpu->env;
5653     hwaddr phys_addr;
5654     target_ulong page_size;
5655     int prot;
5656     int ret;
5657
5658     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env), &phys_addr,
5659                         &prot, &page_size);
5660
5661     if (ret != 0) {
5662         return -1;
5663     }
5664
5665     return phys_addr;
5666 }
5667
5668 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
5669 {
5670     if ((env->uncached_cpsr & CPSR_M) == mode) {
5671         env->regs[13] = val;
5672     } else {
5673         env->banked_r13[bank_number(mode)] = val;
5674     }
5675 }
5676
5677 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
5678 {
5679     if ((env->uncached_cpsr & CPSR_M) == mode) {
5680         return env->regs[13];
5681     } else {
5682         return env->banked_r13[bank_number(mode)];
5683     }
5684 }
5685
5686 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5687 {
5688     ARMCPU *cpu = arm_env_get_cpu(env);
5689
5690     switch (reg) {
5691     case 0: /* APSR */
5692         return xpsr_read(env) & 0xf8000000;
5693     case 1: /* IAPSR */
5694         return xpsr_read(env) & 0xf80001ff;
5695     case 2: /* EAPSR */
5696         return xpsr_read(env) & 0xff00fc00;
5697     case 3: /* xPSR */
5698         return xpsr_read(env) & 0xff00fdff;
5699     case 5: /* IPSR */
5700         return xpsr_read(env) & 0x000001ff;
5701     case 6: /* EPSR */
5702         return xpsr_read(env) & 0x0700fc00;
5703     case 7: /* IEPSR */
5704         return xpsr_read(env) & 0x0700edff;
5705     case 8: /* MSP */
5706         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
5707     case 9: /* PSP */
5708         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
5709     case 16: /* PRIMASK */
5710         return (env->daif & PSTATE_I) != 0;
5711     case 17: /* BASEPRI */
5712     case 18: /* BASEPRI_MAX */
5713         return env->v7m.basepri;
5714     case 19: /* FAULTMASK */
5715         return (env->daif & PSTATE_F) != 0;
5716     case 20: /* CONTROL */
5717         return env->v7m.control;
5718     default:
5719         /* ??? For debugging only.  */
5720         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
5721         return 0;
5722     }
5723 }
5724
5725 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5726 {
5727     ARMCPU *cpu = arm_env_get_cpu(env);
5728
5729     switch (reg) {
5730     case 0: /* APSR */
5731         xpsr_write(env, val, 0xf8000000);
5732         break;
5733     case 1: /* IAPSR */
5734         xpsr_write(env, val, 0xf8000000);
5735         break;
5736     case 2: /* EAPSR */
5737         xpsr_write(env, val, 0xfe00fc00);
5738         break;
5739     case 3: /* xPSR */
5740         xpsr_write(env, val, 0xfe00fc00);
5741         break;
5742     case 5: /* IPSR */
5743         /* IPSR bits are readonly.  */
5744         break;
5745     case 6: /* EPSR */
5746         xpsr_write(env, val, 0x0600fc00);
5747         break;
5748     case 7: /* IEPSR */
5749         xpsr_write(env, val, 0x0600fc00);
5750         break;
5751     case 8: /* MSP */
5752         if (env->v7m.current_sp)
5753             env->v7m.other_sp = val;
5754         else
5755             env->regs[13] = val;
5756         break;
5757     case 9: /* PSP */
5758         if (env->v7m.current_sp)
5759             env->regs[13] = val;
5760         else
5761             env->v7m.other_sp = val;
5762         break;
5763     case 16: /* PRIMASK */
5764         if (val & 1) {
5765             env->daif |= PSTATE_I;
5766         } else {
5767             env->daif &= ~PSTATE_I;
5768         }
5769         break;
5770     case 17: /* BASEPRI */
5771         env->v7m.basepri = val & 0xff;
5772         break;
5773     case 18: /* BASEPRI_MAX */
5774         val &= 0xff;
5775         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
5776             env->v7m.basepri = val;
5777         break;
5778     case 19: /* FAULTMASK */
5779         if (val & 1) {
5780             env->daif |= PSTATE_F;
5781         } else {
5782             env->daif &= ~PSTATE_F;
5783         }
5784         break;
5785     case 20: /* CONTROL */
5786         env->v7m.control = val & 3;
5787         switch_v7m_sp(env, (val & 2) != 0);
5788         break;
5789     default:
5790         /* ??? For debugging only.  */
5791         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
5792         return;
5793     }
5794 }
5795
5796 #endif
5797
5798 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
5799 {
5800     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
5801      * Note that we do not implement the (architecturally mandated)
5802      * alignment fault for attempts to use this on Device memory
5803      * (which matches the usual QEMU behaviour of not implementing either
5804      * alignment faults or any memory attribute handling).
5805      */
5806
5807     ARMCPU *cpu = arm_env_get_cpu(env);
5808     uint64_t blocklen = 4 << cpu->dcz_blocksize;
5809     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
5810
5811 #ifndef CONFIG_USER_ONLY
5812     {
5813         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
5814          * the block size so we might have to do more than one TLB lookup.
5815          * We know that in fact for any v8 CPU the page size is at least 4K
5816          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
5817          * 1K as an artefact of legacy v5 subpage support being present in the
5818          * same QEMU executable.
5819          */
5820         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
5821         void *hostaddr[maxidx];
5822         int try, i;
5823
5824         for (try = 0; try < 2; try++) {
5825
5826             for (i = 0; i < maxidx; i++) {
5827                 hostaddr[i] = tlb_vaddr_to_host(env,
5828                                                 vaddr + TARGET_PAGE_SIZE * i,
5829                                                 1, cpu_mmu_index(env));
5830                 if (!hostaddr[i]) {
5831                     break;
5832                 }
5833             }
5834             if (i == maxidx) {
5835                 /* If it's all in the TLB it's fair game for just writing to;
5836                  * we know we don't need to update dirty status, etc.
5837                  */
5838                 for (i = 0; i < maxidx - 1; i++) {
5839                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
5840                 }
5841                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
5842                 return;
5843             }
5844             /* OK, try a store and see if we can populate the tlb. This
5845              * might cause an exception if the memory isn't writable,
5846              * in which case we will longjmp out of here. We must for
5847              * this purpose use the actual register value passed to us
5848              * so that we get the fault address right.
5849              */
5850             helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
5851             /* Now we can populate the other TLB entries, if any */
5852             for (i = 0; i < maxidx; i++) {
5853                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
5854                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
5855                     helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
5856                 }
5857             }
5858         }
5859
5860         /* Slow path (probably attempt to do this to an I/O device or
5861          * similar, or clearing of a block of code we have translations
5862          * cached for). Just do a series of byte writes as the architecture
5863          * demands. It's not worth trying to use a cpu_physical_memory_map(),
5864          * memset(), unmap() sequence here because:
5865          *  + we'd need to account for the blocksize being larger than a page
5866          *  + the direct-RAM access case is almost always going to be dealt
5867          *    with in the fastpath code above, so there's no speed benefit
5868          *  + we would have to deal with the map returning NULL because the
5869          *    bounce buffer was in use
5870          */
5871         for (i = 0; i < blocklen; i++) {
5872             helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
5873         }
5874     }
5875 #else
5876     memset(g2h(vaddr), 0, blocklen);
5877 #endif
5878 }
5879
5880 /* Note that signed overflow is undefined in C.  The following routines are
5881    careful to use unsigned types where modulo arithmetic is required.
5882    Failure to do so _will_ break on newer gcc.  */
5883
5884 /* Signed saturating arithmetic.  */
5885
5886 /* Perform 16-bit signed saturating addition.  */
5887 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
5888 {
5889     uint16_t res;
5890
5891     res = a + b;
5892     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
5893         if (a & 0x8000)
5894             res = 0x8000;
5895         else
5896             res = 0x7fff;
5897     }
5898     return res;
5899 }
5900
5901 /* Perform 8-bit signed saturating addition.  */
5902 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
5903 {
5904     uint8_t res;
5905
5906     res = a + b;
5907     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
5908         if (a & 0x80)
5909             res = 0x80;
5910         else
5911             res = 0x7f;
5912     }
5913     return res;
5914 }
5915
5916 /* Perform 16-bit signed saturating subtraction.  */
5917 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
5918 {
5919     uint16_t res;
5920
5921     res = a - b;
5922     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
5923         if (a & 0x8000)
5924             res = 0x8000;
5925         else
5926             res = 0x7fff;
5927     }
5928     return res;
5929 }
5930
5931 /* Perform 8-bit signed saturating subtraction.  */
5932 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
5933 {
5934     uint8_t res;
5935
5936     res = a - b;
5937     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
5938         if (a & 0x80)
5939             res = 0x80;
5940         else
5941             res = 0x7f;
5942     }
5943     return res;
5944 }
5945
5946 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
5947 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
5948 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
5949 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
5950 #define PFX q
5951
5952 #include "op_addsub.h"
5953
5954 /* Unsigned saturating arithmetic.  */
5955 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
5956 {
5957     uint16_t res;
5958     res = a + b;
5959     if (res < a)
5960         res = 0xffff;
5961     return res;
5962 }
5963
5964 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
5965 {
5966     if (a > b)
5967         return a - b;
5968     else
5969         return 0;
5970 }
5971
5972 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
5973 {
5974     uint8_t res;
5975     res = a + b;
5976     if (res < a)
5977         res = 0xff;
5978     return res;
5979 }
5980
5981 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
5982 {
5983     if (a > b)
5984         return a - b;
5985     else
5986         return 0;
5987 }
5988
5989 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
5990 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
5991 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
5992 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
5993 #define PFX uq
5994
5995 #include "op_addsub.h"
5996
5997 /* Signed modulo arithmetic.  */
5998 #define SARITH16(a, b, n, op) do { \
5999     int32_t sum; \
6000     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6001     RESULT(sum, n, 16); \
6002     if (sum >= 0) \
6003         ge |= 3 << (n * 2); \
6004     } while(0)
6005
6006 #define SARITH8(a, b, n, op) do { \
6007     int32_t sum; \
6008     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6009     RESULT(sum, n, 8); \
6010     if (sum >= 0) \
6011         ge |= 1 << n; \
6012     } while(0)
6013
6014
6015 #define ADD16(a, b, n) SARITH16(a, b, n, +)
6016 #define SUB16(a, b, n) SARITH16(a, b, n, -)
6017 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
6018 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
6019 #define PFX s
6020 #define ARITH_GE
6021
6022 #include "op_addsub.h"
6023
6024 /* Unsigned modulo arithmetic.  */
6025 #define ADD16(a, b, n) do { \
6026     uint32_t sum; \
6027     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
6028     RESULT(sum, n, 16); \
6029     if ((sum >> 16) == 1) \
6030         ge |= 3 << (n * 2); \
6031     } while(0)
6032
6033 #define ADD8(a, b, n) do { \
6034     uint32_t sum; \
6035     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
6036     RESULT(sum, n, 8); \
6037     if ((sum >> 8) == 1) \
6038         ge |= 1 << n; \
6039     } while(0)
6040
6041 #define SUB16(a, b, n) do { \
6042     uint32_t sum; \
6043     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
6044     RESULT(sum, n, 16); \
6045     if ((sum >> 16) == 0) \
6046         ge |= 3 << (n * 2); \
6047     } while(0)
6048
6049 #define SUB8(a, b, n) do { \
6050     uint32_t sum; \
6051     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
6052     RESULT(sum, n, 8); \
6053     if ((sum >> 8) == 0) \
6054         ge |= 1 << n; \
6055     } while(0)
6056
6057 #define PFX u
6058 #define ARITH_GE
6059
6060 #include "op_addsub.h"
6061
6062 /* Halved signed arithmetic.  */
6063 #define ADD16(a, b, n) \
6064   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
6065 #define SUB16(a, b, n) \
6066   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
6067 #define ADD8(a, b, n) \
6068   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
6069 #define SUB8(a, b, n) \
6070   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
6071 #define PFX sh
6072
6073 #include "op_addsub.h"
6074
6075 /* Halved unsigned arithmetic.  */
6076 #define ADD16(a, b, n) \
6077   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6078 #define SUB16(a, b, n) \
6079   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6080 #define ADD8(a, b, n) \
6081   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6082 #define SUB8(a, b, n) \
6083   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6084 #define PFX uh
6085
6086 #include "op_addsub.h"
6087
6088 static inline uint8_t do_usad(uint8_t a, uint8_t b)
6089 {
6090     if (a > b)
6091         return a - b;
6092     else
6093         return b - a;
6094 }
6095
6096 /* Unsigned sum of absolute byte differences.  */
6097 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
6098 {
6099     uint32_t sum;
6100     sum = do_usad(a, b);
6101     sum += do_usad(a >> 8, b >> 8);
6102     sum += do_usad(a >> 16, b >>16);
6103     sum += do_usad(a >> 24, b >> 24);
6104     return sum;
6105 }
6106
6107 /* For ARMv6 SEL instruction.  */
6108 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
6109 {
6110     uint32_t mask;
6111
6112     mask = 0;
6113     if (flags & 1)
6114         mask |= 0xff;
6115     if (flags & 2)
6116         mask |= 0xff00;
6117     if (flags & 4)
6118         mask |= 0xff0000;
6119     if (flags & 8)
6120         mask |= 0xff000000;
6121     return (a & mask) | (b & ~mask);
6122 }
6123
6124 /* VFP support.  We follow the convention used for VFP instructions:
6125    Single precision routines have a "s" suffix, double precision a
6126    "d" suffix.  */
6127
6128 /* Convert host exception flags to vfp form.  */
6129 static inline int vfp_exceptbits_from_host(int host_bits)
6130 {
6131     int target_bits = 0;
6132
6133     if (host_bits & float_flag_invalid)
6134         target_bits |= 1;
6135     if (host_bits & float_flag_divbyzero)
6136         target_bits |= 2;
6137     if (host_bits & float_flag_overflow)
6138         target_bits |= 4;
6139     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
6140         target_bits |= 8;
6141     if (host_bits & float_flag_inexact)
6142         target_bits |= 0x10;
6143     if (host_bits & float_flag_input_denormal)
6144         target_bits |= 0x80;
6145     return target_bits;
6146 }
6147
6148 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
6149 {
6150     int i;
6151     uint32_t fpscr;
6152
6153     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
6154             | (env->vfp.vec_len << 16)
6155             | (env->vfp.vec_stride << 20);
6156     i = get_float_exception_flags(&env->vfp.fp_status);
6157     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
6158     fpscr |= vfp_exceptbits_from_host(i);
6159     return fpscr;
6160 }
6161
6162 uint32_t vfp_get_fpscr(CPUARMState *env)
6163 {
6164     return HELPER(vfp_get_fpscr)(env);
6165 }
6166
6167 /* Convert vfp exception flags to target form.  */
6168 static inline int vfp_exceptbits_to_host(int target_bits)
6169 {
6170     int host_bits = 0;
6171
6172     if (target_bits & 1)
6173         host_bits |= float_flag_invalid;
6174     if (target_bits & 2)
6175         host_bits |= float_flag_divbyzero;
6176     if (target_bits & 4)
6177         host_bits |= float_flag_overflow;
6178     if (target_bits & 8)
6179         host_bits |= float_flag_underflow;
6180     if (target_bits & 0x10)
6181         host_bits |= float_flag_inexact;
6182     if (target_bits & 0x80)
6183         host_bits |= float_flag_input_denormal;
6184     return host_bits;
6185 }
6186
6187 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
6188 {
6189     int i;
6190     uint32_t changed;
6191
6192     changed = env->vfp.xregs[ARM_VFP_FPSCR];
6193     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
6194     env->vfp.vec_len = (val >> 16) & 7;
6195     env->vfp.vec_stride = (val >> 20) & 3;
6196
6197     changed ^= val;
6198     if (changed & (3 << 22)) {
6199         i = (val >> 22) & 3;
6200         switch (i) {
6201         case FPROUNDING_TIEEVEN:
6202             i = float_round_nearest_even;
6203             break;
6204         case FPROUNDING_POSINF:
6205             i = float_round_up;
6206             break;
6207         case FPROUNDING_NEGINF:
6208             i = float_round_down;
6209             break;
6210         case FPROUNDING_ZERO:
6211             i = float_round_to_zero;
6212             break;
6213         }
6214         set_float_rounding_mode(i, &env->vfp.fp_status);
6215     }
6216     if (changed & (1 << 24)) {
6217         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
6218         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
6219     }
6220     if (changed & (1 << 25))
6221         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
6222
6223     i = vfp_exceptbits_to_host(val);
6224     set_float_exception_flags(i, &env->vfp.fp_status);
6225     set_float_exception_flags(0, &env->vfp.standard_fp_status);
6226 }
6227
6228 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
6229 {
6230     HELPER(vfp_set_fpscr)(env, val);
6231 }
6232
6233 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
6234
6235 #define VFP_BINOP(name) \
6236 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
6237 { \
6238     float_status *fpst = fpstp; \
6239     return float32_ ## name(a, b, fpst); \
6240 } \
6241 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
6242 { \
6243     float_status *fpst = fpstp; \
6244     return float64_ ## name(a, b, fpst); \
6245 }
6246 VFP_BINOP(add)
6247 VFP_BINOP(sub)
6248 VFP_BINOP(mul)
6249 VFP_BINOP(div)
6250 VFP_BINOP(min)
6251 VFP_BINOP(max)
6252 VFP_BINOP(minnum)
6253 VFP_BINOP(maxnum)
6254 #undef VFP_BINOP
6255
6256 float32 VFP_HELPER(neg, s)(float32 a)
6257 {
6258     return float32_chs(a);
6259 }
6260
6261 float64 VFP_HELPER(neg, d)(float64 a)
6262 {
6263     return float64_chs(a);
6264 }
6265
6266 float32 VFP_HELPER(abs, s)(float32 a)
6267 {
6268     return float32_abs(a);
6269 }
6270
6271 float64 VFP_HELPER(abs, d)(float64 a)
6272 {
6273     return float64_abs(a);
6274 }
6275
6276 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
6277 {
6278     return float32_sqrt(a, &env->vfp.fp_status);
6279 }
6280
6281 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
6282 {
6283     return float64_sqrt(a, &env->vfp.fp_status);
6284 }
6285
6286 /* XXX: check quiet/signaling case */
6287 #define DO_VFP_cmp(p, type) \
6288 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
6289 { \
6290     uint32_t flags; \
6291     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
6292     case 0: flags = 0x6; break; \
6293     case -1: flags = 0x8; break; \
6294     case 1: flags = 0x2; break; \
6295     default: case 2: flags = 0x3; break; \
6296     } \
6297     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6298         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6299 } \
6300 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
6301 { \
6302     uint32_t flags; \
6303     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
6304     case 0: flags = 0x6; break; \
6305     case -1: flags = 0x8; break; \
6306     case 1: flags = 0x2; break; \
6307     default: case 2: flags = 0x3; break; \
6308     } \
6309     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6310         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6311 }
6312 DO_VFP_cmp(s, float32)
6313 DO_VFP_cmp(d, float64)
6314 #undef DO_VFP_cmp
6315
6316 /* Integer to float and float to integer conversions */
6317
6318 #define CONV_ITOF(name, fsz, sign) \
6319     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
6320 { \
6321     float_status *fpst = fpstp; \
6322     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
6323 }
6324
6325 #define CONV_FTOI(name, fsz, sign, round) \
6326 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
6327 { \
6328     float_status *fpst = fpstp; \
6329     if (float##fsz##_is_any_nan(x)) { \
6330         float_raise(float_flag_invalid, fpst); \
6331         return 0; \
6332     } \
6333     return float##fsz##_to_##sign##int32##round(x, fpst); \
6334 }
6335
6336 #define FLOAT_CONVS(name, p, fsz, sign) \
6337 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
6338 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
6339 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
6340
6341 FLOAT_CONVS(si, s, 32, )
6342 FLOAT_CONVS(si, d, 64, )
6343 FLOAT_CONVS(ui, s, 32, u)
6344 FLOAT_CONVS(ui, d, 64, u)
6345
6346 #undef CONV_ITOF
6347 #undef CONV_FTOI
6348 #undef FLOAT_CONVS
6349
6350 /* floating point conversion */
6351 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
6352 {
6353     float64 r = float32_to_float64(x, &env->vfp.fp_status);
6354     /* ARM requires that S<->D conversion of any kind of NaN generates
6355      * a quiet NaN by forcing the most significant frac bit to 1.
6356      */
6357     return float64_maybe_silence_nan(r);
6358 }
6359
6360 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
6361 {
6362     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
6363     /* ARM requires that S<->D conversion of any kind of NaN generates
6364      * a quiet NaN by forcing the most significant frac bit to 1.
6365      */
6366     return float32_maybe_silence_nan(r);
6367 }
6368
6369 /* VFP3 fixed point conversion.  */
6370 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6371 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
6372                                      void *fpstp) \
6373 { \
6374     float_status *fpst = fpstp; \
6375     float##fsz tmp; \
6376     tmp = itype##_to_##float##fsz(x, fpst); \
6377     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
6378 }
6379
6380 /* Notice that we want only input-denormal exception flags from the
6381  * scalbn operation: the other possible flags (overflow+inexact if
6382  * we overflow to infinity, output-denormal) aren't correct for the
6383  * complete scale-and-convert operation.
6384  */
6385 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
6386 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
6387                                              uint32_t shift, \
6388                                              void *fpstp) \
6389 { \
6390     float_status *fpst = fpstp; \
6391     int old_exc_flags = get_float_exception_flags(fpst); \
6392     float##fsz tmp; \
6393     if (float##fsz##_is_any_nan(x)) { \
6394         float_raise(float_flag_invalid, fpst); \
6395         return 0; \
6396     } \
6397     tmp = float##fsz##_scalbn(x, shift, fpst); \
6398     old_exc_flags |= get_float_exception_flags(fpst) \
6399         & float_flag_input_denormal; \
6400     set_float_exception_flags(old_exc_flags, fpst); \
6401     return float##fsz##_to_##itype##round(tmp, fpst); \
6402 }
6403
6404 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
6405 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
6406 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
6407 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6408
6409 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
6410 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
6411 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6412
6413 VFP_CONV_FIX(sh, d, 64, 64, int16)
6414 VFP_CONV_FIX(sl, d, 64, 64, int32)
6415 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
6416 VFP_CONV_FIX(uh, d, 64, 64, uint16)
6417 VFP_CONV_FIX(ul, d, 64, 64, uint32)
6418 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
6419 VFP_CONV_FIX(sh, s, 32, 32, int16)
6420 VFP_CONV_FIX(sl, s, 32, 32, int32)
6421 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
6422 VFP_CONV_FIX(uh, s, 32, 32, uint16)
6423 VFP_CONV_FIX(ul, s, 32, 32, uint32)
6424 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
6425 #undef VFP_CONV_FIX
6426 #undef VFP_CONV_FIX_FLOAT
6427 #undef VFP_CONV_FLOAT_FIX_ROUND
6428
6429 /* Set the current fp rounding mode and return the old one.
6430  * The argument is a softfloat float_round_ value.
6431  */
6432 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
6433 {
6434     float_status *fp_status = &env->vfp.fp_status;
6435
6436     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
6437     set_float_rounding_mode(rmode, fp_status);
6438
6439     return prev_rmode;
6440 }
6441
6442 /* Set the current fp rounding mode in the standard fp status and return
6443  * the old one. This is for NEON instructions that need to change the
6444  * rounding mode but wish to use the standard FPSCR values for everything
6445  * else. Always set the rounding mode back to the correct value after
6446  * modifying it.
6447  * The argument is a softfloat float_round_ value.
6448  */
6449 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
6450 {
6451     float_status *fp_status = &env->vfp.standard_fp_status;
6452
6453     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
6454     set_float_rounding_mode(rmode, fp_status);
6455
6456     return prev_rmode;
6457 }
6458
6459 /* Half precision conversions.  */
6460 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
6461 {
6462     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6463     float32 r = float16_to_float32(make_float16(a), ieee, s);
6464     if (ieee) {
6465         return float32_maybe_silence_nan(r);
6466     }
6467     return r;
6468 }
6469
6470 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
6471 {
6472     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6473     float16 r = float32_to_float16(a, ieee, s);
6474     if (ieee) {
6475         r = float16_maybe_silence_nan(r);
6476     }
6477     return float16_val(r);
6478 }
6479
6480 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
6481 {
6482     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
6483 }
6484
6485 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
6486 {
6487     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
6488 }
6489
6490 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
6491 {
6492     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
6493 }
6494
6495 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
6496 {
6497     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
6498 }
6499
6500 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
6501 {
6502     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6503     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
6504     if (ieee) {
6505         return float64_maybe_silence_nan(r);
6506     }
6507     return r;
6508 }
6509
6510 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
6511 {
6512     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6513     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
6514     if (ieee) {
6515         r = float16_maybe_silence_nan(r);
6516     }
6517     return float16_val(r);
6518 }
6519
6520 #define float32_two make_float32(0x40000000)
6521 #define float32_three make_float32(0x40400000)
6522 #define float32_one_point_five make_float32(0x3fc00000)
6523
6524 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
6525 {
6526     float_status *s = &env->vfp.standard_fp_status;
6527     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
6528         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
6529         if (!(float32_is_zero(a) || float32_is_zero(b))) {
6530             float_raise(float_flag_input_denormal, s);
6531         }
6532         return float32_two;
6533     }
6534     return float32_sub(float32_two, float32_mul(a, b, s), s);
6535 }
6536
6537 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
6538 {
6539     float_status *s = &env->vfp.standard_fp_status;
6540     float32 product;
6541     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
6542         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
6543         if (!(float32_is_zero(a) || float32_is_zero(b))) {
6544             float_raise(float_flag_input_denormal, s);
6545         }
6546         return float32_one_point_five;
6547     }
6548     product = float32_mul(a, b, s);
6549     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
6550 }
6551
6552 /* NEON helpers.  */
6553
6554 /* Constants 256 and 512 are used in some helpers; we avoid relying on
6555  * int->float conversions at run-time.  */
6556 #define float64_256 make_float64(0x4070000000000000LL)
6557 #define float64_512 make_float64(0x4080000000000000LL)
6558 #define float32_maxnorm make_float32(0x7f7fffff)
6559 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
6560
6561 /* Reciprocal functions
6562  *
6563  * The algorithm that must be used to calculate the estimate
6564  * is specified by the ARM ARM, see FPRecipEstimate()
6565  */
6566
6567 static float64 recip_estimate(float64 a, float_status *real_fp_status)
6568 {
6569     /* These calculations mustn't set any fp exception flags,
6570      * so we use a local copy of the fp_status.
6571      */
6572     float_status dummy_status = *real_fp_status;
6573     float_status *s = &dummy_status;
6574     /* q = (int)(a * 512.0) */
6575     float64 q = float64_mul(float64_512, a, s);
6576     int64_t q_int = float64_to_int64_round_to_zero(q, s);
6577
6578     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
6579     q = int64_to_float64(q_int, s);
6580     q = float64_add(q, float64_half, s);
6581     q = float64_div(q, float64_512, s);
6582     q = float64_div(float64_one, q, s);
6583
6584     /* s = (int)(256.0 * r + 0.5) */
6585     q = float64_mul(q, float64_256, s);
6586     q = float64_add(q, float64_half, s);
6587     q_int = float64_to_int64_round_to_zero(q, s);
6588
6589     /* return (double)s / 256.0 */
6590     return float64_div(int64_to_float64(q_int, s), float64_256, s);
6591 }
6592
6593 /* Common wrapper to call recip_estimate */
6594 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
6595 {
6596     uint64_t val64 = float64_val(num);
6597     uint64_t frac = extract64(val64, 0, 52);
6598     int64_t exp = extract64(val64, 52, 11);
6599     uint64_t sbit;
6600     float64 scaled, estimate;
6601
6602     /* Generate the scaled number for the estimate function */
6603     if (exp == 0) {
6604         if (extract64(frac, 51, 1) == 0) {
6605             exp = -1;
6606             frac = extract64(frac, 0, 50) << 2;
6607         } else {
6608             frac = extract64(frac, 0, 51) << 1;
6609         }
6610     }
6611
6612     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
6613     scaled = make_float64((0x3feULL << 52)
6614                           | extract64(frac, 44, 8) << 44);
6615
6616     estimate = recip_estimate(scaled, fpst);
6617
6618     /* Build new result */
6619     val64 = float64_val(estimate);
6620     sbit = 0x8000000000000000ULL & val64;
6621     exp = off - exp;
6622     frac = extract64(val64, 0, 52);
6623
6624     if (exp == 0) {
6625         frac = 1ULL << 51 | extract64(frac, 1, 51);
6626     } else if (exp == -1) {
6627         frac = 1ULL << 50 | extract64(frac, 2, 50);
6628         exp = 0;
6629     }
6630
6631     return make_float64(sbit | (exp << 52) | frac);
6632 }
6633
6634 static bool round_to_inf(float_status *fpst, bool sign_bit)
6635 {
6636     switch (fpst->float_rounding_mode) {
6637     case float_round_nearest_even: /* Round to Nearest */
6638         return true;
6639     case float_round_up: /* Round to +Inf */
6640         return !sign_bit;
6641     case float_round_down: /* Round to -Inf */
6642         return sign_bit;
6643     case float_round_to_zero: /* Round to Zero */
6644         return false;
6645     }
6646
6647     g_assert_not_reached();
6648 }
6649
6650 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
6651 {
6652     float_status *fpst = fpstp;
6653     float32 f32 = float32_squash_input_denormal(input, fpst);
6654     uint32_t f32_val = float32_val(f32);
6655     uint32_t f32_sbit = 0x80000000ULL & f32_val;
6656     int32_t f32_exp = extract32(f32_val, 23, 8);
6657     uint32_t f32_frac = extract32(f32_val, 0, 23);
6658     float64 f64, r64;
6659     uint64_t r64_val;
6660     int64_t r64_exp;
6661     uint64_t r64_frac;
6662
6663     if (float32_is_any_nan(f32)) {
6664         float32 nan = f32;
6665         if (float32_is_signaling_nan(f32)) {
6666             float_raise(float_flag_invalid, fpst);
6667             nan = float32_maybe_silence_nan(f32);
6668         }
6669         if (fpst->default_nan_mode) {
6670             nan =  float32_default_nan;
6671         }
6672         return nan;
6673     } else if (float32_is_infinity(f32)) {
6674         return float32_set_sign(float32_zero, float32_is_neg(f32));
6675     } else if (float32_is_zero(f32)) {
6676         float_raise(float_flag_divbyzero, fpst);
6677         return float32_set_sign(float32_infinity, float32_is_neg(f32));
6678     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
6679         /* Abs(value) < 2.0^-128 */
6680         float_raise(float_flag_overflow | float_flag_inexact, fpst);
6681         if (round_to_inf(fpst, f32_sbit)) {
6682             return float32_set_sign(float32_infinity, float32_is_neg(f32));
6683         } else {
6684             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
6685         }
6686     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
6687         float_raise(float_flag_underflow, fpst);
6688         return float32_set_sign(float32_zero, float32_is_neg(f32));
6689     }
6690
6691
6692     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
6693     r64 = call_recip_estimate(f64, 253, fpst);
6694     r64_val = float64_val(r64);
6695     r64_exp = extract64(r64_val, 52, 11);
6696     r64_frac = extract64(r64_val, 0, 52);
6697
6698     /* result = sign : result_exp<7:0> : fraction<51:29>; */
6699     return make_float32(f32_sbit |
6700                         (r64_exp & 0xff) << 23 |
6701                         extract64(r64_frac, 29, 24));
6702 }
6703
6704 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
6705 {
6706     float_status *fpst = fpstp;
6707     float64 f64 = float64_squash_input_denormal(input, fpst);
6708     uint64_t f64_val = float64_val(f64);
6709     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
6710     int64_t f64_exp = extract64(f64_val, 52, 11);
6711     float64 r64;
6712     uint64_t r64_val;
6713     int64_t r64_exp;
6714     uint64_t r64_frac;
6715
6716     /* Deal with any special cases */
6717     if (float64_is_any_nan(f64)) {
6718         float64 nan = f64;
6719         if (float64_is_signaling_nan(f64)) {
6720             float_raise(float_flag_invalid, fpst);
6721             nan = float64_maybe_silence_nan(f64);
6722         }
6723         if (fpst->default_nan_mode) {
6724             nan =  float64_default_nan;
6725         }
6726         return nan;
6727     } else if (float64_is_infinity(f64)) {
6728         return float64_set_sign(float64_zero, float64_is_neg(f64));
6729     } else if (float64_is_zero(f64)) {
6730         float_raise(float_flag_divbyzero, fpst);
6731         return float64_set_sign(float64_infinity, float64_is_neg(f64));
6732     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
6733         /* Abs(value) < 2.0^-1024 */
6734         float_raise(float_flag_overflow | float_flag_inexact, fpst);
6735         if (round_to_inf(fpst, f64_sbit)) {
6736             return float64_set_sign(float64_infinity, float64_is_neg(f64));
6737         } else {
6738             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
6739         }
6740     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
6741         float_raise(float_flag_underflow, fpst);
6742         return float64_set_sign(float64_zero, float64_is_neg(f64));
6743     }
6744
6745     r64 = call_recip_estimate(f64, 2045, fpst);
6746     r64_val = float64_val(r64);
6747     r64_exp = extract64(r64_val, 52, 11);
6748     r64_frac = extract64(r64_val, 0, 52);
6749
6750     /* result = sign : result_exp<10:0> : fraction<51:0> */
6751     return make_float64(f64_sbit |
6752                         ((r64_exp & 0x7ff) << 52) |
6753                         r64_frac);
6754 }
6755
6756 /* The algorithm that must be used to calculate the estimate
6757  * is specified by the ARM ARM.
6758  */
6759 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
6760 {
6761     /* These calculations mustn't set any fp exception flags,
6762      * so we use a local copy of the fp_status.
6763      */
6764     float_status dummy_status = *real_fp_status;
6765     float_status *s = &dummy_status;
6766     float64 q;
6767     int64_t q_int;
6768
6769     if (float64_lt(a, float64_half, s)) {
6770         /* range 0.25 <= a < 0.5 */
6771
6772         /* a in units of 1/512 rounded down */
6773         /* q0 = (int)(a * 512.0);  */
6774         q = float64_mul(float64_512, a, s);
6775         q_int = float64_to_int64_round_to_zero(q, s);
6776
6777         /* reciprocal root r */
6778         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
6779         q = int64_to_float64(q_int, s);
6780         q = float64_add(q, float64_half, s);
6781         q = float64_div(q, float64_512, s);
6782         q = float64_sqrt(q, s);
6783         q = float64_div(float64_one, q, s);
6784     } else {
6785         /* range 0.5 <= a < 1.0 */
6786
6787         /* a in units of 1/256 rounded down */
6788         /* q1 = (int)(a * 256.0); */
6789         q = float64_mul(float64_256, a, s);
6790         int64_t q_int = float64_to_int64_round_to_zero(q, s);
6791
6792         /* reciprocal root r */
6793         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
6794         q = int64_to_float64(q_int, s);
6795         q = float64_add(q, float64_half, s);
6796         q = float64_div(q, float64_256, s);
6797         q = float64_sqrt(q, s);
6798         q = float64_div(float64_one, q, s);
6799     }
6800     /* r in units of 1/256 rounded to nearest */
6801     /* s = (int)(256.0 * r + 0.5); */
6802
6803     q = float64_mul(q, float64_256,s );
6804     q = float64_add(q, float64_half, s);
6805     q_int = float64_to_int64_round_to_zero(q, s);
6806
6807     /* return (double)s / 256.0;*/
6808     return float64_div(int64_to_float64(q_int, s), float64_256, s);
6809 }
6810
6811 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
6812 {
6813     float_status *s = fpstp;
6814     float32 f32 = float32_squash_input_denormal(input, s);
6815     uint32_t val = float32_val(f32);
6816     uint32_t f32_sbit = 0x80000000 & val;
6817     int32_t f32_exp = extract32(val, 23, 8);
6818     uint32_t f32_frac = extract32(val, 0, 23);
6819     uint64_t f64_frac;
6820     uint64_t val64;
6821     int result_exp;
6822     float64 f64;
6823
6824     if (float32_is_any_nan(f32)) {
6825         float32 nan = f32;
6826         if (float32_is_signaling_nan(f32)) {
6827             float_raise(float_flag_invalid, s);
6828             nan = float32_maybe_silence_nan(f32);
6829         }
6830         if (s->default_nan_mode) {
6831             nan =  float32_default_nan;
6832         }
6833         return nan;
6834     } else if (float32_is_zero(f32)) {
6835         float_raise(float_flag_divbyzero, s);
6836         return float32_set_sign(float32_infinity, float32_is_neg(f32));
6837     } else if (float32_is_neg(f32)) {
6838         float_raise(float_flag_invalid, s);
6839         return float32_default_nan;
6840     } else if (float32_is_infinity(f32)) {
6841         return float32_zero;
6842     }
6843
6844     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
6845      * preserving the parity of the exponent.  */
6846
6847     f64_frac = ((uint64_t) f32_frac) << 29;
6848     if (f32_exp == 0) {
6849         while (extract64(f64_frac, 51, 1) == 0) {
6850             f64_frac = f64_frac << 1;
6851             f32_exp = f32_exp-1;
6852         }
6853         f64_frac = extract64(f64_frac, 0, 51) << 1;
6854     }
6855
6856     if (extract64(f32_exp, 0, 1) == 0) {
6857         f64 = make_float64(((uint64_t) f32_sbit) << 32
6858                            | (0x3feULL << 52)
6859                            | f64_frac);
6860     } else {
6861         f64 = make_float64(((uint64_t) f32_sbit) << 32
6862                            | (0x3fdULL << 52)
6863                            | f64_frac);
6864     }
6865
6866     result_exp = (380 - f32_exp) / 2;
6867
6868     f64 = recip_sqrt_estimate(f64, s);
6869
6870     val64 = float64_val(f64);
6871
6872     val = ((result_exp & 0xff) << 23)
6873         | ((val64 >> 29)  & 0x7fffff);
6874     return make_float32(val);
6875 }
6876
6877 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
6878 {
6879     float_status *s = fpstp;
6880     float64 f64 = float64_squash_input_denormal(input, s);
6881     uint64_t val = float64_val(f64);
6882     uint64_t f64_sbit = 0x8000000000000000ULL & val;
6883     int64_t f64_exp = extract64(val, 52, 11);
6884     uint64_t f64_frac = extract64(val, 0, 52);
6885     int64_t result_exp;
6886     uint64_t result_frac;
6887
6888     if (float64_is_any_nan(f64)) {
6889         float64 nan = f64;
6890         if (float64_is_signaling_nan(f64)) {
6891             float_raise(float_flag_invalid, s);
6892             nan = float64_maybe_silence_nan(f64);
6893         }
6894         if (s->default_nan_mode) {
6895             nan =  float64_default_nan;
6896         }
6897         return nan;
6898     } else if (float64_is_zero(f64)) {
6899         float_raise(float_flag_divbyzero, s);
6900         return float64_set_sign(float64_infinity, float64_is_neg(f64));
6901     } else if (float64_is_neg(f64)) {
6902         float_raise(float_flag_invalid, s);
6903         return float64_default_nan;
6904     } else if (float64_is_infinity(f64)) {
6905         return float64_zero;
6906     }
6907
6908     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
6909      * preserving the parity of the exponent.  */
6910
6911     if (f64_exp == 0) {
6912         while (extract64(f64_frac, 51, 1) == 0) {
6913             f64_frac = f64_frac << 1;
6914             f64_exp = f64_exp - 1;
6915         }
6916         f64_frac = extract64(f64_frac, 0, 51) << 1;
6917     }
6918
6919     if (extract64(f64_exp, 0, 1) == 0) {
6920         f64 = make_float64(f64_sbit
6921                            | (0x3feULL << 52)
6922                            | f64_frac);
6923     } else {
6924         f64 = make_float64(f64_sbit
6925                            | (0x3fdULL << 52)
6926                            | f64_frac);
6927     }
6928
6929     result_exp = (3068 - f64_exp) / 2;
6930
6931     f64 = recip_sqrt_estimate(f64, s);
6932
6933     result_frac = extract64(float64_val(f64), 0, 52);
6934
6935     return make_float64(f64_sbit |
6936                         ((result_exp & 0x7ff) << 52) |
6937                         result_frac);
6938 }
6939
6940 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
6941 {
6942     float_status *s = fpstp;
6943     float64 f64;
6944
6945     if ((a & 0x80000000) == 0) {
6946         return 0xffffffff;
6947     }
6948
6949     f64 = make_float64((0x3feULL << 52)
6950                        | ((int64_t)(a & 0x7fffffff) << 21));
6951
6952     f64 = recip_estimate(f64, s);
6953
6954     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
6955 }
6956
6957 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
6958 {
6959     float_status *fpst = fpstp;
6960     float64 f64;
6961
6962     if ((a & 0xc0000000) == 0) {
6963         return 0xffffffff;
6964     }
6965
6966     if (a & 0x80000000) {
6967         f64 = make_float64((0x3feULL << 52)
6968                            | ((uint64_t)(a & 0x7fffffff) << 21));
6969     } else { /* bits 31-30 == '01' */
6970         f64 = make_float64((0x3fdULL << 52)
6971                            | ((uint64_t)(a & 0x3fffffff) << 22));
6972     }
6973
6974     f64 = recip_sqrt_estimate(f64, fpst);
6975
6976     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
6977 }
6978
6979 /* VFPv4 fused multiply-accumulate */
6980 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
6981 {
6982     float_status *fpst = fpstp;
6983     return float32_muladd(a, b, c, 0, fpst);
6984 }
6985
6986 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
6987 {
6988     float_status *fpst = fpstp;
6989     return float64_muladd(a, b, c, 0, fpst);
6990 }
6991
6992 /* ARMv8 round to integral */
6993 float32 HELPER(rints_exact)(float32 x, void *fp_status)
6994 {
6995     return float32_round_to_int(x, fp_status);
6996 }
6997
6998 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
6999 {
7000     return float64_round_to_int(x, fp_status);
7001 }
7002
7003 float32 HELPER(rints)(float32 x, void *fp_status)
7004 {
7005     int old_flags = get_float_exception_flags(fp_status), new_flags;
7006     float32 ret;
7007
7008     ret = float32_round_to_int(x, fp_status);
7009
7010     /* Suppress any inexact exceptions the conversion produced */
7011     if (!(old_flags & float_flag_inexact)) {
7012         new_flags = get_float_exception_flags(fp_status);
7013         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
7014     }
7015
7016     return ret;
7017 }
7018
7019 float64 HELPER(rintd)(float64 x, void *fp_status)
7020 {
7021     int old_flags = get_float_exception_flags(fp_status), new_flags;
7022     float64 ret;
7023
7024     ret = float64_round_to_int(x, fp_status);
7025
7026     new_flags = get_float_exception_flags(fp_status);
7027
7028     /* Suppress any inexact exceptions the conversion produced */
7029     if (!(old_flags & float_flag_inexact)) {
7030         new_flags = get_float_exception_flags(fp_status);
7031         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
7032     }
7033
7034     return ret;
7035 }
7036
7037 /* Convert ARM rounding mode to softfloat */
7038 int arm_rmode_to_sf(int rmode)
7039 {
7040     switch (rmode) {
7041     case FPROUNDING_TIEAWAY:
7042         rmode = float_round_ties_away;
7043         break;
7044     case FPROUNDING_ODD:
7045         /* FIXME: add support for TIEAWAY and ODD */
7046         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
7047                       rmode);
7048     case FPROUNDING_TIEEVEN:
7049     default:
7050         rmode = float_round_nearest_even;
7051         break;
7052     case FPROUNDING_POSINF:
7053         rmode = float_round_up;
7054         break;
7055     case FPROUNDING_NEGINF:
7056         rmode = float_round_down;
7057         break;
7058     case FPROUNDING_ZERO:
7059         rmode = float_round_to_zero;
7060         break;
7061     }
7062     return rmode;
7063 }
7064
7065 /* CRC helpers.
7066  * The upper bytes of val (above the number specified by 'bytes') must have
7067  * been zeroed out by the caller.
7068  */
7069 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
7070 {
7071     uint8_t buf[4];
7072
7073     stl_le_p(buf, val);
7074
7075     /* zlib crc32 converts the accumulator and output to one's complement.  */
7076     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
7077 }
7078
7079 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
7080 {
7081     uint8_t buf[4];
7082
7083     stl_le_p(buf, val);
7084
7085     /* Linux crc32c converts the output to one's complement.  */
7086     return crc32c(acc, buf, bytes) ^ 0xffffffff;
7087 }