4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu-common.h"
23 #include "qemu/host-utils.h"
25 #include "disas/disas.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
32 #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64)
36 #include "trace-tcg.h"
39 #define PREFIX_REPZ 0x01
40 #define PREFIX_REPNZ 0x02
41 #define PREFIX_LOCK 0x04
42 #define PREFIX_DATA 0x08
43 #define PREFIX_ADR 0x10
44 #define PREFIX_VEX 0x20
47 #define CODE64(s) ((s)->code64)
48 #define REX_X(s) ((s)->rex_x)
49 #define REX_B(s) ((s)->rex_b)
64 //#define MACRO_TEST 1
66 /* global register indexes */
67 static TCGv_ptr cpu_env
;
69 static TCGv cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
, cpu_cc_srcT
;
70 static TCGv_i32 cpu_cc_op
;
71 static TCGv cpu_regs
[CPU_NB_REGS
];
74 /* local register indexes (only used inside old micro ops) */
75 static TCGv cpu_tmp0
, cpu_tmp4
;
76 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
77 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
78 static TCGv_i64 cpu_tmp1_i64
;
80 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
82 #include "exec/gen-icount.h"
85 static int x86_64_hregs
;
88 typedef struct DisasContext
{
89 /* current insn context */
90 int override
; /* -1 if no override */
94 target_ulong pc
; /* pc = eip + cs_base */
95 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
96 static state change (stop translation) */
97 /* current block context */
98 target_ulong cs_base
; /* base of CS segment */
99 int pe
; /* protected mode */
100 int code32
; /* 32 bit code segment */
102 int lma
; /* long mode active */
103 int code64
; /* 64 bit code segment */
106 int vex_l
; /* vex vector length */
107 int vex_v
; /* vex vvvv register, without 1's compliment. */
108 int ss32
; /* 32 bit stack segment */
109 CCOp cc_op
; /* current CC operation */
111 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
112 int f_st
; /* currently unused */
113 int vm86
; /* vm86 mode */
116 int tf
; /* TF cpu flag */
117 int singlestep_enabled
; /* "hardware" single step enabled */
118 int jmp_opt
; /* use direct block chaining for direct jumps */
119 int repz_opt
; /* optimize jumps within repz instructions */
120 int mem_index
; /* select memory access functions */
121 uint64_t flags
; /* all execution flags */
122 struct TranslationBlock
*tb
;
123 int popl_esp_hack
; /* for correct popl with esp base handling */
124 int rip_offset
; /* only used in x86_64, but left for simplicity */
126 int cpuid_ext_features
;
127 int cpuid_ext2_features
;
128 int cpuid_ext3_features
;
129 int cpuid_7_0_ebx_features
;
132 static void gen_eob(DisasContext
*s
);
133 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
134 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
135 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
);
137 /* i386 arith/logic operations */
157 OP_SHL1
, /* undocumented */
173 /* I386 int registers */
174 OR_EAX
, /* MUST be even numbered */
183 OR_TMP0
= 16, /* temporary operand register */
185 OR_A0
, /* temporary register used when doing address evaluation */
195 /* Bit set if the global variable is live after setting CC_OP to X. */
196 static const uint8_t cc_op_live
[CC_OP_NB
] = {
197 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
198 [CC_OP_EFLAGS
] = USES_CC_SRC
,
199 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
200 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
202 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRCT
,
203 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
204 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
205 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
206 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
207 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
208 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
209 [CC_OP_BMILGB
... CC_OP_BMILGQ
] = USES_CC_DST
| USES_CC_SRC
,
210 [CC_OP_ADCX
] = USES_CC_DST
| USES_CC_SRC
,
211 [CC_OP_ADOX
] = USES_CC_SRC
| USES_CC_SRC2
,
212 [CC_OP_ADCOX
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
216 static void set_cc_op(DisasContext
*s
, CCOp op
)
220 if (s
->cc_op
== op
) {
224 /* Discard CC computation that will no longer be used. */
225 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
226 if (dead
& USES_CC_DST
) {
227 tcg_gen_discard_tl(cpu_cc_dst
);
229 if (dead
& USES_CC_SRC
) {
230 tcg_gen_discard_tl(cpu_cc_src
);
232 if (dead
& USES_CC_SRC2
) {
233 tcg_gen_discard_tl(cpu_cc_src2
);
235 if (dead
& USES_CC_SRCT
) {
236 tcg_gen_discard_tl(cpu_cc_srcT
);
239 if (op
== CC_OP_DYNAMIC
) {
240 /* The DYNAMIC setting is translator only, and should never be
241 stored. Thus we always consider it clean. */
242 s
->cc_op_dirty
= false;
244 /* Discard any computed CC_OP value (see shifts). */
245 if (s
->cc_op
== CC_OP_DYNAMIC
) {
246 tcg_gen_discard_i32(cpu_cc_op
);
248 s
->cc_op_dirty
= true;
253 static void gen_update_cc_op(DisasContext
*s
)
255 if (s
->cc_op_dirty
) {
256 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
257 s
->cc_op_dirty
= false;
263 #define NB_OP_SIZES 4
265 #else /* !TARGET_X86_64 */
267 #define NB_OP_SIZES 3
269 #endif /* !TARGET_X86_64 */
271 #if defined(HOST_WORDS_BIGENDIAN)
272 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
273 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
274 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
275 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
276 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
278 #define REG_B_OFFSET 0
279 #define REG_H_OFFSET 1
280 #define REG_W_OFFSET 0
281 #define REG_L_OFFSET 0
282 #define REG_LH_OFFSET 4
285 /* In instruction encodings for byte register accesses the
286 * register number usually indicates "low 8 bits of register N";
287 * however there are some special cases where N 4..7 indicates
288 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
289 * true for this special case, false otherwise.
291 static inline bool byte_reg_is_xH(int reg
)
297 if (reg
>= 8 || x86_64_hregs
) {
304 /* Select the size of a push/pop operation. */
305 static inline TCGMemOp
mo_pushpop(DisasContext
*s
, TCGMemOp ot
)
308 return ot
== MO_16
? MO_16
: MO_64
;
314 /* Select only size 64 else 32. Used for SSE operand sizes. */
315 static inline TCGMemOp
mo_64_32(TCGMemOp ot
)
318 return ot
== MO_64
? MO_64
: MO_32
;
324 /* Select size 8 if lsb of B is clear, else OT. Used for decoding
325 byte vs word opcodes. */
326 static inline TCGMemOp
mo_b_d(int b
, TCGMemOp ot
)
328 return b
& 1 ? ot
: MO_8
;
331 /* Select size 8 if lsb of B is clear, else OT capped at 32.
332 Used for decoding operand size of port opcodes. */
333 static inline TCGMemOp
mo_b_d32(int b
, TCGMemOp ot
)
335 return b
& 1 ? (ot
== MO_16
? MO_16
: MO_32
) : MO_8
;
338 static void gen_op_mov_reg_v(TCGMemOp ot
, int reg
, TCGv t0
)
342 if (!byte_reg_is_xH(reg
)) {
343 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
345 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
349 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
352 /* For x86_64, this sets the higher half of register to zero.
353 For i386, this is equivalent to a mov. */
354 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
358 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
366 static inline void gen_op_mov_v_reg(TCGMemOp ot
, TCGv t0
, int reg
)
368 if (ot
== MO_8
&& byte_reg_is_xH(reg
)) {
369 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
370 tcg_gen_ext8u_tl(t0
, t0
);
372 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
376 static inline void gen_op_movl_A0_reg(int reg
)
378 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
381 static inline void gen_op_addl_A0_im(int32_t val
)
383 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
385 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
390 static inline void gen_op_addq_A0_im(int64_t val
)
392 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
396 static void gen_add_A0_im(DisasContext
*s
, int val
)
400 gen_op_addq_A0_im(val
);
403 gen_op_addl_A0_im(val
);
406 static inline void gen_op_jmp_v(TCGv dest
)
408 tcg_gen_st_tl(dest
, cpu_env
, offsetof(CPUX86State
, eip
));
411 static inline void gen_op_add_reg_im(TCGMemOp size
, int reg
, int32_t val
)
413 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
414 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
417 static inline void gen_op_add_reg_T0(TCGMemOp size
, int reg
)
419 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
420 gen_op_mov_reg_v(size
, reg
, cpu_tmp0
);
423 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
425 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
427 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
428 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
429 /* For x86_64, this sets the higher half of register to zero.
430 For i386, this is equivalent to a nop. */
431 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
434 static inline void gen_op_movl_A0_seg(int reg
)
436 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
439 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
441 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
444 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
445 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
447 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
448 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
451 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
456 static inline void gen_op_movq_A0_seg(int reg
)
458 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
461 static inline void gen_op_addq_A0_seg(int reg
)
463 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
464 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
467 static inline void gen_op_movq_A0_reg(int reg
)
469 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
472 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
474 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
476 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
477 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
481 static inline void gen_op_ld_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
483 tcg_gen_qemu_ld_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
486 static inline void gen_op_st_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
488 tcg_gen_qemu_st_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
491 static inline void gen_op_st_rm_T0_A0(DisasContext
*s
, int idx
, int d
)
494 gen_op_st_v(s
, idx
, cpu_T
[0], cpu_A0
);
496 gen_op_mov_reg_v(idx
, d
, cpu_T
[0]);
500 static inline void gen_jmp_im(target_ulong pc
)
502 tcg_gen_movi_tl(cpu_tmp0
, pc
);
503 gen_op_jmp_v(cpu_tmp0
);
506 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
510 override
= s
->override
;
515 gen_op_movq_A0_seg(override
);
516 gen_op_addq_A0_reg_sN(0, R_ESI
);
518 gen_op_movq_A0_reg(R_ESI
);
524 if (s
->addseg
&& override
< 0)
527 gen_op_movl_A0_seg(override
);
528 gen_op_addl_A0_reg_sN(0, R_ESI
);
530 gen_op_movl_A0_reg(R_ESI
);
534 /* 16 address, always override */
537 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_ESI
]);
538 gen_op_addl_A0_seg(s
, override
);
545 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
550 gen_op_movq_A0_reg(R_EDI
);
555 gen_op_movl_A0_seg(R_ES
);
556 gen_op_addl_A0_reg_sN(0, R_EDI
);
558 gen_op_movl_A0_reg(R_EDI
);
562 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_EDI
]);
563 gen_op_addl_A0_seg(s
, R_ES
);
570 static inline void gen_op_movl_T0_Dshift(TCGMemOp ot
)
572 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
573 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
576 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, TCGMemOp size
, bool sign
)
581 tcg_gen_ext8s_tl(dst
, src
);
583 tcg_gen_ext8u_tl(dst
, src
);
588 tcg_gen_ext16s_tl(dst
, src
);
590 tcg_gen_ext16u_tl(dst
, src
);
596 tcg_gen_ext32s_tl(dst
, src
);
598 tcg_gen_ext32u_tl(dst
, src
);
607 static void gen_extu(TCGMemOp ot
, TCGv reg
)
609 gen_ext_tl(reg
, reg
, ot
, false);
612 static void gen_exts(TCGMemOp ot
, TCGv reg
)
614 gen_ext_tl(reg
, reg
, ot
, true);
617 static inline void gen_op_jnz_ecx(TCGMemOp size
, TCGLabel
*label1
)
619 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
620 gen_extu(size
, cpu_tmp0
);
621 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
624 static inline void gen_op_jz_ecx(TCGMemOp size
, TCGLabel
*label1
)
626 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
627 gen_extu(size
, cpu_tmp0
);
628 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
631 static void gen_helper_in_func(TCGMemOp ot
, TCGv v
, TCGv_i32 n
)
635 gen_helper_inb(v
, cpu_env
, n
);
638 gen_helper_inw(v
, cpu_env
, n
);
641 gen_helper_inl(v
, cpu_env
, n
);
648 static void gen_helper_out_func(TCGMemOp ot
, TCGv_i32 v
, TCGv_i32 n
)
652 gen_helper_outb(cpu_env
, v
, n
);
655 gen_helper_outw(cpu_env
, v
, n
);
658 gen_helper_outl(cpu_env
, v
, n
);
665 static void gen_check_io(DisasContext
*s
, TCGMemOp ot
, target_ulong cur_eip
,
669 target_ulong next_eip
;
672 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
676 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
679 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
682 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
685 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
691 if(s
->flags
& HF_SVMI_MASK
) {
696 svm_flags
|= (1 << (4 + ot
));
697 next_eip
= s
->pc
- s
->cs_base
;
698 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
699 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
700 tcg_const_i32(svm_flags
),
701 tcg_const_i32(next_eip
- cur_eip
));
705 static inline void gen_movs(DisasContext
*s
, TCGMemOp ot
)
707 gen_string_movl_A0_ESI(s
);
708 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
709 gen_string_movl_A0_EDI(s
);
710 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
711 gen_op_movl_T0_Dshift(ot
);
712 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
713 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
716 static void gen_op_update1_cc(void)
718 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
721 static void gen_op_update2_cc(void)
723 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
724 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
727 static void gen_op_update3_cc(TCGv reg
)
729 tcg_gen_mov_tl(cpu_cc_src2
, reg
);
730 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
731 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
734 static inline void gen_op_testl_T0_T1_cc(void)
736 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
739 static void gen_op_update_neg_cc(void)
741 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
742 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
743 tcg_gen_movi_tl(cpu_cc_srcT
, 0);
746 /* compute all eflags to cc_src */
747 static void gen_compute_eflags(DisasContext
*s
)
749 TCGv zero
, dst
, src1
, src2
;
752 if (s
->cc_op
== CC_OP_EFLAGS
) {
755 if (s
->cc_op
== CC_OP_CLR
) {
756 tcg_gen_movi_tl(cpu_cc_src
, CC_Z
| CC_P
);
757 set_cc_op(s
, CC_OP_EFLAGS
);
766 /* Take care to not read values that are not live. */
767 live
= cc_op_live
[s
->cc_op
] & ~USES_CC_SRCT
;
768 dead
= live
^ (USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
);
770 zero
= tcg_const_tl(0);
771 if (dead
& USES_CC_DST
) {
774 if (dead
& USES_CC_SRC
) {
777 if (dead
& USES_CC_SRC2
) {
783 gen_helper_cc_compute_all(cpu_cc_src
, dst
, src1
, src2
, cpu_cc_op
);
784 set_cc_op(s
, CC_OP_EFLAGS
);
791 typedef struct CCPrepare
{
801 /* compute eflags.C to reg */
802 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
808 case CC_OP_SUBB
... CC_OP_SUBQ
:
809 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
810 size
= s
->cc_op
- CC_OP_SUBB
;
811 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
812 /* If no temporary was used, be careful not to alias t1 and t0. */
813 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
814 tcg_gen_mov_tl(t0
, cpu_cc_srcT
);
818 case CC_OP_ADDB
... CC_OP_ADDQ
:
819 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
820 size
= s
->cc_op
- CC_OP_ADDB
;
821 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
822 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
824 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
825 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
827 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
829 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
831 case CC_OP_INCB
... CC_OP_INCQ
:
832 case CC_OP_DECB
... CC_OP_DECQ
:
833 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
834 .mask
= -1, .no_setcond
= true };
836 case CC_OP_SHLB
... CC_OP_SHLQ
:
837 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
838 size
= s
->cc_op
- CC_OP_SHLB
;
839 shift
= (8 << size
) - 1;
840 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
841 .mask
= (target_ulong
)1 << shift
};
843 case CC_OP_MULB
... CC_OP_MULQ
:
844 return (CCPrepare
) { .cond
= TCG_COND_NE
,
845 .reg
= cpu_cc_src
, .mask
= -1 };
847 case CC_OP_BMILGB
... CC_OP_BMILGQ
:
848 size
= s
->cc_op
- CC_OP_BMILGB
;
849 t0
= gen_ext_tl(reg
, cpu_cc_src
, size
, false);
850 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
854 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_dst
,
855 .mask
= -1, .no_setcond
= true };
858 case CC_OP_SARB
... CC_OP_SARQ
:
860 return (CCPrepare
) { .cond
= TCG_COND_NE
,
861 .reg
= cpu_cc_src
, .mask
= CC_C
};
864 /* The need to compute only C from CC_OP_DYNAMIC is important
865 in efficiently implementing e.g. INC at the start of a TB. */
867 gen_helper_cc_compute_c(reg
, cpu_cc_dst
, cpu_cc_src
,
868 cpu_cc_src2
, cpu_cc_op
);
869 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
870 .mask
= -1, .no_setcond
= true };
874 /* compute eflags.P to reg */
875 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
877 gen_compute_eflags(s
);
878 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
882 /* compute eflags.S to reg */
883 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
887 gen_compute_eflags(s
);
893 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
896 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
899 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
900 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
901 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
906 /* compute eflags.O to reg */
907 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
912 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src2
,
913 .mask
= -1, .no_setcond
= true };
915 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
917 gen_compute_eflags(s
);
918 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
923 /* compute eflags.Z to reg */
924 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
928 gen_compute_eflags(s
);
934 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
937 return (CCPrepare
) { .cond
= TCG_COND_ALWAYS
, .mask
= -1 };
940 TCGMemOp size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
941 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
942 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
947 /* perform a conditional store into register 'reg' according to jump opcode
948 value 'b'. In the fast case, T0 is guaranted not to be used. */
949 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
951 int inv
, jcc_op
, cond
;
957 jcc_op
= (b
>> 1) & 7;
960 case CC_OP_SUBB
... CC_OP_SUBQ
:
961 /* We optimize relational operators for the cmp/jcc case. */
962 size
= s
->cc_op
- CC_OP_SUBB
;
965 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
966 gen_extu(size
, cpu_tmp4
);
967 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
968 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
969 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
978 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
979 gen_exts(size
, cpu_tmp4
);
980 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
981 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
982 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
992 /* This actually generates good code for JC, JZ and JS. */
995 cc
= gen_prepare_eflags_o(s
, reg
);
998 cc
= gen_prepare_eflags_c(s
, reg
);
1001 cc
= gen_prepare_eflags_z(s
, reg
);
1004 gen_compute_eflags(s
);
1005 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1006 .mask
= CC_Z
| CC_C
};
1009 cc
= gen_prepare_eflags_s(s
, reg
);
1012 cc
= gen_prepare_eflags_p(s
, reg
);
1015 gen_compute_eflags(s
);
1016 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1019 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1020 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1021 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1026 gen_compute_eflags(s
);
1027 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1030 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1031 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1032 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1033 .mask
= CC_S
| CC_Z
};
1040 cc
.cond
= tcg_invert_cond(cc
.cond
);
1045 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1047 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1049 if (cc
.no_setcond
) {
1050 if (cc
.cond
== TCG_COND_EQ
) {
1051 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1053 tcg_gen_mov_tl(reg
, cc
.reg
);
1058 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1059 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1060 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1061 tcg_gen_andi_tl(reg
, reg
, 1);
1064 if (cc
.mask
!= -1) {
1065 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1069 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1071 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1075 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1077 gen_setcc1(s
, JCC_B
<< 1, reg
);
1080 /* generate a conditional jump to label 'l1' according to jump opcode
1081 value 'b'. In the fast case, T0 is guaranted not to be used. */
1082 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, TCGLabel
*l1
)
1084 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1086 if (cc
.mask
!= -1) {
1087 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1091 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1093 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1097 /* Generate a conditional jump to label 'l1' according to jump opcode
1098 value 'b'. In the fast case, T0 is guaranted not to be used.
1099 A translation block must end soon. */
1100 static inline void gen_jcc1(DisasContext
*s
, int b
, TCGLabel
*l1
)
1102 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1104 gen_update_cc_op(s
);
1105 if (cc
.mask
!= -1) {
1106 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1109 set_cc_op(s
, CC_OP_DYNAMIC
);
1111 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1113 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1117 /* XXX: does not work with gdbstub "ice" single step - not a
1119 static TCGLabel
*gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1121 TCGLabel
*l1
= gen_new_label();
1122 TCGLabel
*l2
= gen_new_label();
1123 gen_op_jnz_ecx(s
->aflag
, l1
);
1125 gen_jmp_tb(s
, next_eip
, 1);
1130 static inline void gen_stos(DisasContext
*s
, TCGMemOp ot
)
1132 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EAX
);
1133 gen_string_movl_A0_EDI(s
);
1134 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1135 gen_op_movl_T0_Dshift(ot
);
1136 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1139 static inline void gen_lods(DisasContext
*s
, TCGMemOp ot
)
1141 gen_string_movl_A0_ESI(s
);
1142 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1143 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[0]);
1144 gen_op_movl_T0_Dshift(ot
);
1145 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1148 static inline void gen_scas(DisasContext
*s
, TCGMemOp ot
)
1150 gen_string_movl_A0_EDI(s
);
1151 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1152 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1153 gen_op_movl_T0_Dshift(ot
);
1154 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1157 static inline void gen_cmps(DisasContext
*s
, TCGMemOp ot
)
1159 gen_string_movl_A0_EDI(s
);
1160 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1161 gen_string_movl_A0_ESI(s
);
1162 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1163 gen_op_movl_T0_Dshift(ot
);
1164 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1165 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1168 static inline void gen_ins(DisasContext
*s
, TCGMemOp ot
)
1170 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
1173 gen_string_movl_A0_EDI(s
);
1174 /* Note: we must do this dummy write first to be restartable in
1175 case of page fault. */
1176 tcg_gen_movi_tl(cpu_T
[0], 0);
1177 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1178 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1179 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1180 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1181 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1182 gen_op_movl_T0_Dshift(ot
);
1183 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1184 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
1189 static inline void gen_outs(DisasContext
*s
, TCGMemOp ot
)
1191 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
1194 gen_string_movl_A0_ESI(s
);
1195 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1197 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[R_EDX
]);
1198 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1199 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1200 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1202 gen_op_movl_T0_Dshift(ot
);
1203 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1204 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
1209 /* same method as Valgrind : we generate jumps to current or next
1211 #define GEN_REPZ(op) \
1212 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1213 target_ulong cur_eip, target_ulong next_eip) \
1216 gen_update_cc_op(s); \
1217 l2 = gen_jz_ecx_string(s, next_eip); \
1218 gen_ ## op(s, ot); \
1219 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1220 /* a loop would cause two single step exceptions if ECX = 1 \
1221 before rep string_insn */ \
1223 gen_op_jz_ecx(s->aflag, l2); \
1224 gen_jmp(s, cur_eip); \
1227 #define GEN_REPZ2(op) \
1228 static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \
1229 target_ulong cur_eip, \
1230 target_ulong next_eip, \
1234 gen_update_cc_op(s); \
1235 l2 = gen_jz_ecx_string(s, next_eip); \
1236 gen_ ## op(s, ot); \
1237 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1238 gen_update_cc_op(s); \
1239 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1241 gen_op_jz_ecx(s->aflag, l2); \
1242 gen_jmp(s, cur_eip); \
1253 static void gen_helper_fp_arith_ST0_FT0(int op
)
1257 gen_helper_fadd_ST0_FT0(cpu_env
);
1260 gen_helper_fmul_ST0_FT0(cpu_env
);
1263 gen_helper_fcom_ST0_FT0(cpu_env
);
1266 gen_helper_fcom_ST0_FT0(cpu_env
);
1269 gen_helper_fsub_ST0_FT0(cpu_env
);
1272 gen_helper_fsubr_ST0_FT0(cpu_env
);
1275 gen_helper_fdiv_ST0_FT0(cpu_env
);
1278 gen_helper_fdivr_ST0_FT0(cpu_env
);
1283 /* NOTE the exception in "r" op ordering */
1284 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1286 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1289 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1292 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1295 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1298 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1301 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1304 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1309 /* if d == OR_TMP0, it means memory operand (address in A0) */
1310 static void gen_op(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
)
1313 gen_op_mov_v_reg(ot
, cpu_T
[0], d
);
1315 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1319 gen_compute_eflags_c(s1
, cpu_tmp4
);
1320 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1321 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1322 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1323 gen_op_update3_cc(cpu_tmp4
);
1324 set_cc_op(s1
, CC_OP_ADCB
+ ot
);
1327 gen_compute_eflags_c(s1
, cpu_tmp4
);
1328 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1329 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1330 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1331 gen_op_update3_cc(cpu_tmp4
);
1332 set_cc_op(s1
, CC_OP_SBBB
+ ot
);
1335 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1336 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1337 gen_op_update2_cc();
1338 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1341 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1342 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1343 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1344 gen_op_update2_cc();
1345 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1349 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1350 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1351 gen_op_update1_cc();
1352 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1355 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1356 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1357 gen_op_update1_cc();
1358 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1361 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1362 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1363 gen_op_update1_cc();
1364 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1367 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1368 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1369 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1370 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1375 /* if d == OR_TMP0, it means memory operand (address in A0) */
1376 static void gen_inc(DisasContext
*s1
, TCGMemOp ot
, int d
, int c
)
1379 gen_op_mov_v_reg(ot
, cpu_T
[0], d
);
1381 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1383 gen_compute_eflags_c(s1
, cpu_cc_src
);
1385 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1386 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1388 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1389 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1391 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1392 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1395 static void gen_shift_flags(DisasContext
*s
, TCGMemOp ot
, TCGv result
,
1396 TCGv shm1
, TCGv count
, bool is_right
)
1398 TCGv_i32 z32
, s32
, oldop
;
1401 /* Store the results into the CC variables. If we know that the
1402 variable must be dead, store unconditionally. Otherwise we'll
1403 need to not disrupt the current contents. */
1404 z_tl
= tcg_const_tl(0);
1405 if (cc_op_live
[s
->cc_op
] & USES_CC_DST
) {
1406 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_dst
, count
, z_tl
,
1407 result
, cpu_cc_dst
);
1409 tcg_gen_mov_tl(cpu_cc_dst
, result
);
1411 if (cc_op_live
[s
->cc_op
] & USES_CC_SRC
) {
1412 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_src
, count
, z_tl
,
1415 tcg_gen_mov_tl(cpu_cc_src
, shm1
);
1417 tcg_temp_free(z_tl
);
1419 /* Get the two potential CC_OP values into temporaries. */
1420 tcg_gen_movi_i32(cpu_tmp2_i32
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1421 if (s
->cc_op
== CC_OP_DYNAMIC
) {
1424 tcg_gen_movi_i32(cpu_tmp3_i32
, s
->cc_op
);
1425 oldop
= cpu_tmp3_i32
;
1428 /* Conditionally store the CC_OP value. */
1429 z32
= tcg_const_i32(0);
1430 s32
= tcg_temp_new_i32();
1431 tcg_gen_trunc_tl_i32(s32
, count
);
1432 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, s32
, z32
, cpu_tmp2_i32
, oldop
);
1433 tcg_temp_free_i32(z32
);
1434 tcg_temp_free_i32(s32
);
1436 /* The CC_OP value is no longer predictable. */
1437 set_cc_op(s
, CC_OP_DYNAMIC
);
1440 static void gen_shift_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1441 int is_right
, int is_arith
)
1443 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1446 if (op1
== OR_TMP0
) {
1447 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1449 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1452 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1453 tcg_gen_subi_tl(cpu_tmp0
, cpu_T
[1], 1);
1457 gen_exts(ot
, cpu_T
[0]);
1458 tcg_gen_sar_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1459 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1461 gen_extu(ot
, cpu_T
[0]);
1462 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1463 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1466 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1467 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1471 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1473 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, cpu_T
[1], is_right
);
1476 static void gen_shift_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1477 int is_right
, int is_arith
)
1479 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1483 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1485 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1491 gen_exts(ot
, cpu_T
[0]);
1492 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1493 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1495 gen_extu(ot
, cpu_T
[0]);
1496 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1497 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1500 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1501 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1506 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1508 /* update eflags if non zero shift */
1510 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1511 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1512 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1516 static void gen_rot_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
, int is_right
)
1518 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1522 if (op1
== OR_TMP0
) {
1523 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1525 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1528 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1532 /* Replicate the 8-bit input so that a 32-bit rotate works. */
1533 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
1534 tcg_gen_muli_tl(cpu_T
[0], cpu_T
[0], 0x01010101);
1537 /* Replicate the 16-bit input so that a 32-bit rotate works. */
1538 tcg_gen_deposit_tl(cpu_T
[0], cpu_T
[0], cpu_T
[0], 16, 16);
1541 #ifdef TARGET_X86_64
1543 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1544 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
1546 tcg_gen_rotr_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1548 tcg_gen_rotl_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1550 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1555 tcg_gen_rotr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1557 tcg_gen_rotl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1563 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1565 /* We'll need the flags computed into CC_SRC. */
1566 gen_compute_eflags(s
);
1568 /* The value that was "rotated out" is now present at the other end
1569 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1570 since we've computed the flags into CC_SRC, these variables are
1573 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1574 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1575 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1577 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1578 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1580 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1581 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1583 /* Now conditionally store the new CC_OP value. If the shift count
1584 is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
1585 Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
1586 exactly as we computed above. */
1587 t0
= tcg_const_i32(0);
1588 t1
= tcg_temp_new_i32();
1589 tcg_gen_trunc_tl_i32(t1
, cpu_T
[1]);
1590 tcg_gen_movi_i32(cpu_tmp2_i32
, CC_OP_ADCOX
);
1591 tcg_gen_movi_i32(cpu_tmp3_i32
, CC_OP_EFLAGS
);
1592 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, t1
, t0
,
1593 cpu_tmp2_i32
, cpu_tmp3_i32
);
1594 tcg_temp_free_i32(t0
);
1595 tcg_temp_free_i32(t1
);
1597 /* The CC_OP value is no longer predictable. */
1598 set_cc_op(s
, CC_OP_DYNAMIC
);
1601 static void gen_rot_rm_im(DisasContext
*s
, TCGMemOp ot
, int op1
, int op2
,
1604 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1608 if (op1
== OR_TMP0
) {
1609 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1611 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1617 #ifdef TARGET_X86_64
1619 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1621 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1623 tcg_gen_rotli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1625 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1630 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], op2
);
1632 tcg_gen_rotli_tl(cpu_T
[0], cpu_T
[0], op2
);
1643 shift
= mask
+ 1 - shift
;
1645 gen_extu(ot
, cpu_T
[0]);
1646 tcg_gen_shli_tl(cpu_tmp0
, cpu_T
[0], shift
);
1647 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], mask
+ 1 - shift
);
1648 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
1654 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1657 /* Compute the flags into CC_SRC. */
1658 gen_compute_eflags(s
);
1660 /* The value that was "rotated out" is now present at the other end
1661 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1662 since we've computed the flags into CC_SRC, these variables are
1665 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1666 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1667 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1669 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1670 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1672 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1673 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1674 set_cc_op(s
, CC_OP_ADCOX
);
1678 /* XXX: add faster immediate = 1 case */
1679 static void gen_rotc_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1682 gen_compute_eflags(s
);
1683 assert(s
->cc_op
== CC_OP_EFLAGS
);
1687 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1689 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1694 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1697 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1700 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1702 #ifdef TARGET_X86_64
1704 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1713 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1716 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1719 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1721 #ifdef TARGET_X86_64
1723 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1731 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1734 /* XXX: add faster immediate case */
1735 static void gen_shiftd_rm_T1(DisasContext
*s
, TCGMemOp ot
, int op1
,
1736 bool is_right
, TCGv count_in
)
1738 target_ulong mask
= (ot
== MO_64
? 63 : 31);
1742 if (op1
== OR_TMP0
) {
1743 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1745 gen_op_mov_v_reg(ot
, cpu_T
[0], op1
);
1748 count
= tcg_temp_new();
1749 tcg_gen_andi_tl(count
, count_in
, mask
);
1753 /* Note: we implement the Intel behaviour for shift count > 16.
1754 This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
1755 portion by constructing it as a 32-bit value. */
1757 tcg_gen_deposit_tl(cpu_tmp0
, cpu_T
[0], cpu_T
[1], 16, 16);
1758 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
1759 tcg_gen_mov_tl(cpu_T
[0], cpu_tmp0
);
1761 tcg_gen_deposit_tl(cpu_T
[1], cpu_T
[0], cpu_T
[1], 16, 16);
1764 #ifdef TARGET_X86_64
1766 /* Concatenate the two 32-bit values and use a 64-bit shift. */
1767 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1769 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1770 tcg_gen_shr_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1771 tcg_gen_shr_i64(cpu_T
[0], cpu_T
[0], count
);
1773 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[1], cpu_T
[0]);
1774 tcg_gen_shl_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1775 tcg_gen_shl_i64(cpu_T
[0], cpu_T
[0], count
);
1776 tcg_gen_shri_i64(cpu_tmp0
, cpu_tmp0
, 32);
1777 tcg_gen_shri_i64(cpu_T
[0], cpu_T
[0], 32);
1782 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1784 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1786 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1787 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], count
);
1788 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1790 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1792 /* Only needed if count > 16, for Intel behaviour. */
1793 tcg_gen_subfi_tl(cpu_tmp4
, 33, count
);
1794 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[1], cpu_tmp4
);
1795 tcg_gen_or_tl(cpu_tmp0
, cpu_tmp0
, cpu_tmp4
);
1798 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1799 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], count
);
1800 tcg_gen_shr_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1802 tcg_gen_movi_tl(cpu_tmp4
, 0);
1803 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[1], count
, cpu_tmp4
,
1804 cpu_tmp4
, cpu_T
[1]);
1805 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1810 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1812 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, count
, is_right
);
1813 tcg_temp_free(count
);
1816 static void gen_shift(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int s
)
1819 gen_op_mov_v_reg(ot
, cpu_T
[1], s
);
1822 gen_rot_rm_T1(s1
, ot
, d
, 0);
1825 gen_rot_rm_T1(s1
, ot
, d
, 1);
1829 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1832 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1835 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1838 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1841 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1846 static void gen_shifti(DisasContext
*s1
, int op
, TCGMemOp ot
, int d
, int c
)
1850 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1853 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1857 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1860 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1863 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1866 /* currently not optimized */
1867 tcg_gen_movi_tl(cpu_T
[1], c
);
1868 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1873 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
1880 int mod
, rm
, code
, override
, must_add_seg
;
1883 override
= s
->override
;
1884 must_add_seg
= s
->addseg
;
1887 mod
= (modrm
>> 6) & 3;
1900 code
= cpu_ldub_code(env
, s
->pc
++);
1901 scale
= (code
>> 6) & 3;
1902 index
= ((code
>> 3) & 7) | REX_X(s
);
1904 index
= -1; /* no index */
1912 if ((base
& 7) == 5) {
1914 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1916 if (CODE64(s
) && !havesib
) {
1917 disp
+= s
->pc
+ s
->rip_offset
;
1924 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
1928 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
1933 /* For correct popl handling with esp. */
1934 if (base
== R_ESP
&& s
->popl_esp_hack
) {
1935 disp
+= s
->popl_esp_hack
;
1938 /* Compute the address, with a minimum number of TCG ops. */
1942 sum
= cpu_regs
[index
];
1944 tcg_gen_shli_tl(cpu_A0
, cpu_regs
[index
], scale
);
1948 tcg_gen_add_tl(cpu_A0
, sum
, cpu_regs
[base
]);
1951 } else if (base
>= 0) {
1952 sum
= cpu_regs
[base
];
1954 if (TCGV_IS_UNUSED(sum
)) {
1955 tcg_gen_movi_tl(cpu_A0
, disp
);
1957 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
1962 if (base
== R_EBP
|| base
== R_ESP
) {
1969 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
1970 offsetof(CPUX86State
, segs
[override
].base
));
1972 if (s
->aflag
== MO_32
) {
1973 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
1975 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
1979 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
1982 if (s
->aflag
== MO_32
) {
1983 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
1991 disp
= cpu_lduw_code(env
, s
->pc
);
1993 tcg_gen_movi_tl(cpu_A0
, disp
);
1994 rm
= 0; /* avoid SS override */
2001 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2005 disp
= (int16_t)cpu_lduw_code(env
, s
->pc
);
2013 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_ESI
]);
2016 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBX
], cpu_regs
[R_EDI
]);
2019 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_ESI
]);
2022 tcg_gen_add_tl(cpu_A0
, cpu_regs
[R_EBP
], cpu_regs
[R_EDI
]);
2025 sum
= cpu_regs
[R_ESI
];
2028 sum
= cpu_regs
[R_EDI
];
2031 sum
= cpu_regs
[R_EBP
];
2035 sum
= cpu_regs
[R_EBX
];
2038 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
2039 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2043 if (rm
== 2 || rm
== 3 || rm
== 6) {
2049 gen_op_addl_A0_seg(s
, override
);
2058 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2060 int mod
, rm
, base
, code
;
2062 mod
= (modrm
>> 6) & 3;
2073 code
= cpu_ldub_code(env
, s
->pc
++);
2115 /* used for LEA and MOV AX, mem */
2116 static void gen_add_A0_ds_seg(DisasContext
*s
)
2118 int override
, must_add_seg
;
2119 must_add_seg
= s
->addseg
;
2121 if (s
->override
>= 0) {
2122 override
= s
->override
;
2126 #ifdef TARGET_X86_64
2128 gen_op_addq_A0_seg(override
);
2132 gen_op_addl_A0_seg(s
, override
);
2137 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2139 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2140 TCGMemOp ot
, int reg
, int is_store
)
2144 mod
= (modrm
>> 6) & 3;
2145 rm
= (modrm
& 7) | REX_B(s
);
2149 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
2150 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
2152 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
2154 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2157 gen_lea_modrm(env
, s
, modrm
);
2160 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
2161 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2163 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
2165 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2170 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
)
2176 ret
= cpu_ldub_code(env
, s
->pc
);
2180 ret
= cpu_lduw_code(env
, s
->pc
);
2184 #ifdef TARGET_X86_64
2187 ret
= cpu_ldl_code(env
, s
->pc
);
2196 static inline int insn_const_size(TCGMemOp ot
)
2205 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2207 TranslationBlock
*tb
;
2210 pc
= s
->cs_base
+ eip
;
2212 /* NOTE: we handle the case where the TB spans two pages here */
2213 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2214 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2215 /* jump to same page: we can use a direct jump */
2216 tcg_gen_goto_tb(tb_num
);
2218 tcg_gen_exit_tb((uintptr_t)tb
+ tb_num
);
2220 /* jump to another page: currently not optimized */
2226 static inline void gen_jcc(DisasContext
*s
, int b
,
2227 target_ulong val
, target_ulong next_eip
)
2232 l1
= gen_new_label();
2235 gen_goto_tb(s
, 0, next_eip
);
2238 gen_goto_tb(s
, 1, val
);
2239 s
->is_jmp
= DISAS_TB_JUMP
;
2241 l1
= gen_new_label();
2242 l2
= gen_new_label();
2245 gen_jmp_im(next_eip
);
2255 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, TCGMemOp ot
, int b
,
2260 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2262 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2263 if (cc
.mask
!= -1) {
2264 TCGv t0
= tcg_temp_new();
2265 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2269 cc
.reg2
= tcg_const_tl(cc
.imm
);
2272 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2273 cpu_T
[0], cpu_regs
[reg
]);
2274 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
2276 if (cc
.mask
!= -1) {
2277 tcg_temp_free(cc
.reg
);
2280 tcg_temp_free(cc
.reg2
);
2284 static inline void gen_op_movl_T0_seg(int seg_reg
)
2286 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2287 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2290 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2292 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2293 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2294 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2295 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2296 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2297 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2300 /* move T0 to seg_reg and compute if the CPU state may change. Never
2301 call this function with seg_reg == R_CS */
2302 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2304 if (s
->pe
&& !s
->vm86
) {
2305 /* XXX: optimize by finding processor state dynamically */
2306 gen_update_cc_op(s
);
2307 gen_jmp_im(cur_eip
);
2308 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2309 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2310 /* abort translation because the addseg value may change or
2311 because ss32 may change. For R_SS, translation must always
2312 stop as a special handling must be done to disable hardware
2313 interrupts for the next instruction */
2314 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2315 s
->is_jmp
= DISAS_TB_JUMP
;
2317 gen_op_movl_seg_T0_vm(seg_reg
);
2318 if (seg_reg
== R_SS
)
2319 s
->is_jmp
= DISAS_TB_JUMP
;
2323 static inline int svm_is_rep(int prefixes
)
2325 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2329 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2330 uint32_t type
, uint64_t param
)
2332 /* no SVM activated; fast case */
2333 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2335 gen_update_cc_op(s
);
2336 gen_jmp_im(pc_start
- s
->cs_base
);
2337 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2338 tcg_const_i64(param
));
2342 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2344 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2347 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2349 #ifdef TARGET_X86_64
2351 gen_op_add_reg_im(MO_64
, R_ESP
, addend
);
2355 gen_op_add_reg_im(MO_32
, R_ESP
, addend
);
2357 gen_op_add_reg_im(MO_16
, R_ESP
, addend
);
2361 /* Generate a push. It depends on ss32, addseg and dflag. */
2362 static void gen_push_v(DisasContext
*s
, TCGv val
)
2364 TCGMemOp a_ot
, d_ot
= mo_pushpop(s
, s
->dflag
);
2365 int size
= 1 << d_ot
;
2366 TCGv new_esp
= cpu_A0
;
2368 tcg_gen_subi_tl(cpu_A0
, cpu_regs
[R_ESP
], size
);
2372 } else if (s
->ss32
) {
2376 tcg_gen_mov_tl(new_esp
, cpu_A0
);
2377 gen_op_addl_A0_seg(s
, R_SS
);
2379 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2384 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2385 tcg_gen_mov_tl(new_esp
, cpu_A0
);
2386 gen_op_addl_A0_seg(s
, R_SS
);
2389 gen_op_st_v(s
, d_ot
, val
, cpu_A0
);
2390 gen_op_mov_reg_v(a_ot
, R_ESP
, new_esp
);
2393 /* two step pop is necessary for precise exceptions */
2394 static TCGMemOp
gen_pop_T0(DisasContext
*s
)
2396 TCGMemOp d_ot
= mo_pushpop(s
, s
->dflag
);
2400 addr
= cpu_regs
[R_ESP
];
2401 } else if (!s
->ss32
) {
2402 tcg_gen_ext16u_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2403 gen_op_addl_A0_seg(s
, R_SS
);
2404 } else if (s
->addseg
) {
2405 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2406 gen_op_addl_A0_seg(s
, R_SS
);
2408 tcg_gen_ext32u_tl(cpu_A0
, cpu_regs
[R_ESP
]);
2411 gen_op_ld_v(s
, d_ot
, cpu_T
[0], addr
);
2415 static void gen_pop_update(DisasContext
*s
, TCGMemOp ot
)
2417 gen_stack_update(s
, 1 << ot
);
2420 static void gen_stack_A0(DisasContext
*s
)
2422 gen_op_movl_A0_reg(R_ESP
);
2424 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2425 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2427 gen_op_addl_A0_seg(s
, R_SS
);
2430 /* NOTE: wrap around in 16 bit not fully handled */
2431 static void gen_pusha(DisasContext
*s
)
2434 gen_op_movl_A0_reg(R_ESP
);
2435 gen_op_addl_A0_im(-8 << s
->dflag
);
2437 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2438 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2440 gen_op_addl_A0_seg(s
, R_SS
);
2441 for(i
= 0;i
< 8; i
++) {
2442 gen_op_mov_v_reg(MO_32
, cpu_T
[0], 7 - i
);
2443 gen_op_st_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2444 gen_op_addl_A0_im(1 << s
->dflag
);
2446 gen_op_mov_reg_v(MO_16
+ s
->ss32
, R_ESP
, cpu_T
[1]);
2449 /* NOTE: wrap around in 16 bit not fully handled */
2450 static void gen_popa(DisasContext
*s
)
2453 gen_op_movl_A0_reg(R_ESP
);
2455 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2456 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2457 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 8 << s
->dflag
);
2459 gen_op_addl_A0_seg(s
, R_SS
);
2460 for(i
= 0;i
< 8; i
++) {
2461 /* ESP is not reloaded */
2463 gen_op_ld_v(s
, s
->dflag
, cpu_T
[0], cpu_A0
);
2464 gen_op_mov_reg_v(s
->dflag
, 7 - i
, cpu_T
[0]);
2466 gen_op_addl_A0_im(1 << s
->dflag
);
2468 gen_op_mov_reg_v(MO_16
+ s
->ss32
, R_ESP
, cpu_T
[1]);
2471 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2473 TCGMemOp ot
= mo_pushpop(s
, s
->dflag
);
2474 int opsize
= 1 << ot
;
2477 #ifdef TARGET_X86_64
2479 gen_op_movl_A0_reg(R_ESP
);
2480 gen_op_addq_A0_im(-opsize
);
2481 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2484 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EBP
);
2485 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2487 /* XXX: must save state */
2488 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2489 tcg_const_i32((ot
== MO_64
)),
2492 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[1]);
2493 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2494 gen_op_mov_reg_v(MO_64
, R_ESP
, cpu_T
[1]);
2498 gen_op_movl_A0_reg(R_ESP
);
2499 gen_op_addl_A0_im(-opsize
);
2501 tcg_gen_ext16u_tl(cpu_A0
, cpu_A0
);
2502 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2504 gen_op_addl_A0_seg(s
, R_SS
);
2506 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EBP
);
2507 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2509 /* XXX: must save state */
2510 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2511 tcg_const_i32(s
->dflag
- 1),
2514 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[1]);
2515 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2516 gen_op_mov_reg_v(MO_16
+ s
->ss32
, R_ESP
, cpu_T
[1]);
2520 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2522 gen_update_cc_op(s
);
2523 gen_jmp_im(cur_eip
);
2524 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2525 s
->is_jmp
= DISAS_TB_JUMP
;
2528 /* an interrupt is different from an exception because of the
2530 static void gen_interrupt(DisasContext
*s
, int intno
,
2531 target_ulong cur_eip
, target_ulong next_eip
)
2533 gen_update_cc_op(s
);
2534 gen_jmp_im(cur_eip
);
2535 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2536 tcg_const_i32(next_eip
- cur_eip
));
2537 s
->is_jmp
= DISAS_TB_JUMP
;
2540 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2542 gen_update_cc_op(s
);
2543 gen_jmp_im(cur_eip
);
2544 gen_helper_debug(cpu_env
);
2545 s
->is_jmp
= DISAS_TB_JUMP
;
2548 /* generate a generic end of block. Trace exception is also generated
2550 static void gen_eob(DisasContext
*s
)
2552 gen_update_cc_op(s
);
2553 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2554 gen_helper_reset_inhibit_irq(cpu_env
);
2556 if (s
->tb
->flags
& HF_RF_MASK
) {
2557 gen_helper_reset_rf(cpu_env
);
2559 if (s
->singlestep_enabled
) {
2560 gen_helper_debug(cpu_env
);
2562 gen_helper_single_step(cpu_env
);
2566 s
->is_jmp
= DISAS_TB_JUMP
;
2569 /* generate a jump to eip. No segment change must happen before as a
2570 direct call to the next block may occur */
2571 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2573 gen_update_cc_op(s
);
2574 set_cc_op(s
, CC_OP_DYNAMIC
);
2576 gen_goto_tb(s
, tb_num
, eip
);
2577 s
->is_jmp
= DISAS_TB_JUMP
;
2584 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2586 gen_jmp_tb(s
, eip
, 0);
2589 static inline void gen_ldq_env_A0(DisasContext
*s
, int offset
)
2591 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2592 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2595 static inline void gen_stq_env_A0(DisasContext
*s
, int offset
)
2597 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2598 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2601 static inline void gen_ldo_env_A0(DisasContext
*s
, int offset
)
2603 int mem_index
= s
->mem_index
;
2604 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2605 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2606 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2607 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2608 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2611 static inline void gen_sto_env_A0(DisasContext
*s
, int offset
)
2613 int mem_index
= s
->mem_index
;
2614 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2615 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2616 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2617 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2618 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2621 static inline void gen_op_movo(int d_offset
, int s_offset
)
2623 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ offsetof(XMMReg
, XMM_Q(0)));
2624 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ offsetof(XMMReg
, XMM_Q(0)));
2625 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ offsetof(XMMReg
, XMM_Q(1)));
2626 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ offsetof(XMMReg
, XMM_Q(1)));
2629 static inline void gen_op_movq(int d_offset
, int s_offset
)
2631 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2632 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2635 static inline void gen_op_movl(int d_offset
, int s_offset
)
2637 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2638 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2641 static inline void gen_op_movq_env_0(int d_offset
)
2643 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2644 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2647 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2648 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2649 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2650 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2651 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2652 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2654 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2655 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2658 #define SSE_SPECIAL ((void *)1)
2659 #define SSE_DUMMY ((void *)2)
2661 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2662 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2663 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2665 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2666 /* 3DNow! extensions */
2667 [0x0e] = { SSE_DUMMY
}, /* femms */
2668 [0x0f] = { SSE_DUMMY
}, /* pf... */
2669 /* pure SSE operations */
2670 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2671 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2672 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2673 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2674 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2675 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2676 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2677 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2679 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2680 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2681 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2682 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2683 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2684 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2685 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2686 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2687 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2688 [0x51] = SSE_FOP(sqrt
),
2689 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2690 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2691 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2692 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2693 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2694 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2695 [0x58] = SSE_FOP(add
),
2696 [0x59] = SSE_FOP(mul
),
2697 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2698 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2699 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2700 [0x5c] = SSE_FOP(sub
),
2701 [0x5d] = SSE_FOP(min
),
2702 [0x5e] = SSE_FOP(div
),
2703 [0x5f] = SSE_FOP(max
),
2705 [0xc2] = SSE_FOP(cmpeq
),
2706 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2707 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2709 /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
2710 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2711 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2713 /* MMX ops and their SSE extensions */
2714 [0x60] = MMX_OP2(punpcklbw
),
2715 [0x61] = MMX_OP2(punpcklwd
),
2716 [0x62] = MMX_OP2(punpckldq
),
2717 [0x63] = MMX_OP2(packsswb
),
2718 [0x64] = MMX_OP2(pcmpgtb
),
2719 [0x65] = MMX_OP2(pcmpgtw
),
2720 [0x66] = MMX_OP2(pcmpgtl
),
2721 [0x67] = MMX_OP2(packuswb
),
2722 [0x68] = MMX_OP2(punpckhbw
),
2723 [0x69] = MMX_OP2(punpckhwd
),
2724 [0x6a] = MMX_OP2(punpckhdq
),
2725 [0x6b] = MMX_OP2(packssdw
),
2726 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2727 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2728 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2729 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2730 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2731 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2732 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2733 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2734 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2735 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2736 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2737 [0x74] = MMX_OP2(pcmpeqb
),
2738 [0x75] = MMX_OP2(pcmpeqw
),
2739 [0x76] = MMX_OP2(pcmpeql
),
2740 [0x77] = { SSE_DUMMY
}, /* emms */
2741 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2742 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2743 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2744 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2745 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2746 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2747 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2748 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2749 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2750 [0xd1] = MMX_OP2(psrlw
),
2751 [0xd2] = MMX_OP2(psrld
),
2752 [0xd3] = MMX_OP2(psrlq
),
2753 [0xd4] = MMX_OP2(paddq
),
2754 [0xd5] = MMX_OP2(pmullw
),
2755 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2756 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2757 [0xd8] = MMX_OP2(psubusb
),
2758 [0xd9] = MMX_OP2(psubusw
),
2759 [0xda] = MMX_OP2(pminub
),
2760 [0xdb] = MMX_OP2(pand
),
2761 [0xdc] = MMX_OP2(paddusb
),
2762 [0xdd] = MMX_OP2(paddusw
),
2763 [0xde] = MMX_OP2(pmaxub
),
2764 [0xdf] = MMX_OP2(pandn
),
2765 [0xe0] = MMX_OP2(pavgb
),
2766 [0xe1] = MMX_OP2(psraw
),
2767 [0xe2] = MMX_OP2(psrad
),
2768 [0xe3] = MMX_OP2(pavgw
),
2769 [0xe4] = MMX_OP2(pmulhuw
),
2770 [0xe5] = MMX_OP2(pmulhw
),
2771 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2772 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2773 [0xe8] = MMX_OP2(psubsb
),
2774 [0xe9] = MMX_OP2(psubsw
),
2775 [0xea] = MMX_OP2(pminsw
),
2776 [0xeb] = MMX_OP2(por
),
2777 [0xec] = MMX_OP2(paddsb
),
2778 [0xed] = MMX_OP2(paddsw
),
2779 [0xee] = MMX_OP2(pmaxsw
),
2780 [0xef] = MMX_OP2(pxor
),
2781 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2782 [0xf1] = MMX_OP2(psllw
),
2783 [0xf2] = MMX_OP2(pslld
),
2784 [0xf3] = MMX_OP2(psllq
),
2785 [0xf4] = MMX_OP2(pmuludq
),
2786 [0xf5] = MMX_OP2(pmaddwd
),
2787 [0xf6] = MMX_OP2(psadbw
),
2788 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
2789 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
2790 [0xf8] = MMX_OP2(psubb
),
2791 [0xf9] = MMX_OP2(psubw
),
2792 [0xfa] = MMX_OP2(psubl
),
2793 [0xfb] = MMX_OP2(psubq
),
2794 [0xfc] = MMX_OP2(paddb
),
2795 [0xfd] = MMX_OP2(paddw
),
2796 [0xfe] = MMX_OP2(paddl
),
2799 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
2800 [0 + 2] = MMX_OP2(psrlw
),
2801 [0 + 4] = MMX_OP2(psraw
),
2802 [0 + 6] = MMX_OP2(psllw
),
2803 [8 + 2] = MMX_OP2(psrld
),
2804 [8 + 4] = MMX_OP2(psrad
),
2805 [8 + 6] = MMX_OP2(pslld
),
2806 [16 + 2] = MMX_OP2(psrlq
),
2807 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2808 [16 + 6] = MMX_OP2(psllq
),
2809 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2812 static const SSEFunc_0_epi sse_op_table3ai
[] = {
2813 gen_helper_cvtsi2ss
,
2817 #ifdef TARGET_X86_64
2818 static const SSEFunc_0_epl sse_op_table3aq
[] = {
2819 gen_helper_cvtsq2ss
,
2824 static const SSEFunc_i_ep sse_op_table3bi
[] = {
2825 gen_helper_cvttss2si
,
2826 gen_helper_cvtss2si
,
2827 gen_helper_cvttsd2si
,
2831 #ifdef TARGET_X86_64
2832 static const SSEFunc_l_ep sse_op_table3bq
[] = {
2833 gen_helper_cvttss2sq
,
2834 gen_helper_cvtss2sq
,
2835 gen_helper_cvttsd2sq
,
2840 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
2851 static const SSEFunc_0_epp sse_op_table5
[256] = {
2852 [0x0c] = gen_helper_pi2fw
,
2853 [0x0d] = gen_helper_pi2fd
,
2854 [0x1c] = gen_helper_pf2iw
,
2855 [0x1d] = gen_helper_pf2id
,
2856 [0x8a] = gen_helper_pfnacc
,
2857 [0x8e] = gen_helper_pfpnacc
,
2858 [0x90] = gen_helper_pfcmpge
,
2859 [0x94] = gen_helper_pfmin
,
2860 [0x96] = gen_helper_pfrcp
,
2861 [0x97] = gen_helper_pfrsqrt
,
2862 [0x9a] = gen_helper_pfsub
,
2863 [0x9e] = gen_helper_pfadd
,
2864 [0xa0] = gen_helper_pfcmpgt
,
2865 [0xa4] = gen_helper_pfmax
,
2866 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2867 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2868 [0xaa] = gen_helper_pfsubr
,
2869 [0xae] = gen_helper_pfacc
,
2870 [0xb0] = gen_helper_pfcmpeq
,
2871 [0xb4] = gen_helper_pfmul
,
2872 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
2873 [0xb7] = gen_helper_pmulhrw_mmx
,
2874 [0xbb] = gen_helper_pswapd
,
2875 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
2878 struct SSEOpHelper_epp
{
2879 SSEFunc_0_epp op
[2];
2883 struct SSEOpHelper_eppi
{
2884 SSEFunc_0_eppi op
[2];
2888 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
2889 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
2890 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
2891 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
2892 #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
2893 CPUID_EXT_PCLMULQDQ }
2894 #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
2896 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
2897 [0x00] = SSSE3_OP(pshufb
),
2898 [0x01] = SSSE3_OP(phaddw
),
2899 [0x02] = SSSE3_OP(phaddd
),
2900 [0x03] = SSSE3_OP(phaddsw
),
2901 [0x04] = SSSE3_OP(pmaddubsw
),
2902 [0x05] = SSSE3_OP(phsubw
),
2903 [0x06] = SSSE3_OP(phsubd
),
2904 [0x07] = SSSE3_OP(phsubsw
),
2905 [0x08] = SSSE3_OP(psignb
),
2906 [0x09] = SSSE3_OP(psignw
),
2907 [0x0a] = SSSE3_OP(psignd
),
2908 [0x0b] = SSSE3_OP(pmulhrsw
),
2909 [0x10] = SSE41_OP(pblendvb
),
2910 [0x14] = SSE41_OP(blendvps
),
2911 [0x15] = SSE41_OP(blendvpd
),
2912 [0x17] = SSE41_OP(ptest
),
2913 [0x1c] = SSSE3_OP(pabsb
),
2914 [0x1d] = SSSE3_OP(pabsw
),
2915 [0x1e] = SSSE3_OP(pabsd
),
2916 [0x20] = SSE41_OP(pmovsxbw
),
2917 [0x21] = SSE41_OP(pmovsxbd
),
2918 [0x22] = SSE41_OP(pmovsxbq
),
2919 [0x23] = SSE41_OP(pmovsxwd
),
2920 [0x24] = SSE41_OP(pmovsxwq
),
2921 [0x25] = SSE41_OP(pmovsxdq
),
2922 [0x28] = SSE41_OP(pmuldq
),
2923 [0x29] = SSE41_OP(pcmpeqq
),
2924 [0x2a] = SSE41_SPECIAL
, /* movntqda */
2925 [0x2b] = SSE41_OP(packusdw
),
2926 [0x30] = SSE41_OP(pmovzxbw
),
2927 [0x31] = SSE41_OP(pmovzxbd
),
2928 [0x32] = SSE41_OP(pmovzxbq
),
2929 [0x33] = SSE41_OP(pmovzxwd
),
2930 [0x34] = SSE41_OP(pmovzxwq
),
2931 [0x35] = SSE41_OP(pmovzxdq
),
2932 [0x37] = SSE42_OP(pcmpgtq
),
2933 [0x38] = SSE41_OP(pminsb
),
2934 [0x39] = SSE41_OP(pminsd
),
2935 [0x3a] = SSE41_OP(pminuw
),
2936 [0x3b] = SSE41_OP(pminud
),
2937 [0x3c] = SSE41_OP(pmaxsb
),
2938 [0x3d] = SSE41_OP(pmaxsd
),
2939 [0x3e] = SSE41_OP(pmaxuw
),
2940 [0x3f] = SSE41_OP(pmaxud
),
2941 [0x40] = SSE41_OP(pmulld
),
2942 [0x41] = SSE41_OP(phminposuw
),
2943 [0xdb] = AESNI_OP(aesimc
),
2944 [0xdc] = AESNI_OP(aesenc
),
2945 [0xdd] = AESNI_OP(aesenclast
),
2946 [0xde] = AESNI_OP(aesdec
),
2947 [0xdf] = AESNI_OP(aesdeclast
),
2950 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
2951 [0x08] = SSE41_OP(roundps
),
2952 [0x09] = SSE41_OP(roundpd
),
2953 [0x0a] = SSE41_OP(roundss
),
2954 [0x0b] = SSE41_OP(roundsd
),
2955 [0x0c] = SSE41_OP(blendps
),
2956 [0x0d] = SSE41_OP(blendpd
),
2957 [0x0e] = SSE41_OP(pblendw
),
2958 [0x0f] = SSSE3_OP(palignr
),
2959 [0x14] = SSE41_SPECIAL
, /* pextrb */
2960 [0x15] = SSE41_SPECIAL
, /* pextrw */
2961 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
2962 [0x17] = SSE41_SPECIAL
, /* extractps */
2963 [0x20] = SSE41_SPECIAL
, /* pinsrb */
2964 [0x21] = SSE41_SPECIAL
, /* insertps */
2965 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
2966 [0x40] = SSE41_OP(dpps
),
2967 [0x41] = SSE41_OP(dppd
),
2968 [0x42] = SSE41_OP(mpsadbw
),
2969 [0x44] = PCLMULQDQ_OP(pclmulqdq
),
2970 [0x60] = SSE42_OP(pcmpestrm
),
2971 [0x61] = SSE42_OP(pcmpestri
),
2972 [0x62] = SSE42_OP(pcmpistrm
),
2973 [0x63] = SSE42_OP(pcmpistri
),
2974 [0xdf] = AESNI_OP(aeskeygenassist
),
2977 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
2978 target_ulong pc_start
, int rex_r
)
2980 int b1
, op1_offset
, op2_offset
, is_xmm
, val
;
2981 int modrm
, mod
, rm
, reg
;
2982 SSEFunc_0_epp sse_fn_epp
;
2983 SSEFunc_0_eppi sse_fn_eppi
;
2984 SSEFunc_0_ppi sse_fn_ppi
;
2985 SSEFunc_0_eppt sse_fn_eppt
;
2989 if (s
->prefix
& PREFIX_DATA
)
2991 else if (s
->prefix
& PREFIX_REPZ
)
2993 else if (s
->prefix
& PREFIX_REPNZ
)
2997 sse_fn_epp
= sse_op_table1
[b
][b1
];
3001 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3011 /* simple MMX/SSE operation */
3012 if (s
->flags
& HF_TS_MASK
) {
3013 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3016 if (s
->flags
& HF_EM_MASK
) {
3018 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3021 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3022 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3025 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3028 gen_helper_emms(cpu_env
);
3033 gen_helper_emms(cpu_env
);
3036 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3037 the static cpu state) */
3039 gen_helper_enter_mmx(cpu_env
);
3042 modrm
= cpu_ldub_code(env
, s
->pc
++);
3043 reg
= ((modrm
>> 3) & 7);
3046 mod
= (modrm
>> 6) & 3;
3047 if (sse_fn_epp
== SSE_SPECIAL
) {
3050 case 0x0e7: /* movntq */
3053 gen_lea_modrm(env
, s
, modrm
);
3054 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3056 case 0x1e7: /* movntdq */
3057 case 0x02b: /* movntps */
3058 case 0x12b: /* movntps */
3061 gen_lea_modrm(env
, s
, modrm
);
3062 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3064 case 0x3f0: /* lddqu */
3067 gen_lea_modrm(env
, s
, modrm
);
3068 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3070 case 0x22b: /* movntss */
3071 case 0x32b: /* movntsd */
3074 gen_lea_modrm(env
, s
, modrm
);
3076 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3077 xmm_regs
[reg
].XMM_Q(0)));
3079 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3080 xmm_regs
[reg
].XMM_L(0)));
3081 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3084 case 0x6e: /* movd mm, ea */
3085 #ifdef TARGET_X86_64
3086 if (s
->dflag
== MO_64
) {
3087 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3088 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3092 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3093 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3094 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3095 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3096 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3099 case 0x16e: /* movd xmm, ea */
3100 #ifdef TARGET_X86_64
3101 if (s
->dflag
== MO_64
) {
3102 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3103 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3104 offsetof(CPUX86State
,xmm_regs
[reg
]));
3105 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3109 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3110 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3111 offsetof(CPUX86State
,xmm_regs
[reg
]));
3112 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3113 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3116 case 0x6f: /* movq mm, ea */
3118 gen_lea_modrm(env
, s
, modrm
);
3119 gen_ldq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3122 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3123 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3124 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3125 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3128 case 0x010: /* movups */
3129 case 0x110: /* movupd */
3130 case 0x028: /* movaps */
3131 case 0x128: /* movapd */
3132 case 0x16f: /* movdqa xmm, ea */
3133 case 0x26f: /* movdqu xmm, ea */
3135 gen_lea_modrm(env
, s
, modrm
);
3136 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3138 rm
= (modrm
& 7) | REX_B(s
);
3139 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3140 offsetof(CPUX86State
,xmm_regs
[rm
]));
3143 case 0x210: /* movss xmm, ea */
3145 gen_lea_modrm(env
, s
, modrm
);
3146 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3147 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3148 tcg_gen_movi_tl(cpu_T
[0], 0);
3149 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3150 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3151 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3153 rm
= (modrm
& 7) | REX_B(s
);
3154 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3155 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3158 case 0x310: /* movsd xmm, ea */
3160 gen_lea_modrm(env
, s
, modrm
);
3161 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3162 xmm_regs
[reg
].XMM_Q(0)));
3163 tcg_gen_movi_tl(cpu_T
[0], 0);
3164 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3165 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3167 rm
= (modrm
& 7) | REX_B(s
);
3168 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3169 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3172 case 0x012: /* movlps */
3173 case 0x112: /* movlpd */
3175 gen_lea_modrm(env
, s
, modrm
);
3176 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3177 xmm_regs
[reg
].XMM_Q(0)));
3180 rm
= (modrm
& 7) | REX_B(s
);
3181 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3182 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3185 case 0x212: /* movsldup */
3187 gen_lea_modrm(env
, s
, modrm
);
3188 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3190 rm
= (modrm
& 7) | REX_B(s
);
3191 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3192 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3193 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3194 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3196 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3197 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3198 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3199 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3201 case 0x312: /* movddup */
3203 gen_lea_modrm(env
, s
, modrm
);
3204 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3205 xmm_regs
[reg
].XMM_Q(0)));
3207 rm
= (modrm
& 7) | REX_B(s
);
3208 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3209 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3211 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3212 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3214 case 0x016: /* movhps */
3215 case 0x116: /* movhpd */
3217 gen_lea_modrm(env
, s
, modrm
);
3218 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3219 xmm_regs
[reg
].XMM_Q(1)));
3222 rm
= (modrm
& 7) | REX_B(s
);
3223 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3224 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3227 case 0x216: /* movshdup */
3229 gen_lea_modrm(env
, s
, modrm
);
3230 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3232 rm
= (modrm
& 7) | REX_B(s
);
3233 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3234 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3235 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3236 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3238 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3239 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3240 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3241 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3246 int bit_index
, field_length
;
3248 if (b1
== 1 && reg
!= 0)
3250 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3251 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3252 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3253 offsetof(CPUX86State
,xmm_regs
[reg
]));
3255 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3256 tcg_const_i32(bit_index
),
3257 tcg_const_i32(field_length
));
3259 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3260 tcg_const_i32(bit_index
),
3261 tcg_const_i32(field_length
));
3264 case 0x7e: /* movd ea, mm */
3265 #ifdef TARGET_X86_64
3266 if (s
->dflag
== MO_64
) {
3267 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3268 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3269 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3273 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3274 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3275 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3278 case 0x17e: /* movd ea, xmm */
3279 #ifdef TARGET_X86_64
3280 if (s
->dflag
== MO_64
) {
3281 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3282 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3283 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3287 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3288 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3289 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3292 case 0x27e: /* movq xmm, ea */
3294 gen_lea_modrm(env
, s
, modrm
);
3295 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3296 xmm_regs
[reg
].XMM_Q(0)));
3298 rm
= (modrm
& 7) | REX_B(s
);
3299 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3300 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3302 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3304 case 0x7f: /* movq ea, mm */
3306 gen_lea_modrm(env
, s
, modrm
);
3307 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3310 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3311 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3314 case 0x011: /* movups */
3315 case 0x111: /* movupd */
3316 case 0x029: /* movaps */
3317 case 0x129: /* movapd */
3318 case 0x17f: /* movdqa ea, xmm */
3319 case 0x27f: /* movdqu ea, xmm */
3321 gen_lea_modrm(env
, s
, modrm
);
3322 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3324 rm
= (modrm
& 7) | REX_B(s
);
3325 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3326 offsetof(CPUX86State
,xmm_regs
[reg
]));
3329 case 0x211: /* movss ea, xmm */
3331 gen_lea_modrm(env
, s
, modrm
);
3332 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3333 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3335 rm
= (modrm
& 7) | REX_B(s
);
3336 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3337 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3340 case 0x311: /* movsd ea, xmm */
3342 gen_lea_modrm(env
, s
, modrm
);
3343 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3344 xmm_regs
[reg
].XMM_Q(0)));
3346 rm
= (modrm
& 7) | REX_B(s
);
3347 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3348 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3351 case 0x013: /* movlps */
3352 case 0x113: /* movlpd */
3354 gen_lea_modrm(env
, s
, modrm
);
3355 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3356 xmm_regs
[reg
].XMM_Q(0)));
3361 case 0x017: /* movhps */
3362 case 0x117: /* movhpd */
3364 gen_lea_modrm(env
, s
, modrm
);
3365 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3366 xmm_regs
[reg
].XMM_Q(1)));
3371 case 0x71: /* shift mm, im */
3374 case 0x171: /* shift xmm, im */
3380 val
= cpu_ldub_code(env
, s
->pc
++);
3382 tcg_gen_movi_tl(cpu_T
[0], val
);
3383 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3384 tcg_gen_movi_tl(cpu_T
[0], 0);
3385 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3386 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3388 tcg_gen_movi_tl(cpu_T
[0], val
);
3389 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3390 tcg_gen_movi_tl(cpu_T
[0], 0);
3391 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3392 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3394 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3395 (((modrm
>> 3)) & 7)][b1
];
3400 rm
= (modrm
& 7) | REX_B(s
);
3401 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3404 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3406 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3407 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3408 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3410 case 0x050: /* movmskps */
3411 rm
= (modrm
& 7) | REX_B(s
);
3412 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3413 offsetof(CPUX86State
,xmm_regs
[rm
]));
3414 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3415 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3417 case 0x150: /* movmskpd */
3418 rm
= (modrm
& 7) | REX_B(s
);
3419 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3420 offsetof(CPUX86State
,xmm_regs
[rm
]));
3421 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3422 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3424 case 0x02a: /* cvtpi2ps */
3425 case 0x12a: /* cvtpi2pd */
3426 gen_helper_enter_mmx(cpu_env
);
3428 gen_lea_modrm(env
, s
, modrm
);
3429 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3430 gen_ldq_env_A0(s
, op2_offset
);
3433 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3435 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3436 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3437 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3440 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3444 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3448 case 0x22a: /* cvtsi2ss */
3449 case 0x32a: /* cvtsi2sd */
3450 ot
= mo_64_32(s
->dflag
);
3451 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3452 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3453 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3455 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3456 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3457 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3459 #ifdef TARGET_X86_64
3460 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3461 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3467 case 0x02c: /* cvttps2pi */
3468 case 0x12c: /* cvttpd2pi */
3469 case 0x02d: /* cvtps2pi */
3470 case 0x12d: /* cvtpd2pi */
3471 gen_helper_enter_mmx(cpu_env
);
3473 gen_lea_modrm(env
, s
, modrm
);
3474 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3475 gen_ldo_env_A0(s
, op2_offset
);
3477 rm
= (modrm
& 7) | REX_B(s
);
3478 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3480 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3481 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3482 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3485 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3488 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3491 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3494 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3498 case 0x22c: /* cvttss2si */
3499 case 0x22d: /* cvtss2si */
3500 case 0x32c: /* cvttsd2si */
3501 case 0x32d: /* cvtsd2si */
3502 ot
= mo_64_32(s
->dflag
);
3504 gen_lea_modrm(env
, s
, modrm
);
3506 gen_ldq_env_A0(s
, offsetof(CPUX86State
, xmm_t0
.XMM_Q(0)));
3508 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3509 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3511 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3513 rm
= (modrm
& 7) | REX_B(s
);
3514 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3516 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3518 SSEFunc_i_ep sse_fn_i_ep
=
3519 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3520 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3521 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3523 #ifdef TARGET_X86_64
3524 SSEFunc_l_ep sse_fn_l_ep
=
3525 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3526 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3531 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3533 case 0xc4: /* pinsrw */
3536 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
3537 val
= cpu_ldub_code(env
, s
->pc
++);
3540 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3541 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3544 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3545 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3548 case 0xc5: /* pextrw */
3552 ot
= mo_64_32(s
->dflag
);
3553 val
= cpu_ldub_code(env
, s
->pc
++);
3556 rm
= (modrm
& 7) | REX_B(s
);
3557 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3558 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3562 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3563 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3565 reg
= ((modrm
>> 3) & 7) | rex_r
;
3566 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3568 case 0x1d6: /* movq ea, xmm */
3570 gen_lea_modrm(env
, s
, modrm
);
3571 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3572 xmm_regs
[reg
].XMM_Q(0)));
3574 rm
= (modrm
& 7) | REX_B(s
);
3575 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3576 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3577 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3580 case 0x2d6: /* movq2dq */
3581 gen_helper_enter_mmx(cpu_env
);
3583 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3584 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3585 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3587 case 0x3d6: /* movdq2q */
3588 gen_helper_enter_mmx(cpu_env
);
3589 rm
= (modrm
& 7) | REX_B(s
);
3590 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3591 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3593 case 0xd7: /* pmovmskb */
3598 rm
= (modrm
& 7) | REX_B(s
);
3599 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3600 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3603 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3604 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3606 reg
= ((modrm
>> 3) & 7) | rex_r
;
3607 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
3613 if ((b
& 0xf0) == 0xf0) {
3616 modrm
= cpu_ldub_code(env
, s
->pc
++);
3618 reg
= ((modrm
>> 3) & 7) | rex_r
;
3619 mod
= (modrm
>> 6) & 3;
3624 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3628 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3632 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3634 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3636 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3637 gen_lea_modrm(env
, s
, modrm
);
3639 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3640 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3641 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3642 gen_ldq_env_A0(s
, op2_offset
+
3643 offsetof(XMMReg
, XMM_Q(0)));
3645 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3646 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3647 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
3648 s
->mem_index
, MO_LEUL
);
3649 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3650 offsetof(XMMReg
, XMM_L(0)));
3652 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3653 tcg_gen_qemu_ld_tl(cpu_tmp0
, cpu_A0
,
3654 s
->mem_index
, MO_LEUW
);
3655 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3656 offsetof(XMMReg
, XMM_W(0)));
3658 case 0x2a: /* movntqda */
3659 gen_ldo_env_A0(s
, op1_offset
);
3662 gen_ldo_env_A0(s
, op2_offset
);
3666 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3668 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3670 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3671 gen_lea_modrm(env
, s
, modrm
);
3672 gen_ldq_env_A0(s
, op2_offset
);
3675 if (sse_fn_epp
== SSE_SPECIAL
) {
3679 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3680 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3681 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3684 set_cc_op(s
, CC_OP_EFLAGS
);
3691 /* Various integer extensions at 0f 38 f[0-f]. */
3692 b
= modrm
| (b1
<< 8);
3693 modrm
= cpu_ldub_code(env
, s
->pc
++);
3694 reg
= ((modrm
>> 3) & 7) | rex_r
;
3697 case 0x3f0: /* crc32 Gd,Eb */
3698 case 0x3f1: /* crc32 Gd,Ey */
3700 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
)) {
3703 if ((b
& 0xff) == 0xf0) {
3705 } else if (s
->dflag
!= MO_64
) {
3706 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3711 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[reg
]);
3712 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3713 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3714 cpu_T
[0], tcg_const_i32(8 << ot
));
3716 ot
= mo_64_32(s
->dflag
);
3717 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3720 case 0x1f0: /* crc32 or movbe */
3722 /* For these insns, the f3 prefix is supposed to have priority
3723 over the 66 prefix, but that's not what we implement above
3725 if (s
->prefix
& PREFIX_REPNZ
) {
3729 case 0x0f0: /* movbe Gy,My */
3730 case 0x0f1: /* movbe My,Gy */
3731 if (!(s
->cpuid_ext_features
& CPUID_EXT_MOVBE
)) {
3734 if (s
->dflag
!= MO_64
) {
3735 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3740 gen_lea_modrm(env
, s
, modrm
);
3742 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
3743 s
->mem_index
, ot
| MO_BE
);
3744 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3746 tcg_gen_qemu_st_tl(cpu_regs
[reg
], cpu_A0
,
3747 s
->mem_index
, ot
| MO_BE
);
3751 case 0x0f2: /* andn Gy, By, Ey */
3752 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3753 || !(s
->prefix
& PREFIX_VEX
)
3757 ot
= mo_64_32(s
->dflag
);
3758 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3759 tcg_gen_andc_tl(cpu_T
[0], cpu_regs
[s
->vex_v
], cpu_T
[0]);
3760 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3761 gen_op_update1_cc();
3762 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3765 case 0x0f7: /* bextr Gy, Ey, By */
3766 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3767 || !(s
->prefix
& PREFIX_VEX
)
3771 ot
= mo_64_32(s
->dflag
);
3775 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3776 /* Extract START, and shift the operand.
3777 Shifts larger than operand size get zeros. */
3778 tcg_gen_ext8u_tl(cpu_A0
, cpu_regs
[s
->vex_v
]);
3779 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3781 bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3782 zero
= tcg_const_tl(0);
3783 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_T
[0], cpu_A0
, bound
,
3785 tcg_temp_free(zero
);
3787 /* Extract the LEN into a mask. Lengths larger than
3788 operand size get all ones. */
3789 tcg_gen_shri_tl(cpu_A0
, cpu_regs
[s
->vex_v
], 8);
3790 tcg_gen_ext8u_tl(cpu_A0
, cpu_A0
);
3791 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_A0
, cpu_A0
, bound
,
3793 tcg_temp_free(bound
);
3794 tcg_gen_movi_tl(cpu_T
[1], 1);
3795 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_A0
);
3796 tcg_gen_subi_tl(cpu_T
[1], cpu_T
[1], 1);
3797 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3799 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3800 gen_op_update1_cc();
3801 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3805 case 0x0f5: /* bzhi Gy, Ey, By */
3806 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3807 || !(s
->prefix
& PREFIX_VEX
)
3811 ot
= mo_64_32(s
->dflag
);
3812 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3813 tcg_gen_ext8u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3815 TCGv bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3816 /* Note that since we're using BMILG (in order to get O
3817 cleared) we need to store the inverse into C. */
3818 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_cc_src
,
3820 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_T
[1], cpu_T
[1],
3821 bound
, bound
, cpu_T
[1]);
3822 tcg_temp_free(bound
);
3824 tcg_gen_movi_tl(cpu_A0
, -1);
3825 tcg_gen_shl_tl(cpu_A0
, cpu_A0
, cpu_T
[1]);
3826 tcg_gen_andc_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3827 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
3828 gen_op_update1_cc();
3829 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
3832 case 0x3f6: /* mulx By, Gy, rdx, Ey */
3833 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3834 || !(s
->prefix
& PREFIX_VEX
)
3838 ot
= mo_64_32(s
->dflag
);
3839 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3842 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3843 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EDX
]);
3844 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
3845 cpu_tmp2_i32
, cpu_tmp3_i32
);
3846 tcg_gen_extu_i32_tl(cpu_regs
[s
->vex_v
], cpu_tmp2_i32
);
3847 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp3_i32
);
3849 #ifdef TARGET_X86_64
3851 tcg_gen_mulu2_i64(cpu_regs
[s
->vex_v
], cpu_regs
[reg
],
3852 cpu_T
[0], cpu_regs
[R_EDX
]);
3858 case 0x3f5: /* pdep Gy, By, Ey */
3859 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3860 || !(s
->prefix
& PREFIX_VEX
)
3864 ot
= mo_64_32(s
->dflag
);
3865 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3866 /* Note that by zero-extending the mask operand, we
3867 automatically handle zero-extending the result. */
3869 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3871 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3873 gen_helper_pdep(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3876 case 0x2f5: /* pext Gy, By, Ey */
3877 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3878 || !(s
->prefix
& PREFIX_VEX
)
3882 ot
= mo_64_32(s
->dflag
);
3883 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3884 /* Note that by zero-extending the mask operand, we
3885 automatically handle zero-extending the result. */
3887 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3889 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3891 gen_helper_pext(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
3894 case 0x1f6: /* adcx Gy, Ey */
3895 case 0x2f6: /* adox Gy, Ey */
3896 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_ADX
)) {
3899 TCGv carry_in
, carry_out
, zero
;
3902 ot
= mo_64_32(s
->dflag
);
3903 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3905 /* Re-use the carry-out from a previous round. */
3906 TCGV_UNUSED(carry_in
);
3907 carry_out
= (b
== 0x1f6 ? cpu_cc_dst
: cpu_cc_src2
);
3911 carry_in
= cpu_cc_dst
;
3912 end_op
= CC_OP_ADCX
;
3914 end_op
= CC_OP_ADCOX
;
3919 end_op
= CC_OP_ADCOX
;
3921 carry_in
= cpu_cc_src2
;
3922 end_op
= CC_OP_ADOX
;
3926 end_op
= CC_OP_ADCOX
;
3927 carry_in
= carry_out
;
3930 end_op
= (b
== 0x1f6 ? CC_OP_ADCX
: CC_OP_ADOX
);
3933 /* If we can't reuse carry-out, get it out of EFLAGS. */
3934 if (TCGV_IS_UNUSED(carry_in
)) {
3935 if (s
->cc_op
!= CC_OP_ADCX
&& s
->cc_op
!= CC_OP_ADOX
) {
3936 gen_compute_eflags(s
);
3938 carry_in
= cpu_tmp0
;
3939 tcg_gen_shri_tl(carry_in
, cpu_cc_src
,
3940 ctz32(b
== 0x1f6 ? CC_C
: CC_O
));
3941 tcg_gen_andi_tl(carry_in
, carry_in
, 1);
3945 #ifdef TARGET_X86_64
3947 /* If we know TL is 64-bit, and we want a 32-bit
3948 result, just do everything in 64-bit arithmetic. */
3949 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_regs
[reg
]);
3950 tcg_gen_ext32u_i64(cpu_T
[0], cpu_T
[0]);
3951 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], cpu_regs
[reg
]);
3952 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], carry_in
);
3953 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_T
[0]);
3954 tcg_gen_shri_i64(carry_out
, cpu_T
[0], 32);
3958 /* Otherwise compute the carry-out in two steps. */
3959 zero
= tcg_const_tl(0);
3960 tcg_gen_add2_tl(cpu_T
[0], carry_out
,
3963 tcg_gen_add2_tl(cpu_regs
[reg
], carry_out
,
3964 cpu_regs
[reg
], carry_out
,
3966 tcg_temp_free(zero
);
3969 set_cc_op(s
, end_op
);
3973 case 0x1f7: /* shlx Gy, Ey, By */
3974 case 0x2f7: /* sarx Gy, Ey, By */
3975 case 0x3f7: /* shrx Gy, Ey, By */
3976 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3977 || !(s
->prefix
& PREFIX_VEX
)
3981 ot
= mo_64_32(s
->dflag
);
3982 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3984 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 63);
3986 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 31);
3989 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3990 } else if (b
== 0x2f7) {
3992 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
3994 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3997 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
3999 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4001 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4007 case 0x3f3: /* Group 17 */
4008 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
4009 || !(s
->prefix
& PREFIX_VEX
)
4013 ot
= mo_64_32(s
->dflag
);
4014 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4017 case 1: /* blsr By,Ey */
4018 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[0]);
4019 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4020 gen_op_mov_reg_v(ot
, s
->vex_v
, cpu_T
[0]);
4021 gen_op_update2_cc();
4022 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4025 case 2: /* blsmsk By,Ey */
4026 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4027 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4028 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4029 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4030 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4033 case 3: /* blsi By, Ey */
4034 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4035 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4036 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4037 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4038 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4054 modrm
= cpu_ldub_code(env
, s
->pc
++);
4056 reg
= ((modrm
>> 3) & 7) | rex_r
;
4057 mod
= (modrm
>> 6) & 3;
4062 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
4066 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
4069 if (sse_fn_eppi
== SSE_SPECIAL
) {
4070 ot
= mo_64_32(s
->dflag
);
4071 rm
= (modrm
& 7) | REX_B(s
);
4073 gen_lea_modrm(env
, s
, modrm
);
4074 reg
= ((modrm
>> 3) & 7) | rex_r
;
4075 val
= cpu_ldub_code(env
, s
->pc
++);
4077 case 0x14: /* pextrb */
4078 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4079 xmm_regs
[reg
].XMM_B(val
& 15)));
4081 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4083 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4084 s
->mem_index
, MO_UB
);
4087 case 0x15: /* pextrw */
4088 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4089 xmm_regs
[reg
].XMM_W(val
& 7)));
4091 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4093 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4094 s
->mem_index
, MO_LEUW
);
4098 if (ot
== MO_32
) { /* pextrd */
4099 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4100 offsetof(CPUX86State
,
4101 xmm_regs
[reg
].XMM_L(val
& 3)));
4103 tcg_gen_extu_i32_tl(cpu_regs
[rm
], cpu_tmp2_i32
);
4105 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
4106 s
->mem_index
, MO_LEUL
);
4108 } else { /* pextrq */
4109 #ifdef TARGET_X86_64
4110 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4111 offsetof(CPUX86State
,
4112 xmm_regs
[reg
].XMM_Q(val
& 1)));
4114 tcg_gen_mov_i64(cpu_regs
[rm
], cpu_tmp1_i64
);
4116 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
4117 s
->mem_index
, MO_LEQ
);
4124 case 0x17: /* extractps */
4125 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4126 xmm_regs
[reg
].XMM_L(val
& 3)));
4128 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4130 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4131 s
->mem_index
, MO_LEUL
);
4134 case 0x20: /* pinsrb */
4136 gen_op_mov_v_reg(MO_32
, cpu_T
[0], rm
);
4138 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
4139 s
->mem_index
, MO_UB
);
4141 tcg_gen_st8_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4142 xmm_regs
[reg
].XMM_B(val
& 15)));
4144 case 0x21: /* insertps */
4146 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4147 offsetof(CPUX86State
,xmm_regs
[rm
]
4148 .XMM_L((val
>> 6) & 3)));
4150 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4151 s
->mem_index
, MO_LEUL
);
4153 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4154 offsetof(CPUX86State
,xmm_regs
[reg
]
4155 .XMM_L((val
>> 4) & 3)));
4157 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4158 cpu_env
, offsetof(CPUX86State
,
4159 xmm_regs
[reg
].XMM_L(0)));
4161 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4162 cpu_env
, offsetof(CPUX86State
,
4163 xmm_regs
[reg
].XMM_L(1)));
4165 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4166 cpu_env
, offsetof(CPUX86State
,
4167 xmm_regs
[reg
].XMM_L(2)));
4169 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4170 cpu_env
, offsetof(CPUX86State
,
4171 xmm_regs
[reg
].XMM_L(3)));
4174 if (ot
== MO_32
) { /* pinsrd */
4176 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_regs
[rm
]);
4178 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4179 s
->mem_index
, MO_LEUL
);
4181 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4182 offsetof(CPUX86State
,
4183 xmm_regs
[reg
].XMM_L(val
& 3)));
4184 } else { /* pinsrq */
4185 #ifdef TARGET_X86_64
4187 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4189 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
4190 s
->mem_index
, MO_LEQ
);
4192 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4193 offsetof(CPUX86State
,
4194 xmm_regs
[reg
].XMM_Q(val
& 1)));
4205 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4207 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4209 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4210 gen_lea_modrm(env
, s
, modrm
);
4211 gen_ldo_env_A0(s
, op2_offset
);
4214 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4216 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4218 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4219 gen_lea_modrm(env
, s
, modrm
);
4220 gen_ldq_env_A0(s
, op2_offset
);
4223 val
= cpu_ldub_code(env
, s
->pc
++);
4225 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4226 set_cc_op(s
, CC_OP_EFLAGS
);
4228 if (s
->dflag
== MO_64
) {
4229 /* The helper must use entire 64-bit gp registers */
4234 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4235 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4236 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4240 /* Various integer extensions at 0f 3a f[0-f]. */
4241 b
= modrm
| (b1
<< 8);
4242 modrm
= cpu_ldub_code(env
, s
->pc
++);
4243 reg
= ((modrm
>> 3) & 7) | rex_r
;
4246 case 0x3f0: /* rorx Gy,Ey, Ib */
4247 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4248 || !(s
->prefix
& PREFIX_VEX
)
4252 ot
= mo_64_32(s
->dflag
);
4253 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4254 b
= cpu_ldub_code(env
, s
->pc
++);
4256 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], b
& 63);
4258 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4259 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, b
& 31);
4260 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4262 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4274 /* generic MMX or SSE operation */
4276 case 0x70: /* pshufx insn */
4277 case 0xc6: /* pshufx insn */
4278 case 0xc2: /* compare insns */
4285 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4289 gen_lea_modrm(env
, s
, modrm
);
4290 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4296 /* Most sse scalar operations. */
4299 } else if (b1
== 3) {
4304 case 0x2e: /* ucomis[sd] */
4305 case 0x2f: /* comis[sd] */
4317 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
4318 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
4319 offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4323 gen_ldq_env_A0(s
, offsetof(CPUX86State
, xmm_t0
.XMM_D(0)));
4326 /* 128 bit access */
4327 gen_ldo_env_A0(s
, op2_offset
);
4331 rm
= (modrm
& 7) | REX_B(s
);
4332 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4335 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4337 gen_lea_modrm(env
, s
, modrm
);
4338 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4339 gen_ldq_env_A0(s
, op2_offset
);
4342 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4346 case 0x0f: /* 3DNow! data insns */
4347 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4349 val
= cpu_ldub_code(env
, s
->pc
++);
4350 sse_fn_epp
= sse_op_table5
[val
];
4354 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4355 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4356 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4358 case 0x70: /* pshufx insn */
4359 case 0xc6: /* pshufx insn */
4360 val
= cpu_ldub_code(env
, s
->pc
++);
4361 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4362 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4363 /* XXX: introduce a new table? */
4364 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4365 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4369 val
= cpu_ldub_code(env
, s
->pc
++);
4372 sse_fn_epp
= sse_op_table4
[val
][b1
];
4374 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4375 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4376 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4379 /* maskmov : we must prepare A0 */
4382 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EDI
]);
4383 gen_extu(s
->aflag
, cpu_A0
);
4384 gen_add_A0_ds_seg(s
);
4386 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4387 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4388 /* XXX: introduce a new table? */
4389 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4390 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4393 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4394 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4395 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4398 if (b
== 0x2e || b
== 0x2f) {
4399 set_cc_op(s
, CC_OP_EFLAGS
);
4404 /* convert one instruction. s->is_jmp is set if the translation must
4405 be stopped. Return the next pc value */
4406 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4407 target_ulong pc_start
)
4411 TCGMemOp ot
, aflag
, dflag
;
4412 int modrm
, reg
, rm
, mod
, op
, opreg
, val
;
4413 target_ulong next_eip
, tval
;
4416 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4417 tcg_gen_debug_insn_start(pc_start
);
4424 #ifdef TARGET_X86_64
4429 s
->rip_offset
= 0; /* for relative ip address */
4433 b
= cpu_ldub_code(env
, s
->pc
);
4435 /* Collect prefixes. */
4438 prefixes
|= PREFIX_REPZ
;
4441 prefixes
|= PREFIX_REPNZ
;
4444 prefixes
|= PREFIX_LOCK
;
4465 prefixes
|= PREFIX_DATA
;
4468 prefixes
|= PREFIX_ADR
;
4470 #ifdef TARGET_X86_64
4474 rex_w
= (b
>> 3) & 1;
4475 rex_r
= (b
& 0x4) << 1;
4476 s
->rex_x
= (b
& 0x2) << 2;
4477 REX_B(s
) = (b
& 0x1) << 3;
4478 x86_64_hregs
= 1; /* select uniform byte register addressing */
4483 case 0xc5: /* 2-byte VEX */
4484 case 0xc4: /* 3-byte VEX */
4485 /* VEX prefixes cannot be used except in 32-bit mode.
4486 Otherwise the instruction is LES or LDS. */
4487 if (s
->code32
&& !s
->vm86
) {
4488 static const int pp_prefix
[4] = {
4489 0, PREFIX_DATA
, PREFIX_REPZ
, PREFIX_REPNZ
4491 int vex3
, vex2
= cpu_ldub_code(env
, s
->pc
);
4493 if (!CODE64(s
) && (vex2
& 0xc0) != 0xc0) {
4494 /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
4495 otherwise the instruction is LES or LDS. */
4500 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
4501 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
4502 | PREFIX_LOCK
| PREFIX_DATA
)) {
4505 #ifdef TARGET_X86_64
4510 rex_r
= (~vex2
>> 4) & 8;
4513 b
= cpu_ldub_code(env
, s
->pc
++);
4515 #ifdef TARGET_X86_64
4516 s
->rex_x
= (~vex2
>> 3) & 8;
4517 s
->rex_b
= (~vex2
>> 2) & 8;
4519 vex3
= cpu_ldub_code(env
, s
->pc
++);
4520 rex_w
= (vex3
>> 7) & 1;
4521 switch (vex2
& 0x1f) {
4522 case 0x01: /* Implied 0f leading opcode bytes. */
4523 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4525 case 0x02: /* Implied 0f 38 leading opcode bytes. */
4528 case 0x03: /* Implied 0f 3a leading opcode bytes. */
4531 default: /* Reserved for future use. */
4535 s
->vex_v
= (~vex3
>> 3) & 0xf;
4536 s
->vex_l
= (vex3
>> 2) & 1;
4537 prefixes
|= pp_prefix
[vex3
& 3] | PREFIX_VEX
;
4542 /* Post-process prefixes. */
4544 /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
4545 data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
4546 over 0x66 if both are present. */
4547 dflag
= (rex_w
> 0 ? MO_64
: prefixes
& PREFIX_DATA
? MO_16
: MO_32
);
4548 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
4549 aflag
= (prefixes
& PREFIX_ADR
? MO_32
: MO_64
);
4551 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
4552 if (s
->code32
^ ((prefixes
& PREFIX_DATA
) != 0)) {
4557 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
4558 if (s
->code32
^ ((prefixes
& PREFIX_ADR
) != 0)) {
4565 s
->prefix
= prefixes
;
4569 /* lock generation */
4570 if (prefixes
& PREFIX_LOCK
)
4573 /* now check op code */
4577 /**************************/
4578 /* extended op code */
4579 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4582 /**************************/
4597 ot
= mo_b_d(b
, dflag
);
4600 case 0: /* OP Ev, Gv */
4601 modrm
= cpu_ldub_code(env
, s
->pc
++);
4602 reg
= ((modrm
>> 3) & 7) | rex_r
;
4603 mod
= (modrm
>> 6) & 3;
4604 rm
= (modrm
& 7) | REX_B(s
);
4606 gen_lea_modrm(env
, s
, modrm
);
4608 } else if (op
== OP_XORL
&& rm
== reg
) {
4610 /* xor reg, reg optimisation */
4611 set_cc_op(s
, CC_OP_CLR
);
4612 tcg_gen_movi_tl(cpu_T
[0], 0);
4613 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
4618 gen_op_mov_v_reg(ot
, cpu_T
[1], reg
);
4619 gen_op(s
, op
, ot
, opreg
);
4621 case 1: /* OP Gv, Ev */
4622 modrm
= cpu_ldub_code(env
, s
->pc
++);
4623 mod
= (modrm
>> 6) & 3;
4624 reg
= ((modrm
>> 3) & 7) | rex_r
;
4625 rm
= (modrm
& 7) | REX_B(s
);
4627 gen_lea_modrm(env
, s
, modrm
);
4628 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4629 } else if (op
== OP_XORL
&& rm
== reg
) {
4632 gen_op_mov_v_reg(ot
, cpu_T
[1], rm
);
4634 gen_op(s
, op
, ot
, reg
);
4636 case 2: /* OP A, Iv */
4637 val
= insn_get(env
, s
, ot
);
4638 tcg_gen_movi_tl(cpu_T
[1], val
);
4639 gen_op(s
, op
, ot
, OR_EAX
);
4648 case 0x80: /* GRP1 */
4654 ot
= mo_b_d(b
, dflag
);
4656 modrm
= cpu_ldub_code(env
, s
->pc
++);
4657 mod
= (modrm
>> 6) & 3;
4658 rm
= (modrm
& 7) | REX_B(s
);
4659 op
= (modrm
>> 3) & 7;
4665 s
->rip_offset
= insn_const_size(ot
);
4666 gen_lea_modrm(env
, s
, modrm
);
4677 val
= insn_get(env
, s
, ot
);
4680 val
= (int8_t)insn_get(env
, s
, MO_8
);
4683 tcg_gen_movi_tl(cpu_T
[1], val
);
4684 gen_op(s
, op
, ot
, opreg
);
4688 /**************************/
4689 /* inc, dec, and other misc arith */
4690 case 0x40 ... 0x47: /* inc Gv */
4692 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4694 case 0x48 ... 0x4f: /* dec Gv */
4696 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4698 case 0xf6: /* GRP3 */
4700 ot
= mo_b_d(b
, dflag
);
4702 modrm
= cpu_ldub_code(env
, s
->pc
++);
4703 mod
= (modrm
>> 6) & 3;
4704 rm
= (modrm
& 7) | REX_B(s
);
4705 op
= (modrm
>> 3) & 7;
4708 s
->rip_offset
= insn_const_size(ot
);
4709 gen_lea_modrm(env
, s
, modrm
);
4710 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4712 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
4717 val
= insn_get(env
, s
, ot
);
4718 tcg_gen_movi_tl(cpu_T
[1], val
);
4719 gen_op_testl_T0_T1_cc();
4720 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4723 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4725 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4727 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4731 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4733 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4735 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4737 gen_op_update_neg_cc();
4738 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4743 gen_op_mov_v_reg(MO_8
, cpu_T
[1], R_EAX
);
4744 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4745 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4746 /* XXX: use 32 bit mul which could be faster */
4747 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4748 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4749 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4750 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4751 set_cc_op(s
, CC_OP_MULB
);
4754 gen_op_mov_v_reg(MO_16
, cpu_T
[1], R_EAX
);
4755 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4756 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4757 /* XXX: use 32 bit mul which could be faster */
4758 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4759 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4760 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4761 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4762 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
4763 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4764 set_cc_op(s
, CC_OP_MULW
);
4768 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4769 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4770 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4771 cpu_tmp2_i32
, cpu_tmp3_i32
);
4772 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4773 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4774 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4775 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4776 set_cc_op(s
, CC_OP_MULL
);
4778 #ifdef TARGET_X86_64
4780 tcg_gen_mulu2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4781 cpu_T
[0], cpu_regs
[R_EAX
]);
4782 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4783 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4784 set_cc_op(s
, CC_OP_MULQ
);
4792 gen_op_mov_v_reg(MO_8
, cpu_T
[1], R_EAX
);
4793 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4794 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4795 /* XXX: use 32 bit mul which could be faster */
4796 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4797 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4798 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4799 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4800 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4801 set_cc_op(s
, CC_OP_MULB
);
4804 gen_op_mov_v_reg(MO_16
, cpu_T
[1], R_EAX
);
4805 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4806 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4807 /* XXX: use 32 bit mul which could be faster */
4808 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4809 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
4810 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4811 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4812 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4813 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4814 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
4815 set_cc_op(s
, CC_OP_MULW
);
4819 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4820 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4821 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4822 cpu_tmp2_i32
, cpu_tmp3_i32
);
4823 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4824 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4825 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
4826 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4827 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
4828 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
4829 set_cc_op(s
, CC_OP_MULL
);
4831 #ifdef TARGET_X86_64
4833 tcg_gen_muls2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4834 cpu_T
[0], cpu_regs
[R_EAX
]);
4835 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4836 tcg_gen_sari_tl(cpu_cc_src
, cpu_regs
[R_EAX
], 63);
4837 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_regs
[R_EDX
]);
4838 set_cc_op(s
, CC_OP_MULQ
);
4846 gen_jmp_im(pc_start
- s
->cs_base
);
4847 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4850 gen_jmp_im(pc_start
- s
->cs_base
);
4851 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4855 gen_jmp_im(pc_start
- s
->cs_base
);
4856 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4858 #ifdef TARGET_X86_64
4860 gen_jmp_im(pc_start
- s
->cs_base
);
4861 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4869 gen_jmp_im(pc_start
- s
->cs_base
);
4870 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4873 gen_jmp_im(pc_start
- s
->cs_base
);
4874 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4878 gen_jmp_im(pc_start
- s
->cs_base
);
4879 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4881 #ifdef TARGET_X86_64
4883 gen_jmp_im(pc_start
- s
->cs_base
);
4884 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4894 case 0xfe: /* GRP4 */
4895 case 0xff: /* GRP5 */
4896 ot
= mo_b_d(b
, dflag
);
4898 modrm
= cpu_ldub_code(env
, s
->pc
++);
4899 mod
= (modrm
>> 6) & 3;
4900 rm
= (modrm
& 7) | REX_B(s
);
4901 op
= (modrm
>> 3) & 7;
4902 if (op
>= 2 && b
== 0xfe) {
4906 if (op
== 2 || op
== 4) {
4907 /* operand size for jumps is 64 bit */
4909 } else if (op
== 3 || op
== 5) {
4910 ot
= dflag
!= MO_16
? MO_32
+ (rex_w
== 1) : MO_16
;
4911 } else if (op
== 6) {
4912 /* default push size is 64 bit */
4913 ot
= mo_pushpop(s
, dflag
);
4917 gen_lea_modrm(env
, s
, modrm
);
4918 if (op
>= 2 && op
!= 3 && op
!= 5)
4919 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4921 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
4925 case 0: /* inc Ev */
4930 gen_inc(s
, ot
, opreg
, 1);
4932 case 1: /* dec Ev */
4937 gen_inc(s
, ot
, opreg
, -1);
4939 case 2: /* call Ev */
4940 /* XXX: optimize if memory (no 'and' is necessary) */
4941 if (dflag
== MO_16
) {
4942 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4944 next_eip
= s
->pc
- s
->cs_base
;
4945 tcg_gen_movi_tl(cpu_T
[1], next_eip
);
4946 gen_push_v(s
, cpu_T
[1]);
4947 gen_op_jmp_v(cpu_T
[0]);
4950 case 3: /* lcall Ev */
4951 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4952 gen_add_A0_im(s
, 1 << ot
);
4953 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
4955 if (s
->pe
&& !s
->vm86
) {
4956 gen_update_cc_op(s
);
4957 gen_jmp_im(pc_start
- s
->cs_base
);
4958 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4959 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4960 tcg_const_i32(dflag
- 1),
4961 tcg_const_i32(s
->pc
- pc_start
));
4963 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4964 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4965 tcg_const_i32(dflag
- 1),
4966 tcg_const_i32(s
->pc
- s
->cs_base
));
4970 case 4: /* jmp Ev */
4971 if (dflag
== MO_16
) {
4972 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4974 gen_op_jmp_v(cpu_T
[0]);
4977 case 5: /* ljmp Ev */
4978 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4979 gen_add_A0_im(s
, 1 << ot
);
4980 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
4982 if (s
->pe
&& !s
->vm86
) {
4983 gen_update_cc_op(s
);
4984 gen_jmp_im(pc_start
- s
->cs_base
);
4985 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4986 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4987 tcg_const_i32(s
->pc
- pc_start
));
4989 gen_op_movl_seg_T0_vm(R_CS
);
4990 gen_op_jmp_v(cpu_T
[1]);
4994 case 6: /* push Ev */
4995 gen_push_v(s
, cpu_T
[0]);
5002 case 0x84: /* test Ev, Gv */
5004 ot
= mo_b_d(b
, dflag
);
5006 modrm
= cpu_ldub_code(env
, s
->pc
++);
5007 reg
= ((modrm
>> 3) & 7) | rex_r
;
5009 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5010 gen_op_mov_v_reg(ot
, cpu_T
[1], reg
);
5011 gen_op_testl_T0_T1_cc();
5012 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5015 case 0xa8: /* test eAX, Iv */
5017 ot
= mo_b_d(b
, dflag
);
5018 val
= insn_get(env
, s
, ot
);
5020 gen_op_mov_v_reg(ot
, cpu_T
[0], OR_EAX
);
5021 tcg_gen_movi_tl(cpu_T
[1], val
);
5022 gen_op_testl_T0_T1_cc();
5023 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5026 case 0x98: /* CWDE/CBW */
5028 #ifdef TARGET_X86_64
5030 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EAX
);
5031 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5032 gen_op_mov_reg_v(MO_64
, R_EAX
, cpu_T
[0]);
5036 gen_op_mov_v_reg(MO_16
, cpu_T
[0], R_EAX
);
5037 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5038 gen_op_mov_reg_v(MO_32
, R_EAX
, cpu_T
[0]);
5041 gen_op_mov_v_reg(MO_8
, cpu_T
[0], R_EAX
);
5042 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5043 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
5049 case 0x99: /* CDQ/CWD */
5051 #ifdef TARGET_X86_64
5053 gen_op_mov_v_reg(MO_64
, cpu_T
[0], R_EAX
);
5054 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
5055 gen_op_mov_reg_v(MO_64
, R_EDX
, cpu_T
[0]);
5059 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EAX
);
5060 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5061 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
5062 gen_op_mov_reg_v(MO_32
, R_EDX
, cpu_T
[0]);
5065 gen_op_mov_v_reg(MO_16
, cpu_T
[0], R_EAX
);
5066 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5067 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
5068 gen_op_mov_reg_v(MO_16
, R_EDX
, cpu_T
[0]);
5074 case 0x1af: /* imul Gv, Ev */
5075 case 0x69: /* imul Gv, Ev, I */
5078 modrm
= cpu_ldub_code(env
, s
->pc
++);
5079 reg
= ((modrm
>> 3) & 7) | rex_r
;
5081 s
->rip_offset
= insn_const_size(ot
);
5084 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5086 val
= insn_get(env
, s
, ot
);
5087 tcg_gen_movi_tl(cpu_T
[1], val
);
5088 } else if (b
== 0x6b) {
5089 val
= (int8_t)insn_get(env
, s
, MO_8
);
5090 tcg_gen_movi_tl(cpu_T
[1], val
);
5092 gen_op_mov_v_reg(ot
, cpu_T
[1], reg
);
5095 #ifdef TARGET_X86_64
5097 tcg_gen_muls2_i64(cpu_regs
[reg
], cpu_T
[1], cpu_T
[0], cpu_T
[1]);
5098 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5099 tcg_gen_sari_tl(cpu_cc_src
, cpu_cc_dst
, 63);
5100 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[1]);
5104 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5105 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
5106 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
5107 cpu_tmp2_i32
, cpu_tmp3_i32
);
5108 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
5109 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
5110 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5111 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
5112 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
5115 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5116 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
5117 /* XXX: use 32 bit mul which could be faster */
5118 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5119 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5120 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
5121 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5122 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5125 set_cc_op(s
, CC_OP_MULB
+ ot
);
5128 case 0x1c1: /* xadd Ev, Gv */
5129 ot
= mo_b_d(b
, dflag
);
5130 modrm
= cpu_ldub_code(env
, s
->pc
++);
5131 reg
= ((modrm
>> 3) & 7) | rex_r
;
5132 mod
= (modrm
>> 6) & 3;
5134 rm
= (modrm
& 7) | REX_B(s
);
5135 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
5136 gen_op_mov_v_reg(ot
, cpu_T
[1], rm
);
5137 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5138 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5139 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5141 gen_lea_modrm(env
, s
, modrm
);
5142 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
5143 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5144 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5145 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5146 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5148 gen_op_update2_cc();
5149 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5152 case 0x1b1: /* cmpxchg Ev, Gv */
5154 TCGLabel
*label1
, *label2
;
5155 TCGv t0
, t1
, t2
, a0
;
5157 ot
= mo_b_d(b
, dflag
);
5158 modrm
= cpu_ldub_code(env
, s
->pc
++);
5159 reg
= ((modrm
>> 3) & 7) | rex_r
;
5160 mod
= (modrm
>> 6) & 3;
5161 t0
= tcg_temp_local_new();
5162 t1
= tcg_temp_local_new();
5163 t2
= tcg_temp_local_new();
5164 a0
= tcg_temp_local_new();
5165 gen_op_mov_v_reg(ot
, t1
, reg
);
5167 rm
= (modrm
& 7) | REX_B(s
);
5168 gen_op_mov_v_reg(ot
, t0
, rm
);
5170 gen_lea_modrm(env
, s
, modrm
);
5171 tcg_gen_mov_tl(a0
, cpu_A0
);
5172 gen_op_ld_v(s
, ot
, t0
, a0
);
5173 rm
= 0; /* avoid warning */
5175 label1
= gen_new_label();
5176 tcg_gen_mov_tl(t2
, cpu_regs
[R_EAX
]);
5179 tcg_gen_brcond_tl(TCG_COND_EQ
, t2
, t0
, label1
);
5180 label2
= gen_new_label();
5182 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5184 gen_set_label(label1
);
5185 gen_op_mov_reg_v(ot
, rm
, t1
);
5187 /* perform no-op store cycle like physical cpu; must be
5188 before changing accumulator to ensure idempotency if
5189 the store faults and the instruction is restarted */
5190 gen_op_st_v(s
, ot
, t0
, a0
);
5191 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5193 gen_set_label(label1
);
5194 gen_op_st_v(s
, ot
, t1
, a0
);
5196 gen_set_label(label2
);
5197 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5198 tcg_gen_mov_tl(cpu_cc_srcT
, t2
);
5199 tcg_gen_sub_tl(cpu_cc_dst
, t2
, t0
);
5200 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5207 case 0x1c7: /* cmpxchg8b */
5208 modrm
= cpu_ldub_code(env
, s
->pc
++);
5209 mod
= (modrm
>> 6) & 3;
5210 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5212 #ifdef TARGET_X86_64
5213 if (dflag
== MO_64
) {
5214 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5216 gen_jmp_im(pc_start
- s
->cs_base
);
5217 gen_update_cc_op(s
);
5218 gen_lea_modrm(env
, s
, modrm
);
5219 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5223 if (!(s
->cpuid_features
& CPUID_CX8
))
5225 gen_jmp_im(pc_start
- s
->cs_base
);
5226 gen_update_cc_op(s
);
5227 gen_lea_modrm(env
, s
, modrm
);
5228 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5230 set_cc_op(s
, CC_OP_EFLAGS
);
5233 /**************************/
5235 case 0x50 ... 0x57: /* push */
5236 gen_op_mov_v_reg(MO_32
, cpu_T
[0], (b
& 7) | REX_B(s
));
5237 gen_push_v(s
, cpu_T
[0]);
5239 case 0x58 ... 0x5f: /* pop */
5241 /* NOTE: order is important for pop %sp */
5242 gen_pop_update(s
, ot
);
5243 gen_op_mov_reg_v(ot
, (b
& 7) | REX_B(s
), cpu_T
[0]);
5245 case 0x60: /* pusha */
5250 case 0x61: /* popa */
5255 case 0x68: /* push Iv */
5257 ot
= mo_pushpop(s
, dflag
);
5259 val
= insn_get(env
, s
, ot
);
5261 val
= (int8_t)insn_get(env
, s
, MO_8
);
5262 tcg_gen_movi_tl(cpu_T
[0], val
);
5263 gen_push_v(s
, cpu_T
[0]);
5265 case 0x8f: /* pop Ev */
5266 modrm
= cpu_ldub_code(env
, s
->pc
++);
5267 mod
= (modrm
>> 6) & 3;
5270 /* NOTE: order is important for pop %sp */
5271 gen_pop_update(s
, ot
);
5272 rm
= (modrm
& 7) | REX_B(s
);
5273 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5275 /* NOTE: order is important too for MMU exceptions */
5276 s
->popl_esp_hack
= 1 << ot
;
5277 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5278 s
->popl_esp_hack
= 0;
5279 gen_pop_update(s
, ot
);
5282 case 0xc8: /* enter */
5285 val
= cpu_lduw_code(env
, s
->pc
);
5287 level
= cpu_ldub_code(env
, s
->pc
++);
5288 gen_enter(s
, val
, level
);
5291 case 0xc9: /* leave */
5292 /* XXX: exception not precise (ESP is updated before potential exception) */
5294 gen_op_mov_v_reg(MO_64
, cpu_T
[0], R_EBP
);
5295 gen_op_mov_reg_v(MO_64
, R_ESP
, cpu_T
[0]);
5296 } else if (s
->ss32
) {
5297 gen_op_mov_v_reg(MO_32
, cpu_T
[0], R_EBP
);
5298 gen_op_mov_reg_v(MO_32
, R_ESP
, cpu_T
[0]);
5300 gen_op_mov_v_reg(MO_16
, cpu_T
[0], R_EBP
);
5301 gen_op_mov_reg_v(MO_16
, R_ESP
, cpu_T
[0]);
5304 gen_op_mov_reg_v(ot
, R_EBP
, cpu_T
[0]);
5305 gen_pop_update(s
, ot
);
5307 case 0x06: /* push es */
5308 case 0x0e: /* push cs */
5309 case 0x16: /* push ss */
5310 case 0x1e: /* push ds */
5313 gen_op_movl_T0_seg(b
>> 3);
5314 gen_push_v(s
, cpu_T
[0]);
5316 case 0x1a0: /* push fs */
5317 case 0x1a8: /* push gs */
5318 gen_op_movl_T0_seg((b
>> 3) & 7);
5319 gen_push_v(s
, cpu_T
[0]);
5321 case 0x07: /* pop es */
5322 case 0x17: /* pop ss */
5323 case 0x1f: /* pop ds */
5328 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5329 gen_pop_update(s
, ot
);
5331 /* if reg == SS, inhibit interrupts/trace. */
5332 /* If several instructions disable interrupts, only the
5334 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5335 gen_helper_set_inhibit_irq(cpu_env
);
5339 gen_jmp_im(s
->pc
- s
->cs_base
);
5343 case 0x1a1: /* pop fs */
5344 case 0x1a9: /* pop gs */
5346 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5347 gen_pop_update(s
, ot
);
5349 gen_jmp_im(s
->pc
- s
->cs_base
);
5354 /**************************/
5357 case 0x89: /* mov Gv, Ev */
5358 ot
= mo_b_d(b
, dflag
);
5359 modrm
= cpu_ldub_code(env
, s
->pc
++);
5360 reg
= ((modrm
>> 3) & 7) | rex_r
;
5362 /* generate a generic store */
5363 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5366 case 0xc7: /* mov Ev, Iv */
5367 ot
= mo_b_d(b
, dflag
);
5368 modrm
= cpu_ldub_code(env
, s
->pc
++);
5369 mod
= (modrm
>> 6) & 3;
5371 s
->rip_offset
= insn_const_size(ot
);
5372 gen_lea_modrm(env
, s
, modrm
);
5374 val
= insn_get(env
, s
, ot
);
5375 tcg_gen_movi_tl(cpu_T
[0], val
);
5377 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5379 gen_op_mov_reg_v(ot
, (modrm
& 7) | REX_B(s
), cpu_T
[0]);
5383 case 0x8b: /* mov Ev, Gv */
5384 ot
= mo_b_d(b
, dflag
);
5385 modrm
= cpu_ldub_code(env
, s
->pc
++);
5386 reg
= ((modrm
>> 3) & 7) | rex_r
;
5388 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5389 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5391 case 0x8e: /* mov seg, Gv */
5392 modrm
= cpu_ldub_code(env
, s
->pc
++);
5393 reg
= (modrm
>> 3) & 7;
5394 if (reg
>= 6 || reg
== R_CS
)
5396 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
5397 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5399 /* if reg == SS, inhibit interrupts/trace */
5400 /* If several instructions disable interrupts, only the
5402 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5403 gen_helper_set_inhibit_irq(cpu_env
);
5407 gen_jmp_im(s
->pc
- s
->cs_base
);
5411 case 0x8c: /* mov Gv, seg */
5412 modrm
= cpu_ldub_code(env
, s
->pc
++);
5413 reg
= (modrm
>> 3) & 7;
5414 mod
= (modrm
>> 6) & 3;
5417 gen_op_movl_T0_seg(reg
);
5418 ot
= mod
== 3 ? dflag
: MO_16
;
5419 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5422 case 0x1b6: /* movzbS Gv, Eb */
5423 case 0x1b7: /* movzwS Gv, Eb */
5424 case 0x1be: /* movsbS Gv, Eb */
5425 case 0x1bf: /* movswS Gv, Eb */
5430 /* d_ot is the size of destination */
5432 /* ot is the size of source */
5433 ot
= (b
& 1) + MO_8
;
5434 /* s_ot is the sign+size of source */
5435 s_ot
= b
& 8 ? MO_SIGN
| ot
: ot
;
5437 modrm
= cpu_ldub_code(env
, s
->pc
++);
5438 reg
= ((modrm
>> 3) & 7) | rex_r
;
5439 mod
= (modrm
>> 6) & 3;
5440 rm
= (modrm
& 7) | REX_B(s
);
5443 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
5446 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5449 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5452 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5456 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5459 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
5461 gen_lea_modrm(env
, s
, modrm
);
5462 gen_op_ld_v(s
, s_ot
, cpu_T
[0], cpu_A0
);
5463 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
5468 case 0x8d: /* lea */
5470 modrm
= cpu_ldub_code(env
, s
->pc
++);
5471 mod
= (modrm
>> 6) & 3;
5474 reg
= ((modrm
>> 3) & 7) | rex_r
;
5475 /* we must ensure that no segment is added */
5479 gen_lea_modrm(env
, s
, modrm
);
5481 gen_op_mov_reg_v(ot
, reg
, cpu_A0
);
5484 case 0xa0: /* mov EAX, Ov */
5486 case 0xa2: /* mov Ov, EAX */
5489 target_ulong offset_addr
;
5491 ot
= mo_b_d(b
, dflag
);
5493 #ifdef TARGET_X86_64
5495 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5500 offset_addr
= insn_get(env
, s
, s
->aflag
);
5503 tcg_gen_movi_tl(cpu_A0
, offset_addr
);
5504 gen_add_A0_ds_seg(s
);
5506 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
5507 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[0]);
5509 gen_op_mov_v_reg(ot
, cpu_T
[0], R_EAX
);
5510 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5514 case 0xd7: /* xlat */
5515 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EBX
]);
5516 tcg_gen_ext8u_tl(cpu_T
[0], cpu_regs
[R_EAX
]);
5517 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5518 gen_extu(s
->aflag
, cpu_A0
);
5519 gen_add_A0_ds_seg(s
);
5520 gen_op_ld_v(s
, MO_8
, cpu_T
[0], cpu_A0
);
5521 gen_op_mov_reg_v(MO_8
, R_EAX
, cpu_T
[0]);
5523 case 0xb0 ... 0xb7: /* mov R, Ib */
5524 val
= insn_get(env
, s
, MO_8
);
5525 tcg_gen_movi_tl(cpu_T
[0], val
);
5526 gen_op_mov_reg_v(MO_8
, (b
& 7) | REX_B(s
), cpu_T
[0]);
5528 case 0xb8 ... 0xbf: /* mov R, Iv */
5529 #ifdef TARGET_X86_64
5530 if (dflag
== MO_64
) {
5533 tmp
= cpu_ldq_code(env
, s
->pc
);
5535 reg
= (b
& 7) | REX_B(s
);
5536 tcg_gen_movi_tl(cpu_T
[0], tmp
);
5537 gen_op_mov_reg_v(MO_64
, reg
, cpu_T
[0]);
5542 val
= insn_get(env
, s
, ot
);
5543 reg
= (b
& 7) | REX_B(s
);
5544 tcg_gen_movi_tl(cpu_T
[0], val
);
5545 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
5549 case 0x91 ... 0x97: /* xchg R, EAX */
5552 reg
= (b
& 7) | REX_B(s
);
5556 case 0x87: /* xchg Ev, Gv */
5557 ot
= mo_b_d(b
, dflag
);
5558 modrm
= cpu_ldub_code(env
, s
->pc
++);
5559 reg
= ((modrm
>> 3) & 7) | rex_r
;
5560 mod
= (modrm
>> 6) & 3;
5562 rm
= (modrm
& 7) | REX_B(s
);
5564 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
5565 gen_op_mov_v_reg(ot
, cpu_T
[1], rm
);
5566 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
5567 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5569 gen_lea_modrm(env
, s
, modrm
);
5570 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
5571 /* for xchg, lock is implicit */
5572 if (!(prefixes
& PREFIX_LOCK
))
5574 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5575 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5576 if (!(prefixes
& PREFIX_LOCK
))
5577 gen_helper_unlock();
5578 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5581 case 0xc4: /* les Gv */
5582 /* In CODE64 this is VEX3; see above. */
5585 case 0xc5: /* lds Gv */
5586 /* In CODE64 this is VEX2; see above. */
5589 case 0x1b2: /* lss Gv */
5592 case 0x1b4: /* lfs Gv */
5595 case 0x1b5: /* lgs Gv */
5598 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
5599 modrm
= cpu_ldub_code(env
, s
->pc
++);
5600 reg
= ((modrm
>> 3) & 7) | rex_r
;
5601 mod
= (modrm
>> 6) & 3;
5604 gen_lea_modrm(env
, s
, modrm
);
5605 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5606 gen_add_A0_im(s
, 1 << ot
);
5607 /* load the segment first to handle exceptions properly */
5608 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5609 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5610 /* then put the data */
5611 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
5613 gen_jmp_im(s
->pc
- s
->cs_base
);
5618 /************************/
5626 ot
= mo_b_d(b
, dflag
);
5627 modrm
= cpu_ldub_code(env
, s
->pc
++);
5628 mod
= (modrm
>> 6) & 3;
5629 op
= (modrm
>> 3) & 7;
5635 gen_lea_modrm(env
, s
, modrm
);
5638 opreg
= (modrm
& 7) | REX_B(s
);
5643 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5646 shift
= cpu_ldub_code(env
, s
->pc
++);
5648 gen_shifti(s
, op
, ot
, opreg
, shift
);
5663 case 0x1a4: /* shld imm */
5667 case 0x1a5: /* shld cl */
5671 case 0x1ac: /* shrd imm */
5675 case 0x1ad: /* shrd cl */
5680 modrm
= cpu_ldub_code(env
, s
->pc
++);
5681 mod
= (modrm
>> 6) & 3;
5682 rm
= (modrm
& 7) | REX_B(s
);
5683 reg
= ((modrm
>> 3) & 7) | rex_r
;
5685 gen_lea_modrm(env
, s
, modrm
);
5690 gen_op_mov_v_reg(ot
, cpu_T
[1], reg
);
5693 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5694 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5697 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5701 /************************/
5704 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5705 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5706 /* XXX: what to do if illegal op ? */
5707 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5710 modrm
= cpu_ldub_code(env
, s
->pc
++);
5711 mod
= (modrm
>> 6) & 3;
5713 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5716 gen_lea_modrm(env
, s
, modrm
);
5718 case 0x00 ... 0x07: /* fxxxs */
5719 case 0x10 ... 0x17: /* fixxxl */
5720 case 0x20 ... 0x27: /* fxxxl */
5721 case 0x30 ... 0x37: /* fixxx */
5728 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5729 s
->mem_index
, MO_LEUL
);
5730 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5733 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5734 s
->mem_index
, MO_LEUL
);
5735 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5738 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5739 s
->mem_index
, MO_LEQ
);
5740 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5744 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5745 s
->mem_index
, MO_LESW
);
5746 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5750 gen_helper_fp_arith_ST0_FT0(op1
);
5752 /* fcomp needs pop */
5753 gen_helper_fpop(cpu_env
);
5757 case 0x08: /* flds */
5758 case 0x0a: /* fsts */
5759 case 0x0b: /* fstps */
5760 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5761 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5762 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5767 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5768 s
->mem_index
, MO_LEUL
);
5769 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5772 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5773 s
->mem_index
, MO_LEUL
);
5774 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5777 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5778 s
->mem_index
, MO_LEQ
);
5779 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5783 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5784 s
->mem_index
, MO_LESW
);
5785 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5790 /* XXX: the corresponding CPUID bit must be tested ! */
5793 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5794 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5795 s
->mem_index
, MO_LEUL
);
5798 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5799 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5800 s
->mem_index
, MO_LEQ
);
5804 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5805 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5806 s
->mem_index
, MO_LEUW
);
5809 gen_helper_fpop(cpu_env
);
5814 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5815 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5816 s
->mem_index
, MO_LEUL
);
5819 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5820 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5821 s
->mem_index
, MO_LEUL
);
5824 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5825 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5826 s
->mem_index
, MO_LEQ
);
5830 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5831 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5832 s
->mem_index
, MO_LEUW
);
5836 gen_helper_fpop(cpu_env
);
5840 case 0x0c: /* fldenv mem */
5841 gen_update_cc_op(s
);
5842 gen_jmp_im(pc_start
- s
->cs_base
);
5843 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5845 case 0x0d: /* fldcw mem */
5846 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
5847 s
->mem_index
, MO_LEUW
);
5848 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5850 case 0x0e: /* fnstenv mem */
5851 gen_update_cc_op(s
);
5852 gen_jmp_im(pc_start
- s
->cs_base
);
5853 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5855 case 0x0f: /* fnstcw mem */
5856 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5857 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5858 s
->mem_index
, MO_LEUW
);
5860 case 0x1d: /* fldt mem */
5861 gen_update_cc_op(s
);
5862 gen_jmp_im(pc_start
- s
->cs_base
);
5863 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5865 case 0x1f: /* fstpt mem */
5866 gen_update_cc_op(s
);
5867 gen_jmp_im(pc_start
- s
->cs_base
);
5868 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5869 gen_helper_fpop(cpu_env
);
5871 case 0x2c: /* frstor mem */
5872 gen_update_cc_op(s
);
5873 gen_jmp_im(pc_start
- s
->cs_base
);
5874 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5876 case 0x2e: /* fnsave mem */
5877 gen_update_cc_op(s
);
5878 gen_jmp_im(pc_start
- s
->cs_base
);
5879 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
- 1));
5881 case 0x2f: /* fnstsw mem */
5882 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5883 tcg_gen_qemu_st_i32(cpu_tmp2_i32
, cpu_A0
,
5884 s
->mem_index
, MO_LEUW
);
5886 case 0x3c: /* fbld */
5887 gen_update_cc_op(s
);
5888 gen_jmp_im(pc_start
- s
->cs_base
);
5889 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5891 case 0x3e: /* fbstp */
5892 gen_update_cc_op(s
);
5893 gen_jmp_im(pc_start
- s
->cs_base
);
5894 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5895 gen_helper_fpop(cpu_env
);
5897 case 0x3d: /* fildll */
5898 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5899 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5901 case 0x3f: /* fistpll */
5902 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5903 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
5904 gen_helper_fpop(cpu_env
);
5910 /* register float ops */
5914 case 0x08: /* fld sti */
5915 gen_helper_fpush(cpu_env
);
5916 gen_helper_fmov_ST0_STN(cpu_env
,
5917 tcg_const_i32((opreg
+ 1) & 7));
5919 case 0x09: /* fxchg sti */
5920 case 0x29: /* fxchg4 sti, undocumented op */
5921 case 0x39: /* fxchg7 sti, undocumented op */
5922 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5924 case 0x0a: /* grp d9/2 */
5927 /* check exceptions (FreeBSD FPU probe) */
5928 gen_update_cc_op(s
);
5929 gen_jmp_im(pc_start
- s
->cs_base
);
5930 gen_helper_fwait(cpu_env
);
5936 case 0x0c: /* grp d9/4 */
5939 gen_helper_fchs_ST0(cpu_env
);
5942 gen_helper_fabs_ST0(cpu_env
);
5945 gen_helper_fldz_FT0(cpu_env
);
5946 gen_helper_fcom_ST0_FT0(cpu_env
);
5949 gen_helper_fxam_ST0(cpu_env
);
5955 case 0x0d: /* grp d9/5 */
5959 gen_helper_fpush(cpu_env
);
5960 gen_helper_fld1_ST0(cpu_env
);
5963 gen_helper_fpush(cpu_env
);
5964 gen_helper_fldl2t_ST0(cpu_env
);
5967 gen_helper_fpush(cpu_env
);
5968 gen_helper_fldl2e_ST0(cpu_env
);
5971 gen_helper_fpush(cpu_env
);
5972 gen_helper_fldpi_ST0(cpu_env
);
5975 gen_helper_fpush(cpu_env
);
5976 gen_helper_fldlg2_ST0(cpu_env
);
5979 gen_helper_fpush(cpu_env
);
5980 gen_helper_fldln2_ST0(cpu_env
);
5983 gen_helper_fpush(cpu_env
);
5984 gen_helper_fldz_ST0(cpu_env
);
5991 case 0x0e: /* grp d9/6 */
5994 gen_helper_f2xm1(cpu_env
);
5997 gen_helper_fyl2x(cpu_env
);
6000 gen_helper_fptan(cpu_env
);
6002 case 3: /* fpatan */
6003 gen_helper_fpatan(cpu_env
);
6005 case 4: /* fxtract */
6006 gen_helper_fxtract(cpu_env
);
6008 case 5: /* fprem1 */
6009 gen_helper_fprem1(cpu_env
);
6011 case 6: /* fdecstp */
6012 gen_helper_fdecstp(cpu_env
);
6015 case 7: /* fincstp */
6016 gen_helper_fincstp(cpu_env
);
6020 case 0x0f: /* grp d9/7 */
6023 gen_helper_fprem(cpu_env
);
6025 case 1: /* fyl2xp1 */
6026 gen_helper_fyl2xp1(cpu_env
);
6029 gen_helper_fsqrt(cpu_env
);
6031 case 3: /* fsincos */
6032 gen_helper_fsincos(cpu_env
);
6034 case 5: /* fscale */
6035 gen_helper_fscale(cpu_env
);
6037 case 4: /* frndint */
6038 gen_helper_frndint(cpu_env
);
6041 gen_helper_fsin(cpu_env
);
6045 gen_helper_fcos(cpu_env
);
6049 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6050 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6051 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6057 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
6059 gen_helper_fpop(cpu_env
);
6061 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6062 gen_helper_fp_arith_ST0_FT0(op1
);
6066 case 0x02: /* fcom */
6067 case 0x22: /* fcom2, undocumented op */
6068 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6069 gen_helper_fcom_ST0_FT0(cpu_env
);
6071 case 0x03: /* fcomp */
6072 case 0x23: /* fcomp3, undocumented op */
6073 case 0x32: /* fcomp5, undocumented op */
6074 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6075 gen_helper_fcom_ST0_FT0(cpu_env
);
6076 gen_helper_fpop(cpu_env
);
6078 case 0x15: /* da/5 */
6080 case 1: /* fucompp */
6081 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6082 gen_helper_fucom_ST0_FT0(cpu_env
);
6083 gen_helper_fpop(cpu_env
);
6084 gen_helper_fpop(cpu_env
);
6092 case 0: /* feni (287 only, just do nop here) */
6094 case 1: /* fdisi (287 only, just do nop here) */
6097 gen_helper_fclex(cpu_env
);
6099 case 3: /* fninit */
6100 gen_helper_fninit(cpu_env
);
6102 case 4: /* fsetpm (287 only, just do nop here) */
6108 case 0x1d: /* fucomi */
6109 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6112 gen_update_cc_op(s
);
6113 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6114 gen_helper_fucomi_ST0_FT0(cpu_env
);
6115 set_cc_op(s
, CC_OP_EFLAGS
);
6117 case 0x1e: /* fcomi */
6118 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6121 gen_update_cc_op(s
);
6122 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6123 gen_helper_fcomi_ST0_FT0(cpu_env
);
6124 set_cc_op(s
, CC_OP_EFLAGS
);
6126 case 0x28: /* ffree sti */
6127 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6129 case 0x2a: /* fst sti */
6130 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6132 case 0x2b: /* fstp sti */
6133 case 0x0b: /* fstp1 sti, undocumented op */
6134 case 0x3a: /* fstp8 sti, undocumented op */
6135 case 0x3b: /* fstp9 sti, undocumented op */
6136 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6137 gen_helper_fpop(cpu_env
);
6139 case 0x2c: /* fucom st(i) */
6140 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6141 gen_helper_fucom_ST0_FT0(cpu_env
);
6143 case 0x2d: /* fucomp st(i) */
6144 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6145 gen_helper_fucom_ST0_FT0(cpu_env
);
6146 gen_helper_fpop(cpu_env
);
6148 case 0x33: /* de/3 */
6150 case 1: /* fcompp */
6151 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6152 gen_helper_fcom_ST0_FT0(cpu_env
);
6153 gen_helper_fpop(cpu_env
);
6154 gen_helper_fpop(cpu_env
);
6160 case 0x38: /* ffreep sti, undocumented op */
6161 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6162 gen_helper_fpop(cpu_env
);
6164 case 0x3c: /* df/4 */
6167 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6168 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6169 gen_op_mov_reg_v(MO_16
, R_EAX
, cpu_T
[0]);
6175 case 0x3d: /* fucomip */
6176 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6179 gen_update_cc_op(s
);
6180 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6181 gen_helper_fucomi_ST0_FT0(cpu_env
);
6182 gen_helper_fpop(cpu_env
);
6183 set_cc_op(s
, CC_OP_EFLAGS
);
6185 case 0x3e: /* fcomip */
6186 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6189 gen_update_cc_op(s
);
6190 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6191 gen_helper_fcomi_ST0_FT0(cpu_env
);
6192 gen_helper_fpop(cpu_env
);
6193 set_cc_op(s
, CC_OP_EFLAGS
);
6195 case 0x10 ... 0x13: /* fcmovxx */
6200 static const uint8_t fcmov_cc
[8] = {
6207 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6210 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6211 l1
= gen_new_label();
6212 gen_jcc1_noeob(s
, op1
, l1
);
6213 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6222 /************************/
6225 case 0xa4: /* movsS */
6227 ot
= mo_b_d(b
, dflag
);
6228 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6229 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6235 case 0xaa: /* stosS */
6237 ot
= mo_b_d(b
, dflag
);
6238 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6239 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6244 case 0xac: /* lodsS */
6246 ot
= mo_b_d(b
, dflag
);
6247 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6248 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6253 case 0xae: /* scasS */
6255 ot
= mo_b_d(b
, dflag
);
6256 if (prefixes
& PREFIX_REPNZ
) {
6257 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6258 } else if (prefixes
& PREFIX_REPZ
) {
6259 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6265 case 0xa6: /* cmpsS */
6267 ot
= mo_b_d(b
, dflag
);
6268 if (prefixes
& PREFIX_REPNZ
) {
6269 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6270 } else if (prefixes
& PREFIX_REPZ
) {
6271 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6276 case 0x6c: /* insS */
6278 ot
= mo_b_d32(b
, dflag
);
6279 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6280 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6281 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6282 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6283 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6286 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6287 gen_jmp(s
, s
->pc
- s
->cs_base
);
6291 case 0x6e: /* outsS */
6293 ot
= mo_b_d32(b
, dflag
);
6294 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6295 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6296 svm_is_rep(prefixes
) | 4);
6297 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6298 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6301 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6302 gen_jmp(s
, s
->pc
- s
->cs_base
);
6307 /************************/
6312 ot
= mo_b_d32(b
, dflag
);
6313 val
= cpu_ldub_code(env
, s
->pc
++);
6314 tcg_gen_movi_tl(cpu_T
[0], val
);
6315 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6316 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6317 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6320 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6321 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6322 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[1]);
6323 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6325 gen_jmp(s
, s
->pc
- s
->cs_base
);
6330 ot
= mo_b_d32(b
, dflag
);
6331 val
= cpu_ldub_code(env
, s
->pc
++);
6332 tcg_gen_movi_tl(cpu_T
[0], val
);
6333 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6334 svm_is_rep(prefixes
));
6335 gen_op_mov_v_reg(ot
, cpu_T
[1], R_EAX
);
6337 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6340 tcg_gen_movi_i32(cpu_tmp2_i32
, val
);
6341 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6342 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6343 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6345 gen_jmp(s
, s
->pc
- s
->cs_base
);
6350 ot
= mo_b_d32(b
, dflag
);
6351 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6352 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6353 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6354 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6357 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6358 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6359 gen_op_mov_reg_v(ot
, R_EAX
, cpu_T
[1]);
6360 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6362 gen_jmp(s
, s
->pc
- s
->cs_base
);
6367 ot
= mo_b_d32(b
, dflag
);
6368 tcg_gen_ext16u_tl(cpu_T
[0], cpu_regs
[R_EDX
]);
6369 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6370 svm_is_rep(prefixes
));
6371 gen_op_mov_v_reg(ot
, cpu_T
[1], R_EAX
);
6373 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6376 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6377 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6378 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6379 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
6381 gen_jmp(s
, s
->pc
- s
->cs_base
);
6385 /************************/
6387 case 0xc2: /* ret im */
6388 val
= cpu_ldsw_code(env
, s
->pc
);
6391 gen_stack_update(s
, val
+ (1 << ot
));
6392 /* Note that gen_pop_T0 uses a zero-extending load. */
6393 gen_op_jmp_v(cpu_T
[0]);
6396 case 0xc3: /* ret */
6398 gen_pop_update(s
, ot
);
6399 /* Note that gen_pop_T0 uses a zero-extending load. */
6400 gen_op_jmp_v(cpu_T
[0]);
6403 case 0xca: /* lret im */
6404 val
= cpu_ldsw_code(env
, s
->pc
);
6407 if (s
->pe
&& !s
->vm86
) {
6408 gen_update_cc_op(s
);
6409 gen_jmp_im(pc_start
- s
->cs_base
);
6410 gen_helper_lret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6411 tcg_const_i32(val
));
6415 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6416 /* NOTE: keeping EIP updated is not a problem in case of
6418 gen_op_jmp_v(cpu_T
[0]);
6420 gen_op_addl_A0_im(1 << dflag
);
6421 gen_op_ld_v(s
, dflag
, cpu_T
[0], cpu_A0
);
6422 gen_op_movl_seg_T0_vm(R_CS
);
6423 /* add stack offset */
6424 gen_stack_update(s
, val
+ (2 << dflag
));
6428 case 0xcb: /* lret */
6431 case 0xcf: /* iret */
6432 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6435 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6436 set_cc_op(s
, CC_OP_EFLAGS
);
6437 } else if (s
->vm86
) {
6439 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6441 gen_helper_iret_real(cpu_env
, tcg_const_i32(dflag
- 1));
6442 set_cc_op(s
, CC_OP_EFLAGS
);
6445 gen_update_cc_op(s
);
6446 gen_jmp_im(pc_start
- s
->cs_base
);
6447 gen_helper_iret_protected(cpu_env
, tcg_const_i32(dflag
- 1),
6448 tcg_const_i32(s
->pc
- s
->cs_base
));
6449 set_cc_op(s
, CC_OP_EFLAGS
);
6453 case 0xe8: /* call im */
6455 if (dflag
!= MO_16
) {
6456 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6458 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6460 next_eip
= s
->pc
- s
->cs_base
;
6462 if (dflag
== MO_16
) {
6464 } else if (!CODE64(s
)) {
6467 tcg_gen_movi_tl(cpu_T
[0], next_eip
);
6468 gen_push_v(s
, cpu_T
[0]);
6472 case 0x9a: /* lcall im */
6474 unsigned int selector
, offset
;
6479 offset
= insn_get(env
, s
, ot
);
6480 selector
= insn_get(env
, s
, MO_16
);
6482 tcg_gen_movi_tl(cpu_T
[0], selector
);
6483 tcg_gen_movi_tl(cpu_T
[1], offset
);
6486 case 0xe9: /* jmp im */
6487 if (dflag
!= MO_16
) {
6488 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6490 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6492 tval
+= s
->pc
- s
->cs_base
;
6493 if (dflag
== MO_16
) {
6495 } else if (!CODE64(s
)) {
6500 case 0xea: /* ljmp im */
6502 unsigned int selector
, offset
;
6507 offset
= insn_get(env
, s
, ot
);
6508 selector
= insn_get(env
, s
, MO_16
);
6510 tcg_gen_movi_tl(cpu_T
[0], selector
);
6511 tcg_gen_movi_tl(cpu_T
[1], offset
);
6514 case 0xeb: /* jmp Jb */
6515 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6516 tval
+= s
->pc
- s
->cs_base
;
6517 if (dflag
== MO_16
) {
6522 case 0x70 ... 0x7f: /* jcc Jb */
6523 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6525 case 0x180 ... 0x18f: /* jcc Jv */
6526 if (dflag
!= MO_16
) {
6527 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6529 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6532 next_eip
= s
->pc
- s
->cs_base
;
6534 if (dflag
== MO_16
) {
6537 gen_jcc(s
, b
, tval
, next_eip
);
6540 case 0x190 ... 0x19f: /* setcc Gv */
6541 modrm
= cpu_ldub_code(env
, s
->pc
++);
6542 gen_setcc1(s
, b
, cpu_T
[0]);
6543 gen_ldst_modrm(env
, s
, modrm
, MO_8
, OR_TMP0
, 1);
6545 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6546 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6550 modrm
= cpu_ldub_code(env
, s
->pc
++);
6551 reg
= ((modrm
>> 3) & 7) | rex_r
;
6552 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6555 /************************/
6557 case 0x9c: /* pushf */
6558 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6559 if (s
->vm86
&& s
->iopl
!= 3) {
6560 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6562 gen_update_cc_op(s
);
6563 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6564 gen_push_v(s
, cpu_T
[0]);
6567 case 0x9d: /* popf */
6568 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6569 if (s
->vm86
&& s
->iopl
!= 3) {
6570 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6574 if (dflag
!= MO_16
) {
6575 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6576 tcg_const_i32((TF_MASK
| AC_MASK
|
6581 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6582 tcg_const_i32((TF_MASK
| AC_MASK
|
6584 IF_MASK
| IOPL_MASK
)
6588 if (s
->cpl
<= s
->iopl
) {
6589 if (dflag
!= MO_16
) {
6590 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6591 tcg_const_i32((TF_MASK
|
6597 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6598 tcg_const_i32((TF_MASK
|
6606 if (dflag
!= MO_16
) {
6607 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6608 tcg_const_i32((TF_MASK
| AC_MASK
|
6609 ID_MASK
| NT_MASK
)));
6611 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6612 tcg_const_i32((TF_MASK
| AC_MASK
|
6618 gen_pop_update(s
, ot
);
6619 set_cc_op(s
, CC_OP_EFLAGS
);
6620 /* abort translation because TF/AC flag may change */
6621 gen_jmp_im(s
->pc
- s
->cs_base
);
6625 case 0x9e: /* sahf */
6626 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6628 gen_op_mov_v_reg(MO_8
, cpu_T
[0], R_AH
);
6629 gen_compute_eflags(s
);
6630 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6631 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6632 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6634 case 0x9f: /* lahf */
6635 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6637 gen_compute_eflags(s
);
6638 /* Note: gen_compute_eflags() only gives the condition codes */
6639 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6640 gen_op_mov_reg_v(MO_8
, R_AH
, cpu_T
[0]);
6642 case 0xf5: /* cmc */
6643 gen_compute_eflags(s
);
6644 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6646 case 0xf8: /* clc */
6647 gen_compute_eflags(s
);
6648 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6650 case 0xf9: /* stc */
6651 gen_compute_eflags(s
);
6652 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6654 case 0xfc: /* cld */
6655 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6656 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6658 case 0xfd: /* std */
6659 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6660 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6663 /************************/
6664 /* bit operations */
6665 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6667 modrm
= cpu_ldub_code(env
, s
->pc
++);
6668 op
= (modrm
>> 3) & 7;
6669 mod
= (modrm
>> 6) & 3;
6670 rm
= (modrm
& 7) | REX_B(s
);
6673 gen_lea_modrm(env
, s
, modrm
);
6674 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6676 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
6679 val
= cpu_ldub_code(env
, s
->pc
++);
6680 tcg_gen_movi_tl(cpu_T
[1], val
);
6685 case 0x1a3: /* bt Gv, Ev */
6688 case 0x1ab: /* bts */
6691 case 0x1b3: /* btr */
6694 case 0x1bb: /* btc */
6698 modrm
= cpu_ldub_code(env
, s
->pc
++);
6699 reg
= ((modrm
>> 3) & 7) | rex_r
;
6700 mod
= (modrm
>> 6) & 3;
6701 rm
= (modrm
& 7) | REX_B(s
);
6702 gen_op_mov_v_reg(MO_32
, cpu_T
[1], reg
);
6704 gen_lea_modrm(env
, s
, modrm
);
6705 /* specific case: we need to add a displacement */
6706 gen_exts(ot
, cpu_T
[1]);
6707 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6708 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6709 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6710 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6712 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
6715 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6716 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6721 tcg_gen_movi_tl(cpu_tmp0
, 1);
6722 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6723 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6726 tcg_gen_movi_tl(cpu_tmp0
, 1);
6727 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6728 tcg_gen_andc_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6732 tcg_gen_movi_tl(cpu_tmp0
, 1);
6733 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6734 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6739 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
6741 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
6745 /* Delay all CC updates until after the store above. Note that
6746 C is the result of the test, Z is unchanged, and the others
6747 are all undefined. */
6749 case CC_OP_MULB
... CC_OP_MULQ
:
6750 case CC_OP_ADDB
... CC_OP_ADDQ
:
6751 case CC_OP_ADCB
... CC_OP_ADCQ
:
6752 case CC_OP_SUBB
... CC_OP_SUBQ
:
6753 case CC_OP_SBBB
... CC_OP_SBBQ
:
6754 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
6755 case CC_OP_INCB
... CC_OP_INCQ
:
6756 case CC_OP_DECB
... CC_OP_DECQ
:
6757 case CC_OP_SHLB
... CC_OP_SHLQ
:
6758 case CC_OP_SARB
... CC_OP_SARQ
:
6759 case CC_OP_BMILGB
... CC_OP_BMILGQ
:
6760 /* Z was going to be computed from the non-zero status of CC_DST.
6761 We can get that same Z value (and the new C value) by leaving
6762 CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the
6764 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6765 set_cc_op(s
, ((s
->cc_op
- CC_OP_MULB
) & 3) + CC_OP_SARB
);
6768 /* Otherwise, generate EFLAGS and replace the C bit. */
6769 gen_compute_eflags(s
);
6770 tcg_gen_deposit_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp4
,
6775 case 0x1bc: /* bsf / tzcnt */
6776 case 0x1bd: /* bsr / lzcnt */
6778 modrm
= cpu_ldub_code(env
, s
->pc
++);
6779 reg
= ((modrm
>> 3) & 7) | rex_r
;
6780 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
6781 gen_extu(ot
, cpu_T
[0]);
6783 /* Note that lzcnt and tzcnt are in different extensions. */
6784 if ((prefixes
& PREFIX_REPZ
)
6786 ? s
->cpuid_ext3_features
& CPUID_EXT3_ABM
6787 : s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)) {
6789 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
6791 /* For lzcnt, reduce the target_ulong result by the
6792 number of zeros that we expect to find at the top. */
6793 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6794 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- size
);
6796 /* For tzcnt, a zero input must return the operand size:
6797 force all bits outside the operand size to 1. */
6798 target_ulong mask
= (target_ulong
)-2 << (size
- 1);
6799 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], mask
);
6800 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6802 /* For lzcnt/tzcnt, C and Z bits are defined and are
6803 related to the result. */
6804 gen_op_update1_cc();
6805 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
6807 /* For bsr/bsf, only the Z bit is defined and it is related
6808 to the input and not the result. */
6809 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
6810 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6812 /* For bsr, return the bit index of the first 1 bit,
6813 not the count of leading zeros. */
6814 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6815 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- 1);
6817 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6819 /* ??? The manual says that the output is undefined when the
6820 input is zero, but real hardware leaves it unchanged, and
6821 real programs appear to depend on that. */
6822 tcg_gen_movi_tl(cpu_tmp0
, 0);
6823 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[0], cpu_cc_dst
, cpu_tmp0
,
6824 cpu_regs
[reg
], cpu_T
[0]);
6826 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
6828 /************************/
6830 case 0x27: /* daa */
6833 gen_update_cc_op(s
);
6834 gen_helper_daa(cpu_env
);
6835 set_cc_op(s
, CC_OP_EFLAGS
);
6837 case 0x2f: /* das */
6840 gen_update_cc_op(s
);
6841 gen_helper_das(cpu_env
);
6842 set_cc_op(s
, CC_OP_EFLAGS
);
6844 case 0x37: /* aaa */
6847 gen_update_cc_op(s
);
6848 gen_helper_aaa(cpu_env
);
6849 set_cc_op(s
, CC_OP_EFLAGS
);
6851 case 0x3f: /* aas */
6854 gen_update_cc_op(s
);
6855 gen_helper_aas(cpu_env
);
6856 set_cc_op(s
, CC_OP_EFLAGS
);
6858 case 0xd4: /* aam */
6861 val
= cpu_ldub_code(env
, s
->pc
++);
6863 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6865 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6866 set_cc_op(s
, CC_OP_LOGICB
);
6869 case 0xd5: /* aad */
6872 val
= cpu_ldub_code(env
, s
->pc
++);
6873 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6874 set_cc_op(s
, CC_OP_LOGICB
);
6876 /************************/
6878 case 0x90: /* nop */
6879 /* XXX: correct lock test for all insn */
6880 if (prefixes
& PREFIX_LOCK
) {
6883 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6885 goto do_xchg_reg_eax
;
6887 if (prefixes
& PREFIX_REPZ
) {
6888 gen_update_cc_op(s
);
6889 gen_jmp_im(pc_start
- s
->cs_base
);
6890 gen_helper_pause(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6891 s
->is_jmp
= DISAS_TB_JUMP
;
6894 case 0x9b: /* fwait */
6895 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6896 (HF_MP_MASK
| HF_TS_MASK
)) {
6897 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6899 gen_update_cc_op(s
);
6900 gen_jmp_im(pc_start
- s
->cs_base
);
6901 gen_helper_fwait(cpu_env
);
6904 case 0xcc: /* int3 */
6905 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6907 case 0xcd: /* int N */
6908 val
= cpu_ldub_code(env
, s
->pc
++);
6909 if (s
->vm86
&& s
->iopl
!= 3) {
6910 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6912 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6915 case 0xce: /* into */
6918 gen_update_cc_op(s
);
6919 gen_jmp_im(pc_start
- s
->cs_base
);
6920 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6923 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6924 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6926 gen_debug(s
, pc_start
- s
->cs_base
);
6929 tb_flush(CPU(x86_env_get_cpu(env
)));
6930 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6934 case 0xfa: /* cli */
6936 if (s
->cpl
<= s
->iopl
) {
6937 gen_helper_cli(cpu_env
);
6939 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6943 gen_helper_cli(cpu_env
);
6945 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6949 case 0xfb: /* sti */
6951 if (s
->cpl
<= s
->iopl
) {
6953 gen_helper_sti(cpu_env
);
6954 /* interruptions are enabled only the first insn after sti */
6955 /* If several instructions disable interrupts, only the
6957 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6958 gen_helper_set_inhibit_irq(cpu_env
);
6959 /* give a chance to handle pending irqs */
6960 gen_jmp_im(s
->pc
- s
->cs_base
);
6963 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6969 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6973 case 0x62: /* bound */
6977 modrm
= cpu_ldub_code(env
, s
->pc
++);
6978 reg
= (modrm
>> 3) & 7;
6979 mod
= (modrm
>> 6) & 3;
6982 gen_op_mov_v_reg(ot
, cpu_T
[0], reg
);
6983 gen_lea_modrm(env
, s
, modrm
);
6984 gen_jmp_im(pc_start
- s
->cs_base
);
6985 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6987 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6989 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6992 case 0x1c8 ... 0x1cf: /* bswap reg */
6993 reg
= (b
& 7) | REX_B(s
);
6994 #ifdef TARGET_X86_64
6995 if (dflag
== MO_64
) {
6996 gen_op_mov_v_reg(MO_64
, cpu_T
[0], reg
);
6997 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6998 gen_op_mov_reg_v(MO_64
, reg
, cpu_T
[0]);
7002 gen_op_mov_v_reg(MO_32
, cpu_T
[0], reg
);
7003 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
7004 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
7005 gen_op_mov_reg_v(MO_32
, reg
, cpu_T
[0]);
7008 case 0xd6: /* salc */
7011 gen_compute_eflags_c(s
, cpu_T
[0]);
7012 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
7013 gen_op_mov_reg_v(MO_8
, R_EAX
, cpu_T
[0]);
7015 case 0xe0: /* loopnz */
7016 case 0xe1: /* loopz */
7017 case 0xe2: /* loop */
7018 case 0xe3: /* jecxz */
7020 TCGLabel
*l1
, *l2
, *l3
;
7022 tval
= (int8_t)insn_get(env
, s
, MO_8
);
7023 next_eip
= s
->pc
- s
->cs_base
;
7025 if (dflag
== MO_16
) {
7029 l1
= gen_new_label();
7030 l2
= gen_new_label();
7031 l3
= gen_new_label();
7034 case 0: /* loopnz */
7036 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7037 gen_op_jz_ecx(s
->aflag
, l3
);
7038 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
7041 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7042 gen_op_jnz_ecx(s
->aflag
, l1
);
7046 gen_op_jz_ecx(s
->aflag
, l1
);
7051 gen_jmp_im(next_eip
);
7060 case 0x130: /* wrmsr */
7061 case 0x132: /* rdmsr */
7063 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7065 gen_update_cc_op(s
);
7066 gen_jmp_im(pc_start
- s
->cs_base
);
7068 gen_helper_rdmsr(cpu_env
);
7070 gen_helper_wrmsr(cpu_env
);
7074 case 0x131: /* rdtsc */
7075 gen_update_cc_op(s
);
7076 gen_jmp_im(pc_start
- s
->cs_base
);
7077 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
7080 gen_helper_rdtsc(cpu_env
);
7081 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
7083 gen_jmp(s
, s
->pc
- s
->cs_base
);
7086 case 0x133: /* rdpmc */
7087 gen_update_cc_op(s
);
7088 gen_jmp_im(pc_start
- s
->cs_base
);
7089 gen_helper_rdpmc(cpu_env
);
7091 case 0x134: /* sysenter */
7092 /* For Intel SYSENTER is valid on 64-bit */
7093 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7096 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7098 gen_update_cc_op(s
);
7099 gen_jmp_im(pc_start
- s
->cs_base
);
7100 gen_helper_sysenter(cpu_env
);
7104 case 0x135: /* sysexit */
7105 /* For Intel SYSEXIT is valid on 64-bit */
7106 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7109 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7111 gen_update_cc_op(s
);
7112 gen_jmp_im(pc_start
- s
->cs_base
);
7113 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
- 1));
7117 #ifdef TARGET_X86_64
7118 case 0x105: /* syscall */
7119 /* XXX: is it usable in real mode ? */
7120 gen_update_cc_op(s
);
7121 gen_jmp_im(pc_start
- s
->cs_base
);
7122 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7125 case 0x107: /* sysret */
7127 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7129 gen_update_cc_op(s
);
7130 gen_jmp_im(pc_start
- s
->cs_base
);
7131 gen_helper_sysret(cpu_env
, tcg_const_i32(dflag
- 1));
7132 /* condition codes are modified only in long mode */
7134 set_cc_op(s
, CC_OP_EFLAGS
);
7140 case 0x1a2: /* cpuid */
7141 gen_update_cc_op(s
);
7142 gen_jmp_im(pc_start
- s
->cs_base
);
7143 gen_helper_cpuid(cpu_env
);
7145 case 0xf4: /* hlt */
7147 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7149 gen_update_cc_op(s
);
7150 gen_jmp_im(pc_start
- s
->cs_base
);
7151 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7152 s
->is_jmp
= DISAS_TB_JUMP
;
7156 modrm
= cpu_ldub_code(env
, s
->pc
++);
7157 mod
= (modrm
>> 6) & 3;
7158 op
= (modrm
>> 3) & 7;
7161 if (!s
->pe
|| s
->vm86
)
7163 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7164 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7165 ot
= mod
== 3 ? dflag
: MO_16
;
7166 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7169 if (!s
->pe
|| s
->vm86
)
7172 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7174 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7175 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7176 gen_jmp_im(pc_start
- s
->cs_base
);
7177 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7178 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7182 if (!s
->pe
|| s
->vm86
)
7184 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7185 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7186 ot
= mod
== 3 ? dflag
: MO_16
;
7187 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7190 if (!s
->pe
|| s
->vm86
)
7193 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7195 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7196 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7197 gen_jmp_im(pc_start
- s
->cs_base
);
7198 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7199 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7204 if (!s
->pe
|| s
->vm86
)
7206 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7207 gen_update_cc_op(s
);
7209 gen_helper_verr(cpu_env
, cpu_T
[0]);
7211 gen_helper_verw(cpu_env
, cpu_T
[0]);
7213 set_cc_op(s
, CC_OP_EFLAGS
);
7220 modrm
= cpu_ldub_code(env
, s
->pc
++);
7221 mod
= (modrm
>> 6) & 3;
7222 op
= (modrm
>> 3) & 7;
7228 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7229 gen_lea_modrm(env
, s
, modrm
);
7230 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7231 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7232 gen_add_A0_im(s
, 2);
7233 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7234 if (dflag
== MO_16
) {
7235 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7237 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7242 case 0: /* monitor */
7243 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7246 gen_update_cc_op(s
);
7247 gen_jmp_im(pc_start
- s
->cs_base
);
7248 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[R_EAX
]);
7249 gen_extu(s
->aflag
, cpu_A0
);
7250 gen_add_A0_ds_seg(s
);
7251 gen_helper_monitor(cpu_env
, cpu_A0
);
7254 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7257 gen_update_cc_op(s
);
7258 gen_jmp_im(pc_start
- s
->cs_base
);
7259 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7263 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7267 gen_helper_clac(cpu_env
);
7268 gen_jmp_im(s
->pc
- s
->cs_base
);
7272 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7276 gen_helper_stac(cpu_env
);
7277 gen_jmp_im(s
->pc
- s
->cs_base
);
7284 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7285 gen_lea_modrm(env
, s
, modrm
);
7286 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7287 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7288 gen_add_A0_im(s
, 2);
7289 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7290 if (dflag
== MO_16
) {
7291 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7293 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7299 gen_update_cc_op(s
);
7300 gen_jmp_im(pc_start
- s
->cs_base
);
7303 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7306 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7309 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
- 1),
7310 tcg_const_i32(s
->pc
- pc_start
));
7312 s
->is_jmp
= DISAS_TB_JUMP
;
7315 case 1: /* VMMCALL */
7316 if (!(s
->flags
& HF_SVME_MASK
))
7318 gen_helper_vmmcall(cpu_env
);
7320 case 2: /* VMLOAD */
7321 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7324 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7327 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7330 case 3: /* VMSAVE */
7331 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7334 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7337 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
- 1));
7341 if ((!(s
->flags
& HF_SVME_MASK
) &&
7342 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7346 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7349 gen_helper_stgi(cpu_env
);
7353 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7356 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7359 gen_helper_clgi(cpu_env
);
7362 case 6: /* SKINIT */
7363 if ((!(s
->flags
& HF_SVME_MASK
) &&
7364 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7367 gen_helper_skinit(cpu_env
);
7369 case 7: /* INVLPGA */
7370 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7373 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7376 gen_helper_invlpga(cpu_env
,
7377 tcg_const_i32(s
->aflag
- 1));
7383 } else if (s
->cpl
!= 0) {
7384 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7386 gen_svm_check_intercept(s
, pc_start
,
7387 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7388 gen_lea_modrm(env
, s
, modrm
);
7389 gen_op_ld_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
7390 gen_add_A0_im(s
, 2);
7391 gen_op_ld_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7392 if (dflag
== MO_16
) {
7393 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffffff);
7396 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7397 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7399 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7400 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7405 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7406 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7407 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7409 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7411 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 1);
7415 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7417 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7418 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7419 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7420 gen_jmp_im(s
->pc
- s
->cs_base
);
7425 if (mod
!= 3) { /* invlpg */
7427 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7429 gen_update_cc_op(s
);
7430 gen_jmp_im(pc_start
- s
->cs_base
);
7431 gen_lea_modrm(env
, s
, modrm
);
7432 gen_helper_invlpg(cpu_env
, cpu_A0
);
7433 gen_jmp_im(s
->pc
- s
->cs_base
);
7438 case 0: /* swapgs */
7439 #ifdef TARGET_X86_64
7442 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7444 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7445 offsetof(CPUX86State
,segs
[R_GS
].base
));
7446 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7447 offsetof(CPUX86State
,kernelgsbase
));
7448 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7449 offsetof(CPUX86State
,segs
[R_GS
].base
));
7450 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7451 offsetof(CPUX86State
,kernelgsbase
));
7459 case 1: /* rdtscp */
7460 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7462 gen_update_cc_op(s
);
7463 gen_jmp_im(pc_start
- s
->cs_base
);
7464 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
7467 gen_helper_rdtscp(cpu_env
);
7468 if (s
->tb
->cflags
& CF_USE_ICOUNT
) {
7470 gen_jmp(s
, s
->pc
- s
->cs_base
);
7482 case 0x108: /* invd */
7483 case 0x109: /* wbinvd */
7485 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7487 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7491 case 0x63: /* arpl or movslS (x86_64) */
7492 #ifdef TARGET_X86_64
7495 /* d_ot is the size of destination */
7498 modrm
= cpu_ldub_code(env
, s
->pc
++);
7499 reg
= ((modrm
>> 3) & 7) | rex_r
;
7500 mod
= (modrm
>> 6) & 3;
7501 rm
= (modrm
& 7) | REX_B(s
);
7504 gen_op_mov_v_reg(MO_32
, cpu_T
[0], rm
);
7506 if (d_ot
== MO_64
) {
7507 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7509 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
7511 gen_lea_modrm(env
, s
, modrm
);
7512 gen_op_ld_v(s
, MO_32
| MO_SIGN
, cpu_T
[0], cpu_A0
);
7513 gen_op_mov_reg_v(d_ot
, reg
, cpu_T
[0]);
7519 TCGv t0
, t1
, t2
, a0
;
7521 if (!s
->pe
|| s
->vm86
)
7523 t0
= tcg_temp_local_new();
7524 t1
= tcg_temp_local_new();
7525 t2
= tcg_temp_local_new();
7527 modrm
= cpu_ldub_code(env
, s
->pc
++);
7528 reg
= (modrm
>> 3) & 7;
7529 mod
= (modrm
>> 6) & 3;
7532 gen_lea_modrm(env
, s
, modrm
);
7533 gen_op_ld_v(s
, ot
, t0
, cpu_A0
);
7534 a0
= tcg_temp_local_new();
7535 tcg_gen_mov_tl(a0
, cpu_A0
);
7537 gen_op_mov_v_reg(ot
, t0
, rm
);
7540 gen_op_mov_v_reg(ot
, t1
, reg
);
7541 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7542 tcg_gen_andi_tl(t1
, t1
, 3);
7543 tcg_gen_movi_tl(t2
, 0);
7544 label1
= gen_new_label();
7545 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7546 tcg_gen_andi_tl(t0
, t0
, ~3);
7547 tcg_gen_or_tl(t0
, t0
, t1
);
7548 tcg_gen_movi_tl(t2
, CC_Z
);
7549 gen_set_label(label1
);
7551 gen_op_st_v(s
, ot
, t0
, a0
);
7554 gen_op_mov_reg_v(ot
, rm
, t0
);
7556 gen_compute_eflags(s
);
7557 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7558 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7564 case 0x102: /* lar */
7565 case 0x103: /* lsl */
7569 if (!s
->pe
|| s
->vm86
)
7571 ot
= dflag
!= MO_16
? MO_32
: MO_16
;
7572 modrm
= cpu_ldub_code(env
, s
->pc
++);
7573 reg
= ((modrm
>> 3) & 7) | rex_r
;
7574 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7575 t0
= tcg_temp_local_new();
7576 gen_update_cc_op(s
);
7578 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7580 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7582 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7583 label1
= gen_new_label();
7584 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7585 gen_op_mov_reg_v(ot
, reg
, t0
);
7586 gen_set_label(label1
);
7587 set_cc_op(s
, CC_OP_EFLAGS
);
7592 modrm
= cpu_ldub_code(env
, s
->pc
++);
7593 mod
= (modrm
>> 6) & 3;
7594 op
= (modrm
>> 3) & 7;
7596 case 0: /* prefetchnta */
7597 case 1: /* prefetchnt0 */
7598 case 2: /* prefetchnt0 */
7599 case 3: /* prefetchnt0 */
7602 gen_lea_modrm(env
, s
, modrm
);
7603 /* nothing more to do */
7605 default: /* nop (multi byte) */
7606 gen_nop_modrm(env
, s
, modrm
);
7610 case 0x119 ... 0x11f: /* nop (multi byte) */
7611 modrm
= cpu_ldub_code(env
, s
->pc
++);
7612 gen_nop_modrm(env
, s
, modrm
);
7614 case 0x120: /* mov reg, crN */
7615 case 0x122: /* mov crN, reg */
7617 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7619 modrm
= cpu_ldub_code(env
, s
->pc
++);
7620 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7621 * AMD documentation (24594.pdf) and testing of
7622 * intel 386 and 486 processors all show that the mod bits
7623 * are assumed to be 1's, regardless of actual values.
7625 rm
= (modrm
& 7) | REX_B(s
);
7626 reg
= ((modrm
>> 3) & 7) | rex_r
;
7631 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7632 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7641 gen_update_cc_op(s
);
7642 gen_jmp_im(pc_start
- s
->cs_base
);
7644 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
7645 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7647 gen_jmp_im(s
->pc
- s
->cs_base
);
7650 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7651 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
7659 case 0x121: /* mov reg, drN */
7660 case 0x123: /* mov drN, reg */
7662 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7664 modrm
= cpu_ldub_code(env
, s
->pc
++);
7665 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7666 * AMD documentation (24594.pdf) and testing of
7667 * intel 386 and 486 processors all show that the mod bits
7668 * are assumed to be 1's, regardless of actual values.
7670 rm
= (modrm
& 7) | REX_B(s
);
7671 reg
= ((modrm
>> 3) & 7) | rex_r
;
7676 /* XXX: do it dynamically with CR4.DE bit */
7677 if (reg
== 4 || reg
== 5 || reg
>= 8)
7680 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7681 gen_op_mov_v_reg(ot
, cpu_T
[0], rm
);
7682 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7683 gen_jmp_im(s
->pc
- s
->cs_base
);
7686 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7687 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7688 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
7692 case 0x106: /* clts */
7694 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7696 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7697 gen_helper_clts(cpu_env
);
7698 /* abort block because static cpu state changed */
7699 gen_jmp_im(s
->pc
- s
->cs_base
);
7703 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7704 case 0x1c3: /* MOVNTI reg, mem */
7705 if (!(s
->cpuid_features
& CPUID_SSE2
))
7707 ot
= mo_64_32(dflag
);
7708 modrm
= cpu_ldub_code(env
, s
->pc
++);
7709 mod
= (modrm
>> 6) & 3;
7712 reg
= ((modrm
>> 3) & 7) | rex_r
;
7713 /* generate a generic store */
7714 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7717 modrm
= cpu_ldub_code(env
, s
->pc
++);
7718 mod
= (modrm
>> 6) & 3;
7719 op
= (modrm
>> 3) & 7;
7721 case 0: /* fxsave */
7722 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7723 (s
->prefix
& PREFIX_LOCK
))
7725 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7726 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7729 gen_lea_modrm(env
, s
, modrm
);
7730 gen_update_cc_op(s
);
7731 gen_jmp_im(pc_start
- s
->cs_base
);
7732 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7734 case 1: /* fxrstor */
7735 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7736 (s
->prefix
& PREFIX_LOCK
))
7738 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7739 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7742 gen_lea_modrm(env
, s
, modrm
);
7743 gen_update_cc_op(s
);
7744 gen_jmp_im(pc_start
- s
->cs_base
);
7745 gen_helper_fxrstor(cpu_env
, cpu_A0
, tcg_const_i32(dflag
== MO_64
));
7747 case 2: /* ldmxcsr */
7748 case 3: /* stmxcsr */
7749 if (s
->flags
& HF_TS_MASK
) {
7750 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7753 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7756 gen_lea_modrm(env
, s
, modrm
);
7758 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
7759 s
->mem_index
, MO_LEUL
);
7760 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7762 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7763 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
7766 case 5: /* lfence */
7767 case 6: /* mfence */
7768 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7771 case 7: /* sfence / clflush */
7772 if ((modrm
& 0xc7) == 0xc0) {
7774 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7775 if (!(s
->cpuid_features
& CPUID_SSE
))
7779 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7781 gen_lea_modrm(env
, s
, modrm
);
7788 case 0x10d: /* 3DNow! prefetch(w) */
7789 modrm
= cpu_ldub_code(env
, s
->pc
++);
7790 mod
= (modrm
>> 6) & 3;
7793 gen_lea_modrm(env
, s
, modrm
);
7794 /* ignore for now */
7796 case 0x1aa: /* rsm */
7797 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7798 if (!(s
->flags
& HF_SMM_MASK
))
7800 gen_update_cc_op(s
);
7801 gen_jmp_im(s
->pc
- s
->cs_base
);
7802 gen_helper_rsm(cpu_env
);
7805 case 0x1b8: /* SSE4.2 popcnt */
7806 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7809 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7812 modrm
= cpu_ldub_code(env
, s
->pc
++);
7813 reg
= ((modrm
>> 3) & 7) | rex_r
;
7815 if (s
->prefix
& PREFIX_DATA
) {
7818 ot
= mo_64_32(dflag
);
7821 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7822 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7823 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
7825 set_cc_op(s
, CC_OP_EFLAGS
);
7827 case 0x10e ... 0x10f:
7828 /* 3DNow! instructions, ignore prefixes */
7829 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7830 case 0x110 ... 0x117:
7831 case 0x128 ... 0x12f:
7832 case 0x138 ... 0x13a:
7833 case 0x150 ... 0x179:
7834 case 0x17c ... 0x17f:
7836 case 0x1c4 ... 0x1c6:
7837 case 0x1d0 ... 0x1fe:
7838 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7843 /* lock generation */
7844 if (s
->prefix
& PREFIX_LOCK
)
7845 gen_helper_unlock();
7848 if (s
->prefix
& PREFIX_LOCK
)
7849 gen_helper_unlock();
7850 /* XXX: ensure that no lock was generated */
7851 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7855 void optimize_flags_init(void)
7857 static const char reg_names
[CPU_NB_REGS
][4] = {
7858 #ifdef TARGET_X86_64
7888 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7889 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7890 offsetof(CPUX86State
, cc_op
), "cc_op");
7891 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7893 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7895 cpu_cc_src2
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src2
),
7898 for (i
= 0; i
< CPU_NB_REGS
; ++i
) {
7899 cpu_regs
[i
] = tcg_global_mem_new(TCG_AREG0
,
7900 offsetof(CPUX86State
, regs
[i
]),
7905 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7906 basic block 'tb'. If search_pc is TRUE, also generate PC
7907 information for each intermediate instruction. */
7908 static inline void gen_intermediate_code_internal(X86CPU
*cpu
,
7909 TranslationBlock
*tb
,
7912 CPUState
*cs
= CPU(cpu
);
7913 CPUX86State
*env
= &cpu
->env
;
7914 DisasContext dc1
, *dc
= &dc1
;
7915 target_ulong pc_ptr
;
7919 target_ulong pc_start
;
7920 target_ulong cs_base
;
7924 /* generate intermediate code */
7926 cs_base
= tb
->cs_base
;
7929 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7930 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7931 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7932 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7934 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7935 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7936 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7937 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7938 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
7939 dc
->cc_op
= CC_OP_DYNAMIC
;
7940 dc
->cc_op_dirty
= false;
7941 dc
->cs_base
= cs_base
;
7943 dc
->popl_esp_hack
= 0;
7944 /* select memory access functions */
7946 if (flags
& HF_SOFTMMU_MASK
) {
7947 dc
->mem_index
= cpu_mmu_index(env
);
7949 dc
->cpuid_features
= env
->features
[FEAT_1_EDX
];
7950 dc
->cpuid_ext_features
= env
->features
[FEAT_1_ECX
];
7951 dc
->cpuid_ext2_features
= env
->features
[FEAT_8000_0001_EDX
];
7952 dc
->cpuid_ext3_features
= env
->features
[FEAT_8000_0001_ECX
];
7953 dc
->cpuid_7_0_ebx_features
= env
->features
[FEAT_7_0_EBX
];
7954 #ifdef TARGET_X86_64
7955 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7956 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7959 dc
->jmp_opt
= !(dc
->tf
|| cs
->singlestep_enabled
||
7960 (flags
& HF_INHIBIT_IRQ_MASK
)
7961 #ifndef CONFIG_SOFTMMU
7962 || (flags
& HF_SOFTMMU_MASK
)
7965 /* Do not optimize repz jumps at all in icount mode, because
7966 rep movsS instructions are execured with different paths
7967 in !repz_opt and repz_opt modes. The first one was used
7968 always except single step mode. And this setting
7969 disables jumps optimization and control paths become
7970 equivalent in run and single step modes.
7971 Now there will be no jump optimization for repz in
7972 record/replay modes and there will always be an
7973 additional step for ecx=0 when icount is enabled.
7975 dc
->repz_opt
= !dc
->jmp_opt
&& !(tb
->cflags
& CF_USE_ICOUNT
);
7977 /* check addseg logic */
7978 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7979 printf("ERROR addseg\n");
7982 cpu_T
[0] = tcg_temp_new();
7983 cpu_T
[1] = tcg_temp_new();
7984 cpu_A0
= tcg_temp_new();
7986 cpu_tmp0
= tcg_temp_new();
7987 cpu_tmp1_i64
= tcg_temp_new_i64();
7988 cpu_tmp2_i32
= tcg_temp_new_i32();
7989 cpu_tmp3_i32
= tcg_temp_new_i32();
7990 cpu_tmp4
= tcg_temp_new();
7991 cpu_ptr0
= tcg_temp_new_ptr();
7992 cpu_ptr1
= tcg_temp_new_ptr();
7993 cpu_cc_srcT
= tcg_temp_local_new();
7995 dc
->is_jmp
= DISAS_NEXT
;
7999 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8001 max_insns
= CF_COUNT_MASK
;
8005 #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64)
8006 /* Detect vsyscall */
8007 if (unlikely(pc_ptr
>= TARGET_VSYSCALL_START
8008 && pc_ptr
< TARGET_VSYSCALL_END
)) {
8009 gen_helper_vsyscall(cpu_env
);
8014 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
8015 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
8016 if (bp
->pc
== pc_ptr
&&
8017 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
8018 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
8019 goto done_generating
;
8024 j
= tcg_op_buf_count();
8028 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8030 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
8031 gen_opc_cc_op
[lj
] = dc
->cc_op
;
8032 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
8033 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
8035 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8038 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
8040 /* stop translation if indicated */
8043 /* if single step mode, we generate only one instruction and
8044 generate an exception */
8045 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
8046 the flag and abort the translation to give the irqs a
8047 change to be happen */
8048 if (dc
->tf
|| dc
->singlestep_enabled
||
8049 (flags
& HF_INHIBIT_IRQ_MASK
)) {
8050 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8054 /* Do not cross the boundary of the pages in icount mode,
8055 it can cause an exception. Do it only when boundary is
8056 crossed by the first instruction in the block.
8057 If current instruction already crossed the bound - it's ok,
8058 because an exception hasn't stopped this code.
8060 if ((tb
->cflags
& CF_USE_ICOUNT
)
8061 && ((pc_ptr
& TARGET_PAGE_MASK
)
8062 != ((pc_ptr
+ TARGET_MAX_INSN_SIZE
- 1) & TARGET_PAGE_MASK
)
8063 || (pc_ptr
& ~TARGET_PAGE_MASK
) == 0)) {
8064 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8068 /* if too long translation, stop generation too */
8069 if (tcg_op_buf_full() ||
8070 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
8071 num_insns
>= max_insns
) {
8072 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8077 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8082 if (tb
->cflags
& CF_LAST_IO
)
8085 gen_tb_end(tb
, num_insns
);
8087 /* we don't forget to fill the last values */
8089 j
= tcg_op_buf_count();
8092 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8096 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8098 qemu_log("----------------\n");
8099 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8100 #ifdef TARGET_X86_64
8105 disas_flags
= !dc
->code32
;
8106 log_target_disas(cs
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8112 tb
->size
= pc_ptr
- pc_start
;
8113 tb
->icount
= num_insns
;
8117 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8119 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, false);
8122 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8124 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, true);
8127 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8131 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8133 qemu_log("RESTORE:\n");
8134 for(i
= 0;i
<= pc_pos
; i
++) {
8135 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8136 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8137 tcg_ctx
.gen_opc_pc
[i
]);
8140 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8141 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8142 (uint32_t)tb
->cs_base
);
8145 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8146 cc_op
= gen_opc_cc_op
[pc_pos
];
8147 if (cc_op
!= CC_OP_DYNAMIC
)