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Merge tag 'v2.4.0-rc1'
[qemu/ar7.git] / target-i386 / cpu.c
blobe29774916ef436447acac02a38fb44a605ffce4c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu-common.h"
21 #include "cpu.h"
22 #include "sysemu/kvm.h"
23 #include "sysemu/cpus.h"
24 #include "kvm_i386.h"
25
26 #include "qemu/error-report.h"
27 #include "qemu/option.h"
28 #include "qemu/config-file.h"
29 #include "qapi/qmp/qerror.h"
30
31 #include "qapi-types.h"
32 #include "qapi-visit.h"
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hw/hw.h"
37 #if defined(CONFIG_KVM)
38 #include <linux/kvm_para.h>
39 #endif
40
41 #include "sysemu/sysemu.h"
42 #include "hw/qdev-properties.h"
43 #include "hw/cpu/icc_bus.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "exec/address-spaces.h"
46 #include "hw/xen/xen.h"
47 #include "hw/i386/apic_internal.h"
48 #endif
49
50
51 /* Cache topology CPUID constants: */
52
53 /* CPUID Leaf 2 Descriptors */
54
55 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
56 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
57 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
58
59
60 /* CPUID Leaf 4 constants: */
61
62 /* EAX: */
63 #define CPUID_4_TYPE_DCACHE 1
64 #define CPUID_4_TYPE_ICACHE 2
65 #define CPUID_4_TYPE_UNIFIED 3
66
67 #define CPUID_4_LEVEL(l) ((l) << 5)
68
69 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
70 #define CPUID_4_FULLY_ASSOC (1 << 9)
71
72 /* EDX: */
73 #define CPUID_4_NO_INVD_SHARING (1 << 0)
74 #define CPUID_4_INCLUSIVE (1 << 1)
75 #define CPUID_4_COMPLEX_IDX (1 << 2)
76
77 #define ASSOC_FULL 0xFF
78
79 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
80 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
81 a == 2 ? 0x2 : \
82 a == 4 ? 0x4 : \
83 a == 8 ? 0x6 : \
84 a == 16 ? 0x8 : \
85 a == 32 ? 0xA : \
86 a == 48 ? 0xB : \
87 a == 64 ? 0xC : \
88 a == 96 ? 0xD : \
89 a == 128 ? 0xE : \
90 a == ASSOC_FULL ? 0xF : \
91 0 /* invalid value */)
92
93
94 /* Definitions of the hardcoded cache entries we expose: */
95
96 /* L1 data cache: */
97 #define L1D_LINE_SIZE 64
98 #define L1D_ASSOCIATIVITY 8
99 #define L1D_SETS 64
100 #define L1D_PARTITIONS 1
101 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
102 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
103 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
104 #define L1D_LINES_PER_TAG 1
105 #define L1D_SIZE_KB_AMD 64
106 #define L1D_ASSOCIATIVITY_AMD 2
107
108 /* L1 instruction cache: */
109 #define L1I_LINE_SIZE 64
110 #define L1I_ASSOCIATIVITY 8
111 #define L1I_SETS 64
112 #define L1I_PARTITIONS 1
113 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
114 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
115 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
116 #define L1I_LINES_PER_TAG 1
117 #define L1I_SIZE_KB_AMD 64
118 #define L1I_ASSOCIATIVITY_AMD 2
119
120 /* Level 2 unified cache: */
121 #define L2_LINE_SIZE 64
122 #define L2_ASSOCIATIVITY 16
123 #define L2_SETS 4096
124 #define L2_PARTITIONS 1
125 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
126 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
127 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
128 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
129 #define L2_LINES_PER_TAG 1
130 #define L2_SIZE_KB_AMD 512
131
132 /* No L3 cache: */
133 #define L3_SIZE_KB 0 /* disabled */
134 #define L3_ASSOCIATIVITY 0 /* disabled */
135 #define L3_LINES_PER_TAG 0 /* disabled */
136 #define L3_LINE_SIZE 0 /* disabled */
137
138 /* TLB definitions: */
139
140 #define L1_DTLB_2M_ASSOC 1
141 #define L1_DTLB_2M_ENTRIES 255
142 #define L1_DTLB_4K_ASSOC 1
143 #define L1_DTLB_4K_ENTRIES 255
144
145 #define L1_ITLB_2M_ASSOC 1
146 #define L1_ITLB_2M_ENTRIES 255
147 #define L1_ITLB_4K_ASSOC 1
148 #define L1_ITLB_4K_ENTRIES 255
149
150 #define L2_DTLB_2M_ASSOC 0 /* disabled */
151 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
152 #define L2_DTLB_4K_ASSOC 4
153 #define L2_DTLB_4K_ENTRIES 512
154
155 #define L2_ITLB_2M_ASSOC 0 /* disabled */
156 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
157 #define L2_ITLB_4K_ASSOC 4
158 #define L2_ITLB_4K_ENTRIES 512
159
160
161
162 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
163 uint32_t vendor2, uint32_t vendor3)
164 {
165 int i;
166 for (i = 0; i < 4; i++) {
167 dst[i] = vendor1 >> (8 * i);
168 dst[i + 4] = vendor2 >> (8 * i);
169 dst[i + 8] = vendor3 >> (8 * i);
170 }
171 dst[CPUID_VENDOR_SZ] = '\0';
172 }
173
174 /* feature flags taken from "Intel Processor Identification and the CPUID
175 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
176 * between feature naming conventions, aliases may be added.
177 */
178 static const char *feature_name[] = {
179 "fpu", "vme", "de", "pse",
180 "tsc", "msr", "pae", "mce",
181 "cx8", "apic", NULL, "sep",
182 "mtrr", "pge", "mca", "cmov",
183 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
184 NULL, "ds" /* Intel dts */, "acpi", "mmx",
185 "fxsr", "sse", "sse2", "ss",
186 "ht" /* Intel htt */, "tm", "ia64", "pbe",
187 };
188 static const char *ext_feature_name[] = {
189 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
190 "ds_cpl", "vmx", "smx", "est",
191 "tm2", "ssse3", "cid", NULL,
192 "fma", "cx16", "xtpr", "pdcm",
193 NULL, "pcid", "dca", "sse4.1|sse4_1",
194 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
195 "tsc-deadline", "aes", "xsave", "osxsave",
196 "avx", "f16c", "rdrand", "hypervisor",
197 };
198 /* Feature names that are already defined on feature_name[] but are set on
199 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
200 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
201 * if and only if CPU vendor is AMD.
202 */
203 static const char *ext2_feature_name[] = {
204 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
205 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
206 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
207 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
208 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
209 "nx|xd", NULL, "mmxext", NULL /* mmx */,
210 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
211 NULL, "lm|i64", "3dnowext", "3dnow",
212 };
213 static const char *ext3_feature_name[] = {
214 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
215 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
216 "3dnowprefetch", "osvw", "ibs", "xop",
217 "skinit", "wdt", NULL, "lwp",
218 "fma4", "tce", NULL, "nodeid_msr",
219 NULL, "tbm", "topoext", "perfctr_core",
220 "perfctr_nb", NULL, NULL, NULL,
221 NULL, NULL, NULL, NULL,
222 };
223
224 static const char *ext4_feature_name[] = {
225 NULL, NULL, "xstore", "xstore-en",
226 NULL, NULL, "xcrypt", "xcrypt-en",
227 "ace2", "ace2-en", "phe", "phe-en",
228 "pmm", "pmm-en", NULL, NULL,
229 NULL, NULL, NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 };
234
235 static const char *kvm_feature_name[] = {
236 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
237 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
238 NULL, NULL, NULL, NULL,
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 "kvmclock-stable-bit", NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 };
245
246 static const char *svm_feature_name[] = {
247 "npt", "lbrv", "svm_lock", "nrip_save",
248 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
249 NULL, NULL, "pause_filter", NULL,
250 "pfthreshold", NULL, NULL, NULL,
251 NULL, NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 };
256
257 static const char *cpuid_7_0_ebx_feature_name[] = {
258 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
259 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
260 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
261 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
262 };
263
264 static const char *cpuid_apm_edx_feature_name[] = {
265 NULL, NULL, NULL, NULL,
266 NULL, NULL, NULL, NULL,
267 "invtsc", NULL, NULL, NULL,
268 NULL, NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 };
274
275 static const char *cpuid_xsave_feature_name[] = {
276 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
277 NULL, NULL, NULL, NULL,
278 NULL, NULL, NULL, NULL,
279 NULL, NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 };
285
286 static const char *cpuid_6_feature_name[] = {
287 NULL, NULL, "arat", NULL,
288 NULL, NULL, NULL, NULL,
289 NULL, NULL, NULL, NULL,
290 NULL, NULL, NULL, NULL,
291 NULL, NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL,
293 NULL, NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 };
296
297 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
298 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
299 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
300 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
301 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
302 CPUID_PSE36 | CPUID_FXSR)
303 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
304 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
305 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
306 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
307 CPUID_PAE | CPUID_SEP | CPUID_APIC)
308
309 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
310 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
311 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
312 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
313 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
314 /* partly implemented:
315 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
316 /* missing:
317 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
318 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
319 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
320 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
321 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
322 /* missing:
323 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
324 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
325 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
326 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
327 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
328 CPUID_EXT_RDRAND */
329
330 #ifdef TARGET_X86_64
331 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
332 #else
333 #define TCG_EXT2_X86_64_FEATURES 0
334 #endif
335
336 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
337 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
338 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
339 TCG_EXT2_X86_64_FEATURES)
340 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
341 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
342 #define TCG_EXT4_FEATURES 0
343 #define TCG_SVM_FEATURES 0
344 #define TCG_KVM_FEATURES 0
345 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
346 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
347 /* missing:
348 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
349 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
350 CPUID_7_0_EBX_RDSEED */
351 #define TCG_APM_FEATURES 0
352 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
353
354
355 typedef struct FeatureWordInfo {
356 const char **feat_names;
357 uint32_t cpuid_eax; /* Input EAX for CPUID */
358 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
359 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
360 int cpuid_reg; /* output register (R_* constant) */
361 uint32_t tcg_features; /* Feature flags supported by TCG */
362 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
363 } FeatureWordInfo;
364
365 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
366 [FEAT_1_EDX] = {
367 .feat_names = feature_name,
368 .cpuid_eax = 1, .cpuid_reg = R_EDX,
369 .tcg_features = TCG_FEATURES,
370 },
371 [FEAT_1_ECX] = {
372 .feat_names = ext_feature_name,
373 .cpuid_eax = 1, .cpuid_reg = R_ECX,
374 .tcg_features = TCG_EXT_FEATURES,
375 },
376 [FEAT_8000_0001_EDX] = {
377 .feat_names = ext2_feature_name,
378 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
379 .tcg_features = TCG_EXT2_FEATURES,
380 },
381 [FEAT_8000_0001_ECX] = {
382 .feat_names = ext3_feature_name,
383 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
384 .tcg_features = TCG_EXT3_FEATURES,
385 },
386 [FEAT_C000_0001_EDX] = {
387 .feat_names = ext4_feature_name,
388 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
389 .tcg_features = TCG_EXT4_FEATURES,
390 },
391 [FEAT_KVM] = {
392 .feat_names = kvm_feature_name,
393 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
394 .tcg_features = TCG_KVM_FEATURES,
395 },
396 [FEAT_SVM] = {
397 .feat_names = svm_feature_name,
398 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
399 .tcg_features = TCG_SVM_FEATURES,
400 },
401 [FEAT_7_0_EBX] = {
402 .feat_names = cpuid_7_0_ebx_feature_name,
403 .cpuid_eax = 7,
404 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
405 .cpuid_reg = R_EBX,
406 .tcg_features = TCG_7_0_EBX_FEATURES,
407 },
408 [FEAT_8000_0007_EDX] = {
409 .feat_names = cpuid_apm_edx_feature_name,
410 .cpuid_eax = 0x80000007,
411 .cpuid_reg = R_EDX,
412 .tcg_features = TCG_APM_FEATURES,
413 .unmigratable_flags = CPUID_APM_INVTSC,
414 },
415 [FEAT_XSAVE] = {
416 .feat_names = cpuid_xsave_feature_name,
417 .cpuid_eax = 0xd,
418 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
419 .cpuid_reg = R_EAX,
420 .tcg_features = 0,
421 },
422 [FEAT_6_EAX] = {
423 .feat_names = cpuid_6_feature_name,
424 .cpuid_eax = 6, .cpuid_reg = R_EAX,
425 .tcg_features = TCG_6_EAX_FEATURES,
426 },
427 };
428
429 typedef struct X86RegisterInfo32 {
430 /* Name of register */
431 const char *name;
432 /* QAPI enum value register */
433 X86CPURegister32 qapi_enum;
434 } X86RegisterInfo32;
435
436 #define REGISTER(reg) \
437 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
438 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
439 REGISTER(EAX),
440 REGISTER(ECX),
441 REGISTER(EDX),
442 REGISTER(EBX),
443 REGISTER(ESP),
444 REGISTER(EBP),
445 REGISTER(ESI),
446 REGISTER(EDI),
447 };
448 #undef REGISTER
449
450 typedef struct ExtSaveArea {
451 uint32_t feature, bits;
452 uint32_t offset, size;
453 } ExtSaveArea;
454
455 static const ExtSaveArea ext_save_areas[] = {
456 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
457 .offset = 0x240, .size = 0x100 },
458 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
459 .offset = 0x3c0, .size = 0x40 },
460 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
461 .offset = 0x400, .size = 0x40 },
462 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
463 .offset = 0x440, .size = 0x40 },
464 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
465 .offset = 0x480, .size = 0x200 },
466 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
467 .offset = 0x680, .size = 0x400 },
468 };
469
470 const char *get_register_name_32(unsigned int reg)
471 {
472 if (reg >= CPU_NB_REGS32) {
473 return NULL;
474 }
475 return x86_reg_info_32[reg].name;
476 }
477
478 /* KVM-specific features that are automatically added to all CPU models
479 * when KVM is enabled.
480 */
481 static uint32_t kvm_default_features[FEATURE_WORDS] = {
482 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
483 (1 << KVM_FEATURE_NOP_IO_DELAY) |
484 (1 << KVM_FEATURE_CLOCKSOURCE2) |
485 (1 << KVM_FEATURE_ASYNC_PF) |
486 (1 << KVM_FEATURE_STEAL_TIME) |
487 (1 << KVM_FEATURE_PV_EOI) |
488 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
489 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
490 };
491
492 /* Features that are not added by default to any CPU model when KVM is enabled.
493 */
494 static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
495 [FEAT_1_EDX] = CPUID_ACPI,
496 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
497 [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM,
498 };
499
500 void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
501 {
502 kvm_default_features[w] &= ~features;
503 }
504
505 void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features)
506 {
507 kvm_default_unset_features[w] &= ~features;
508 }
509
510 /*
511 * Returns the set of feature flags that are supported and migratable by
512 * QEMU, for a given FeatureWord.
513 */
514 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
515 {
516 FeatureWordInfo *wi = &feature_word_info[w];
517 uint32_t r = 0;
518 int i;
519
520 for (i = 0; i < 32; i++) {
521 uint32_t f = 1U << i;
522 /* If the feature name is unknown, it is not supported by QEMU yet */
523 if (!wi->feat_names[i]) {
524 continue;
525 }
526 /* Skip features known to QEMU, but explicitly marked as unmigratable */
527 if (wi->unmigratable_flags & f) {
528 continue;
529 }
530 r |= f;
531 }
532 return r;
533 }
534
535 void host_cpuid(uint32_t function, uint32_t count,
536 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
537 {
538 uint32_t vec[4];
539
540 #ifdef __x86_64__
541 asm volatile("cpuid"
542 : "=a"(vec[0]), "=b"(vec[1]),
543 "=c"(vec[2]), "=d"(vec[3])
544 : "0"(function), "c"(count) : "cc");
545 #elif defined(__i386__)
546 asm volatile("pusha \n\t"
547 "cpuid \n\t"
548 "mov %%eax, 0(%2) \n\t"
549 "mov %%ebx, 4(%2) \n\t"
550 "mov %%ecx, 8(%2) \n\t"
551 "mov %%edx, 12(%2) \n\t"
552 "popa"
553 : : "a"(function), "c"(count), "S"(vec)
554 : "memory", "cc");
555 #else
556 abort();
557 #endif
558
559 if (eax)
560 *eax = vec[0];
561 if (ebx)
562 *ebx = vec[1];
563 if (ecx)
564 *ecx = vec[2];
565 if (edx)
566 *edx = vec[3];
567 }
568
569 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
570
571 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
572 * a substring. ex if !NULL points to the first char after a substring,
573 * otherwise the string is assumed to sized by a terminating nul.
574 * Return lexical ordering of *s1:*s2.
575 */
576 static int sstrcmp(const char *s1, const char *e1,
577 const char *s2, const char *e2)
578 {
579 for (;;) {
580 if (!*s1 || !*s2 || *s1 != *s2)
581 return (*s1 - *s2);
582 ++s1, ++s2;
583 if (s1 == e1 && s2 == e2)
584 return (0);
585 else if (s1 == e1)
586 return (*s2);
587 else if (s2 == e2)
588 return (*s1);
589 }
590 }
591
592 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
593 * '|' delimited (possibly empty) strings in which case search for a match
594 * within the alternatives proceeds left to right. Return 0 for success,
595 * non-zero otherwise.
596 */
597 static int altcmp(const char *s, const char *e, const char *altstr)
598 {
599 const char *p, *q;
600
601 for (q = p = altstr; ; ) {
602 while (*p && *p != '|')
603 ++p;
604 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
605 return (0);
606 if (!*p)
607 return (1);
608 else
609 q = ++p;
610 }
611 }
612
613 /* search featureset for flag *[s..e), if found set corresponding bit in
614 * *pval and return true, otherwise return false
615 */
616 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
617 const char **featureset)
618 {
619 uint32_t mask;
620 const char **ppc;
621 bool found = false;
622
623 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
624 if (*ppc && !altcmp(s, e, *ppc)) {
625 *pval |= mask;
626 found = true;
627 }
628 }
629 return found;
630 }
631
632 static void add_flagname_to_bitmaps(const char *flagname,
633 FeatureWordArray words,
634 Error **errp)
635 {
636 FeatureWord w;
637 for (w = 0; w < FEATURE_WORDS; w++) {
638 FeatureWordInfo *wi = &feature_word_info[w];
639 if (wi->feat_names &&
640 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
641 break;
642 }
643 }
644 if (w == FEATURE_WORDS) {
645 error_setg(errp, "CPU feature %s not found", flagname);
646 }
647 }
648
649 /* CPU class name definitions: */
650
651 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
652 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
653
654 /* Return type name for a given CPU model name
655 * Caller is responsible for freeing the returned string.
656 */
657 static char *x86_cpu_type_name(const char *model_name)
658 {
659 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
660 }
661
662 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
663 {
664 ObjectClass *oc;
665 char *typename;
666
667 if (cpu_model == NULL) {
668 return NULL;
669 }
670
671 typename = x86_cpu_type_name(cpu_model);
672 oc = object_class_by_name(typename);
673 g_free(typename);
674 return oc;
675 }
676
677 struct X86CPUDefinition {
678 const char *name;
679 uint32_t level;
680 uint32_t xlevel;
681 uint32_t xlevel2;
682 /* vendor is zero-terminated, 12 character ASCII string */
683 char vendor[CPUID_VENDOR_SZ + 1];
684 int family;
685 int model;
686 int stepping;
687 FeatureWordArray features;
688 char model_id[48];
689 bool cache_info_passthrough;
690 };
691
692 static X86CPUDefinition builtin_x86_defs[] = {
693 {
694 .name = "qemu64",
695 .level = 0xd,
696 .vendor = CPUID_VENDOR_AMD,
697 .family = 6,
698 .model = 6,
699 .stepping = 3,
700 .features[FEAT_1_EDX] =
701 PPRO_FEATURES |
702 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
703 CPUID_PSE36,
704 .features[FEAT_1_ECX] =
705 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
706 .features[FEAT_8000_0001_EDX] =
707 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
708 .features[FEAT_8000_0001_ECX] =
709 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
710 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
711 .xlevel = 0x8000000A,
712 },
713 {
714 .name = "phenom",
715 .level = 5,
716 .vendor = CPUID_VENDOR_AMD,
717 .family = 16,
718 .model = 2,
719 .stepping = 3,
720 /* Missing: CPUID_HT */
721 .features[FEAT_1_EDX] =
722 PPRO_FEATURES |
723 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
724 CPUID_PSE36 | CPUID_VME,
725 .features[FEAT_1_ECX] =
726 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
727 CPUID_EXT_POPCNT,
728 .features[FEAT_8000_0001_EDX] =
729 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
730 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
731 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
732 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
733 CPUID_EXT3_CR8LEG,
734 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
735 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
736 .features[FEAT_8000_0001_ECX] =
737 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
738 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
739 /* Missing: CPUID_SVM_LBRV */
740 .features[FEAT_SVM] =
741 CPUID_SVM_NPT,
742 .xlevel = 0x8000001A,
743 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
744 },
745 {
746 .name = "core2duo",
747 .level = 10,
748 .vendor = CPUID_VENDOR_INTEL,
749 .family = 6,
750 .model = 15,
751 .stepping = 11,
752 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
753 .features[FEAT_1_EDX] =
754 PPRO_FEATURES |
755 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
756 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
757 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
758 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
759 .features[FEAT_1_ECX] =
760 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
761 CPUID_EXT_CX16,
762 .features[FEAT_8000_0001_EDX] =
763 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
764 .features[FEAT_8000_0001_ECX] =
765 CPUID_EXT3_LAHF_LM,
766 .xlevel = 0x80000008,
767 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
768 },
769 {
770 .name = "kvm64",
771 .level = 0xd,
772 .vendor = CPUID_VENDOR_INTEL,
773 .family = 15,
774 .model = 6,
775 .stepping = 1,
776 /* Missing: CPUID_HT */
777 .features[FEAT_1_EDX] =
778 PPRO_FEATURES | CPUID_VME |
779 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
780 CPUID_PSE36,
781 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
782 .features[FEAT_1_ECX] =
783 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
784 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
785 .features[FEAT_8000_0001_EDX] =
786 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
787 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
788 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
789 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
790 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
791 .features[FEAT_8000_0001_ECX] =
792 0,
793 .xlevel = 0x80000008,
794 .model_id = "Common KVM processor"
795 },
796 {
797 .name = "qemu32",
798 .level = 4,
799 .vendor = CPUID_VENDOR_INTEL,
800 .family = 6,
801 .model = 6,
802 .stepping = 3,
803 .features[FEAT_1_EDX] =
804 PPRO_FEATURES,
805 .features[FEAT_1_ECX] =
806 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
807 .xlevel = 0x80000004,
808 },
809 {
810 .name = "kvm32",
811 .level = 5,
812 .vendor = CPUID_VENDOR_INTEL,
813 .family = 15,
814 .model = 6,
815 .stepping = 1,
816 .features[FEAT_1_EDX] =
817 PPRO_FEATURES | CPUID_VME |
818 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
819 .features[FEAT_1_ECX] =
820 CPUID_EXT_SSE3,
821 .features[FEAT_8000_0001_ECX] =
822 0,
823 .xlevel = 0x80000008,
824 .model_id = "Common 32-bit KVM processor"
825 },
826 {
827 .name = "coreduo",
828 .level = 10,
829 .vendor = CPUID_VENDOR_INTEL,
830 .family = 6,
831 .model = 14,
832 .stepping = 8,
833 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
834 .features[FEAT_1_EDX] =
835 PPRO_FEATURES | CPUID_VME |
836 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
837 CPUID_SS,
838 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
839 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
840 .features[FEAT_1_ECX] =
841 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
842 .features[FEAT_8000_0001_EDX] =
843 CPUID_EXT2_NX,
844 .xlevel = 0x80000008,
845 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
846 },
847 {
848 .name = "486",
849 .level = 1,
850 .vendor = CPUID_VENDOR_INTEL,
851 .family = 4,
852 .model = 8,
853 .stepping = 0,
854 .features[FEAT_1_EDX] =
855 I486_FEATURES,
856 .xlevel = 0,
857 },
858 {
859 .name = "pentium",
860 .level = 1,
861 .vendor = CPUID_VENDOR_INTEL,
862 .family = 5,
863 .model = 4,
864 .stepping = 3,
865 .features[FEAT_1_EDX] =
866 PENTIUM_FEATURES,
867 .xlevel = 0,
868 },
869 {
870 .name = "pentium2",
871 .level = 2,
872 .vendor = CPUID_VENDOR_INTEL,
873 .family = 6,
874 .model = 5,
875 .stepping = 2,
876 .features[FEAT_1_EDX] =
877 PENTIUM2_FEATURES,
878 .xlevel = 0,
879 },
880 {
881 .name = "pentium3",
882 .level = 3,
883 .vendor = CPUID_VENDOR_INTEL,
884 .family = 6,
885 .model = 7,
886 .stepping = 3,
887 .features[FEAT_1_EDX] =
888 PENTIUM3_FEATURES,
889 .xlevel = 0,
890 },
891 {
892 .name = "athlon",
893 .level = 2,
894 .vendor = CPUID_VENDOR_AMD,
895 .family = 6,
896 .model = 2,
897 .stepping = 3,
898 .features[FEAT_1_EDX] =
899 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
900 CPUID_MCA,
901 .features[FEAT_8000_0001_EDX] =
902 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
903 .xlevel = 0x80000008,
904 },
905 {
906 .name = "n270",
907 .level = 10,
908 .vendor = CPUID_VENDOR_INTEL,
909 .family = 6,
910 .model = 28,
911 .stepping = 2,
912 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
913 .features[FEAT_1_EDX] =
914 PPRO_FEATURES |
915 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
916 CPUID_ACPI | CPUID_SS,
917 /* Some CPUs got no CPUID_SEP */
918 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
919 * CPUID_EXT_XTPR */
920 .features[FEAT_1_ECX] =
921 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
922 CPUID_EXT_MOVBE,
923 .features[FEAT_8000_0001_EDX] =
924 CPUID_EXT2_NX,
925 .features[FEAT_8000_0001_ECX] =
926 CPUID_EXT3_LAHF_LM,
927 .xlevel = 0x80000008,
928 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
929 },
930 {
931 .name = "Conroe",
932 .level = 10,
933 .vendor = CPUID_VENDOR_INTEL,
934 .family = 6,
935 .model = 15,
936 .stepping = 3,
937 .features[FEAT_1_EDX] =
938 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
939 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
940 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
941 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
942 CPUID_DE | CPUID_FP87,
943 .features[FEAT_1_ECX] =
944 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
945 .features[FEAT_8000_0001_EDX] =
946 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
947 .features[FEAT_8000_0001_ECX] =
948 CPUID_EXT3_LAHF_LM,
949 .xlevel = 0x80000008,
950 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
951 },
952 {
953 .name = "Penryn",
954 .level = 10,
955 .vendor = CPUID_VENDOR_INTEL,
956 .family = 6,
957 .model = 23,
958 .stepping = 3,
959 .features[FEAT_1_EDX] =
960 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
961 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
962 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
963 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
964 CPUID_DE | CPUID_FP87,
965 .features[FEAT_1_ECX] =
966 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
967 CPUID_EXT_SSE3,
968 .features[FEAT_8000_0001_EDX] =
969 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
970 .features[FEAT_8000_0001_ECX] =
971 CPUID_EXT3_LAHF_LM,
972 .xlevel = 0x80000008,
973 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
974 },
975 {
976 .name = "Nehalem",
977 .level = 11,
978 .vendor = CPUID_VENDOR_INTEL,
979 .family = 6,
980 .model = 26,
981 .stepping = 3,
982 .features[FEAT_1_EDX] =
983 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
984 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
985 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
986 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
987 CPUID_DE | CPUID_FP87,
988 .features[FEAT_1_ECX] =
989 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
990 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
991 .features[FEAT_8000_0001_EDX] =
992 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
993 .features[FEAT_8000_0001_ECX] =
994 CPUID_EXT3_LAHF_LM,
995 .xlevel = 0x80000008,
996 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
997 },
998 {
999 .name = "Westmere",
1000 .level = 11,
1001 .vendor = CPUID_VENDOR_INTEL,
1002 .family = 6,
1003 .model = 44,
1004 .stepping = 1,
1005 .features[FEAT_1_EDX] =
1006 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1007 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1008 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1009 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1010 CPUID_DE | CPUID_FP87,
1011 .features[FEAT_1_ECX] =
1012 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1013 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1014 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1015 .features[FEAT_8000_0001_EDX] =
1016 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1017 .features[FEAT_8000_0001_ECX] =
1018 CPUID_EXT3_LAHF_LM,
1019 .features[FEAT_6_EAX] =
1020 CPUID_6_EAX_ARAT,
1021 .xlevel = 0x80000008,
1022 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1023 },
1024 {
1025 .name = "SandyBridge",
1026 .level = 0xd,
1027 .vendor = CPUID_VENDOR_INTEL,
1028 .family = 6,
1029 .model = 42,
1030 .stepping = 1,
1031 .features[FEAT_1_EDX] =
1032 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1033 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1034 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1035 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1036 CPUID_DE | CPUID_FP87,
1037 .features[FEAT_1_ECX] =
1038 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1039 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1040 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1041 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1042 CPUID_EXT_SSE3,
1043 .features[FEAT_8000_0001_EDX] =
1044 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1045 CPUID_EXT2_SYSCALL,
1046 .features[FEAT_8000_0001_ECX] =
1047 CPUID_EXT3_LAHF_LM,
1048 .features[FEAT_XSAVE] =
1049 CPUID_XSAVE_XSAVEOPT,
1050 .features[FEAT_6_EAX] =
1051 CPUID_6_EAX_ARAT,
1052 .xlevel = 0x80000008,
1053 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1054 },
1055 {
1056 .name = "IvyBridge",
1057 .level = 0xd,
1058 .vendor = CPUID_VENDOR_INTEL,
1059 .family = 6,
1060 .model = 58,
1061 .stepping = 9,
1062 .features[FEAT_1_EDX] =
1063 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1064 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1065 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1066 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1067 CPUID_DE | CPUID_FP87,
1068 .features[FEAT_1_ECX] =
1069 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1070 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1071 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1072 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1073 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1074 .features[FEAT_7_0_EBX] =
1075 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1076 CPUID_7_0_EBX_ERMS,
1077 .features[FEAT_8000_0001_EDX] =
1078 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1079 CPUID_EXT2_SYSCALL,
1080 .features[FEAT_8000_0001_ECX] =
1081 CPUID_EXT3_LAHF_LM,
1082 .features[FEAT_XSAVE] =
1083 CPUID_XSAVE_XSAVEOPT,
1084 .features[FEAT_6_EAX] =
1085 CPUID_6_EAX_ARAT,
1086 .xlevel = 0x80000008,
1087 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1088 },
1089 {
1090 .name = "Haswell-noTSX",
1091 .level = 0xd,
1092 .vendor = CPUID_VENDOR_INTEL,
1093 .family = 6,
1094 .model = 60,
1095 .stepping = 1,
1096 .features[FEAT_1_EDX] =
1097 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1098 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1099 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1100 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1101 CPUID_DE | CPUID_FP87,
1102 .features[FEAT_1_ECX] =
1103 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1104 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1105 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1106 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1107 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1108 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1109 .features[FEAT_8000_0001_EDX] =
1110 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1111 CPUID_EXT2_SYSCALL,
1112 .features[FEAT_8000_0001_ECX] =
1113 CPUID_EXT3_LAHF_LM,
1114 .features[FEAT_7_0_EBX] =
1115 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1116 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1117 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1118 .features[FEAT_XSAVE] =
1119 CPUID_XSAVE_XSAVEOPT,
1120 .features[FEAT_6_EAX] =
1121 CPUID_6_EAX_ARAT,
1122 .xlevel = 0x80000008,
1123 .model_id = "Intel Core Processor (Haswell, no TSX)",
1124 }, {
1125 .name = "Haswell",
1126 .level = 0xd,
1127 .vendor = CPUID_VENDOR_INTEL,
1128 .family = 6,
1129 .model = 60,
1130 .stepping = 1,
1131 .features[FEAT_1_EDX] =
1132 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1133 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1134 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1135 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1136 CPUID_DE | CPUID_FP87,
1137 .features[FEAT_1_ECX] =
1138 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1139 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1140 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1141 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1142 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1143 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1144 .features[FEAT_8000_0001_EDX] =
1145 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1146 CPUID_EXT2_SYSCALL,
1147 .features[FEAT_8000_0001_ECX] =
1148 CPUID_EXT3_LAHF_LM,
1149 .features[FEAT_7_0_EBX] =
1150 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1151 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1152 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1153 CPUID_7_0_EBX_RTM,
1154 .features[FEAT_XSAVE] =
1155 CPUID_XSAVE_XSAVEOPT,
1156 .features[FEAT_6_EAX] =
1157 CPUID_6_EAX_ARAT,
1158 .xlevel = 0x80000008,
1159 .model_id = "Intel Core Processor (Haswell)",
1160 },
1161 {
1162 .name = "Broadwell-noTSX",
1163 .level = 0xd,
1164 .vendor = CPUID_VENDOR_INTEL,
1165 .family = 6,
1166 .model = 61,
1167 .stepping = 2,
1168 .features[FEAT_1_EDX] =
1169 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1170 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1171 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1172 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1173 CPUID_DE | CPUID_FP87,
1174 .features[FEAT_1_ECX] =
1175 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1176 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1177 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1178 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1179 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1180 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1181 .features[FEAT_8000_0001_EDX] =
1182 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1183 CPUID_EXT2_SYSCALL,
1184 .features[FEAT_8000_0001_ECX] =
1185 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1186 .features[FEAT_7_0_EBX] =
1187 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1188 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1189 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1190 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1191 CPUID_7_0_EBX_SMAP,
1192 .features[FEAT_XSAVE] =
1193 CPUID_XSAVE_XSAVEOPT,
1194 .features[FEAT_6_EAX] =
1195 CPUID_6_EAX_ARAT,
1196 .xlevel = 0x80000008,
1197 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1198 },
1199 {
1200 .name = "Broadwell",
1201 .level = 0xd,
1202 .vendor = CPUID_VENDOR_INTEL,
1203 .family = 6,
1204 .model = 61,
1205 .stepping = 2,
1206 .features[FEAT_1_EDX] =
1207 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1208 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1209 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1210 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1211 CPUID_DE | CPUID_FP87,
1212 .features[FEAT_1_ECX] =
1213 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1214 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1215 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1216 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1217 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1218 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1219 .features[FEAT_8000_0001_EDX] =
1220 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1221 CPUID_EXT2_SYSCALL,
1222 .features[FEAT_8000_0001_ECX] =
1223 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1224 .features[FEAT_7_0_EBX] =
1225 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1226 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1227 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1228 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1229 CPUID_7_0_EBX_SMAP,
1230 .features[FEAT_XSAVE] =
1231 CPUID_XSAVE_XSAVEOPT,
1232 .features[FEAT_6_EAX] =
1233 CPUID_6_EAX_ARAT,
1234 .xlevel = 0x80000008,
1235 .model_id = "Intel Core Processor (Broadwell)",
1236 },
1237 {
1238 .name = "Opteron_G1",
1239 .level = 5,
1240 .vendor = CPUID_VENDOR_AMD,
1241 .family = 15,
1242 .model = 6,
1243 .stepping = 1,
1244 .features[FEAT_1_EDX] =
1245 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1246 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1247 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1248 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1249 CPUID_DE | CPUID_FP87,
1250 .features[FEAT_1_ECX] =
1251 CPUID_EXT_SSE3,
1252 .features[FEAT_8000_0001_EDX] =
1253 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1254 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1255 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1256 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1257 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1258 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1259 .xlevel = 0x80000008,
1260 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1261 },
1262 {
1263 .name = "Opteron_G2",
1264 .level = 5,
1265 .vendor = CPUID_VENDOR_AMD,
1266 .family = 15,
1267 .model = 6,
1268 .stepping = 1,
1269 .features[FEAT_1_EDX] =
1270 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1271 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1272 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1273 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1274 CPUID_DE | CPUID_FP87,
1275 .features[FEAT_1_ECX] =
1276 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1277 .features[FEAT_8000_0001_EDX] =
1278 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1279 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1280 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1281 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1282 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1283 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1284 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1285 .features[FEAT_8000_0001_ECX] =
1286 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1287 .xlevel = 0x80000008,
1288 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1289 },
1290 {
1291 .name = "Opteron_G3",
1292 .level = 5,
1293 .vendor = CPUID_VENDOR_AMD,
1294 .family = 15,
1295 .model = 6,
1296 .stepping = 1,
1297 .features[FEAT_1_EDX] =
1298 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1299 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1300 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1301 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1302 CPUID_DE | CPUID_FP87,
1303 .features[FEAT_1_ECX] =
1304 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1305 CPUID_EXT_SSE3,
1306 .features[FEAT_8000_0001_EDX] =
1307 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1308 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1309 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1310 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1311 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1312 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1313 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1314 .features[FEAT_8000_0001_ECX] =
1315 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1316 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1317 .xlevel = 0x80000008,
1318 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1319 },
1320 {
1321 .name = "Opteron_G4",
1322 .level = 0xd,
1323 .vendor = CPUID_VENDOR_AMD,
1324 .family = 21,
1325 .model = 1,
1326 .stepping = 2,
1327 .features[FEAT_1_EDX] =
1328 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1329 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1330 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1331 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1332 CPUID_DE | CPUID_FP87,
1333 .features[FEAT_1_ECX] =
1334 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1335 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1336 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1337 CPUID_EXT_SSE3,
1338 .features[FEAT_8000_0001_EDX] =
1339 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1340 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1341 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1342 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1343 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1344 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1345 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1346 .features[FEAT_8000_0001_ECX] =
1347 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1348 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1349 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1350 CPUID_EXT3_LAHF_LM,
1351 /* no xsaveopt! */
1352 .xlevel = 0x8000001A,
1353 .model_id = "AMD Opteron 62xx class CPU",
1354 },
1355 {
1356 .name = "Opteron_G5",
1357 .level = 0xd,
1358 .vendor = CPUID_VENDOR_AMD,
1359 .family = 21,
1360 .model = 2,
1361 .stepping = 0,
1362 .features[FEAT_1_EDX] =
1363 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1364 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1365 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1366 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1367 CPUID_DE | CPUID_FP87,
1368 .features[FEAT_1_ECX] =
1369 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1370 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1371 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1372 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1373 .features[FEAT_8000_0001_EDX] =
1374 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1375 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1376 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1377 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1378 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1379 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1380 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1381 .features[FEAT_8000_0001_ECX] =
1382 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1383 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1384 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1385 CPUID_EXT3_LAHF_LM,
1386 /* no xsaveopt! */
1387 .xlevel = 0x8000001A,
1388 .model_id = "AMD Opteron 63xx class CPU",
1389 },
1390 };
1391
1392 /**
1393 * x86_cpu_compat_set_features:
1394 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1395 * @w: Identifies the feature word to be changed.
1396 * @feat_add: Feature bits to be added to feature word
1397 * @feat_remove: Feature bits to be removed from feature word
1398 *
1399 * Change CPU model feature bits for compatibility.
1400 *
1401 * This function may be used by machine-type compatibility functions
1402 * to enable or disable feature bits on specific CPU models.
1403 */
1404 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1405 uint32_t feat_add, uint32_t feat_remove)
1406 {
1407 X86CPUDefinition *def;
1408 int i;
1409 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1410 def = &builtin_x86_defs[i];
1411 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1412 def->features[w] |= feat_add;
1413 def->features[w] &= ~feat_remove;
1414 }
1415 }
1416 }
1417
1418 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1419 bool migratable_only);
1420
1421 #ifdef CONFIG_KVM
1422
1423 static int cpu_x86_fill_model_id(char *str)
1424 {
1425 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1426 int i;
1427
1428 for (i = 0; i < 3; i++) {
1429 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1430 memcpy(str + i * 16 + 0, &eax, 4);
1431 memcpy(str + i * 16 + 4, &ebx, 4);
1432 memcpy(str + i * 16 + 8, &ecx, 4);
1433 memcpy(str + i * 16 + 12, &edx, 4);
1434 }
1435 return 0;
1436 }
1437
1438 static X86CPUDefinition host_cpudef;
1439
1440 static Property host_x86_cpu_properties[] = {
1441 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
1442 DEFINE_PROP_END_OF_LIST()
1443 };
1444
1445 /* class_init for the "host" CPU model
1446 *
1447 * This function may be called before KVM is initialized.
1448 */
1449 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1450 {
1451 DeviceClass *dc = DEVICE_CLASS(oc);
1452 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1453 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1454
1455 xcc->kvm_required = true;
1456
1457 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1458 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1459
1460 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1461 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1462 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1463 host_cpudef.stepping = eax & 0x0F;
1464
1465 cpu_x86_fill_model_id(host_cpudef.model_id);
1466
1467 xcc->cpu_def = &host_cpudef;
1468 host_cpudef.cache_info_passthrough = true;
1469
1470 /* level, xlevel, xlevel2, and the feature words are initialized on
1471 * instance_init, because they require KVM to be initialized.
1472 */
1473
1474 dc->props = host_x86_cpu_properties;
1475 }
1476
1477 static void host_x86_cpu_initfn(Object *obj)
1478 {
1479 X86CPU *cpu = X86_CPU(obj);
1480 CPUX86State *env = &cpu->env;
1481 KVMState *s = kvm_state;
1482
1483 assert(kvm_enabled());
1484
1485 /* We can't fill the features array here because we don't know yet if
1486 * "migratable" is true or false.
1487 */
1488 cpu->host_features = true;
1489
1490 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1491 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1492 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1493
1494 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1495 }
1496
1497 static const TypeInfo host_x86_cpu_type_info = {
1498 .name = X86_CPU_TYPE_NAME("host"),
1499 .parent = TYPE_X86_CPU,
1500 .instance_init = host_x86_cpu_initfn,
1501 .class_init = host_x86_cpu_class_init,
1502 };
1503
1504 #endif
1505
1506 static void report_unavailable_features(FeatureWord w, uint32_t mask)
1507 {
1508 FeatureWordInfo *f = &feature_word_info[w];
1509 int i;
1510
1511 for (i = 0; i < 32; ++i) {
1512 if (1 << i & mask) {
1513 const char *reg = get_register_name_32(f->cpuid_reg);
1514 assert(reg);
1515 fprintf(stderr, "warning: %s doesn't support requested feature: "
1516 "CPUID.%02XH:%s%s%s [bit %d]\n",
1517 kvm_enabled() ? "host" : "TCG",
1518 f->cpuid_eax, reg,
1519 f->feat_names[i] ? "." : "",
1520 f->feat_names[i] ? f->feat_names[i] : "", i);
1521 }
1522 }
1523 }
1524
1525 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1526 const char *name, Error **errp)
1527 {
1528 X86CPU *cpu = X86_CPU(obj);
1529 CPUX86State *env = &cpu->env;
1530 int64_t value;
1531
1532 value = (env->cpuid_version >> 8) & 0xf;
1533 if (value == 0xf) {
1534 value += (env->cpuid_version >> 20) & 0xff;
1535 }
1536 visit_type_int(v, &value, name, errp);
1537 }
1538
1539 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1540 const char *name, Error **errp)
1541 {
1542 X86CPU *cpu = X86_CPU(obj);
1543 CPUX86State *env = &cpu->env;
1544 const int64_t min = 0;
1545 const int64_t max = 0xff + 0xf;
1546 Error *local_err = NULL;
1547 int64_t value;
1548
1549 visit_type_int(v, &value, name, &local_err);
1550 if (local_err) {
1551 error_propagate(errp, local_err);
1552 return;
1553 }
1554 if (value < min || value > max) {
1555 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1556 name ? name : "null", value, min, max);
1557 return;
1558 }
1559
1560 env->cpuid_version &= ~0xff00f00;
1561 if (value > 0x0f) {
1562 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1563 } else {
1564 env->cpuid_version |= value << 8;
1565 }
1566 }
1567
1568 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1569 const char *name, Error **errp)
1570 {
1571 X86CPU *cpu = X86_CPU(obj);
1572 CPUX86State *env = &cpu->env;
1573 int64_t value;
1574
1575 value = (env->cpuid_version >> 4) & 0xf;
1576 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1577 visit_type_int(v, &value, name, errp);
1578 }
1579
1580 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1581 const char *name, Error **errp)
1582 {
1583 X86CPU *cpu = X86_CPU(obj);
1584 CPUX86State *env = &cpu->env;
1585 const int64_t min = 0;
1586 const int64_t max = 0xff;
1587 Error *local_err = NULL;
1588 int64_t value;
1589
1590 visit_type_int(v, &value, name, &local_err);
1591 if (local_err) {
1592 error_propagate(errp, local_err);
1593 return;
1594 }
1595 if (value < min || value > max) {
1596 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1597 name ? name : "null", value, min, max);
1598 return;
1599 }
1600
1601 env->cpuid_version &= ~0xf00f0;
1602 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1603 }
1604
1605 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1606 void *opaque, const char *name,
1607 Error **errp)
1608 {
1609 X86CPU *cpu = X86_CPU(obj);
1610 CPUX86State *env = &cpu->env;
1611 int64_t value;
1612
1613 value = env->cpuid_version & 0xf;
1614 visit_type_int(v, &value, name, errp);
1615 }
1616
1617 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1618 void *opaque, const char *name,
1619 Error **errp)
1620 {
1621 X86CPU *cpu = X86_CPU(obj);
1622 CPUX86State *env = &cpu->env;
1623 const int64_t min = 0;
1624 const int64_t max = 0xf;
1625 Error *local_err = NULL;
1626 int64_t value;
1627
1628 visit_type_int(v, &value, name, &local_err);
1629 if (local_err) {
1630 error_propagate(errp, local_err);
1631 return;
1632 }
1633 if (value < min || value > max) {
1634 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1635 name ? name : "null", value, min, max);
1636 return;
1637 }
1638
1639 env->cpuid_version &= ~0xf;
1640 env->cpuid_version |= value & 0xf;
1641 }
1642
1643 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1644 {
1645 X86CPU *cpu = X86_CPU(obj);
1646 CPUX86State *env = &cpu->env;
1647 char *value;
1648
1649 value = g_malloc(CPUID_VENDOR_SZ + 1);
1650 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1651 env->cpuid_vendor3);
1652 return value;
1653 }
1654
1655 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1656 Error **errp)
1657 {
1658 X86CPU *cpu = X86_CPU(obj);
1659 CPUX86State *env = &cpu->env;
1660 int i;
1661
1662 if (strlen(value) != CPUID_VENDOR_SZ) {
1663 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
1664 return;
1665 }
1666
1667 env->cpuid_vendor1 = 0;
1668 env->cpuid_vendor2 = 0;
1669 env->cpuid_vendor3 = 0;
1670 for (i = 0; i < 4; i++) {
1671 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1672 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1673 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1674 }
1675 }
1676
1677 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1678 {
1679 X86CPU *cpu = X86_CPU(obj);
1680 CPUX86State *env = &cpu->env;
1681 char *value;
1682 int i;
1683
1684 value = g_malloc(48 + 1);
1685 for (i = 0; i < 48; i++) {
1686 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1687 }
1688 value[48] = '\0';
1689 return value;
1690 }
1691
1692 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1693 Error **errp)
1694 {
1695 X86CPU *cpu = X86_CPU(obj);
1696 CPUX86State *env = &cpu->env;
1697 int c, len, i;
1698
1699 if (model_id == NULL) {
1700 model_id = "";
1701 }
1702 len = strlen(model_id);
1703 memset(env->cpuid_model, 0, 48);
1704 for (i = 0; i < 48; i++) {
1705 if (i >= len) {
1706 c = '\0';
1707 } else {
1708 c = (uint8_t)model_id[i];
1709 }
1710 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1711 }
1712 }
1713
1714 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1715 const char *name, Error **errp)
1716 {
1717 X86CPU *cpu = X86_CPU(obj);
1718 int64_t value;
1719
1720 value = cpu->env.tsc_khz * 1000;
1721 visit_type_int(v, &value, name, errp);
1722 }
1723
1724 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1725 const char *name, Error **errp)
1726 {
1727 X86CPU *cpu = X86_CPU(obj);
1728 const int64_t min = 0;
1729 const int64_t max = INT64_MAX;
1730 Error *local_err = NULL;
1731 int64_t value;
1732
1733 visit_type_int(v, &value, name, &local_err);
1734 if (local_err) {
1735 error_propagate(errp, local_err);
1736 return;
1737 }
1738 if (value < min || value > max) {
1739 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1740 name ? name : "null", value, min, max);
1741 return;
1742 }
1743
1744 cpu->env.tsc_khz = value / 1000;
1745 }
1746
1747 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1748 const char *name, Error **errp)
1749 {
1750 X86CPU *cpu = X86_CPU(obj);
1751 int64_t value = cpu->apic_id;
1752
1753 visit_type_int(v, &value, name, errp);
1754 }
1755
1756 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1757 const char *name, Error **errp)
1758 {
1759 X86CPU *cpu = X86_CPU(obj);
1760 DeviceState *dev = DEVICE(obj);
1761 const int64_t min = 0;
1762 const int64_t max = UINT32_MAX;
1763 Error *error = NULL;
1764 int64_t value;
1765
1766 if (dev->realized) {
1767 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1768 "it was realized", name, object_get_typename(obj));
1769 return;
1770 }
1771
1772 visit_type_int(v, &value, name, &error);
1773 if (error) {
1774 error_propagate(errp, error);
1775 return;
1776 }
1777 if (value < min || value > max) {
1778 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1779 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1780 object_get_typename(obj), name, value, min, max);
1781 return;
1782 }
1783
1784 if ((value != cpu->apic_id) && cpu_exists(value)) {
1785 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1786 return;
1787 }
1788 cpu->apic_id = value;
1789 }
1790
1791 /* Generic getter for "feature-words" and "filtered-features" properties */
1792 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1793 const char *name, Error **errp)
1794 {
1795 uint32_t *array = (uint32_t *)opaque;
1796 FeatureWord w;
1797 Error *err = NULL;
1798 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1799 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1800 X86CPUFeatureWordInfoList *list = NULL;
1801
1802 for (w = 0; w < FEATURE_WORDS; w++) {
1803 FeatureWordInfo *wi = &feature_word_info[w];
1804 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1805 qwi->cpuid_input_eax = wi->cpuid_eax;
1806 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1807 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1808 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1809 qwi->features = array[w];
1810
1811 /* List will be in reverse order, but order shouldn't matter */
1812 list_entries[w].next = list;
1813 list_entries[w].value = &word_infos[w];
1814 list = &list_entries[w];
1815 }
1816
1817 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1818 error_propagate(errp, err);
1819 }
1820
1821 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1822 const char *name, Error **errp)
1823 {
1824 X86CPU *cpu = X86_CPU(obj);
1825 int64_t value = cpu->hyperv_spinlock_attempts;
1826
1827 visit_type_int(v, &value, name, errp);
1828 }
1829
1830 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1831 const char *name, Error **errp)
1832 {
1833 const int64_t min = 0xFFF;
1834 const int64_t max = UINT_MAX;
1835 X86CPU *cpu = X86_CPU(obj);
1836 Error *err = NULL;
1837 int64_t value;
1838
1839 visit_type_int(v, &value, name, &err);
1840 if (err) {
1841 error_propagate(errp, err);
1842 return;
1843 }
1844
1845 if (value < min || value > max) {
1846 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1847 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1848 object_get_typename(obj), name ? name : "null",
1849 value, min, max);
1850 return;
1851 }
1852 cpu->hyperv_spinlock_attempts = value;
1853 }
1854
1855 static PropertyInfo qdev_prop_spinlocks = {
1856 .name = "int",
1857 .get = x86_get_hv_spinlocks,
1858 .set = x86_set_hv_spinlocks,
1859 };
1860
1861 /* Convert all '_' in a feature string option name to '-', to make feature
1862 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1863 */
1864 static inline void feat2prop(char *s)
1865 {
1866 while ((s = strchr(s, '_'))) {
1867 *s = '-';
1868 }
1869 }
1870
1871 /* Parse "+feature,-feature,feature=foo" CPU feature string
1872 */
1873 static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1874 Error **errp)
1875 {
1876 X86CPU *cpu = X86_CPU(cs);
1877 char *featurestr; /* Single 'key=value" string being parsed */
1878 FeatureWord w;
1879 /* Features to be added */
1880 FeatureWordArray plus_features = { 0 };
1881 /* Features to be removed */
1882 FeatureWordArray minus_features = { 0 };
1883 uint32_t numvalue;
1884 CPUX86State *env = &cpu->env;
1885 Error *local_err = NULL;
1886
1887 featurestr = features ? strtok(features, ",") : NULL;
1888
1889 while (featurestr) {
1890 char *val;
1891 if (featurestr[0] == '+') {
1892 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
1893 } else if (featurestr[0] == '-') {
1894 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
1895 } else if ((val = strchr(featurestr, '='))) {
1896 *val = 0; val++;
1897 feat2prop(featurestr);
1898 if (!strcmp(featurestr, "xlevel")) {
1899 char *err;
1900 char num[32];
1901
1902 numvalue = strtoul(val, &err, 0);
1903 if (!*val || *err) {
1904 error_setg(errp, "bad numerical value %s", val);
1905 return;
1906 }
1907 if (numvalue < 0x80000000) {
1908 error_report("xlevel value shall always be >= 0x80000000"
1909 ", fixup will be removed in future versions");
1910 numvalue += 0x80000000;
1911 }
1912 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1913 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1914 } else if (!strcmp(featurestr, "tsc-freq")) {
1915 int64_t tsc_freq;
1916 char *err;
1917 char num[32];
1918
1919 tsc_freq = strtosz_suffix_unit(val, &err,
1920 STRTOSZ_DEFSUFFIX_B, 1000);
1921 if (tsc_freq < 0 || *err) {
1922 error_setg(errp, "bad numerical value %s", val);
1923 return;
1924 }
1925 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1926 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1927 &local_err);
1928 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1929 char *err;
1930 const int min = 0xFFF;
1931 char num[32];
1932 numvalue = strtoul(val, &err, 0);
1933 if (!*val || *err) {
1934 error_setg(errp, "bad numerical value %s", val);
1935 return;
1936 }
1937 if (numvalue < min) {
1938 error_report("hv-spinlocks value shall always be >= 0x%x"
1939 ", fixup will be removed in future versions",
1940 min);
1941 numvalue = min;
1942 }
1943 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1944 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1945 } else {
1946 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1947 }
1948 } else {
1949 feat2prop(featurestr);
1950 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1951 }
1952 if (local_err) {
1953 error_propagate(errp, local_err);
1954 return;
1955 }
1956 featurestr = strtok(NULL, ",");
1957 }
1958
1959 if (cpu->host_features) {
1960 for (w = 0; w < FEATURE_WORDS; w++) {
1961 env->features[w] =
1962 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1963 }
1964 }
1965
1966 for (w = 0; w < FEATURE_WORDS; w++) {
1967 env->features[w] |= plus_features[w];
1968 env->features[w] &= ~minus_features[w];
1969 }
1970 }
1971
1972 /* Print all cpuid feature names in featureset
1973 */
1974 static void listflags(FILE *f, fprintf_function print, const char **featureset)
1975 {
1976 int bit;
1977 bool first = true;
1978
1979 for (bit = 0; bit < 32; bit++) {
1980 if (featureset[bit]) {
1981 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1982 first = false;
1983 }
1984 }
1985 }
1986
1987 /* generate CPU information. */
1988 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1989 {
1990 X86CPUDefinition *def;
1991 char buf[256];
1992 int i;
1993
1994 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1995 def = &builtin_x86_defs[i];
1996 snprintf(buf, sizeof(buf), "%s", def->name);
1997 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1998 }
1999 #ifdef CONFIG_KVM
2000 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2001 "KVM processor with all supported host features "
2002 "(only available in KVM mode)");
2003 #endif
2004
2005 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
2006 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2007 FeatureWordInfo *fw = &feature_word_info[i];
2008
2009 (*cpu_fprintf)(f, " ");
2010 listflags(f, cpu_fprintf, fw->feat_names);
2011 (*cpu_fprintf)(f, "\n");
2012 }
2013 }
2014
2015 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2016 {
2017 CpuDefinitionInfoList *cpu_list = NULL;
2018 X86CPUDefinition *def;
2019 int i;
2020
2021 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2022 CpuDefinitionInfoList *entry;
2023 CpuDefinitionInfo *info;
2024
2025 def = &builtin_x86_defs[i];
2026 info = g_malloc0(sizeof(*info));
2027 info->name = g_strdup(def->name);
2028
2029 entry = g_malloc0(sizeof(*entry));
2030 entry->value = info;
2031 entry->next = cpu_list;
2032 cpu_list = entry;
2033 }
2034
2035 return cpu_list;
2036 }
2037
2038 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2039 bool migratable_only)
2040 {
2041 FeatureWordInfo *wi = &feature_word_info[w];
2042 uint32_t r;
2043
2044 if (kvm_enabled()) {
2045 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2046 wi->cpuid_ecx,
2047 wi->cpuid_reg);
2048 } else if (tcg_enabled()) {
2049 r = wi->tcg_features;
2050 } else {
2051 return ~0;
2052 }
2053 if (migratable_only) {
2054 r &= x86_cpu_get_migratable_flags(w);
2055 }
2056 return r;
2057 }
2058
2059 /*
2060 * Filters CPU feature words based on host availability of each feature.
2061 *
2062 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2063 */
2064 static int x86_cpu_filter_features(X86CPU *cpu)
2065 {
2066 CPUX86State *env = &cpu->env;
2067 FeatureWord w;
2068 int rv = 0;
2069
2070 for (w = 0; w < FEATURE_WORDS; w++) {
2071 uint32_t host_feat =
2072 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2073 uint32_t requested_features = env->features[w];
2074 env->features[w] &= host_feat;
2075 cpu->filtered_features[w] = requested_features & ~env->features[w];
2076 if (cpu->filtered_features[w]) {
2077 if (cpu->check_cpuid || cpu->enforce_cpuid) {
2078 report_unavailable_features(w, cpu->filtered_features[w]);
2079 }
2080 rv = 1;
2081 }
2082 }
2083
2084 return rv;
2085 }
2086
2087 /* Load data from X86CPUDefinition
2088 */
2089 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
2090 {
2091 CPUX86State *env = &cpu->env;
2092 const char *vendor;
2093 char host_vendor[CPUID_VENDOR_SZ + 1];
2094 FeatureWord w;
2095
2096 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2097 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2098 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2099 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2100 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
2101 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2102 cpu->cache_info_passthrough = def->cache_info_passthrough;
2103 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
2104 for (w = 0; w < FEATURE_WORDS; w++) {
2105 env->features[w] = def->features[w];
2106 }
2107
2108 /* Special cases not set in the X86CPUDefinition structs: */
2109 if (kvm_enabled()) {
2110 FeatureWord w;
2111 for (w = 0; w < FEATURE_WORDS; w++) {
2112 env->features[w] |= kvm_default_features[w];
2113 env->features[w] &= ~kvm_default_unset_features[w];
2114 }
2115 }
2116
2117 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
2118
2119 /* sysenter isn't supported in compatibility mode on AMD,
2120 * syscall isn't supported in compatibility mode on Intel.
2121 * Normally we advertise the actual CPU vendor, but you can
2122 * override this using the 'vendor' property if you want to use
2123 * KVM's sysenter/syscall emulation in compatibility mode and
2124 * when doing cross vendor migration
2125 */
2126 vendor = def->vendor;
2127 if (kvm_enabled()) {
2128 uint32_t ebx = 0, ecx = 0, edx = 0;
2129 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2130 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2131 vendor = host_vendor;
2132 }
2133
2134 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2135
2136 }
2137
2138 X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
2139 {
2140 X86CPU *cpu = NULL;
2141 X86CPUClass *xcc;
2142 ObjectClass *oc;
2143 gchar **model_pieces;
2144 char *name, *features;
2145 Error *error = NULL;
2146
2147 model_pieces = g_strsplit(cpu_model, ",", 2);
2148 if (!model_pieces[0]) {
2149 error_setg(&error, "Invalid/empty CPU model name");
2150 goto out;
2151 }
2152 name = model_pieces[0];
2153 features = model_pieces[1];
2154
2155 oc = x86_cpu_class_by_name(name);
2156 if (oc == NULL) {
2157 error_setg(&error, "Unable to find CPU definition: %s", name);
2158 goto out;
2159 }
2160 xcc = X86_CPU_CLASS(oc);
2161
2162 if (xcc->kvm_required && !kvm_enabled()) {
2163 error_setg(&error, "CPU model '%s' requires KVM", name);
2164 goto out;
2165 }
2166
2167 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2168
2169 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2170 if (error) {
2171 goto out;
2172 }
2173
2174 out:
2175 if (error != NULL) {
2176 error_propagate(errp, error);
2177 if (cpu) {
2178 object_unref(OBJECT(cpu));
2179 cpu = NULL;
2180 }
2181 }
2182 g_strfreev(model_pieces);
2183 return cpu;
2184 }
2185
2186 X86CPU *cpu_x86_init(const char *cpu_model)
2187 {
2188 Error *error = NULL;
2189 X86CPU *cpu;
2190
2191 cpu = cpu_x86_create(cpu_model, &error);
2192 if (error) {
2193 goto out;
2194 }
2195
2196 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2197
2198 out:
2199 if (error) {
2200 error_report_err(error);
2201 if (cpu != NULL) {
2202 object_unref(OBJECT(cpu));
2203 cpu = NULL;
2204 }
2205 }
2206 return cpu;
2207 }
2208
2209 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2210 {
2211 X86CPUDefinition *cpudef = data;
2212 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2213
2214 xcc->cpu_def = cpudef;
2215 }
2216
2217 static void x86_register_cpudef_type(X86CPUDefinition *def)
2218 {
2219 char *typename = x86_cpu_type_name(def->name);
2220 TypeInfo ti = {
2221 .name = typename,
2222 .parent = TYPE_X86_CPU,
2223 .class_init = x86_cpu_cpudef_class_init,
2224 .class_data = def,
2225 };
2226
2227 type_register(&ti);
2228 g_free(typename);
2229 }
2230
2231 #if !defined(CONFIG_USER_ONLY)
2232
2233 void cpu_clear_apic_feature(CPUX86State *env)
2234 {
2235 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2236 }
2237
2238 #endif /* !CONFIG_USER_ONLY */
2239
2240 /* Initialize list of CPU models, filling some non-static fields if necessary
2241 */
2242 void x86_cpudef_setup(void)
2243 {
2244 int i, j;
2245 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2246
2247 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2248 X86CPUDefinition *def = &builtin_x86_defs[i];
2249
2250 /* Look for specific "cpudef" models that */
2251 /* have the QEMU version in .model_id */
2252 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2253 if (strcmp(model_with_versions[j], def->name) == 0) {
2254 pstrcpy(def->model_id, sizeof(def->model_id),
2255 "QEMU Virtual CPU version ");
2256 pstrcat(def->model_id, sizeof(def->model_id),
2257 qemu_get_version());
2258 break;
2259 }
2260 }
2261 }
2262 }
2263
2264 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2265 uint32_t *eax, uint32_t *ebx,
2266 uint32_t *ecx, uint32_t *edx)
2267 {
2268 X86CPU *cpu = x86_env_get_cpu(env);
2269 CPUState *cs = CPU(cpu);
2270
2271 /* test if maximum index reached */
2272 if (index & 0x80000000) {
2273 if (index > env->cpuid_xlevel) {
2274 if (env->cpuid_xlevel2 > 0) {
2275 /* Handle the Centaur's CPUID instruction. */
2276 if (index > env->cpuid_xlevel2) {
2277 index = env->cpuid_xlevel2;
2278 } else if (index < 0xC0000000) {
2279 index = env->cpuid_xlevel;
2280 }
2281 } else {
2282 /* Intel documentation states that invalid EAX input will
2283 * return the same information as EAX=cpuid_level
2284 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2285 */
2286 index = env->cpuid_level;
2287 }
2288 }
2289 } else {
2290 if (index > env->cpuid_level)
2291 index = env->cpuid_level;
2292 }
2293
2294 switch(index) {
2295 case 0:
2296 *eax = env->cpuid_level;
2297 *ebx = env->cpuid_vendor1;
2298 *edx = env->cpuid_vendor2;
2299 *ecx = env->cpuid_vendor3;
2300 break;
2301 case 1:
2302 *eax = env->cpuid_version;
2303 *ebx = (cpu->apic_id << 24) |
2304 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2305 *ecx = env->features[FEAT_1_ECX];
2306 *edx = env->features[FEAT_1_EDX];
2307 if (cs->nr_cores * cs->nr_threads > 1) {
2308 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2309 *edx |= 1 << 28; /* HTT bit */
2310 }
2311 break;
2312 case 2:
2313 /* cache info: needed for Pentium Pro compatibility */
2314 if (cpu->cache_info_passthrough) {
2315 host_cpuid(index, 0, eax, ebx, ecx, edx);
2316 break;
2317 }
2318 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2319 *ebx = 0;
2320 *ecx = 0;
2321 *edx = (L1D_DESCRIPTOR << 16) | \
2322 (L1I_DESCRIPTOR << 8) | \
2323 (L2_DESCRIPTOR);
2324 break;
2325 case 4:
2326 /* cache info: needed for Core compatibility */
2327 if (cpu->cache_info_passthrough) {
2328 host_cpuid(index, count, eax, ebx, ecx, edx);
2329 *eax &= ~0xFC000000;
2330 } else {
2331 *eax = 0;
2332 switch (count) {
2333 case 0: /* L1 dcache info */
2334 *eax |= CPUID_4_TYPE_DCACHE | \
2335 CPUID_4_LEVEL(1) | \
2336 CPUID_4_SELF_INIT_LEVEL;
2337 *ebx = (L1D_LINE_SIZE - 1) | \
2338 ((L1D_PARTITIONS - 1) << 12) | \
2339 ((L1D_ASSOCIATIVITY - 1) << 22);
2340 *ecx = L1D_SETS - 1;
2341 *edx = CPUID_4_NO_INVD_SHARING;
2342 break;
2343 case 1: /* L1 icache info */
2344 *eax |= CPUID_4_TYPE_ICACHE | \
2345 CPUID_4_LEVEL(1) | \
2346 CPUID_4_SELF_INIT_LEVEL;
2347 *ebx = (L1I_LINE_SIZE - 1) | \
2348 ((L1I_PARTITIONS - 1) << 12) | \
2349 ((L1I_ASSOCIATIVITY - 1) << 22);
2350 *ecx = L1I_SETS - 1;
2351 *edx = CPUID_4_NO_INVD_SHARING;
2352 break;
2353 case 2: /* L2 cache info */
2354 *eax |= CPUID_4_TYPE_UNIFIED | \
2355 CPUID_4_LEVEL(2) | \
2356 CPUID_4_SELF_INIT_LEVEL;
2357 if (cs->nr_threads > 1) {
2358 *eax |= (cs->nr_threads - 1) << 14;
2359 }
2360 *ebx = (L2_LINE_SIZE - 1) | \
2361 ((L2_PARTITIONS - 1) << 12) | \
2362 ((L2_ASSOCIATIVITY - 1) << 22);
2363 *ecx = L2_SETS - 1;
2364 *edx = CPUID_4_NO_INVD_SHARING;
2365 break;
2366 default: /* end of info */
2367 *eax = 0;
2368 *ebx = 0;
2369 *ecx = 0;
2370 *edx = 0;
2371 break;
2372 }
2373 }
2374
2375 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2376 if ((*eax & 31) && cs->nr_cores > 1) {
2377 *eax |= (cs->nr_cores - 1) << 26;
2378 }
2379 break;
2380 case 5:
2381 /* mwait info: needed for Core compatibility */
2382 *eax = 0; /* Smallest monitor-line size in bytes */
2383 *ebx = 0; /* Largest monitor-line size in bytes */
2384 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2385 *edx = 0;
2386 break;
2387 case 6:
2388 /* Thermal and Power Leaf */
2389 *eax = env->features[FEAT_6_EAX];
2390 *ebx = 0;
2391 *ecx = 0;
2392 *edx = 0;
2393 break;
2394 case 7:
2395 /* Structured Extended Feature Flags Enumeration Leaf */
2396 if (count == 0) {
2397 *eax = 0; /* Maximum ECX value for sub-leaves */
2398 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2399 *ecx = 0; /* Reserved */
2400 *edx = 0; /* Reserved */
2401 } else {
2402 *eax = 0;
2403 *ebx = 0;
2404 *ecx = 0;
2405 *edx = 0;
2406 }
2407 break;
2408 case 9:
2409 /* Direct Cache Access Information Leaf */
2410 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2411 *ebx = 0;
2412 *ecx = 0;
2413 *edx = 0;
2414 break;
2415 case 0xA:
2416 /* Architectural Performance Monitoring Leaf */
2417 if (kvm_enabled() && cpu->enable_pmu) {
2418 KVMState *s = cs->kvm_state;
2419
2420 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2421 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2422 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2423 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2424 } else {
2425 *eax = 0;
2426 *ebx = 0;
2427 *ecx = 0;
2428 *edx = 0;
2429 }
2430 break;
2431 case 0xD: {
2432 KVMState *s = cs->kvm_state;
2433 uint64_t kvm_mask;
2434 int i;
2435
2436 /* Processor Extended State */
2437 *eax = 0;
2438 *ebx = 0;
2439 *ecx = 0;
2440 *edx = 0;
2441 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2442 break;
2443 }
2444 kvm_mask =
2445 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2446 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2447
2448 if (count == 0) {
2449 *ecx = 0x240;
2450 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2451 const ExtSaveArea *esa = &ext_save_areas[i];
2452 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2453 (kvm_mask & (1 << i)) != 0) {
2454 if (i < 32) {
2455 *eax |= 1 << i;
2456 } else {
2457 *edx |= 1 << (i - 32);
2458 }
2459 *ecx = MAX(*ecx, esa->offset + esa->size);
2460 }
2461 }
2462 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2463 *ebx = *ecx;
2464 } else if (count == 1) {
2465 *eax = env->features[FEAT_XSAVE];
2466 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2467 const ExtSaveArea *esa = &ext_save_areas[count];
2468 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2469 (kvm_mask & (1 << count)) != 0) {
2470 *eax = esa->size;
2471 *ebx = esa->offset;
2472 }
2473 }
2474 break;
2475 }
2476 case 0x80000000:
2477 *eax = env->cpuid_xlevel;
2478 *ebx = env->cpuid_vendor1;
2479 *edx = env->cpuid_vendor2;
2480 *ecx = env->cpuid_vendor3;
2481 break;
2482 case 0x80000001:
2483 *eax = env->cpuid_version;
2484 *ebx = 0;
2485 *ecx = env->features[FEAT_8000_0001_ECX];
2486 *edx = env->features[FEAT_8000_0001_EDX];
2487
2488 /* The Linux kernel checks for the CMPLegacy bit and
2489 * discards multiple thread information if it is set.
2490 * So dont set it here for Intel to make Linux guests happy.
2491 */
2492 if (cs->nr_cores * cs->nr_threads > 1) {
2493 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2494 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2495 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
2496 *ecx |= 1 << 1; /* CmpLegacy bit */
2497 }
2498 }
2499 break;
2500 case 0x80000002:
2501 case 0x80000003:
2502 case 0x80000004:
2503 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2504 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2505 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2506 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2507 break;
2508 case 0x80000005:
2509 /* cache info (L1 cache) */
2510 if (cpu->cache_info_passthrough) {
2511 host_cpuid(index, 0, eax, ebx, ecx, edx);
2512 break;
2513 }
2514 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2515 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2516 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2517 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2518 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2519 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2520 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2521 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2522 break;
2523 case 0x80000006:
2524 /* cache info (L2 cache) */
2525 if (cpu->cache_info_passthrough) {
2526 host_cpuid(index, 0, eax, ebx, ecx, edx);
2527 break;
2528 }
2529 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2530 (L2_DTLB_2M_ENTRIES << 16) | \
2531 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2532 (L2_ITLB_2M_ENTRIES);
2533 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2534 (L2_DTLB_4K_ENTRIES << 16) | \
2535 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2536 (L2_ITLB_4K_ENTRIES);
2537 *ecx = (L2_SIZE_KB_AMD << 16) | \
2538 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2539 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2540 *edx = ((L3_SIZE_KB/512) << 18) | \
2541 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2542 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2543 break;
2544 case 0x80000007:
2545 *eax = 0;
2546 *ebx = 0;
2547 *ecx = 0;
2548 *edx = env->features[FEAT_8000_0007_EDX];
2549 break;
2550 case 0x80000008:
2551 /* virtual & phys address size in low 2 bytes. */
2552 /* XXX: This value must match the one used in the MMU code. */
2553 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2554 /* 64 bit processor */
2555 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2556 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2557 } else {
2558 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2559 *eax = 0x00000024; /* 36 bits physical */
2560 } else {
2561 *eax = 0x00000020; /* 32 bits physical */
2562 }
2563 }
2564 *ebx = 0;
2565 *ecx = 0;
2566 *edx = 0;
2567 if (cs->nr_cores * cs->nr_threads > 1) {
2568 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2569 }
2570 break;
2571 case 0x8000000A:
2572 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2573 *eax = 0x00000001; /* SVM Revision */
2574 *ebx = 0x00000010; /* nr of ASIDs */
2575 *ecx = 0;
2576 *edx = env->features[FEAT_SVM]; /* optional features */
2577 } else {
2578 *eax = 0;
2579 *ebx = 0;
2580 *ecx = 0;
2581 *edx = 0;
2582 }
2583 break;
2584 case 0xC0000000:
2585 *eax = env->cpuid_xlevel2;
2586 *ebx = 0;
2587 *ecx = 0;
2588 *edx = 0;
2589 break;
2590 case 0xC0000001:
2591 /* Support for VIA CPU's CPUID instruction */
2592 *eax = env->cpuid_version;
2593 *ebx = 0;
2594 *ecx = 0;
2595 *edx = env->features[FEAT_C000_0001_EDX];
2596 break;
2597 case 0xC0000002:
2598 case 0xC0000003:
2599 case 0xC0000004:
2600 /* Reserved for the future, and now filled with zero */
2601 *eax = 0;
2602 *ebx = 0;
2603 *ecx = 0;
2604 *edx = 0;
2605 break;
2606 default:
2607 /* reserved values: zero */
2608 *eax = 0;
2609 *ebx = 0;
2610 *ecx = 0;
2611 *edx = 0;
2612 break;
2613 }
2614 }
2615
2616 /* CPUClass::reset() */
2617 static void x86_cpu_reset(CPUState *s)
2618 {
2619 X86CPU *cpu = X86_CPU(s);
2620 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2621 CPUX86State *env = &cpu->env;
2622 int i;
2623
2624 xcc->parent_reset(s);
2625
2626 memset(env, 0, offsetof(CPUX86State, cpuid_level));
2627
2628 tlb_flush(s, 1);
2629
2630 env->old_exception = -1;
2631
2632 /* init to reset state */
2633
2634 #ifdef CONFIG_SOFTMMU
2635 env->hflags |= HF_SOFTMMU_MASK;
2636 #endif
2637 env->hflags2 |= HF2_GIF_MASK;
2638
2639 cpu_x86_update_cr0(env, 0x60000010);
2640 env->a20_mask = ~0x0;
2641 env->smbase = 0x30000;
2642
2643 env->idt.limit = 0xffff;
2644 env->gdt.limit = 0xffff;
2645 env->ldt.limit = 0xffff;
2646 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2647 env->tr.limit = 0xffff;
2648 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2649
2650 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2651 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2652 DESC_R_MASK | DESC_A_MASK);
2653 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2654 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2655 DESC_A_MASK);
2656 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2657 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2658 DESC_A_MASK);
2659 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2660 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2661 DESC_A_MASK);
2662 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2663 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2664 DESC_A_MASK);
2665 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2666 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2667 DESC_A_MASK);
2668
2669 env->eip = 0xfff0;
2670 env->regs[R_EDX] = env->cpuid_version;
2671
2672 env->eflags = 0x2;
2673
2674 /* FPU init */
2675 for (i = 0; i < 8; i++) {
2676 env->fptags[i] = 1;
2677 }
2678 cpu_set_fpuc(env, 0x37f);
2679
2680 env->mxcsr = 0x1f80;
2681 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2682
2683 env->pat = 0x0007040600070406ULL;
2684 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2685
2686 memset(env->dr, 0, sizeof(env->dr));
2687 env->dr[6] = DR6_FIXED_1;
2688 env->dr[7] = DR7_FIXED_1;
2689 cpu_breakpoint_remove_all(s, BP_CPU);
2690 cpu_watchpoint_remove_all(s, BP_CPU);
2691
2692 env->xcr0 = 1;
2693
2694 /*
2695 * SDM 11.11.5 requires:
2696 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2697 * - IA32_MTRR_PHYSMASKn.V = 0
2698 * All other bits are undefined. For simplification, zero it all.
2699 */
2700 env->mtrr_deftype = 0;
2701 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2702 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2703
2704 #if !defined(CONFIG_USER_ONLY)
2705 /* We hard-wire the BSP to the first CPU. */
2706 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
2707
2708 s->halted = !cpu_is_bsp(cpu);
2709
2710 if (kvm_enabled()) {
2711 kvm_arch_reset_vcpu(cpu);
2712 }
2713 #endif
2714 }
2715
2716 #ifndef CONFIG_USER_ONLY
2717 bool cpu_is_bsp(X86CPU *cpu)
2718 {
2719 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2720 }
2721
2722 /* TODO: remove me, when reset over QOM tree is implemented */
2723 static void x86_cpu_machine_reset_cb(void *opaque)
2724 {
2725 X86CPU *cpu = opaque;
2726 cpu_reset(CPU(cpu));
2727 }
2728 #endif
2729
2730 static void mce_init(X86CPU *cpu)
2731 {
2732 CPUX86State *cenv = &cpu->env;
2733 unsigned int bank;
2734
2735 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2736 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2737 (CPUID_MCE | CPUID_MCA)) {
2738 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2739 cenv->mcg_ctl = ~(uint64_t)0;
2740 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2741 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2742 }
2743 }
2744 }
2745
2746 #ifndef CONFIG_USER_ONLY
2747 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2748 {
2749 DeviceState *dev = DEVICE(cpu);
2750 APICCommonState *apic;
2751 const char *apic_type = "apic";
2752
2753 if (kvm_irqchip_in_kernel()) {
2754 apic_type = "kvm-apic";
2755 } else if (xen_enabled()) {
2756 apic_type = "xen-apic";
2757 }
2758
2759 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2760 if (cpu->apic_state == NULL) {
2761 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2762 return;
2763 }
2764
2765 object_property_add_child(OBJECT(cpu), "apic",
2766 OBJECT(cpu->apic_state), NULL);
2767 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
2768 /* TODO: convert to link<> */
2769 apic = APIC_COMMON(cpu->apic_state);
2770 apic->cpu = cpu;
2771 }
2772
2773 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2774 {
2775 if (cpu->apic_state == NULL) {
2776 return;
2777 }
2778 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2779 errp);
2780 }
2781
2782 static void x86_cpu_machine_done(Notifier *n, void *unused)
2783 {
2784 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2785 MemoryRegion *smram =
2786 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2787
2788 if (smram) {
2789 cpu->smram = g_new(MemoryRegion, 1);
2790 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2791 smram, 0, 1ull << 32);
2792 memory_region_set_enabled(cpu->smram, false);
2793 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2794 }
2795 }
2796 #else
2797 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2798 {
2799 }
2800 #endif
2801
2802
2803 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2804 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2805 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2806 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2807 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2808 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2809 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2810 {
2811 CPUState *cs = CPU(dev);
2812 X86CPU *cpu = X86_CPU(dev);
2813 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2814 CPUX86State *env = &cpu->env;
2815 Error *local_err = NULL;
2816 static bool ht_warned;
2817
2818 if (cpu->apic_id < 0) {
2819 error_setg(errp, "apic-id property was not initialized properly");
2820 return;
2821 }
2822
2823 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2824 env->cpuid_level = 7;
2825 }
2826
2827 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2828 * CPUID[1].EDX.
2829 */
2830 if (IS_AMD_CPU(env)) {
2831 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2832 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2833 & CPUID_EXT2_AMD_ALIASES);
2834 }
2835
2836
2837 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2838 error_setg(&local_err,
2839 kvm_enabled() ?
2840 "Host doesn't support requested features" :
2841 "TCG doesn't support requested features");
2842 goto out;
2843 }
2844
2845 #ifndef CONFIG_USER_ONLY
2846 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2847
2848 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2849 x86_cpu_apic_create(cpu, &local_err);
2850 if (local_err != NULL) {
2851 goto out;
2852 }
2853 }
2854 #endif
2855
2856 mce_init(cpu);
2857
2858 #ifndef CONFIG_USER_ONLY
2859 if (tcg_enabled()) {
2860 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2861 cpu->cpu_as_root = g_new(MemoryRegion, 1);
2862 cs->as = g_new(AddressSpace, 1);
2863
2864 /* Outer container... */
2865 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2866 memory_region_set_enabled(cpu->cpu_as_root, true);
2867
2868 /* ... with two regions inside: normal system memory with low
2869 * priority, and...
2870 */
2871 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2872 get_system_memory(), 0, ~0ull);
2873 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2874 memory_region_set_enabled(cpu->cpu_as_mem, true);
2875 address_space_init(cs->as, cpu->cpu_as_root, "CPU");
2876
2877 /* ... SMRAM with higher priority, linked from /machine/smram. */
2878 cpu->machine_done.notify = x86_cpu_machine_done;
2879 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2880 }
2881 #endif
2882
2883 qemu_init_vcpu(cs);
2884
2885 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2886 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2887 * based on inputs (sockets,cores,threads), it is still better to gives
2888 * users a warning.
2889 *
2890 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2891 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2892 */
2893 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2894 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2895 " -smp options properly.");
2896 ht_warned = true;
2897 }
2898
2899 x86_cpu_apic_realize(cpu, &local_err);
2900 if (local_err != NULL) {
2901 goto out;
2902 }
2903 cpu_reset(cs);
2904
2905 xcc->parent_realize(dev, &local_err);
2906
2907 out:
2908 if (local_err != NULL) {
2909 error_propagate(errp, local_err);
2910 return;
2911 }
2912 }
2913
2914 typedef struct BitProperty {
2915 uint32_t *ptr;
2916 uint32_t mask;
2917 } BitProperty;
2918
2919 static void x86_cpu_get_bit_prop(Object *obj,
2920 struct Visitor *v,
2921 void *opaque,
2922 const char *name,
2923 Error **errp)
2924 {
2925 BitProperty *fp = opaque;
2926 bool value = (*fp->ptr & fp->mask) == fp->mask;
2927 visit_type_bool(v, &value, name, errp);
2928 }
2929
2930 static void x86_cpu_set_bit_prop(Object *obj,
2931 struct Visitor *v,
2932 void *opaque,
2933 const char *name,
2934 Error **errp)
2935 {
2936 DeviceState *dev = DEVICE(obj);
2937 BitProperty *fp = opaque;
2938 Error *local_err = NULL;
2939 bool value;
2940
2941 if (dev->realized) {
2942 qdev_prop_set_after_realize(dev, name, errp);
2943 return;
2944 }
2945
2946 visit_type_bool(v, &value, name, &local_err);
2947 if (local_err) {
2948 error_propagate(errp, local_err);
2949 return;
2950 }
2951
2952 if (value) {
2953 *fp->ptr |= fp->mask;
2954 } else {
2955 *fp->ptr &= ~fp->mask;
2956 }
2957 }
2958
2959 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
2960 void *opaque)
2961 {
2962 BitProperty *prop = opaque;
2963 g_free(prop);
2964 }
2965
2966 /* Register a boolean property to get/set a single bit in a uint32_t field.
2967 *
2968 * The same property name can be registered multiple times to make it affect
2969 * multiple bits in the same FeatureWord. In that case, the getter will return
2970 * true only if all bits are set.
2971 */
2972 static void x86_cpu_register_bit_prop(X86CPU *cpu,
2973 const char *prop_name,
2974 uint32_t *field,
2975 int bitnr)
2976 {
2977 BitProperty *fp;
2978 ObjectProperty *op;
2979 uint32_t mask = (1UL << bitnr);
2980
2981 op = object_property_find(OBJECT(cpu), prop_name, NULL);
2982 if (op) {
2983 fp = op->opaque;
2984 assert(fp->ptr == field);
2985 fp->mask |= mask;
2986 } else {
2987 fp = g_new0(BitProperty, 1);
2988 fp->ptr = field;
2989 fp->mask = mask;
2990 object_property_add(OBJECT(cpu), prop_name, "bool",
2991 x86_cpu_get_bit_prop,
2992 x86_cpu_set_bit_prop,
2993 x86_cpu_release_bit_prop, fp, &error_abort);
2994 }
2995 }
2996
2997 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
2998 FeatureWord w,
2999 int bitnr)
3000 {
3001 Object *obj = OBJECT(cpu);
3002 int i;
3003 char **names;
3004 FeatureWordInfo *fi = &feature_word_info[w];
3005
3006 if (!fi->feat_names) {
3007 return;
3008 }
3009 if (!fi->feat_names[bitnr]) {
3010 return;
3011 }
3012
3013 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3014
3015 feat2prop(names[0]);
3016 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3017
3018 for (i = 1; names[i]; i++) {
3019 feat2prop(names[i]);
3020 object_property_add_alias(obj, names[i], obj, names[0],
3021 &error_abort);
3022 }
3023
3024 g_strfreev(names);
3025 }
3026
3027 static void x86_cpu_initfn(Object *obj)
3028 {
3029 CPUState *cs = CPU(obj);
3030 X86CPU *cpu = X86_CPU(obj);
3031 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
3032 CPUX86State *env = &cpu->env;
3033 FeatureWord w;
3034 static int inited;
3035
3036 cs->env_ptr = env;
3037 cpu_exec_init(cs, &error_abort);
3038
3039 object_property_add(obj, "family", "int",
3040 x86_cpuid_version_get_family,
3041 x86_cpuid_version_set_family, NULL, NULL, NULL);
3042 object_property_add(obj, "model", "int",
3043 x86_cpuid_version_get_model,
3044 x86_cpuid_version_set_model, NULL, NULL, NULL);
3045 object_property_add(obj, "stepping", "int",
3046 x86_cpuid_version_get_stepping,
3047 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
3048 object_property_add_str(obj, "vendor",
3049 x86_cpuid_get_vendor,
3050 x86_cpuid_set_vendor, NULL);
3051 object_property_add_str(obj, "model-id",
3052 x86_cpuid_get_model_id,
3053 x86_cpuid_set_model_id, NULL);
3054 object_property_add(obj, "tsc-frequency", "int",
3055 x86_cpuid_get_tsc_freq,
3056 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
3057 object_property_add(obj, "apic-id", "int",
3058 x86_cpuid_get_apic_id,
3059 x86_cpuid_set_apic_id, NULL, NULL, NULL);
3060 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3061 x86_cpu_get_feature_words,
3062 NULL, NULL, (void *)env->features, NULL);
3063 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3064 x86_cpu_get_feature_words,
3065 NULL, NULL, (void *)cpu->filtered_features, NULL);
3066
3067 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
3068
3069 #ifndef CONFIG_USER_ONLY
3070 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3071 cpu->apic_id = -1;
3072 #endif
3073
3074 for (w = 0; w < FEATURE_WORDS; w++) {
3075 int bitnr;
3076
3077 for (bitnr = 0; bitnr < 32; bitnr++) {
3078 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3079 }
3080 }
3081
3082 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3083
3084 /* init various static tables used in TCG mode */
3085 if (tcg_enabled() && !inited) {
3086 inited = 1;
3087 optimize_flags_init();
3088 }
3089 }
3090
3091 static int64_t x86_cpu_get_arch_id(CPUState *cs)
3092 {
3093 X86CPU *cpu = X86_CPU(cs);
3094
3095 return cpu->apic_id;
3096 }
3097
3098 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3099 {
3100 X86CPU *cpu = X86_CPU(cs);
3101
3102 return cpu->env.cr[0] & CR0_PG_MASK;
3103 }
3104
3105 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3106 {
3107 X86CPU *cpu = X86_CPU(cs);
3108
3109 cpu->env.eip = value;
3110 }
3111
3112 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3113 {
3114 X86CPU *cpu = X86_CPU(cs);
3115
3116 cpu->env.eip = tb->pc - tb->cs_base;
3117 }
3118
3119 static bool x86_cpu_has_work(CPUState *cs)
3120 {
3121 X86CPU *cpu = X86_CPU(cs);
3122 CPUX86State *env = &cpu->env;
3123
3124 #if !defined(CONFIG_USER_ONLY)
3125 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3126 apic_poll_irq(cpu->apic_state);
3127 cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
3128 }
3129 #endif
3130
3131 return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3132 (env->eflags & IF_MASK)) ||
3133 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3134 CPU_INTERRUPT_INIT |
3135 CPU_INTERRUPT_SIPI |
3136 CPU_INTERRUPT_MCE)) ||
3137 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3138 !(env->hflags & HF_SMM_MASK));
3139 }
3140
3141 static Property x86_cpu_properties[] = {
3142 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
3143 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
3144 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
3145 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
3146 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
3147 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
3148 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
3149 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
3150 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3151 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
3152 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
3153 DEFINE_PROP_END_OF_LIST()
3154 };
3155
3156 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3157 {
3158 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3159 CPUClass *cc = CPU_CLASS(oc);
3160 DeviceClass *dc = DEVICE_CLASS(oc);
3161
3162 xcc->parent_realize = dc->realize;
3163 dc->realize = x86_cpu_realizefn;
3164 dc->bus_type = TYPE_ICC_BUS;
3165 dc->props = x86_cpu_properties;
3166
3167 xcc->parent_reset = cc->reset;
3168 cc->reset = x86_cpu_reset;
3169 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
3170
3171 cc->class_by_name = x86_cpu_class_by_name;
3172 cc->parse_features = x86_cpu_parse_featurestr;
3173 cc->has_work = x86_cpu_has_work;
3174 cc->do_interrupt = x86_cpu_do_interrupt;
3175 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
3176 cc->dump_state = x86_cpu_dump_state;
3177 cc->set_pc = x86_cpu_set_pc;
3178 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
3179 cc->gdb_read_register = x86_cpu_gdb_read_register;
3180 cc->gdb_write_register = x86_cpu_gdb_write_register;
3181 cc->get_arch_id = x86_cpu_get_arch_id;
3182 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
3183 #ifdef CONFIG_USER_ONLY
3184 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3185 #else
3186 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
3187 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
3188 cc->write_elf64_note = x86_cpu_write_elf64_note;
3189 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3190 cc->write_elf32_note = x86_cpu_write_elf32_note;
3191 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
3192 cc->vmsd = &vmstate_x86_cpu;
3193 #endif
3194 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
3195 #ifndef CONFIG_USER_ONLY
3196 cc->debug_excp_handler = breakpoint_handler;
3197 #endif
3198 cc->cpu_exec_enter = x86_cpu_exec_enter;
3199 cc->cpu_exec_exit = x86_cpu_exec_exit;
3200 }
3201
3202 static const TypeInfo x86_cpu_type_info = {
3203 .name = TYPE_X86_CPU,
3204 .parent = TYPE_CPU,
3205 .instance_size = sizeof(X86CPU),
3206 .instance_init = x86_cpu_initfn,
3207 .abstract = true,
3208 .class_size = sizeof(X86CPUClass),
3209 .class_init = x86_cpu_common_class_init,
3210 };
3211
3212 static void x86_cpu_register_types(void)
3213 {
3214 int i;
3215
3216 type_register_static(&x86_cpu_type_info);
3217 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3218 x86_register_cpudef_type(&builtin_x86_defs[i]);
3219 }
3220 #ifdef CONFIG_KVM
3221 type_register_static(&host_x86_cpu_type_info);
3222 #endif
3223 }
3224
3225 type_init(x86_cpu_register_types)
AR7 emulation for QEMU