2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/isa/isa.h"
31 #include "hw/sysbus.h"
32 #include "qemu/range.h"
33 #include "hw/xen/xen.h"
34 #include "hw/pci-host/pam.h"
35 #include "sysemu/sysemu.h"
36 #include "hw/i386/ioapic.h"
37 #include "qapi/visitor.h"
38 #include "qemu/error-report.h"
41 * I440FX chipset data sheet.
42 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
45 #define I440FX_PCI_HOST_BRIDGE(obj) \
46 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
48 typedef struct I440FXState
{
49 PCIHostState parent_obj
;
51 uint64_t pci_hole64_size
;
52 uint32_t short_root_bus
;
55 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
56 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
57 #define XEN_PIIX_NUM_PIRQS 128ULL
58 #define PIIX_PIRQC 0x60
61 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
62 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
64 #define RCR_IOPORT 0xcf9
66 typedef struct PIIX3State
{
70 * bitmap to track pic levels.
71 * The pic level is the logical OR of all the PCI irqs mapped to it
72 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
74 * PIRQ is mapped to PIC pins, we track it by
75 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
76 * pic_irq * PIIX_NUM_PIRQS + pirq
78 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
79 #error "unable to encode pic state in 64bit in pic_levels."
85 /* This member isn't used. Just for save/load compatibility */
86 int32_t pci_irq_levels_vmstate
[PIIX_NUM_PIRQS
];
88 /* Reset Control Register contents */
91 /* IO memory region for Reset Control Register (RCR_IOPORT) */
95 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
96 #define PIIX3_PCI_DEVICE(obj) \
97 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
99 #define I440FX_PCI_DEVICE(obj) \
100 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
102 struct PCII440FXState
{
104 PCIDevice parent_obj
;
107 MemoryRegion
*system_memory
;
108 MemoryRegion
*pci_address_space
;
109 MemoryRegion
*ram_memory
;
110 PAMMemoryRegion pam_regions
[13];
111 MemoryRegion smram_region
;
112 MemoryRegion smram
, low_smram
;
116 #define I440FX_PAM 0x59
117 #define I440FX_PAM_SIZE 7
118 #define I440FX_SMRAM 0x72
120 /* Older coreboot versions (4.0 and older) read a config register that doesn't
121 * exist in real hardware, to get the RAM size from QEMU.
123 #define I440FX_COREBOOT_RAM_SIZE 0x57
125 static void piix3_set_irq(void *opaque
, int pirq
, int level
);
126 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pci_intx
);
127 static void piix3_write_config_xen(PCIDevice
*dev
,
128 uint32_t address
, uint32_t val
, int len
);
130 /* return the global irq number corresponding to a given device irq
131 pin. We could also use the bus number to have a more precise
133 static int pci_slot_get_pirq(PCIDevice
*pci_dev
, int pci_intx
)
136 slot_addend
= (pci_dev
->devfn
>> 3) - 1;
137 return (pci_intx
+ slot_addend
) & 3;
140 static void i440fx_update_memory_mappings(PCII440FXState
*d
)
143 PCIDevice
*pd
= PCI_DEVICE(d
);
145 memory_region_transaction_begin();
146 for (i
= 0; i
< 13; i
++) {
147 pam_update(&d
->pam_regions
[i
], i
,
148 pd
->config
[I440FX_PAM
+ ((i
+ 1) / 2)]);
150 memory_region_set_enabled(&d
->smram_region
,
151 !(pd
->config
[I440FX_SMRAM
] & SMRAM_D_OPEN
));
152 memory_region_set_enabled(&d
->smram
,
153 pd
->config
[I440FX_SMRAM
] & SMRAM_G_SMRAME
);
154 memory_region_transaction_commit();
158 static void i440fx_write_config(PCIDevice
*dev
,
159 uint32_t address
, uint32_t val
, int len
)
161 PCII440FXState
*d
= I440FX_PCI_DEVICE(dev
);
163 /* XXX: implement SMRAM.D_LOCK */
164 pci_default_write_config(dev
, address
, val
, len
);
165 if (ranges_overlap(address
, len
, I440FX_PAM
, I440FX_PAM_SIZE
) ||
166 range_covers_byte(address
, len
, I440FX_SMRAM
)) {
167 i440fx_update_memory_mappings(d
);
171 static int i440fx_load_old(QEMUFile
* f
, void *opaque
, int version_id
)
173 PCII440FXState
*d
= opaque
;
174 PCIDevice
*pd
= PCI_DEVICE(d
);
178 ret
= pci_device_load(pd
, f
);
181 i440fx_update_memory_mappings(d
);
182 qemu_get_8s(f
, &smm_enabled
);
184 if (version_id
== 2) {
185 for (i
= 0; i
< PIIX_NUM_PIRQS
; i
++) {
186 qemu_get_be32(f
); /* dummy load for compatibility */
193 static int i440fx_post_load(void *opaque
, int version_id
)
195 PCII440FXState
*d
= opaque
;
197 i440fx_update_memory_mappings(d
);
201 static const VMStateDescription vmstate_i440fx
= {
204 .minimum_version_id
= 3,
205 .minimum_version_id_old
= 1,
206 .load_state_old
= i440fx_load_old
,
207 .post_load
= i440fx_post_load
,
208 .fields
= (VMStateField
[]) {
209 VMSTATE_PCI_DEVICE(parent_obj
, PCII440FXState
),
210 /* Used to be smm_enabled, which was basically always zero because
211 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
214 VMSTATE_END_OF_LIST()
218 static void i440fx_pcihost_get_pci_hole_start(Object
*obj
, Visitor
*v
,
219 const char *name
, void *opaque
,
222 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
223 uint32_t value
= s
->pci_info
.w32
.begin
;
225 visit_type_uint32(v
, name
, &value
, errp
);
228 static void i440fx_pcihost_get_pci_hole_end(Object
*obj
, Visitor
*v
,
229 const char *name
, void *opaque
,
232 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
233 uint32_t value
= s
->pci_info
.w32
.end
;
235 visit_type_uint32(v
, name
, &value
, errp
);
238 static void i440fx_pcihost_get_pci_hole64_start(Object
*obj
, Visitor
*v
,
240 void *opaque
, Error
**errp
)
242 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
245 pci_bus_get_w64_range(h
->bus
, &w64
);
247 visit_type_uint64(v
, name
, &w64
.begin
, errp
);
250 static void i440fx_pcihost_get_pci_hole64_end(Object
*obj
, Visitor
*v
,
251 const char *name
, void *opaque
,
254 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
257 pci_bus_get_w64_range(h
->bus
, &w64
);
259 visit_type_uint64(v
, name
, &w64
.end
, errp
);
262 static void i440fx_pcihost_initfn(Object
*obj
)
264 PCIHostState
*s
= PCI_HOST_BRIDGE(obj
);
265 I440FXState
*d
= I440FX_PCI_HOST_BRIDGE(obj
);
267 memory_region_init_io(&s
->conf_mem
, obj
, &pci_host_conf_le_ops
, s
,
269 memory_region_init_io(&s
->data_mem
, obj
, &pci_host_data_le_ops
, s
,
272 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_START
, "int",
273 i440fx_pcihost_get_pci_hole_start
,
274 NULL
, NULL
, NULL
, NULL
);
276 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_END
, "int",
277 i440fx_pcihost_get_pci_hole_end
,
278 NULL
, NULL
, NULL
, NULL
);
280 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_START
, "int",
281 i440fx_pcihost_get_pci_hole64_start
,
282 NULL
, NULL
, NULL
, NULL
);
284 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_END
, "int",
285 i440fx_pcihost_get_pci_hole64_end
,
286 NULL
, NULL
, NULL
, NULL
);
288 d
->pci_info
.w32
.end
= IO_APIC_DEFAULT_ADDRESS
;
291 static void i440fx_pcihost_realize(DeviceState
*dev
, Error
**errp
)
293 PCIHostState
*s
= PCI_HOST_BRIDGE(dev
);
294 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
296 sysbus_add_io(sbd
, 0xcf8, &s
->conf_mem
);
297 sysbus_init_ioports(sbd
, 0xcf8, 4);
299 sysbus_add_io(sbd
, 0xcfc, &s
->data_mem
);
300 sysbus_init_ioports(sbd
, 0xcfc, 4);
303 static void i440fx_realize(PCIDevice
*dev
, Error
**errp
)
305 dev
->config
[I440FX_SMRAM
] = 0x02;
307 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL
)) {
308 error_report("warning: i440fx doesn't support emulated iommu");
312 PCIBus
*i440fx_init(const char *host_type
, const char *pci_type
,
313 PCII440FXState
**pi440fx_state
,
315 ISABus
**isa_bus
, qemu_irq
*pic
,
316 MemoryRegion
*address_space_mem
,
317 MemoryRegion
*address_space_io
,
319 ram_addr_t below_4g_mem_size
,
320 ram_addr_t above_4g_mem_size
,
321 MemoryRegion
*pci_address_space
,
322 MemoryRegion
*ram_memory
)
333 dev
= qdev_create(NULL
, host_type
);
334 s
= PCI_HOST_BRIDGE(dev
);
335 b
= pci_bus_new(dev
, NULL
, pci_address_space
,
336 address_space_io
, 0, TYPE_PCI_BUS
);
338 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev
), NULL
);
339 qdev_init_nofail(dev
);
341 d
= pci_create_simple(b
, 0, pci_type
);
342 *pi440fx_state
= I440FX_PCI_DEVICE(d
);
344 f
->system_memory
= address_space_mem
;
345 f
->pci_address_space
= pci_address_space
;
346 f
->ram_memory
= ram_memory
;
348 i440fx
= I440FX_PCI_HOST_BRIDGE(dev
);
349 i440fx
->pci_info
.w32
.begin
= below_4g_mem_size
;
351 /* setup pci memory mapping */
352 pc_pci_as_mapping_init(OBJECT(f
), f
->system_memory
,
353 f
->pci_address_space
);
355 /* if *disabled* show SMRAM to all CPUs */
356 memory_region_init_alias(&f
->smram_region
, OBJECT(d
), "smram-region",
357 f
->pci_address_space
, 0xa0000, 0x20000);
358 memory_region_add_subregion_overlap(f
->system_memory
, 0xa0000,
359 &f
->smram_region
, 1);
360 memory_region_set_enabled(&f
->smram_region
, true);
362 /* smram, as seen by SMM CPUs */
363 memory_region_init(&f
->smram
, OBJECT(d
), "smram", 1ull << 32);
364 memory_region_set_enabled(&f
->smram
, true);
365 memory_region_init_alias(&f
->low_smram
, OBJECT(d
), "smram-low",
366 f
->ram_memory
, 0xa0000, 0x20000);
367 memory_region_set_enabled(&f
->low_smram
, true);
368 memory_region_add_subregion(&f
->smram
, 0xa0000, &f
->low_smram
);
369 object_property_add_const_link(qdev_get_machine(), "smram",
370 OBJECT(&f
->smram
), &error_abort
);
372 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
373 &f
->pam_regions
[0], PAM_BIOS_BASE
, PAM_BIOS_SIZE
);
374 for (i
= 0; i
< 12; ++i
) {
375 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
376 &f
->pam_regions
[i
+1], PAM_EXPAN_BASE
+ i
* PAM_EXPAN_SIZE
,
380 /* Xen supports additional interrupt routes from the PCI devices to
381 * the IOAPIC: the four pins of each PCI device on the bus are also
382 * connected to the IOAPIC directly.
383 * These additional routes can be discovered through ACPI. */
385 PCIDevice
*pci_dev
= pci_create_simple_multifunction(b
,
386 -1, true, "PIIX3-xen");
387 piix3
= PIIX3_PCI_DEVICE(pci_dev
);
388 pci_bus_irqs(b
, xen_piix3_set_irq
, xen_pci_slot_get_pirq
,
389 piix3
, XEN_PIIX_NUM_PIRQS
);
391 PCIDevice
*pci_dev
= pci_create_simple_multifunction(b
,
393 piix3
= PIIX3_PCI_DEVICE(pci_dev
);
394 pci_bus_irqs(b
, piix3_set_irq
, pci_slot_get_pirq
, piix3
,
396 pci_bus_set_route_irq_fn(b
, piix3_route_intx_pin_to_irq
);
399 *isa_bus
= ISA_BUS(qdev_get_child_bus(DEVICE(piix3
), "isa.0"));
401 *piix3_devfn
= piix3
->dev
.devfn
;
403 ram_size
= ram_size
/ 8 / 1024 / 1024;
404 if (ram_size
> 255) {
407 d
->config
[I440FX_COREBOOT_RAM_SIZE
] = ram_size
;
409 i440fx_update_memory_mappings(f
);
414 PCIBus
*find_i440fx(void)
416 PCIHostState
*s
= OBJECT_CHECK(PCIHostState
,
417 object_resolve_path("/machine/i440fx", NULL
),
418 TYPE_PCI_HOST_BRIDGE
);
419 return s
? s
->bus
: NULL
;
422 /* PIIX3 PCI to ISA bridge */
423 static void piix3_set_irq_pic(PIIX3State
*piix3
, int pic_irq
)
425 qemu_set_irq(piix3
->pic
[pic_irq
],
426 !!(piix3
->pic_levels
&
427 (((1ULL << PIIX_NUM_PIRQS
) - 1) <<
428 (pic_irq
* PIIX_NUM_PIRQS
))));
431 static void piix3_set_irq_level_internal(PIIX3State
*piix3
, int pirq
, int level
)
436 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
437 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
441 mask
= 1ULL << ((pic_irq
* PIIX_NUM_PIRQS
) + pirq
);
442 piix3
->pic_levels
&= ~mask
;
443 piix3
->pic_levels
|= mask
* !!level
;
446 static void piix3_set_irq_level(PIIX3State
*piix3
, int pirq
, int level
)
450 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
451 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
455 piix3_set_irq_level_internal(piix3
, pirq
, level
);
457 piix3_set_irq_pic(piix3
, pic_irq
);
460 static void piix3_set_irq(void *opaque
, int pirq
, int level
)
462 PIIX3State
*piix3
= opaque
;
463 piix3_set_irq_level(piix3
, pirq
, level
);
466 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pin
)
468 PIIX3State
*piix3
= opaque
;
469 int irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pin
];
472 if (irq
< PIIX_NUM_PIC_IRQS
) {
473 route
.mode
= PCI_INTX_ENABLED
;
476 route
.mode
= PCI_INTX_DISABLED
;
482 /* irq routing is changed. so rebuild bitmap */
483 static void piix3_update_irq_levels(PIIX3State
*piix3
)
487 piix3
->pic_levels
= 0;
488 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
489 piix3_set_irq_level(piix3
, pirq
,
490 pci_bus_get_irq_level(piix3
->dev
.bus
, pirq
));
494 static void piix3_write_config(PCIDevice
*dev
,
495 uint32_t address
, uint32_t val
, int len
)
497 pci_default_write_config(dev
, address
, val
, len
);
498 if (ranges_overlap(address
, len
, PIIX_PIRQC
, 4)) {
499 PIIX3State
*piix3
= PIIX3_PCI_DEVICE(dev
);
502 pci_bus_fire_intx_routing_notifier(piix3
->dev
.bus
);
503 piix3_update_irq_levels(piix3
);
504 for (pic_irq
= 0; pic_irq
< PIIX_NUM_PIC_IRQS
; pic_irq
++) {
505 piix3_set_irq_pic(piix3
, pic_irq
);
510 static void piix3_write_config_xen(PCIDevice
*dev
,
511 uint32_t address
, uint32_t val
, int len
)
513 xen_piix_pci_write_config_client(address
, val
, len
);
514 piix3_write_config(dev
, address
, val
, len
);
517 static void piix3_reset(void *opaque
)
519 PIIX3State
*d
= opaque
;
520 uint8_t *pci_conf
= d
->dev
.config
;
522 pci_conf
[0x04] = 0x07; /* master, memory and I/O */
523 pci_conf
[0x05] = 0x00;
524 pci_conf
[0x06] = 0x00;
525 pci_conf
[0x07] = 0x02; /* PCI_status_devsel_medium */
526 pci_conf
[0x4c] = 0x4d;
527 pci_conf
[0x4e] = 0x03;
528 pci_conf
[0x4f] = 0x00;
529 pci_conf
[0x60] = 0x80;
530 pci_conf
[0x61] = 0x80;
531 pci_conf
[0x62] = 0x80;
532 pci_conf
[0x63] = 0x80;
533 pci_conf
[0x69] = 0x02;
534 pci_conf
[0x70] = 0x80;
535 pci_conf
[0x76] = 0x0c;
536 pci_conf
[0x77] = 0x0c;
537 pci_conf
[0x78] = 0x02;
538 pci_conf
[0x79] = 0x00;
539 pci_conf
[0x80] = 0x00;
540 pci_conf
[0x82] = 0x00;
541 pci_conf
[0xa0] = 0x08;
542 pci_conf
[0xa2] = 0x00;
543 pci_conf
[0xa3] = 0x00;
544 pci_conf
[0xa4] = 0x00;
545 pci_conf
[0xa5] = 0x00;
546 pci_conf
[0xa6] = 0x00;
547 pci_conf
[0xa7] = 0x00;
548 pci_conf
[0xa8] = 0x0f;
549 pci_conf
[0xaa] = 0x00;
550 pci_conf
[0xab] = 0x00;
551 pci_conf
[0xac] = 0x00;
552 pci_conf
[0xae] = 0x00;
558 static int piix3_post_load(void *opaque
, int version_id
)
560 PIIX3State
*piix3
= opaque
;
563 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
564 * might bring the system to a different state than the saved one;
565 * for example, the interrupt could be masked but the i8259 would
566 * not know that yet and would trigger an interrupt in the CPU.
568 * Here, we update irq levels without raising the interrupt.
569 * Interrupt state will be deserialized separately through the i8259.
571 piix3
->pic_levels
= 0;
572 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
573 piix3_set_irq_level_internal(piix3
, pirq
,
574 pci_bus_get_irq_level(piix3
->dev
.bus
, pirq
));
579 static void piix3_pre_save(void *opaque
)
582 PIIX3State
*piix3
= opaque
;
584 for (i
= 0; i
< ARRAY_SIZE(piix3
->pci_irq_levels_vmstate
); i
++) {
585 piix3
->pci_irq_levels_vmstate
[i
] =
586 pci_bus_get_irq_level(piix3
->dev
.bus
, i
);
590 static bool piix3_rcr_needed(void *opaque
)
592 PIIX3State
*piix3
= opaque
;
594 return (piix3
->rcr
!= 0);
597 static const VMStateDescription vmstate_piix3_rcr
= {
600 .minimum_version_id
= 1,
601 .needed
= piix3_rcr_needed
,
602 .fields
= (VMStateField
[]) {
603 VMSTATE_UINT8(rcr
, PIIX3State
),
604 VMSTATE_END_OF_LIST()
608 static const VMStateDescription vmstate_piix3
= {
611 .minimum_version_id
= 2,
612 .post_load
= piix3_post_load
,
613 .pre_save
= piix3_pre_save
,
614 .fields
= (VMStateField
[]) {
615 VMSTATE_PCI_DEVICE(dev
, PIIX3State
),
616 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate
, PIIX3State
,
618 VMSTATE_END_OF_LIST()
620 .subsections
= (const VMStateDescription
*[]) {
627 static void rcr_write(void *opaque
, hwaddr addr
, uint64_t val
, unsigned len
)
629 PIIX3State
*d
= opaque
;
632 qemu_system_reset_request();
635 d
->rcr
= val
& 2; /* keep System Reset type only */
638 static uint64_t rcr_read(void *opaque
, hwaddr addr
, unsigned len
)
640 PIIX3State
*d
= opaque
;
645 static const MemoryRegionOps rcr_ops
= {
648 .endianness
= DEVICE_LITTLE_ENDIAN
651 static void piix3_realize(PCIDevice
*dev
, Error
**errp
)
653 PIIX3State
*d
= PIIX3_PCI_DEVICE(dev
);
655 if (!isa_bus_new(DEVICE(d
), get_system_memory(),
656 pci_address_space_io(dev
), errp
)) {
660 memory_region_init_io(&d
->rcr_mem
, OBJECT(dev
), &rcr_ops
, d
,
661 "piix3-reset-control", 1);
662 memory_region_add_subregion_overlap(pci_address_space_io(dev
), RCR_IOPORT
,
665 qemu_register_reset(piix3_reset
, d
);
668 static void pci_piix3_class_init(ObjectClass
*klass
, void *data
)
670 DeviceClass
*dc
= DEVICE_CLASS(klass
);
671 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
673 dc
->desc
= "ISA bridge";
674 dc
->vmsd
= &vmstate_piix3
;
675 dc
->hotpluggable
= false;
676 k
->realize
= piix3_realize
;
677 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
678 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
679 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_0
;
680 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
682 * Reason: part of PIIX3 southbridge, needs to be wired up by
683 * pc_piix.c's pc_init1()
685 dc
->cannot_instantiate_with_device_add_yet
= true;
688 static const TypeInfo piix3_pci_type_info
= {
689 .name
= TYPE_PIIX3_PCI_DEVICE
,
690 .parent
= TYPE_PCI_DEVICE
,
691 .instance_size
= sizeof(PIIX3State
),
693 .class_init
= pci_piix3_class_init
,
696 static void piix3_class_init(ObjectClass
*klass
, void *data
)
698 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
700 k
->config_write
= piix3_write_config
;
703 static const TypeInfo piix3_info
= {
705 .parent
= TYPE_PIIX3_PCI_DEVICE
,
706 .class_init
= piix3_class_init
,
709 static void piix3_xen_class_init(ObjectClass
*klass
, void *data
)
711 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
713 k
->config_write
= piix3_write_config_xen
;
716 static const TypeInfo piix3_xen_info
= {
718 .parent
= TYPE_PIIX3_PCI_DEVICE
,
719 .class_init
= piix3_xen_class_init
,
722 static void i440fx_class_init(ObjectClass
*klass
, void *data
)
724 DeviceClass
*dc
= DEVICE_CLASS(klass
);
725 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
727 k
->realize
= i440fx_realize
;
728 k
->config_write
= i440fx_write_config
;
729 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
730 k
->device_id
= PCI_DEVICE_ID_INTEL_82441
;
732 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
733 dc
->desc
= "Host bridge";
734 dc
->vmsd
= &vmstate_i440fx
;
736 * PCI-facing part of the host bridge, not usable without the
737 * host-facing part, which can't be device_add'ed, yet.
739 dc
->cannot_instantiate_with_device_add_yet
= true;
740 dc
->hotpluggable
= false;
743 static const TypeInfo i440fx_info
= {
744 .name
= TYPE_I440FX_PCI_DEVICE
,
745 .parent
= TYPE_PCI_DEVICE
,
746 .instance_size
= sizeof(PCII440FXState
),
747 .class_init
= i440fx_class_init
,
750 /* IGD Passthrough Host Bridge. */
756 /* Here we just expose minimal host bridge offset subset. */
757 static const IGDHostInfo igd_host_bridge_infos
[] = {
758 {0x08, 2}, /* revision id */
759 {0x2c, 2}, /* sybsystem vendor id */
760 {0x2e, 2}, /* sybsystem id */
761 {0x50, 2}, /* SNB: processor graphics control register */
762 {0x52, 2}, /* processor graphics control register */
763 {0xa4, 4}, /* SNB: graphics base of stolen memory */
764 {0xa8, 4}, /* SNB: base of GTT stolen memory */
767 static int host_pci_config_read(int pos
, int len
, uint32_t *val
)
771 ssize_t size
= sizeof(path
);
772 /* Access real host bridge. */
773 int rc
= snprintf(path
, size
, "/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
774 0, 0, 0, 0, "config");
777 if (rc
>= size
|| rc
< 0) {
781 config_fd
= open(path
, O_RDWR
);
786 if (lseek(config_fd
, pos
, SEEK_SET
) != pos
) {
792 rc
= read(config_fd
, (uint8_t *)val
, len
);
793 } while (rc
< 0 && (errno
== EINTR
|| errno
== EAGAIN
));
803 static int igd_pt_i440fx_initfn(struct PCIDevice
*pci_dev
)
809 num
= ARRAY_SIZE(igd_host_bridge_infos
);
810 for (i
= 0; i
< num
; i
++) {
811 pos
= igd_host_bridge_infos
[i
].offset
;
812 len
= igd_host_bridge_infos
[i
].len
;
813 rc
= host_pci_config_read(pos
, len
, &val
);
817 pci_default_write_config(pci_dev
, pos
, val
, len
);
823 static void igd_passthrough_i440fx_class_init(ObjectClass
*klass
, void *data
)
825 DeviceClass
*dc
= DEVICE_CLASS(klass
);
826 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
828 k
->init
= igd_pt_i440fx_initfn
;
829 dc
->desc
= "IGD Passthrough Host bridge";
832 static const TypeInfo igd_passthrough_i440fx_info
= {
833 .name
= TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
,
834 .parent
= TYPE_I440FX_PCI_DEVICE
,
835 .instance_size
= sizeof(PCII440FXState
),
836 .class_init
= igd_passthrough_i440fx_class_init
,
839 static const char *i440fx_pcihost_root_bus_path(PCIHostState
*host_bridge
,
842 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(host_bridge
);
844 /* For backwards compat with old device paths */
845 if (s
->short_root_bus
) {
851 static Property i440fx_props
[] = {
852 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE
, I440FXState
,
853 pci_hole64_size
, DEFAULT_PCI_HOLE64_SIZE
),
854 DEFINE_PROP_UINT32("short_root_bus", I440FXState
, short_root_bus
, 0),
855 DEFINE_PROP_END_OF_LIST(),
858 static void i440fx_pcihost_class_init(ObjectClass
*klass
, void *data
)
860 DeviceClass
*dc
= DEVICE_CLASS(klass
);
861 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
863 hc
->root_bus_path
= i440fx_pcihost_root_bus_path
;
864 dc
->realize
= i440fx_pcihost_realize
;
866 dc
->props
= i440fx_props
;
869 static const TypeInfo i440fx_pcihost_info
= {
870 .name
= TYPE_I440FX_PCI_HOST_BRIDGE
,
871 .parent
= TYPE_PCI_HOST_BRIDGE
,
872 .instance_size
= sizeof(I440FXState
),
873 .instance_init
= i440fx_pcihost_initfn
,
874 .class_init
= i440fx_pcihost_class_init
,
877 static void i440fx_register_types(void)
879 type_register_static(&i440fx_info
);
880 type_register_static(&igd_passthrough_i440fx_info
);
881 type_register_static(&piix3_pci_type_info
);
882 type_register_static(&piix3_info
);
883 type_register_static(&piix3_xen_info
);
884 type_register_static(&i440fx_pcihost_info
);
887 type_init(i440fx_register_types
)