dma: Add Xilinx Zynq devcfg device model
[qemu/ar7.git] / include / hw / dma / xlnx-zynq-devcfg.h
blobd40e5c8df6b902e50b7456c7bcdebb3ce806fe81
1 /*
2 * QEMU model of the Xilinx Devcfg Interface
4 * (C) 2011 PetaLogix Pty Ltd
5 * (C) 2014 Xilinx Inc.
6 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
27 #ifndef XLNX_ZYNQ_DEVCFG_H
29 #include "hw/register.h"
30 #include "hw/sysbus.h"
32 #define TYPE_XLNX_ZYNQ_DEVCFG "xlnx.ps7-dev-cfg"
34 #define XLNX_ZYNQ_DEVCFG(obj) \
35 OBJECT_CHECK(XlnxZynqDevcfg, (obj), TYPE_XLNX_ZYNQ_DEVCFG)
37 #define XLNX_ZYNQ_DEVCFG_R_MAX 0x118
39 #define XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN 10
41 typedef struct XlnxZynqDevcfgDMACmd {
42 uint32_t src_addr;
43 uint32_t dest_addr;
44 uint32_t src_len;
45 uint32_t dest_len;
46 } XlnxZynqDevcfgDMACmd;
48 typedef struct XlnxZynqDevcfg {
49 SysBusDevice parent_obj;
51 MemoryRegion iomem;
52 qemu_irq irq;
54 XlnxZynqDevcfgDMACmd dma_cmd_fifo[XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN];
55 uint8_t dma_cmd_fifo_num;
57 uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX];
58 RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX];
59 } XlnxZynqDevcfg;
61 #define XLNX_ZYNQ_DEVCFG_H
62 #endif