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migration: pause-before-switchover for postcopy
[qemu/ar7.git] / hw / block / nand.c
blob76dcd3f76ed584fa16021c40678a92b9afa4f795
1 /*
2 * Flash NAND memory emulation. Based on "16M x 8 Bit NAND Flash
3 * Memory" datasheet for the KM29U128AT / K9F2808U0A chips from
4 * Samsung Electronic.
5 *
6 * Copyright (c) 2006 Openedhand Ltd.
7 * Written by Andrzej Zaborowski <balrog@zabor.org>
8 *
9 * Support for additional features based on "MT29F2G16ABCWP 2Gx16"
10 * datasheet from Micron Technology and "NAND02G-B2C" datasheet
11 * from ST Microelectronics.
12 *
13 * This code is licensed under the GNU GPL v2.
14 *
15 * Contributions after 2012-01-13 are licensed under the terms of the
16 * GNU GPL, version 2 or (at your option) any later version.
17 */
18
19 #ifndef NAND_IO
20
21 #include "qemu/osdep.h"
22 #include "hw/hw.h"
23 #include "hw/block/flash.h"
24 #include "sysemu/block-backend.h"
25 #include "hw/qdev.h"
26 #include "qapi/error.h"
27 #include "qemu/error-report.h"
28
29 # define NAND_CMD_READ0 0x00
30 # define NAND_CMD_READ1 0x01
31 # define NAND_CMD_READ2 0x50
32 # define NAND_CMD_LPREAD2 0x30
33 # define NAND_CMD_NOSERIALREAD2 0x35
34 # define NAND_CMD_RANDOMREAD1 0x05
35 # define NAND_CMD_RANDOMREAD2 0xe0
36 # define NAND_CMD_READID 0x90
37 # define NAND_CMD_RESET 0xff
38 # define NAND_CMD_PAGEPROGRAM1 0x80
39 # define NAND_CMD_PAGEPROGRAM2 0x10
40 # define NAND_CMD_CACHEPROGRAM2 0x15
41 # define NAND_CMD_BLOCKERASE1 0x60
42 # define NAND_CMD_BLOCKERASE2 0xd0
43 # define NAND_CMD_READSTATUS 0x70
44 # define NAND_CMD_COPYBACKPRG1 0x85
45
46 # define NAND_IOSTATUS_ERROR (1 << 0)
47 # define NAND_IOSTATUS_PLANE0 (1 << 1)
48 # define NAND_IOSTATUS_PLANE1 (1 << 2)
49 # define NAND_IOSTATUS_PLANE2 (1 << 3)
50 # define NAND_IOSTATUS_PLANE3 (1 << 4)
51 # define NAND_IOSTATUS_READY (1 << 6)
52 # define NAND_IOSTATUS_UNPROTCT (1 << 7)
53
54 # define MAX_PAGE 0x800
55 # define MAX_OOB 0x40
56
57 typedef struct NANDFlashState NANDFlashState;
58 struct NANDFlashState {
59 DeviceState parent_obj;
60
61 uint8_t manf_id, chip_id;
62 uint8_t buswidth; /* in BYTES */
63 int size, pages;
64 int page_shift, oob_shift, erase_shift, addr_shift;
65 uint8_t *storage;
66 BlockBackend *blk;
67 int mem_oob;
68
69 uint8_t cle, ale, ce, wp, gnd;
70
71 uint8_t io[MAX_PAGE + MAX_OOB + 0x400];
72 uint8_t *ioaddr;
73 int iolen;
74
75 uint32_t cmd;
76 uint64_t addr;
77 int addrlen;
78 int status;
79 int offset;
80
81 void (*blk_write)(NANDFlashState *s);
82 void (*blk_erase)(NANDFlashState *s);
83 void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset);
84
85 uint32_t ioaddr_vmstate;
86 };
87
88 #define TYPE_NAND "nand"
89
90 #define NAND(obj) \
91 OBJECT_CHECK(NANDFlashState, (obj), TYPE_NAND)
92
93 static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
94 {
95 /* Like memcpy() but we logical-AND the data into the destination */
96 int i;
97 for (i = 0; i < n; i++) {
98 dest[i] &= src[i];
99 }
100 }
101
102 # define NAND_NO_AUTOINCR 0x00000001
103 # define NAND_BUSWIDTH_16 0x00000002
104 # define NAND_NO_PADDING 0x00000004
105 # define NAND_CACHEPRG 0x00000008
106 # define NAND_COPYBACK 0x00000010
107 # define NAND_IS_AND 0x00000020
108 # define NAND_4PAGE_ARRAY 0x00000040
109 # define NAND_NO_READRDY 0x00000100
110 # define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK)
111
112 # define NAND_IO
113
114 # define PAGE(addr) ((addr) >> ADDR_SHIFT)
115 # define PAGE_START(page) (PAGE(page) * (PAGE_SIZE + OOB_SIZE))
116 # define PAGE_MASK ((1 << ADDR_SHIFT) - 1)
117 # define OOB_SHIFT (PAGE_SHIFT - 5)
118 # define OOB_SIZE (1 << OOB_SHIFT)
119 # define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
120 # define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8))
121
122 # define PAGE_SIZE 256
123 # define PAGE_SHIFT 8
124 # define PAGE_SECTORS 1
125 # define ADDR_SHIFT 8
126 # include "nand.c"
127 # define PAGE_SIZE 512
128 # define PAGE_SHIFT 9
129 # define PAGE_SECTORS 1
130 # define ADDR_SHIFT 8
131 # include "nand.c"
132 # define PAGE_SIZE 2048
133 # define PAGE_SHIFT 11
134 # define PAGE_SECTORS 4
135 # define ADDR_SHIFT 16
136 # include "nand.c"
137
138 /* Information based on Linux drivers/mtd/nand/nand_ids.c */
139 static const struct {
140 int size;
141 int width;
142 int page_shift;
143 int erase_shift;
144 uint32_t options;
145 } nand_flash_ids[0x100] = {
146 [0 ... 0xff] = { 0 },
147
148 [0x6e] = { 1, 8, 8, 4, 0 },
149 [0x64] = { 2, 8, 8, 4, 0 },
150 [0x6b] = { 4, 8, 9, 4, 0 },
151 [0xe8] = { 1, 8, 8, 4, 0 },
152 [0xec] = { 1, 8, 8, 4, 0 },
153 [0xea] = { 2, 8, 8, 4, 0 },
154 [0xd5] = { 4, 8, 9, 4, 0 },
155 [0xe3] = { 4, 8, 9, 4, 0 },
156 [0xe5] = { 4, 8, 9, 4, 0 },
157 [0xd6] = { 8, 8, 9, 4, 0 },
158
159 [0x39] = { 8, 8, 9, 4, 0 },
160 [0xe6] = { 8, 8, 9, 4, 0 },
161 [0x49] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
162 [0x59] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
163
164 [0x33] = { 16, 8, 9, 5, 0 },
165 [0x73] = { 16, 8, 9, 5, 0 },
166 [0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
167 [0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
168
169 [0x35] = { 32, 8, 9, 5, 0 },
170 [0x75] = { 32, 8, 9, 5, 0 },
171 [0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
172 [0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
173
174 [0x36] = { 64, 8, 9, 5, 0 },
175 [0x76] = { 64, 8, 9, 5, 0 },
176 [0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
177 [0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
178
179 [0x78] = { 128, 8, 9, 5, 0 },
180 [0x39] = { 128, 8, 9, 5, 0 },
181 [0x79] = { 128, 8, 9, 5, 0 },
182 [0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
183 [0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
184 [0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
185 [0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
186
187 [0x71] = { 256, 8, 9, 5, 0 },
188
189 /*
190 * These are the new chips with large page size. The pagesize and the
191 * erasesize is determined from the extended id bytes
192 */
193 # define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
194 # define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
195
196 /* 512 Megabit */
197 [0xa2] = { 64, 8, 0, 0, LP_OPTIONS },
198 [0xf2] = { 64, 8, 0, 0, LP_OPTIONS },
199 [0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 },
200 [0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 },
201
202 /* 1 Gigabit */
203 [0xa1] = { 128, 8, 0, 0, LP_OPTIONS },
204 [0xf1] = { 128, 8, 0, 0, LP_OPTIONS },
205 [0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 },
206 [0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 },
207
208 /* 2 Gigabit */
209 [0xaa] = { 256, 8, 0, 0, LP_OPTIONS },
210 [0xda] = { 256, 8, 0, 0, LP_OPTIONS },
211 [0xba] = { 256, 16, 0, 0, LP_OPTIONS16 },
212 [0xca] = { 256, 16, 0, 0, LP_OPTIONS16 },
213
214 /* 4 Gigabit */
215 [0xac] = { 512, 8, 0, 0, LP_OPTIONS },
216 [0xdc] = { 512, 8, 0, 0, LP_OPTIONS },
217 [0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 },
218 [0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 },
219
220 /* 8 Gigabit */
221 [0xa3] = { 1024, 8, 0, 0, LP_OPTIONS },
222 [0xd3] = { 1024, 8, 0, 0, LP_OPTIONS },
223 [0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
224 [0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
225
226 /* 16 Gigabit */
227 [0xa5] = { 2048, 8, 0, 0, LP_OPTIONS },
228 [0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
229 [0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
230 [0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
231 };
232
233 static void nand_reset(DeviceState *dev)
234 {
235 NANDFlashState *s = NAND(dev);
236 s->cmd = NAND_CMD_READ0;
237 s->addr = 0;
238 s->addrlen = 0;
239 s->iolen = 0;
240 s->offset = 0;
241 s->status &= NAND_IOSTATUS_UNPROTCT;
242 s->status |= NAND_IOSTATUS_READY;
243 }
244
245 static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)
246 {
247 s->ioaddr[s->iolen++] = value;
248 for (value = s->buswidth; --value;) {
249 s->ioaddr[s->iolen++] = 0;
250 }
251 }
252
253 static void nand_command(NANDFlashState *s)
254 {
255 unsigned int offset;
256 switch (s->cmd) {
257 case NAND_CMD_READ0:
258 s->iolen = 0;
259 break;
260
261 case NAND_CMD_READID:
262 s->ioaddr = s->io;
263 s->iolen = 0;
264 nand_pushio_byte(s, s->manf_id);
265 nand_pushio_byte(s, s->chip_id);
266 nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */
267 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
268 /* Page Size, Block Size, Spare Size; bit 6 indicates
269 * 8 vs 16 bit width NAND.
270 */
271 nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15);
272 } else {
273 nand_pushio_byte(s, 0xc0); /* Multi-plane */
274 }
275 break;
276
277 case NAND_CMD_RANDOMREAD2:
278 case NAND_CMD_NOSERIALREAD2:
279 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP))
280 break;
281 offset = s->addr & ((1 << s->addr_shift) - 1);
282 s->blk_load(s, s->addr, offset);
283 if (s->gnd)
284 s->iolen = (1 << s->page_shift) - offset;
285 else
286 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
287 break;
288
289 case NAND_CMD_RESET:
290 nand_reset(DEVICE(s));
291 break;
292
293 case NAND_CMD_PAGEPROGRAM1:
294 s->ioaddr = s->io;
295 s->iolen = 0;
296 break;
297
298 case NAND_CMD_PAGEPROGRAM2:
299 if (s->wp) {
300 s->blk_write(s);
301 }
302 break;
303
304 case NAND_CMD_BLOCKERASE1:
305 break;
306
307 case NAND_CMD_BLOCKERASE2:
308 s->addr &= (1ull << s->addrlen * 8) - 1;
309 s->addr <<= nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP ?
310 16 : 8;
311
312 if (s->wp) {
313 s->blk_erase(s);
314 }
315 break;
316
317 case NAND_CMD_READSTATUS:
318 s->ioaddr = s->io;
319 s->iolen = 0;
320 nand_pushio_byte(s, s->status);
321 break;
322
323 default:
324 printf("%s: Unknown NAND command 0x%02x\n", __FUNCTION__, s->cmd);
325 }
326 }
327
328 static int nand_pre_save(void *opaque)
329 {
330 NANDFlashState *s = NAND(opaque);
331
332 s->ioaddr_vmstate = s->ioaddr - s->io;
333
334 return 0;
335 }
336
337 static int nand_post_load(void *opaque, int version_id)
338 {
339 NANDFlashState *s = NAND(opaque);
340
341 if (s->ioaddr_vmstate > sizeof(s->io)) {
342 return -EINVAL;
343 }
344 s->ioaddr = s->io + s->ioaddr_vmstate;
345
346 return 0;
347 }
348
349 static const VMStateDescription vmstate_nand = {
350 .name = "nand",
351 .version_id = 1,
352 .minimum_version_id = 1,
353 .pre_save = nand_pre_save,
354 .post_load = nand_post_load,
355 .fields = (VMStateField[]) {
356 VMSTATE_UINT8(cle, NANDFlashState),
357 VMSTATE_UINT8(ale, NANDFlashState),
358 VMSTATE_UINT8(ce, NANDFlashState),
359 VMSTATE_UINT8(wp, NANDFlashState),
360 VMSTATE_UINT8(gnd, NANDFlashState),
361 VMSTATE_BUFFER(io, NANDFlashState),
362 VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState),
363 VMSTATE_INT32(iolen, NANDFlashState),
364 VMSTATE_UINT32(cmd, NANDFlashState),
365 VMSTATE_UINT64(addr, NANDFlashState),
366 VMSTATE_INT32(addrlen, NANDFlashState),
367 VMSTATE_INT32(status, NANDFlashState),
368 VMSTATE_INT32(offset, NANDFlashState),
369 /* XXX: do we want to save s->storage too? */
370 VMSTATE_END_OF_LIST()
371 }
372 };
373
374 static void nand_realize(DeviceState *dev, Error **errp)
375 {
376 int pagesize;
377 NANDFlashState *s = NAND(dev);
378 int ret;
379
380
381 s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
382 s->size = nand_flash_ids[s->chip_id].size << 20;
383 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
384 s->page_shift = 11;
385 s->erase_shift = 6;
386 } else {
387 s->page_shift = nand_flash_ids[s->chip_id].page_shift;
388 s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
389 }
390
391 switch (1 << s->page_shift) {
392 case 256:
393 nand_init_256(s);
394 break;
395 case 512:
396 nand_init_512(s);
397 break;
398 case 2048:
399 nand_init_2048(s);
400 break;
401 default:
402 error_setg(errp, "Unsupported NAND block size %#x",
403 1 << s->page_shift);
404 return;
405 }
406
407 pagesize = 1 << s->oob_shift;
408 s->mem_oob = 1;
409 if (s->blk) {
410 if (blk_is_read_only(s->blk)) {
411 error_setg(errp, "Can't use a read-only drive");
412 return;
413 }
414 ret = blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
415 BLK_PERM_ALL, errp);
416 if (ret < 0) {
417 return;
418 }
419 if (blk_getlength(s->blk) >=
420 (s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
421 pagesize = 0;
422 s->mem_oob = 0;
423 }
424 } else {
425 pagesize += 1 << s->page_shift;
426 }
427 if (pagesize) {
428 s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize),
429 0xff, s->pages * pagesize);
430 }
431 /* Give s->ioaddr a sane value in case we save state before it is used. */
432 s->ioaddr = s->io;
433 }
434
435 static Property nand_properties[] = {
436 DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0),
437 DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0),
438 DEFINE_PROP_DRIVE("drive", NANDFlashState, blk),
439 DEFINE_PROP_END_OF_LIST(),
440 };
441
442 static void nand_class_init(ObjectClass *klass, void *data)
443 {
444 DeviceClass *dc = DEVICE_CLASS(klass);
445
446 dc->realize = nand_realize;
447 dc->reset = nand_reset;
448 dc->vmsd = &vmstate_nand;
449 dc->props = nand_properties;
450 }
451
452 static const TypeInfo nand_info = {
453 .name = TYPE_NAND,
454 .parent = TYPE_DEVICE,
455 .instance_size = sizeof(NANDFlashState),
456 .class_init = nand_class_init,
457 };
458
459 static void nand_register_types(void)
460 {
461 type_register_static(&nand_info);
462 }
463
464 /*
465 * Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins. Chip
466 * outputs are R/B and eight I/O pins.
467 *
468 * CE, WP and R/B are active low.
469 */
470 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
471 uint8_t ce, uint8_t wp, uint8_t gnd)
472 {
473 NANDFlashState *s = NAND(dev);
474
475 s->cle = cle;
476 s->ale = ale;
477 s->ce = ce;
478 s->wp = wp;
479 s->gnd = gnd;
480 if (wp) {
481 s->status |= NAND_IOSTATUS_UNPROTCT;
482 } else {
483 s->status &= ~NAND_IOSTATUS_UNPROTCT;
484 }
485 }
486
487 void nand_getpins(DeviceState *dev, int *rb)
488 {
489 *rb = 1;
490 }
491
492 void nand_setio(DeviceState *dev, uint32_t value)
493 {
494 int i;
495 NANDFlashState *s = NAND(dev);
496
497 if (!s->ce && s->cle) {
498 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
499 if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
500 return;
501 if (value == NAND_CMD_RANDOMREAD1) {
502 s->addr &= ~((1 << s->addr_shift) - 1);
503 s->addrlen = 0;
504 return;
505 }
506 }
507 if (value == NAND_CMD_READ0) {
508 s->offset = 0;
509 } else if (value == NAND_CMD_READ1) {
510 s->offset = 0x100;
511 value = NAND_CMD_READ0;
512 } else if (value == NAND_CMD_READ2) {
513 s->offset = 1 << s->page_shift;
514 value = NAND_CMD_READ0;
515 }
516
517 s->cmd = value;
518
519 if (s->cmd == NAND_CMD_READSTATUS ||
520 s->cmd == NAND_CMD_PAGEPROGRAM2 ||
521 s->cmd == NAND_CMD_BLOCKERASE1 ||
522 s->cmd == NAND_CMD_BLOCKERASE2 ||
523 s->cmd == NAND_CMD_NOSERIALREAD2 ||
524 s->cmd == NAND_CMD_RANDOMREAD2 ||
525 s->cmd == NAND_CMD_RESET) {
526 nand_command(s);
527 }
528
529 if (s->cmd != NAND_CMD_RANDOMREAD2) {
530 s->addrlen = 0;
531 }
532 }
533
534 if (s->ale) {
535 unsigned int shift = s->addrlen * 8;
536 uint64_t mask = ~(0xffull << shift);
537 uint64_t v = (uint64_t)value << shift;
538
539 s->addr = (s->addr & mask) | v;
540 s->addrlen ++;
541
542 switch (s->addrlen) {
543 case 1:
544 if (s->cmd == NAND_CMD_READID) {
545 nand_command(s);
546 }
547 break;
548 case 2: /* fix cache address as a byte address */
549 s->addr <<= (s->buswidth - 1);
550 break;
551 case 3:
552 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
553 (s->cmd == NAND_CMD_READ0 ||
554 s->cmd == NAND_CMD_PAGEPROGRAM1)) {
555 nand_command(s);
556 }
557 break;
558 case 4:
559 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
560 nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */
561 (s->cmd == NAND_CMD_READ0 ||
562 s->cmd == NAND_CMD_PAGEPROGRAM1)) {
563 nand_command(s);
564 }
565 break;
566 case 5:
567 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
568 nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */
569 (s->cmd == NAND_CMD_READ0 ||
570 s->cmd == NAND_CMD_PAGEPROGRAM1)) {
571 nand_command(s);
572 }
573 break;
574 default:
575 break;
576 }
577 }
578
579 if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
580 if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) {
581 for (i = s->buswidth; i--; value >>= 8) {
582 s->io[s->iolen ++] = (uint8_t) (value & 0xff);
583 }
584 }
585 } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
586 if ((s->addr & ((1 << s->addr_shift) - 1)) <
587 (1 << s->page_shift) + (1 << s->oob_shift)) {
588 for (i = s->buswidth; i--; s->addr++, value >>= 8) {
589 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] =
590 (uint8_t) (value & 0xff);
591 }
592 }
593 }
594 }
595
596 uint32_t nand_getio(DeviceState *dev)
597 {
598 int offset;
599 uint32_t x = 0;
600 NANDFlashState *s = NAND(dev);
601
602 /* Allow sequential reading */
603 if (!s->iolen && s->cmd == NAND_CMD_READ0) {
604 offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
605 s->offset = 0;
606
607 s->blk_load(s, s->addr, offset);
608 if (s->gnd)
609 s->iolen = (1 << s->page_shift) - offset;
610 else
611 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
612 }
613
614 if (s->ce || s->iolen <= 0) {
615 return 0;
616 }
617
618 for (offset = s->buswidth; offset--;) {
619 x |= s->ioaddr[offset] << (offset << 3);
620 }
621 /* after receiving READ STATUS command all subsequent reads will
622 * return the status register value until another command is issued
623 */
624 if (s->cmd != NAND_CMD_READSTATUS) {
625 s->addr += s->buswidth;
626 s->ioaddr += s->buswidth;
627 s->iolen -= s->buswidth;
628 }
629 return x;
630 }
631
632 uint32_t nand_getbuswidth(DeviceState *dev)
633 {
634 NANDFlashState *s = (NANDFlashState *) dev;
635 return s->buswidth << 3;
636 }
637
638 DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id)
639 {
640 DeviceState *dev;
641
642 if (nand_flash_ids[chip_id].size == 0) {
643 hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
644 }
645 dev = DEVICE(object_new(TYPE_NAND));
646 qdev_prop_set_uint8(dev, "manufacturer_id", manf_id);
647 qdev_prop_set_uint8(dev, "chip_id", chip_id);
648 if (blk) {
649 qdev_prop_set_drive(dev, "drive", blk, &error_fatal);
650 }
651
652 qdev_init_nofail(dev);
653 return dev;
654 }
655
656 type_init(nand_register_types)
657
658 #else
659
660 /* Program a single page */
661 static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
662 {
663 uint64_t off, page, sector, soff;
664 uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
665 if (PAGE(s->addr) >= s->pages)
666 return;
667
668 if (!s->blk) {
669 mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) +
670 s->offset, s->io, s->iolen);
671 } else if (s->mem_oob) {
672 sector = SECTOR(s->addr);
673 off = (s->addr & PAGE_MASK) + s->offset;
674 soff = SECTOR_OFFSET(s->addr);
675 if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
676 PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) {
677 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
678 return;
679 }
680
681 mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off));
682 if (off + s->iolen > PAGE_SIZE) {
683 page = PAGE(s->addr);
684 mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off,
685 MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE));
686 }
687
688 if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
689 PAGE_SECTORS << BDRV_SECTOR_BITS, 0) < 0) {
690 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
691 }
692 } else {
693 off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset;
694 sector = off >> 9;
695 soff = off & 0x1ff;
696 if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
697 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) {
698 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
699 return;
700 }
701
702 mem_and(iobuf + soff, s->io, s->iolen);
703
704 if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
705 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS, 0) < 0) {
706 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
707 }
708 }
709 s->offset = 0;
710 }
711
712 /* Erase a single block */
713 static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
714 {
715 uint64_t i, page, addr;
716 uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
717 addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1);
718
719 if (PAGE(addr) >= s->pages) {
720 return;
721 }
722
723 if (!s->blk) {
724 memset(s->storage + PAGE_START(addr),
725 0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift);
726 } else if (s->mem_oob) {
727 memset(s->storage + (PAGE(addr) << OOB_SHIFT),
728 0xff, OOB_SIZE << s->erase_shift);
729 i = SECTOR(addr);
730 page = SECTOR(addr + (1 << (ADDR_SHIFT + s->erase_shift)));
731 for (; i < page; i ++)
732 if (blk_pwrite(s->blk, i << BDRV_SECTOR_BITS, iobuf,
733 BDRV_SECTOR_SIZE, 0) < 0) {
734 printf("%s: write error in sector %" PRIu64 "\n", __func__, i);
735 }
736 } else {
737 addr = PAGE_START(addr);
738 page = addr >> 9;
739 if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf,
740 BDRV_SECTOR_SIZE) < 0) {
741 printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
742 }
743 memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1);
744 if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf,
745 BDRV_SECTOR_SIZE, 0) < 0) {
746 printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
747 }
748
749 memset(iobuf, 0xff, 0x200);
750 i = (addr & ~0x1ff) + 0x200;
751 for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200;
752 i < addr; i += 0x200) {
753 if (blk_pwrite(s->blk, i, iobuf, BDRV_SECTOR_SIZE, 0) < 0) {
754 printf("%s: write error in sector %" PRIu64 "\n",
755 __func__, i >> 9);
756 }
757 }
758
759 page = i >> 9;
760 if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf,
761 BDRV_SECTOR_SIZE) < 0) {
762 printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
763 }
764 memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1);
765 if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf,
766 BDRV_SECTOR_SIZE, 0) < 0) {
767 printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
768 }
769 }
770 }
771
772 static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
773 uint64_t addr, int offset)
774 {
775 if (PAGE(addr) >= s->pages) {
776 return;
777 }
778
779 if (s->blk) {
780 if (s->mem_oob) {
781 if (blk_pread(s->blk, SECTOR(addr) << BDRV_SECTOR_BITS, s->io,
782 PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) {
783 printf("%s: read error in sector %" PRIu64 "\n",
784 __func__, SECTOR(addr));
785 }
786 memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE,
787 s->storage + (PAGE(s->addr) << OOB_SHIFT),
788 OOB_SIZE);
789 s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset;
790 } else {
791 if (blk_pread(s->blk, PAGE_START(addr), s->io,
792 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) {
793 printf("%s: read error in sector %" PRIu64 "\n",
794 __func__, PAGE_START(addr) >> 9);
795 }
796 s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset;
797 }
798 } else {
799 memcpy(s->io, s->storage + PAGE_START(s->addr) +
800 offset, PAGE_SIZE + OOB_SIZE - offset);
801 s->ioaddr = s->io;
802 }
803 }
804
805 static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
806 {
807 s->oob_shift = PAGE_SHIFT - 5;
808 s->pages = s->size >> PAGE_SHIFT;
809 s->addr_shift = ADDR_SHIFT;
810
811 s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE);
812 s->blk_write = glue(nand_blk_write_, PAGE_SIZE);
813 s->blk_load = glue(nand_blk_load_, PAGE_SIZE);
814 }
815
816 # undef PAGE_SIZE
817 # undef PAGE_SHIFT
818 # undef PAGE_SECTORS
819 # undef ADDR_SHIFT
820 #endif /* NAND_IO */
AR7 emulation for QEMU