2 * ARM AMBA PrimeCell PL031 RTC
4 * Copyright (c) 2007 CodeSourcery
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Contributions after 2012-01-13 are licensed under the terms of the
11 * GNU GPL, version 2 or (at your option) any later version.
14 #include "qemu/osdep.h"
15 #include "qemu-common.h"
16 #include "hw/timer/pl031.h"
17 #include "hw/sysbus.h"
18 #include "qemu/timer.h"
19 #include "sysemu/sysemu.h"
20 #include "qemu/cutils.h"
22 #include "qemu/module.h"
25 #define RTC_DR 0x00 /* Data read register */
26 #define RTC_MR 0x04 /* Match register */
27 #define RTC_LR 0x08 /* Data load register */
28 #define RTC_CR 0x0c /* Control register */
29 #define RTC_IMSC 0x10 /* Interrupt mask and set register */
30 #define RTC_RIS 0x14 /* Raw interrupt status register */
31 #define RTC_MIS 0x18 /* Masked interrupt status register */
32 #define RTC_ICR 0x1c /* Interrupt clear register */
34 static const unsigned char pl031_id
[] = {
35 0x31, 0x10, 0x14, 0x00, /* Device ID */
36 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
39 static void pl031_update(PL031State
*s
)
41 uint32_t flags
= s
->is
& s
->im
;
43 trace_pl031_irq_state(flags
);
44 qemu_set_irq(s
->irq
, flags
);
47 static void pl031_interrupt(void * opaque
)
49 PL031State
*s
= (PL031State
*)opaque
;
52 trace_pl031_alarm_raised();
56 static uint32_t pl031_get_count(PL031State
*s
)
58 int64_t now
= qemu_clock_get_ns(rtc_clock
);
59 return s
->tick_offset
+ now
/ NANOSECONDS_PER_SECOND
;
62 static void pl031_set_alarm(PL031State
*s
)
66 /* The timer wraps around. This subtraction also wraps in the same way,
67 and gives correct results when alarm < now_ticks. */
68 ticks
= s
->mr
- pl031_get_count(s
);
69 trace_pl031_set_alarm(ticks
);
74 int64_t now
= qemu_clock_get_ns(rtc_clock
);
75 timer_mod(s
->timer
, now
+ (int64_t)ticks
* NANOSECONDS_PER_SECOND
);
79 static uint64_t pl031_read(void *opaque
, hwaddr offset
,
82 PL031State
*s
= (PL031State
*)opaque
;
87 r
= pl031_get_count(s
);
102 /* RTC is permanently enabled. */
108 case 0xfe0 ... 0xfff:
109 r
= pl031_id
[(offset
- 0xfe0) >> 2];
112 qemu_log_mask(LOG_GUEST_ERROR
,
113 "pl031: read of write-only register at offset 0x%x\n",
118 qemu_log_mask(LOG_GUEST_ERROR
,
119 "pl031_read: Bad offset 0x%x\n", (int)offset
);
124 trace_pl031_read(offset
, r
);
128 static void pl031_write(void * opaque
, hwaddr offset
,
129 uint64_t value
, unsigned size
)
131 PL031State
*s
= (PL031State
*)opaque
;
133 trace_pl031_write(offset
, value
);
137 s
->tick_offset
+= value
- pl031_get_count(s
);
149 /* The PL031 documentation (DDI0224B) states that the interrupt is
150 cleared when bit 0 of the written value is set. However the
151 arm926e documentation (DDI0287B) states that the interrupt is
152 cleared when any value is written. */
157 /* Written value is ignored. */
163 qemu_log_mask(LOG_GUEST_ERROR
,
164 "pl031: write to read-only register at offset 0x%x\n",
169 qemu_log_mask(LOG_GUEST_ERROR
,
170 "pl031_write: Bad offset 0x%x\n", (int)offset
);
175 static const MemoryRegionOps pl031_ops
= {
177 .write
= pl031_write
,
178 .endianness
= DEVICE_NATIVE_ENDIAN
,
181 static void pl031_init(Object
*obj
)
183 PL031State
*s
= PL031(obj
);
184 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
187 memory_region_init_io(&s
->iomem
, obj
, &pl031_ops
, s
, "pl031", 0x1000);
188 sysbus_init_mmio(dev
, &s
->iomem
);
190 sysbus_init_irq(dev
, &s
->irq
);
191 qemu_get_timedate(&tm
, 0);
192 s
->tick_offset
= mktimegm(&tm
) -
193 qemu_clock_get_ns(rtc_clock
) / NANOSECONDS_PER_SECOND
;
195 s
->timer
= timer_new_ns(rtc_clock
, pl031_interrupt
, s
);
198 static int pl031_pre_save(void *opaque
)
200 PL031State
*s
= opaque
;
203 * The PL031 device model code uses the tick_offset field, which is
204 * the offset between what the guest RTC should read and what the
205 * QEMU rtc_clock reads:
206 * guest_rtc = rtc_clock + tick_offset
208 * tick_offset = guest_rtc - rtc_clock
210 * We want to migrate this offset, which sounds straightforward.
211 * Unfortunately older versions of QEMU migrated a conversion of this
212 * offset into an offset from the vm_clock. (This was in turn an
213 * attempt to be compatible with even older QEMU versions, but it
214 * has incorrect behaviour if the rtc_clock is not the same as the
215 * vm_clock.) So we put the actual tick_offset into a migration
216 * subsection, and the backwards-compatible time-relative-to-vm_clock
217 * in the main migration state.
219 * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
221 int64_t delta
= qemu_clock_get_ns(rtc_clock
) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
222 s
->tick_offset_vmstate
= s
->tick_offset
+ delta
/ NANOSECONDS_PER_SECOND
;
227 static int pl031_pre_load(void *opaque
)
229 PL031State
*s
= opaque
;
231 s
->tick_offset_migrated
= false;
235 static int pl031_post_load(void *opaque
, int version_id
)
237 PL031State
*s
= opaque
;
240 * If we got the tick_offset subsection, then we can just use
241 * the value in that. Otherwise the source is an older QEMU and
242 * has given us the offset from the vm_clock; convert it back to
243 * an offset from the rtc_clock. This will cause time to incorrectly
244 * go backwards compared to the host RTC, but this is unavoidable.
247 if (!s
->tick_offset_migrated
) {
248 int64_t delta
= qemu_clock_get_ns(rtc_clock
) -
249 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
250 s
->tick_offset
= s
->tick_offset_vmstate
-
251 delta
/ NANOSECONDS_PER_SECOND
;
257 static int pl031_tick_offset_post_load(void *opaque
, int version_id
)
259 PL031State
*s
= opaque
;
261 s
->tick_offset_migrated
= true;
265 static bool pl031_tick_offset_needed(void *opaque
)
267 PL031State
*s
= opaque
;
269 return s
->migrate_tick_offset
;
272 static const VMStateDescription vmstate_pl031_tick_offset
= {
273 .name
= "pl031/tick-offset",
275 .minimum_version_id
= 1,
276 .needed
= pl031_tick_offset_needed
,
277 .post_load
= pl031_tick_offset_post_load
,
278 .fields
= (VMStateField
[]) {
279 VMSTATE_UINT32(tick_offset
, PL031State
),
280 VMSTATE_END_OF_LIST()
284 static const VMStateDescription vmstate_pl031
= {
287 .minimum_version_id
= 1,
288 .pre_save
= pl031_pre_save
,
289 .pre_load
= pl031_pre_load
,
290 .post_load
= pl031_post_load
,
291 .fields
= (VMStateField
[]) {
292 VMSTATE_UINT32(tick_offset_vmstate
, PL031State
),
293 VMSTATE_UINT32(mr
, PL031State
),
294 VMSTATE_UINT32(lr
, PL031State
),
295 VMSTATE_UINT32(cr
, PL031State
),
296 VMSTATE_UINT32(im
, PL031State
),
297 VMSTATE_UINT32(is
, PL031State
),
298 VMSTATE_END_OF_LIST()
300 .subsections
= (const VMStateDescription
*[]) {
301 &vmstate_pl031_tick_offset
,
306 static Property pl031_properties
[] = {
308 * True to correctly migrate the tick offset of the RTC. False to
309 * obtain backward migration compatibility with older QEMU versions,
310 * at the expense of the guest RTC going backwards compared with the
311 * host RTC when the VM is saved/restored if using -rtc host.
312 * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
313 * 'false' also permits newer QEMU to migrate to older QEMU.)
315 DEFINE_PROP_BOOL("migrate-tick-offset",
316 PL031State
, migrate_tick_offset
, true),
317 DEFINE_PROP_END_OF_LIST()
320 static void pl031_class_init(ObjectClass
*klass
, void *data
)
322 DeviceClass
*dc
= DEVICE_CLASS(klass
);
324 dc
->vmsd
= &vmstate_pl031
;
325 dc
->props
= pl031_properties
;
328 static const TypeInfo pl031_info
= {
330 .parent
= TYPE_SYS_BUS_DEVICE
,
331 .instance_size
= sizeof(PL031State
),
332 .instance_init
= pl031_init
,
333 .class_init
= pl031_class_init
,
336 static void pl031_register_types(void)
338 type_register_static(&pl031_info
);
341 type_init(pl031_register_types
)