hw/ide/via.c

   1 /*
   2  * QEMU IDE Emulation: PCI VIA82C686B support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/isa/isa.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/dma.h"
  32
  33 #include "hw/ide/pci.h"
  34 #include "trace.h"
  35
  36 static uint64_t bmdma_read(void *opaque, hwaddr addr,
  37                            unsigned size)
  38 {
  39     BMDMAState *bm = opaque;
  40     uint32_t val;
  41
  42     if (size != 1) {
  43         return ((uint64_t)1 << (size * 8)) - 1;
  44     }
  45
  46     switch (addr & 3) {
  47     case 0:
  48         val = bm->cmd;
  49         break;
  50     case 2:
  51         val = bm->status;
  52         break;
  53     default:
  54         val = 0xff;
  55         break;
  56     }
  57
  58     trace_bmdma_read_via(addr, val);
  59     return val;
  60 }
  61
  62 static void bmdma_write(void *opaque, hwaddr addr,
  63                         uint64_t val, unsigned size)
  64 {
  65     BMDMAState *bm = opaque;
  66
  67     if (size != 1) {
  68         return;
  69     }
  70
  71     trace_bmdma_write_via(addr, val);
  72     switch (addr & 3) {
  73     case 0:
  74         bmdma_cmd_writeb(bm, val);
  75         break;
  76     case 2:
  77         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
  78         break;
  79     default:;
  80     }
  81 }
  82
  83 static const MemoryRegionOps via_bmdma_ops = {
  84     .read = bmdma_read,
  85     .write = bmdma_write,
  86 };
  87
  88 static void bmdma_setup_bar(PCIIDEState *d)
  89 {
  90     int i;
  91
  92     memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
  93     for(i = 0;i < 2; i++) {
  94         BMDMAState *bm = &d->bmdma[i];
  95
  96         memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
  97                               "via-bmdma", 4);
  98         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
  99         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 100                               &bmdma_addr_ioport_ops, bm, "bmdma", 4);
 101         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 102     }
 103 }
 104
 105 static void via_reset(void *opaque)
 106 {
 107     PCIIDEState *d = opaque;
 108     PCIDevice *pd = PCI_DEVICE(d);
 109     uint8_t *pci_conf = pd->config;
 110     int i;
 111
 112     for (i = 0; i < 2; i++) {
 113         ide_bus_reset(&d->bus[i]);
 114     }
 115
 116     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
 117     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 118                  PCI_STATUS_DEVSEL_MEDIUM);
 119
 120     pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
 121     pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
 122     pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
 123     pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
 124     pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
 125     pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
 126
 127     /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
 128     pci_set_long(pci_conf + 0x40, 0x0a090600);
 129     /* IDE misc configuration 1/2/3 */
 130     pci_set_long(pci_conf + 0x44, 0x00c00068);
 131     /* IDE Timing control */
 132     pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
 133     /* IDE Address Setup Time */
 134     pci_set_long(pci_conf + 0x4c, 0x000000ff);
 135     /* UltraDMA Extended Timing Control*/
 136     pci_set_long(pci_conf + 0x50, 0x07070707);
 137     /* UltraDMA FIFO Control */
 138     pci_set_long(pci_conf + 0x54, 0x00000004);
 139     /* IDE primary sector size */
 140     pci_set_long(pci_conf + 0x60, 0x00000200);
 141     /* IDE secondary sector size */
 142     pci_set_long(pci_conf + 0x68, 0x00000200);
 143     /* PCI PM Block */
 144     pci_set_long(pci_conf + 0xc0, 0x00020001);
 145 }
 146
 147 static void vt82c686b_init_ports(PCIIDEState *d) {
 148     static const struct {
 149         int iobase;
 150         int iobase2;
 151         int isairq;
 152     } port_info[] = {
 153         {0x1f0, 0x3f6, 14},
 154         {0x170, 0x376, 15},
 155     };
 156     int i;
 157
 158     for (i = 0; i < 2; i++) {
 159         ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
 160         ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
 161                         port_info[i].iobase2);
 162         ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
 163
 164         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 165         d->bmdma[i].bus = &d->bus[i];
 166         ide_register_restart_cb(&d->bus[i]);
 167     }
 168 }
 169
 170 /* via ide func */
 171 static void vt82c686b_ide_realize(PCIDevice *dev, Error **errp)
 172 {
 173     PCIIDEState *d = PCI_IDE(dev);
 174     uint8_t *pci_conf = dev->config;
 175
 176     pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
 177     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 178
 179     qemu_register_reset(via_reset, d);
 180     bmdma_setup_bar(d);
 181     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 182
 183     vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
 184
 185     vt82c686b_init_ports(d);
 186 }
 187
 188 static void vt82c686b_ide_exitfn(PCIDevice *dev)
 189 {
 190     PCIIDEState *d = PCI_IDE(dev);
 191     unsigned i;
 192
 193     for (i = 0; i < 2; ++i) {
 194         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 195         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 196     }
 197 }
 198
 199 void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
 200 {
 201     PCIDevice *dev;
 202
 203     dev = pci_create_simple(bus, devfn, "via-ide");
 204     pci_ide_create_devs(dev, hd_table);
 205 }
 206
 207 static void via_ide_class_init(ObjectClass *klass, void *data)
 208 {
 209     DeviceClass *dc = DEVICE_CLASS(klass);
 210     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 211
 212     k->realize = vt82c686b_ide_realize;
 213     k->exit = vt82c686b_ide_exitfn;
 214     k->vendor_id = PCI_VENDOR_ID_VIA;
 215     k->device_id = PCI_DEVICE_ID_VIA_IDE;
 216     k->revision = 0x06;
 217     k->class_id = PCI_CLASS_STORAGE_IDE;
 218     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 219 }
 220
 221 static const TypeInfo via_ide_info = {
 222     .name          = "via-ide",
 223     .parent        = TYPE_PCI_IDE,
 224     .class_init    = via_ide_class_init,
 225 };
 226
 227 static void via_ide_register_types(void)
 228 {
 229     type_register_static(&via_ide_info);
 230 }
 231
 232 type_init(via_ide_register_types)