target-arm/op_helper.c

   1 /*
   2  *  ARM helper routines
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery, LLC
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "exec/helper-proto.h"
  21 #include "internals.h"
  22 #include "exec/cpu_ldst.h"
  23
  24 #define SIGNBIT (uint32_t)0x80000000
  25 #define SIGNBIT64 ((uint64_t)1 << 63)
  26
  27 static void raise_exception(CPUARMState *env, int tt)
  28 {
  29     ARMCPU *cpu = arm_env_get_cpu(env);
  30     CPUState *cs = CPU(cpu);
  31
  32     cs->exception_index = tt;
  33     cpu_loop_exit(cs);
  34 }
  35
  36 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
  37                           uint32_t rn, uint32_t maxindex)
  38 {
  39     uint32_t val;
  40     uint32_t tmp;
  41     int index;
  42     int shift;
  43     uint64_t *table;
  44     table = (uint64_t *)&env->vfp.regs[rn];
  45     val = 0;
  46     for (shift = 0; shift < 32; shift += 8) {
  47         index = (ireg >> shift) & 0xff;
  48         if (index < maxindex) {
  49             tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
  50             val |= tmp << shift;
  51         } else {
  52             val |= def & (0xff << shift);
  53         }
  54     }
  55     return val;
  56 }
  57
  58 #if !defined(CONFIG_USER_ONLY)
  59
  60 /* try to fill the TLB and return an exception if error. If retaddr is
  61  * NULL, it means that the function was called in C code (i.e. not
  62  * from generated code or from helper.c)
  63  */
  64 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  65               uintptr_t retaddr)
  66 {
  67     int ret;
  68
  69     ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  70     if (unlikely(ret)) {
  71         ARMCPU *cpu = ARM_CPU(cs);
  72         CPUARMState *env = &cpu->env;
  73
  74         if (retaddr) {
  75             /* now we have a real cpu fault */
  76             cpu_restore_state(cs, retaddr);
  77         }
  78         raise_exception(env, cs->exception_index);
  79     }
  80 }
  81 #endif
  82
  83 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
  84 {
  85     uint32_t res = a + b;
  86     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
  87         env->QF = 1;
  88     return res;
  89 }
  90
  91 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
  92 {
  93     uint32_t res = a + b;
  94     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
  95         env->QF = 1;
  96         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
  97     }
  98     return res;
  99 }
 100
 101 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 102 {
 103     uint32_t res = a - b;
 104     if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
 105         env->QF = 1;
 106         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 107     }
 108     return res;
 109 }
 110
 111 uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
 112 {
 113     uint32_t res;
 114     if (val >= 0x40000000) {
 115         res = ~SIGNBIT;
 116         env->QF = 1;
 117     } else if (val <= (int32_t)0xc0000000) {
 118         res = SIGNBIT;
 119         env->QF = 1;
 120     } else {
 121         res = val << 1;
 122     }
 123     return res;
 124 }
 125
 126 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 127 {
 128     uint32_t res = a + b;
 129     if (res < a) {
 130         env->QF = 1;
 131         res = ~0;
 132     }
 133     return res;
 134 }
 135
 136 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 137 {
 138     uint32_t res = a - b;
 139     if (res > a) {
 140         env->QF = 1;
 141         res = 0;
 142     }
 143     return res;
 144 }
 145
 146 /* Signed saturation.  */
 147 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
 148 {
 149     int32_t top;
 150     uint32_t mask;
 151
 152     top = val >> shift;
 153     mask = (1u << shift) - 1;
 154     if (top > 0) {
 155         env->QF = 1;
 156         return mask;
 157     } else if (top < -1) {
 158         env->QF = 1;
 159         return ~mask;
 160     }
 161     return val;
 162 }
 163
 164 /* Unsigned saturation.  */
 165 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
 166 {
 167     uint32_t max;
 168
 169     max = (1u << shift) - 1;
 170     if (val < 0) {
 171         env->QF = 1;
 172         return 0;
 173     } else if (val > max) {
 174         env->QF = 1;
 175         return max;
 176     }
 177     return val;
 178 }
 179
 180 /* Signed saturate.  */
 181 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
 182 {
 183     return do_ssat(env, x, shift);
 184 }
 185
 186 /* Dual halfword signed saturate.  */
 187 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 188 {
 189     uint32_t res;
 190
 191     res = (uint16_t)do_ssat(env, (int16_t)x, shift);
 192     res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
 193     return res;
 194 }
 195
 196 /* Unsigned saturate.  */
 197 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
 198 {
 199     return do_usat(env, x, shift);
 200 }
 201
 202 /* Dual halfword unsigned saturate.  */
 203 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 204 {
 205     uint32_t res;
 206
 207     res = (uint16_t)do_usat(env, (int16_t)x, shift);
 208     res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
 209     return res;
 210 }
 211
 212 void HELPER(wfi)(CPUARMState *env)
 213 {
 214     CPUState *cs = CPU(arm_env_get_cpu(env));
 215
 216     cs->exception_index = EXCP_HLT;
 217     cs->halted = 1;
 218     cpu_loop_exit(cs);
 219 }
 220
 221 void HELPER(wfe)(CPUARMState *env)
 222 {
 223     CPUState *cs = CPU(arm_env_get_cpu(env));
 224
 225     /* Don't actually halt the CPU, just yield back to top
 226      * level loop
 227      */
 228     cs->exception_index = EXCP_YIELD;
 229     cpu_loop_exit(cs);
 230 }
 231
 232 /* Raise an internal-to-QEMU exception. This is limited to only
 233  * those EXCP values which are special cases for QEMU to interrupt
 234  * execution and not to be used for exceptions which are passed to
 235  * the guest (those must all have syndrome information and thus should
 236  * use exception_with_syndrome).
 237  */
 238 void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
 239 {
 240     CPUState *cs = CPU(arm_env_get_cpu(env));
 241
 242     assert(excp_is_internal(excp));
 243     cs->exception_index = excp;
 244     cpu_loop_exit(cs);
 245 }
 246
 247 /* Raise an exception with the specified syndrome register value */
 248 void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
 249                                      uint32_t syndrome)
 250 {
 251     CPUState *cs = CPU(arm_env_get_cpu(env));
 252
 253     assert(!excp_is_internal(excp));
 254     cs->exception_index = excp;
 255     env->exception.syndrome = syndrome;
 256     cpu_loop_exit(cs);
 257 }
 258
 259 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 260 {
 261     return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED);
 262 }
 263
 264 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
 265 {
 266     cpsr_write(env, val, mask);
 267 }
 268
 269 /* Access to user mode registers from privileged modes.  */
 270 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
 271 {
 272     uint32_t val;
 273
 274     if (regno == 13) {
 275         val = env->banked_r13[0];
 276     } else if (regno == 14) {
 277         val = env->banked_r14[0];
 278     } else if (regno >= 8
 279                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 280         val = env->usr_regs[regno - 8];
 281     } else {
 282         val = env->regs[regno];
 283     }
 284     return val;
 285 }
 286
 287 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
 288 {
 289     if (regno == 13) {
 290         env->banked_r13[0] = val;
 291     } else if (regno == 14) {
 292         env->banked_r14[0] = val;
 293     } else if (regno >= 8
 294                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 295         env->usr_regs[regno - 8] = val;
 296     } else {
 297         env->regs[regno] = val;
 298     }
 299 }
 300
 301 void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome)
 302 {
 303     const ARMCPRegInfo *ri = rip;
 304     switch (ri->accessfn(env, ri)) {
 305     case CP_ACCESS_OK:
 306         return;
 307     case CP_ACCESS_TRAP:
 308         env->exception.syndrome = syndrome;
 309         break;
 310     case CP_ACCESS_TRAP_UNCATEGORIZED:
 311         env->exception.syndrome = syn_uncategorized();
 312         break;
 313     default:
 314         g_assert_not_reached();
 315     }
 316     raise_exception(env, EXCP_UDEF);
 317 }
 318
 319 void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
 320 {
 321     const ARMCPRegInfo *ri = rip;
 322
 323     ri->writefn(env, ri, value);
 324 }
 325
 326 uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
 327 {
 328     const ARMCPRegInfo *ri = rip;
 329
 330     return ri->readfn(env, ri);
 331 }
 332
 333 void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
 334 {
 335     const ARMCPRegInfo *ri = rip;
 336
 337     ri->writefn(env, ri, value);
 338 }
 339
 340 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 341 {
 342     const ARMCPRegInfo *ri = rip;
 343
 344     return ri->readfn(env, ri);
 345 }
 346
 347 void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
 348 {
 349     /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
 350      * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
 351      * to catch that case at translate time.
 352      */
 353     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
 354         raise_exception(env, EXCP_UDEF);
 355     }
 356
 357     switch (op) {
 358     case 0x05: /* SPSel */
 359         update_spsel(env, imm);
 360         break;
 361     case 0x1e: /* DAIFSet */
 362         env->daif |= (imm << 6) & PSTATE_DAIF;
 363         break;
 364     case 0x1f: /* DAIFClear */
 365         env->daif &= ~((imm << 6) & PSTATE_DAIF);
 366         break;
 367     default:
 368         g_assert_not_reached();
 369     }
 370 }
 371
 372 void HELPER(clear_pstate_ss)(CPUARMState *env)
 373 {
 374     env->pstate &= ~PSTATE_SS;
 375 }
 376
 377 void HELPER(exception_return)(CPUARMState *env)
 378 {
 379     int cur_el = arm_current_pl(env);
 380     unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
 381     uint32_t spsr = env->banked_spsr[spsr_idx];
 382     int new_el, i;
 383
 384     aarch64_save_sp(env, cur_el);
 385
 386     env->exclusive_addr = -1;
 387
 388     /* We must squash the PSTATE.SS bit to zero unless both of the
 389      * following hold:
 390      *  1. debug exceptions are currently disabled
 391      *  2. singlestep will be active in the EL we return to
 392      * We check 1 here and 2 after we've done the pstate/cpsr write() to
 393      * transition to the EL we're going to.
 394      */
 395     if (arm_generate_debug_exceptions(env)) {
 396         spsr &= ~PSTATE_SS;
 397     }
 398
 399     if (spsr & PSTATE_nRW) {
 400         /* TODO: We currently assume EL1/2/3 are running in AArch64.  */
 401         env->aarch64 = 0;
 402         new_el = 0;
 403         env->uncached_cpsr = 0x10;
 404         cpsr_write(env, spsr, ~0);
 405         if (!arm_singlestep_active(env)) {
 406             env->uncached_cpsr &= ~PSTATE_SS;
 407         }
 408         for (i = 0; i < 15; i++) {
 409             env->regs[i] = env->xregs[i];
 410         }
 411
 412         env->regs[15] = env->elr_el[1] & ~0x1;
 413     } else {
 414         new_el = extract32(spsr, 2, 2);
 415         if (new_el > cur_el
 416             || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
 417             /* Disallow return to an EL which is unimplemented or higher
 418              * than the current one.
 419              */
 420             goto illegal_return;
 421         }
 422         if (extract32(spsr, 1, 1)) {
 423             /* Return with reserved M[1] bit set */
 424             goto illegal_return;
 425         }
 426         if (new_el == 0 && (spsr & PSTATE_SP)) {
 427             /* Return to EL0 with M[0] bit set */
 428             goto illegal_return;
 429         }
 430         env->aarch64 = 1;
 431         pstate_write(env, spsr);
 432         if (!arm_singlestep_active(env)) {
 433             env->pstate &= ~PSTATE_SS;
 434         }
 435         aarch64_restore_sp(env, new_el);
 436         env->pc = env->elr_el[cur_el];
 437     }
 438
 439     return;
 440
 441 illegal_return:
 442     /* Illegal return events of various kinds have architecturally
 443      * mandated behaviour:
 444      * restore NZCV and DAIF from SPSR_ELx
 445      * set PSTATE.IL
 446      * restore PC from ELR_ELx
 447      * no change to exception level, execution state or stack pointer
 448      */
 449     env->pstate |= PSTATE_IL;
 450     env->pc = env->elr_el[cur_el];
 451     spsr &= PSTATE_NZCV | PSTATE_DAIF;
 452     spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
 453     pstate_write(env, spsr);
 454     if (!arm_singlestep_active(env)) {
 455         env->pstate &= ~PSTATE_SS;
 456     }
 457 }
 458
 459 /* Return true if the linked breakpoint entry lbn passes its checks */
 460 static bool linked_bp_matches(ARMCPU *cpu, int lbn)
 461 {
 462     CPUARMState *env = &cpu->env;
 463     uint64_t bcr = env->cp15.dbgbcr[lbn];
 464     int brps = extract32(cpu->dbgdidr, 24, 4);
 465     int ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
 466     int bt;
 467     uint32_t contextidr;
 468
 469     /* Links to unimplemented or non-context aware breakpoints are
 470      * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
 471      * as if linked to an UNKNOWN context-aware breakpoint (in which
 472      * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
 473      * We choose the former.
 474      */
 475     if (lbn > brps || lbn < (brps - ctx_cmps)) {
 476         return false;
 477     }
 478
 479     bcr = env->cp15.dbgbcr[lbn];
 480
 481     if (extract64(bcr, 0, 1) == 0) {
 482         /* Linked breakpoint disabled : generate no events */
 483         return false;
 484     }
 485
 486     bt = extract64(bcr, 20, 4);
 487
 488     /* We match the whole register even if this is AArch32 using the
 489      * short descriptor format (in which case it holds both PROCID and ASID),
 490      * since we don't implement the optional v7 context ID masking.
 491      */
 492     contextidr = extract64(env->cp15.contextidr_el1, 0, 32);
 493
 494     switch (bt) {
 495     case 3: /* linked context ID match */
 496         if (arm_current_pl(env) > 1) {
 497             /* Context matches never fire in EL2 or (AArch64) EL3 */
 498             return false;
 499         }
 500         return (contextidr == extract64(env->cp15.dbgbvr[lbn], 0, 32));
 501     case 5: /* linked address mismatch (reserved in AArch64) */
 502     case 9: /* linked VMID match (reserved if no EL2) */
 503     case 11: /* linked context ID and VMID match (reserved if no EL2) */
 504     default:
 505         /* Links to Unlinked context breakpoints must generate no
 506          * events; we choose to do the same for reserved values too.
 507          */
 508         return false;
 509     }
 510
 511     return false;
 512 }
 513
 514 static bool wp_matches(ARMCPU *cpu, int n)
 515 {
 516     CPUARMState *env = &cpu->env;
 517     uint64_t wcr = env->cp15.dbgwcr[n];
 518     int pac, hmc, ssc, wt, lbn;
 519     /* TODO: check against CPU security state when we implement TrustZone */
 520     bool is_secure = false;
 521
 522     if (!env->cpu_watchpoint[n]
 523         || !(env->cpu_watchpoint[n]->flags & BP_WATCHPOINT_HIT)) {
 524         return false;
 525     }
 526
 527     /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
 528      * enabled and that the address and access type match; check the
 529      * remaining fields, including linked breakpoints.
 530      * Note that some combinations of {PAC, HMC SSC} are reserved and
 531      * must act either like some valid combination or as if the watchpoint
 532      * were disabled. We choose the former, and use this together with
 533      * the fact that EL3 must always be Secure and EL2 must always be
 534      * Non-Secure to simplify the code slightly compared to the full
 535      * table in the ARM ARM.
 536      */
 537     pac = extract64(wcr, 1, 2);
 538     hmc = extract64(wcr, 13, 1);
 539     ssc = extract64(wcr, 14, 2);
 540
 541     switch (ssc) {
 542     case 0:
 543         break;
 544     case 1:
 545     case 3:
 546         if (is_secure) {
 547             return false;
 548         }
 549         break;
 550     case 2:
 551         if (!is_secure) {
 552             return false;
 553         }
 554         break;
 555     }
 556
 557     /* TODO: this is not strictly correct because the LDRT/STRT/LDT/STT
 558      * "unprivileged access" instructions should match watchpoints as if
 559      * they were accesses done at EL0, even if the CPU is at EL1 or higher.
 560      * Implementing this would require reworking the core watchpoint code
 561      * to plumb the mmu_idx through to this point. Luckily Linux does not
 562      * rely on this behaviour currently.
 563      */
 564     switch (arm_current_pl(env)) {
 565     case 3:
 566     case 2:
 567         if (!hmc) {
 568             return false;
 569         }
 570         break;
 571     case 1:
 572         if (extract32(pac, 0, 1) == 0) {
 573             return false;
 574         }
 575         break;
 576     case 0:
 577         if (extract32(pac, 1, 1) == 0) {
 578             return false;
 579         }
 580         break;
 581     default:
 582         g_assert_not_reached();
 583     }
 584
 585     wt = extract64(wcr, 20, 1);
 586     lbn = extract64(wcr, 16, 4);
 587
 588     if (wt && !linked_bp_matches(cpu, lbn)) {
 589         return false;
 590     }
 591
 592     return true;
 593 }
 594
 595 static bool check_watchpoints(ARMCPU *cpu)
 596 {
 597     CPUARMState *env = &cpu->env;
 598     int n;
 599
 600     /* If watchpoints are disabled globally or we can't take debug
 601      * exceptions here then watchpoint firings are ignored.
 602      */
 603     if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
 604         || !arm_generate_debug_exceptions(env)) {
 605         return false;
 606     }
 607
 608     for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
 609         if (wp_matches(cpu, n)) {
 610             return true;
 611         }
 612     }
 613     return false;
 614 }
 615
 616 void arm_debug_excp_handler(CPUState *cs)
 617 {
 618     /* Called by core code when a watchpoint or breakpoint fires;
 619      * need to check which one and raise the appropriate exception.
 620      */
 621     ARMCPU *cpu = ARM_CPU(cs);
 622     CPUARMState *env = &cpu->env;
 623     CPUWatchpoint *wp_hit = cs->watchpoint_hit;
 624
 625     if (wp_hit) {
 626         if (wp_hit->flags & BP_CPU) {
 627             cs->watchpoint_hit = NULL;
 628             if (check_watchpoints(cpu)) {
 629                 bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
 630                 bool same_el = arm_debug_target_el(env) == arm_current_pl(env);
 631
 632                 env->exception.syndrome = syn_watchpoint(same_el, 0, wnr);
 633                 if (extended_addresses_enabled(env)) {
 634                     env->exception.fsr = (1 << 9) | 0x22;
 635                 } else {
 636                     env->exception.fsr = 0x2;
 637                 }
 638                 env->exception.vaddress = wp_hit->hitaddr;
 639                 raise_exception(env, EXCP_DATA_ABORT);
 640             } else {
 641                 cpu_resume_from_signal(cs, NULL);
 642             }
 643         }
 644     }
 645 }
 646
 647 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
 648    The only way to do that in TCG is a conditional branch, which clobbers
 649    all our temporaries.  For now implement these as helper functions.  */
 650
 651 /* Similarly for variable shift instructions.  */
 652
 653 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 654 {
 655     int shift = i & 0xff;
 656     if (shift >= 32) {
 657         if (shift == 32)
 658             env->CF = x & 1;
 659         else
 660             env->CF = 0;
 661         return 0;
 662     } else if (shift != 0) {
 663         env->CF = (x >> (32 - shift)) & 1;
 664         return x << shift;
 665     }
 666     return x;
 667 }
 668
 669 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 670 {
 671     int shift = i & 0xff;
 672     if (shift >= 32) {
 673         if (shift == 32)
 674             env->CF = (x >> 31) & 1;
 675         else
 676             env->CF = 0;
 677         return 0;
 678     } else if (shift != 0) {
 679         env->CF = (x >> (shift - 1)) & 1;
 680         return x >> shift;
 681     }
 682     return x;
 683 }
 684
 685 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 686 {
 687     int shift = i & 0xff;
 688     if (shift >= 32) {
 689         env->CF = (x >> 31) & 1;
 690         return (int32_t)x >> 31;
 691     } else if (shift != 0) {
 692         env->CF = (x >> (shift - 1)) & 1;
 693         return (int32_t)x >> shift;
 694     }
 695     return x;
 696 }
 697
 698 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 699 {
 700     int shift1, shift;
 701     shift1 = i & 0xff;
 702     shift = shift1 & 0x1f;
 703     if (shift == 0) {
 704         if (shift1 != 0)
 705             env->CF = (x >> 31) & 1;
 706         return x;
 707     } else {
 708         env->CF = (x >> (shift - 1)) & 1;
 709         return ((uint32_t)x >> shift) | (x << (32 - shift));
 710     }
 711 }