2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "qemu-common.h"
14 #include "hw/sysbus.h"
15 #include "hw/arm/pxa.h"
16 #include "sysemu/sysemu.h"
17 #include "hw/char/serial.h"
18 #include "hw/i2c/i2c.h"
19 #include "hw/ssi/ssi.h"
20 #include "sysemu/char.h"
21 #include "sysemu/block-backend.h"
22 #include "sysemu/blockdev.h"
23 #include "qemu/cutils.h"
29 { 0x40100000, PXA2XX_PIC_FFUART
},
30 { 0x40200000, PXA2XX_PIC_BTUART
},
31 { 0x40700000, PXA2XX_PIC_STUART
},
32 { 0x41600000, PXA25X_PIC_HWUART
},
34 }, pxa270_serial
[] = {
35 { 0x40100000, PXA2XX_PIC_FFUART
},
36 { 0x40200000, PXA2XX_PIC_BTUART
},
37 { 0x40700000, PXA2XX_PIC_STUART
},
41 typedef struct PXASSPDef
{
47 static PXASSPDef pxa250_ssp
[] = {
48 { 0x41000000, PXA2XX_PIC_SSP
},
53 static PXASSPDef pxa255_ssp
[] = {
54 { 0x41000000, PXA2XX_PIC_SSP
},
55 { 0x41400000, PXA25X_PIC_NSSP
},
60 static PXASSPDef pxa26x_ssp
[] = {
61 { 0x41000000, PXA2XX_PIC_SSP
},
62 { 0x41400000, PXA25X_PIC_NSSP
},
63 { 0x41500000, PXA26X_PIC_ASSP
},
68 static PXASSPDef pxa27x_ssp
[] = {
69 { 0x41000000, PXA2XX_PIC_SSP
},
70 { 0x41700000, PXA27X_PIC_SSP2
},
71 { 0x41900000, PXA2XX_PIC_SSP3
},
75 #define PMCR 0x00 /* Power Manager Control register */
76 #define PSSR 0x04 /* Power Manager Sleep Status register */
77 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
78 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
79 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
80 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
81 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
82 #define PCFR 0x1c /* Power Manager General Configuration register */
83 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
84 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
85 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
86 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
87 #define RCSR 0x30 /* Reset Controller Status register */
88 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
89 #define PTSR 0x38 /* Power Manager Standby Configuration register */
90 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
91 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
92 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
93 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
94 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
95 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
97 static uint64_t pxa2xx_pm_read(void *opaque
, hwaddr addr
,
100 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
103 case PMCR
... PCMD31
:
107 return s
->pm_regs
[addr
>> 2];
110 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
116 static void pxa2xx_pm_write(void *opaque
, hwaddr addr
,
117 uint64_t value
, unsigned size
)
119 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
123 /* Clear the write-one-to-clear bits... */
124 s
->pm_regs
[addr
>> 2] &= ~(value
& 0x2a);
125 /* ...and set the plain r/w bits */
126 s
->pm_regs
[addr
>> 2] &= ~0x15;
127 s
->pm_regs
[addr
>> 2] |= value
& 0x15;
130 case PSSR
: /* Read-clean registers */
133 s
->pm_regs
[addr
>> 2] &= ~value
;
136 default: /* Read-write registers */
138 s
->pm_regs
[addr
>> 2] = value
;
142 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
147 static const MemoryRegionOps pxa2xx_pm_ops
= {
148 .read
= pxa2xx_pm_read
,
149 .write
= pxa2xx_pm_write
,
150 .endianness
= DEVICE_NATIVE_ENDIAN
,
153 static const VMStateDescription vmstate_pxa2xx_pm
= {
156 .minimum_version_id
= 0,
157 .fields
= (VMStateField
[]) {
158 VMSTATE_UINT32_ARRAY(pm_regs
, PXA2xxState
, 0x40),
159 VMSTATE_END_OF_LIST()
163 #define CCCR 0x00 /* Core Clock Configuration register */
164 #define CKEN 0x04 /* Clock Enable register */
165 #define OSCC 0x08 /* Oscillator Configuration register */
166 #define CCSR 0x0c /* Core Clock Status register */
168 static uint64_t pxa2xx_cm_read(void *opaque
, hwaddr addr
,
171 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
177 return s
->cm_regs
[addr
>> 2];
180 return s
->cm_regs
[CCCR
>> 2] | (3 << 28);
183 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
189 static void pxa2xx_cm_write(void *opaque
, hwaddr addr
,
190 uint64_t value
, unsigned size
)
192 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
197 s
->cm_regs
[addr
>> 2] = value
;
201 s
->cm_regs
[addr
>> 2] &= ~0x6c;
202 s
->cm_regs
[addr
>> 2] |= value
& 0x6e;
203 if ((value
>> 1) & 1) /* OON */
204 s
->cm_regs
[addr
>> 2] |= 1 << 0; /* Oscillator is now stable */
208 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
213 static const MemoryRegionOps pxa2xx_cm_ops
= {
214 .read
= pxa2xx_cm_read
,
215 .write
= pxa2xx_cm_write
,
216 .endianness
= DEVICE_NATIVE_ENDIAN
,
219 static const VMStateDescription vmstate_pxa2xx_cm
= {
222 .minimum_version_id
= 0,
223 .fields
= (VMStateField
[]) {
224 VMSTATE_UINT32_ARRAY(cm_regs
, PXA2xxState
, 4),
225 VMSTATE_UINT32(clkcfg
, PXA2xxState
),
226 VMSTATE_UINT32(pmnc
, PXA2xxState
),
227 VMSTATE_END_OF_LIST()
231 static uint64_t pxa2xx_clkcfg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
233 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
237 static void pxa2xx_clkcfg_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
240 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
241 s
->clkcfg
= value
& 0xf;
243 printf("%s: CPU frequency change attempt\n", __func__
);
247 static void pxa2xx_pwrmode_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
250 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
251 static const char *pwrmode
[8] = {
252 "Normal", "Idle", "Deep-idle", "Standby",
253 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
257 printf("%s: CPU voltage change attempt\n", __func__
);
266 if (!(s
->cm_regs
[CCCR
>> 2] & (1U << 31))) { /* CPDIS */
267 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HALT
);
274 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HALT
);
275 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
279 s
->cpu
->env
.uncached_cpsr
= ARM_CPU_MODE_SVC
;
280 s
->cpu
->env
.daif
= PSTATE_A
| PSTATE_F
| PSTATE_I
;
281 s
->cpu
->env
.cp15
.sctlr_ns
= 0;
282 s
->cpu
->env
.cp15
.cpacr_el1
= 0;
283 s
->cpu
->env
.cp15
.ttbr0_el
[1] = 0;
284 s
->cpu
->env
.cp15
.dacr_ns
= 0;
285 s
->pm_regs
[PSSR
>> 2] |= 0x8; /* Set STS */
286 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
289 * The scratch-pad register is almost universally used
290 * for storing the return address on suspend. For the
291 * lack of a resuming bootloader, perform a jump
292 * directly to that address.
294 memset(s
->cpu
->env
.regs
, 0, 4 * 15);
295 s
->cpu
->env
.regs
[15] = s
->pm_regs
[PSPR
>> 2];
298 buffer
= 0xe59ff000; /* ldr pc, [pc, #0] */
299 cpu_physical_memory_write(0, &buffer
, 4);
300 buffer
= s
->pm_regs
[PSPR
>> 2];
301 cpu_physical_memory_write(8, &buffer
, 4);
305 cpu_interrupt(current_cpu
, CPU_INTERRUPT_HALT
);
311 printf("%s: machine entered %s mode\n", __func__
,
316 static uint64_t pxa2xx_cppmnc_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
318 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
322 static void pxa2xx_cppmnc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
325 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
329 static uint64_t pxa2xx_cpccnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
331 PXA2xxState
*s
= (PXA2xxState
*)ri
->opaque
;
333 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
339 static const ARMCPRegInfo pxa_cp_reginfo
[] = {
340 /* cp14 crm==1: perf registers */
341 { .name
= "CPPMNC", .cp
= 14, .crn
= 0, .crm
= 1, .opc1
= 0, .opc2
= 0,
342 .access
= PL1_RW
, .type
= ARM_CP_IO
,
343 .readfn
= pxa2xx_cppmnc_read
, .writefn
= pxa2xx_cppmnc_write
},
344 { .name
= "CPCCNT", .cp
= 14, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
345 .access
= PL1_RW
, .type
= ARM_CP_IO
,
346 .readfn
= pxa2xx_cpccnt_read
, .writefn
= arm_cp_write_ignore
},
347 { .name
= "CPINTEN", .cp
= 14, .crn
= 4, .crm
= 1, .opc1
= 0, .opc2
= 0,
348 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
349 { .name
= "CPFLAG", .cp
= 14, .crn
= 5, .crm
= 1, .opc1
= 0, .opc2
= 0,
350 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
351 { .name
= "CPEVTSEL", .cp
= 14, .crn
= 8, .crm
= 1, .opc1
= 0, .opc2
= 0,
352 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
353 /* cp14 crm==2: performance count registers */
354 { .name
= "CPPMN0", .cp
= 14, .crn
= 0, .crm
= 2, .opc1
= 0, .opc2
= 0,
355 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
356 { .name
= "CPPMN1", .cp
= 14, .crn
= 1, .crm
= 2, .opc1
= 0, .opc2
= 0,
357 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
358 { .name
= "CPPMN2", .cp
= 14, .crn
= 2, .crm
= 2, .opc1
= 0, .opc2
= 0,
359 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
360 { .name
= "CPPMN3", .cp
= 14, .crn
= 2, .crm
= 3, .opc1
= 0, .opc2
= 0,
361 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
362 /* cp14 crn==6: CLKCFG */
363 { .name
= "CLKCFG", .cp
= 14, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
364 .access
= PL1_RW
, .type
= ARM_CP_IO
,
365 .readfn
= pxa2xx_clkcfg_read
, .writefn
= pxa2xx_clkcfg_write
},
366 /* cp14 crn==7: PWRMODE */
367 { .name
= "PWRMODE", .cp
= 14, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 0,
368 .access
= PL1_RW
, .type
= ARM_CP_IO
,
369 .readfn
= arm_cp_read_zero
, .writefn
= pxa2xx_pwrmode_write
},
373 static void pxa2xx_setup_cp14(PXA2xxState
*s
)
375 define_arm_cp_regs_with_opaque(s
->cpu
, pxa_cp_reginfo
, s
);
378 #define MDCNFG 0x00 /* SDRAM Configuration register */
379 #define MDREFR 0x04 /* SDRAM Refresh Control register */
380 #define MSC0 0x08 /* Static Memory Control register 0 */
381 #define MSC1 0x0c /* Static Memory Control register 1 */
382 #define MSC2 0x10 /* Static Memory Control register 2 */
383 #define MECR 0x14 /* Expansion Memory Bus Config register */
384 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
385 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
386 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
387 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
388 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
389 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
390 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
391 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
392 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
393 #define ARB_CNTL 0x48 /* Arbiter Control register */
394 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
395 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
396 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
397 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
398 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
399 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
400 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
402 static uint64_t pxa2xx_mm_read(void *opaque
, hwaddr addr
,
405 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
408 case MDCNFG
... SA1110
:
410 return s
->mm_regs
[addr
>> 2];
413 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
419 static void pxa2xx_mm_write(void *opaque
, hwaddr addr
,
420 uint64_t value
, unsigned size
)
422 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
425 case MDCNFG
... SA1110
:
426 if ((addr
& 3) == 0) {
427 s
->mm_regs
[addr
>> 2] = value
;
432 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
437 static const MemoryRegionOps pxa2xx_mm_ops
= {
438 .read
= pxa2xx_mm_read
,
439 .write
= pxa2xx_mm_write
,
440 .endianness
= DEVICE_NATIVE_ENDIAN
,
443 static const VMStateDescription vmstate_pxa2xx_mm
= {
446 .minimum_version_id
= 0,
447 .fields
= (VMStateField
[]) {
448 VMSTATE_UINT32_ARRAY(mm_regs
, PXA2xxState
, 0x1a),
449 VMSTATE_END_OF_LIST()
453 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
454 #define PXA2XX_SSP(obj) \
455 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
457 /* Synchronous Serial Ports */
460 SysBusDevice parent_obj
;
477 uint32_t rx_fifo
[16];
482 static bool pxa2xx_ssp_vmstate_validate(void *opaque
, int version_id
)
484 PXA2xxSSPState
*s
= opaque
;
486 return s
->rx_start
< sizeof(s
->rx_fifo
);
489 static const VMStateDescription vmstate_pxa2xx_ssp
= {
490 .name
= "pxa2xx-ssp",
492 .minimum_version_id
= 1,
493 .fields
= (VMStateField
[]) {
494 VMSTATE_UINT32(enable
, PXA2xxSSPState
),
495 VMSTATE_UINT32_ARRAY(sscr
, PXA2xxSSPState
, 2),
496 VMSTATE_UINT32(sspsp
, PXA2xxSSPState
),
497 VMSTATE_UINT32(ssto
, PXA2xxSSPState
),
498 VMSTATE_UINT32(ssitr
, PXA2xxSSPState
),
499 VMSTATE_UINT32(sssr
, PXA2xxSSPState
),
500 VMSTATE_UINT8(sstsa
, PXA2xxSSPState
),
501 VMSTATE_UINT8(ssrsa
, PXA2xxSSPState
),
502 VMSTATE_UINT8(ssacd
, PXA2xxSSPState
),
503 VMSTATE_UINT32(rx_level
, PXA2xxSSPState
),
504 VMSTATE_UINT32(rx_start
, PXA2xxSSPState
),
505 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate
),
506 VMSTATE_UINT32_ARRAY(rx_fifo
, PXA2xxSSPState
, 16),
507 VMSTATE_END_OF_LIST()
511 #define SSCR0 0x00 /* SSP Control register 0 */
512 #define SSCR1 0x04 /* SSP Control register 1 */
513 #define SSSR 0x08 /* SSP Status register */
514 #define SSITR 0x0c /* SSP Interrupt Test register */
515 #define SSDR 0x10 /* SSP Data register */
516 #define SSTO 0x28 /* SSP Time-Out register */
517 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
518 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
519 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
520 #define SSTSS 0x38 /* SSP Time Slot Status register */
521 #define SSACD 0x3c /* SSP Audio Clock Divider register */
523 /* Bitfields for above registers */
524 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
525 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
526 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
527 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
528 #define SSCR0_SSE (1 << 7)
529 #define SSCR0_RIM (1 << 22)
530 #define SSCR0_TIM (1 << 23)
531 #define SSCR0_MOD (1U << 31)
532 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
533 #define SSCR1_RIE (1 << 0)
534 #define SSCR1_TIE (1 << 1)
535 #define SSCR1_LBM (1 << 2)
536 #define SSCR1_MWDS (1 << 5)
537 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
538 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
539 #define SSCR1_EFWR (1 << 14)
540 #define SSCR1_PINTE (1 << 18)
541 #define SSCR1_TINTE (1 << 19)
542 #define SSCR1_RSRE (1 << 20)
543 #define SSCR1_TSRE (1 << 21)
544 #define SSCR1_EBCEI (1 << 29)
545 #define SSITR_INT (7 << 5)
546 #define SSSR_TNF (1 << 2)
547 #define SSSR_RNE (1 << 3)
548 #define SSSR_TFS (1 << 5)
549 #define SSSR_RFS (1 << 6)
550 #define SSSR_ROR (1 << 7)
551 #define SSSR_PINT (1 << 18)
552 #define SSSR_TINT (1 << 19)
553 #define SSSR_EOC (1 << 20)
554 #define SSSR_TUR (1 << 21)
555 #define SSSR_BCE (1 << 23)
556 #define SSSR_RW 0x00bc0080
558 static void pxa2xx_ssp_int_update(PXA2xxSSPState
*s
)
562 level
|= s
->ssitr
& SSITR_INT
;
563 level
|= (s
->sssr
& SSSR_BCE
) && (s
->sscr
[1] & SSCR1_EBCEI
);
564 level
|= (s
->sssr
& SSSR_TUR
) && !(s
->sscr
[0] & SSCR0_TIM
);
565 level
|= (s
->sssr
& SSSR_EOC
) && (s
->sssr
& (SSSR_TINT
| SSSR_PINT
));
566 level
|= (s
->sssr
& SSSR_TINT
) && (s
->sscr
[1] & SSCR1_TINTE
);
567 level
|= (s
->sssr
& SSSR_PINT
) && (s
->sscr
[1] & SSCR1_PINTE
);
568 level
|= (s
->sssr
& SSSR_ROR
) && !(s
->sscr
[0] & SSCR0_RIM
);
569 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
570 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
571 qemu_set_irq(s
->irq
, !!level
);
574 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState
*s
)
576 s
->sssr
&= ~(0xf << 12); /* Clear RFL */
577 s
->sssr
&= ~(0xf << 8); /* Clear TFL */
578 s
->sssr
&= ~SSSR_TFS
;
579 s
->sssr
&= ~SSSR_TNF
;
581 s
->sssr
|= ((s
->rx_level
- 1) & 0xf) << 12;
582 if (s
->rx_level
>= SSCR1_RFT(s
->sscr
[1]))
585 s
->sssr
&= ~SSSR_RFS
;
589 s
->sssr
&= ~SSSR_RNE
;
590 /* TX FIFO is never filled, so it is always in underrun
591 condition if SSP is enabled */
596 pxa2xx_ssp_int_update(s
);
599 static uint64_t pxa2xx_ssp_read(void *opaque
, hwaddr addr
,
602 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
617 return s
->sssr
| s
->ssitr
;
621 if (s
->rx_level
< 1) {
622 printf("%s: SSP Rx Underrun\n", __FUNCTION__
);
626 retval
= s
->rx_fifo
[s
->rx_start
++];
628 pxa2xx_ssp_fifo_update(s
);
639 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
645 static void pxa2xx_ssp_write(void *opaque
, hwaddr addr
,
646 uint64_t value64
, unsigned size
)
648 PXA2xxSSPState
*s
= (PXA2xxSSPState
*) opaque
;
649 uint32_t value
= value64
;
653 s
->sscr
[0] = value
& 0xc7ffffff;
654 s
->enable
= value
& SSCR0_SSE
;
655 if (value
& SSCR0_MOD
)
656 printf("%s: Attempt to use network mode\n", __FUNCTION__
);
657 if (s
->enable
&& SSCR0_DSS(value
) < 4)
658 printf("%s: Wrong data size: %i bits\n", __FUNCTION__
,
660 if (!(value
& SSCR0_SSE
)) {
665 pxa2xx_ssp_fifo_update(s
);
670 if (value
& (SSCR1_LBM
| SSCR1_EFWR
))
671 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__
);
672 pxa2xx_ssp_fifo_update(s
);
684 s
->ssitr
= value
& SSITR_INT
;
685 pxa2xx_ssp_int_update(s
);
689 s
->sssr
&= ~(value
& SSSR_RW
);
690 pxa2xx_ssp_int_update(s
);
694 if (SSCR0_UWIRE(s
->sscr
[0])) {
695 if (s
->sscr
[1] & SSCR1_MWDS
)
700 /* Note how 32bits overflow does no harm here */
701 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
703 /* Data goes from here to the Tx FIFO and is shifted out from
704 * there directly to the slave, no need to buffer it.
708 readval
= ssi_transfer(s
->bus
, value
);
709 if (s
->rx_level
< 0x10) {
710 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] = readval
;
715 pxa2xx_ssp_fifo_update(s
);
731 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
736 static const MemoryRegionOps pxa2xx_ssp_ops
= {
737 .read
= pxa2xx_ssp_read
,
738 .write
= pxa2xx_ssp_write
,
739 .endianness
= DEVICE_NATIVE_ENDIAN
,
742 static void pxa2xx_ssp_reset(DeviceState
*d
)
744 PXA2xxSSPState
*s
= PXA2XX_SSP(d
);
747 s
->sscr
[0] = s
->sscr
[1] = 0;
755 s
->rx_start
= s
->rx_level
= 0;
758 static int pxa2xx_ssp_init(SysBusDevice
*sbd
)
760 DeviceState
*dev
= DEVICE(sbd
);
761 PXA2xxSSPState
*s
= PXA2XX_SSP(dev
);
763 sysbus_init_irq(sbd
, &s
->irq
);
765 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pxa2xx_ssp_ops
, s
,
766 "pxa2xx-ssp", 0x1000);
767 sysbus_init_mmio(sbd
, &s
->iomem
);
769 s
->bus
= ssi_create_bus(dev
, "ssi");
773 /* Real-Time Clock */
774 #define RCNR 0x00 /* RTC Counter register */
775 #define RTAR 0x04 /* RTC Alarm register */
776 #define RTSR 0x08 /* RTC Status register */
777 #define RTTR 0x0c /* RTC Timer Trim register */
778 #define RDCR 0x10 /* RTC Day Counter register */
779 #define RYCR 0x14 /* RTC Year Counter register */
780 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
781 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
782 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
783 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
784 #define SWCR 0x28 /* RTC Stopwatch Counter register */
785 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
786 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
787 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
788 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
790 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
791 #define PXA2XX_RTC(obj) \
792 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
796 SysBusDevice parent_obj
;
814 uint32_t last_rtcpicr
;
819 QEMUTimer
*rtc_rdal1
;
820 QEMUTimer
*rtc_rdal2
;
821 QEMUTimer
*rtc_swal1
;
822 QEMUTimer
*rtc_swal2
;
827 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState
*s
)
829 qemu_set_irq(s
->rtc_irq
, !!(s
->rtsr
& 0x2553));
832 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState
*s
)
834 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
835 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
836 (1000 * ((s
->rttr
& 0xffff) + 1));
837 s
->last_rdcr
+= ((rt
- s
->last_hz
) << 15) /
838 (1000 * ((s
->rttr
& 0xffff) + 1));
842 static void pxa2xx_rtc_swupdate(PXA2xxRTCState
*s
)
844 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
845 if (s
->rtsr
& (1 << 12))
846 s
->last_swcr
+= (rt
- s
->last_sw
) / 10;
850 static void pxa2xx_rtc_piupdate(PXA2xxRTCState
*s
)
852 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
853 if (s
->rtsr
& (1 << 15))
854 s
->last_swcr
+= rt
- s
->last_pi
;
858 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState
*s
,
861 if ((rtsr
& (1 << 2)) && !(rtsr
& (1 << 0)))
862 timer_mod(s
->rtc_hz
, s
->last_hz
+
863 (((s
->rtar
- s
->last_rcnr
) * 1000 *
864 ((s
->rttr
& 0xffff) + 1)) >> 15));
866 timer_del(s
->rtc_hz
);
868 if ((rtsr
& (1 << 5)) && !(rtsr
& (1 << 4)))
869 timer_mod(s
->rtc_rdal1
, s
->last_hz
+
870 (((s
->rdar1
- s
->last_rdcr
) * 1000 *
871 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
873 timer_del(s
->rtc_rdal1
);
875 if ((rtsr
& (1 << 7)) && !(rtsr
& (1 << 6)))
876 timer_mod(s
->rtc_rdal2
, s
->last_hz
+
877 (((s
->rdar2
- s
->last_rdcr
) * 1000 *
878 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
880 timer_del(s
->rtc_rdal2
);
882 if ((rtsr
& 0x1200) == 0x1200 && !(rtsr
& (1 << 8)))
883 timer_mod(s
->rtc_swal1
, s
->last_sw
+
884 (s
->swar1
- s
->last_swcr
) * 10); /* TODO: fixup */
886 timer_del(s
->rtc_swal1
);
888 if ((rtsr
& 0x1800) == 0x1800 && !(rtsr
& (1 << 10)))
889 timer_mod(s
->rtc_swal2
, s
->last_sw
+
890 (s
->swar2
- s
->last_swcr
) * 10); /* TODO: fixup */
892 timer_del(s
->rtc_swal2
);
894 if ((rtsr
& 0xc000) == 0xc000 && !(rtsr
& (1 << 13)))
895 timer_mod(s
->rtc_pi
, s
->last_pi
+
896 (s
->piar
& 0xffff) - s
->last_rtcpicr
);
898 timer_del(s
->rtc_pi
);
901 static inline void pxa2xx_rtc_hz_tick(void *opaque
)
903 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
905 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
906 pxa2xx_rtc_int_update(s
);
909 static inline void pxa2xx_rtc_rdal1_tick(void *opaque
)
911 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
913 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
914 pxa2xx_rtc_int_update(s
);
917 static inline void pxa2xx_rtc_rdal2_tick(void *opaque
)
919 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
921 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
922 pxa2xx_rtc_int_update(s
);
925 static inline void pxa2xx_rtc_swal1_tick(void *opaque
)
927 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
929 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
930 pxa2xx_rtc_int_update(s
);
933 static inline void pxa2xx_rtc_swal2_tick(void *opaque
)
935 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
936 s
->rtsr
|= (1 << 10);
937 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
938 pxa2xx_rtc_int_update(s
);
941 static inline void pxa2xx_rtc_pi_tick(void *opaque
)
943 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
944 s
->rtsr
|= (1 << 13);
945 pxa2xx_rtc_piupdate(s
);
947 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
948 pxa2xx_rtc_int_update(s
);
951 static uint64_t pxa2xx_rtc_read(void *opaque
, hwaddr addr
,
954 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
978 return s
->last_rcnr
+
979 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
980 (1000 * ((s
->rttr
& 0xffff) + 1));
982 return s
->last_rdcr
+
983 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
984 (1000 * ((s
->rttr
& 0xffff) + 1));
988 if (s
->rtsr
& (1 << 12))
989 return s
->last_swcr
+
990 (qemu_clock_get_ms(rtc_clock
) - s
->last_sw
) / 10;
994 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1000 static void pxa2xx_rtc_write(void *opaque
, hwaddr addr
,
1001 uint64_t value64
, unsigned size
)
1003 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1004 uint32_t value
= value64
;
1008 if (!(s
->rttr
& (1U << 31))) {
1009 pxa2xx_rtc_hzupdate(s
);
1011 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1016 if ((s
->rtsr
^ value
) & (1 << 15))
1017 pxa2xx_rtc_piupdate(s
);
1019 if ((s
->rtsr
^ value
) & (1 << 12))
1020 pxa2xx_rtc_swupdate(s
);
1022 if (((s
->rtsr
^ value
) & 0x4aac) | (value
& ~0xdaac))
1023 pxa2xx_rtc_alarm_update(s
, value
);
1025 s
->rtsr
= (value
& 0xdaac) | (s
->rtsr
& ~(value
& ~0xdaac));
1026 pxa2xx_rtc_int_update(s
);
1031 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1036 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1041 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1046 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1051 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1055 pxa2xx_rtc_swupdate(s
);
1058 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1063 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1068 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1072 pxa2xx_rtc_hzupdate(s
);
1073 s
->last_rcnr
= value
;
1074 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1078 pxa2xx_rtc_hzupdate(s
);
1079 s
->last_rdcr
= value
;
1080 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1084 s
->last_rycr
= value
;
1088 pxa2xx_rtc_swupdate(s
);
1089 s
->last_swcr
= value
;
1090 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1094 pxa2xx_rtc_piupdate(s
);
1095 s
->last_rtcpicr
= value
& 0xffff;
1096 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1100 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1104 static const MemoryRegionOps pxa2xx_rtc_ops
= {
1105 .read
= pxa2xx_rtc_read
,
1106 .write
= pxa2xx_rtc_write
,
1107 .endianness
= DEVICE_NATIVE_ENDIAN
,
1110 static void pxa2xx_rtc_init(Object
*obj
)
1112 PXA2xxRTCState
*s
= PXA2XX_RTC(obj
);
1113 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1120 qemu_get_timedate(&tm
, 0);
1121 wom
= ((tm
.tm_mday
- 1) / 7) + 1;
1123 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
1124 s
->last_rdcr
= (wom
<< 20) | ((tm
.tm_wday
+ 1) << 17) |
1125 (tm
.tm_hour
<< 12) | (tm
.tm_min
<< 6) | tm
.tm_sec
;
1126 s
->last_rycr
= ((tm
.tm_year
+ 1900) << 9) |
1127 ((tm
.tm_mon
+ 1) << 5) | tm
.tm_mday
;
1128 s
->last_swcr
= (tm
.tm_hour
<< 19) |
1129 (tm
.tm_min
<< 13) | (tm
.tm_sec
<< 7);
1130 s
->last_rtcpicr
= 0;
1131 s
->last_hz
= s
->last_sw
= s
->last_pi
= qemu_clock_get_ms(rtc_clock
);
1133 s
->rtc_hz
= timer_new_ms(rtc_clock
, pxa2xx_rtc_hz_tick
, s
);
1134 s
->rtc_rdal1
= timer_new_ms(rtc_clock
, pxa2xx_rtc_rdal1_tick
, s
);
1135 s
->rtc_rdal2
= timer_new_ms(rtc_clock
, pxa2xx_rtc_rdal2_tick
, s
);
1136 s
->rtc_swal1
= timer_new_ms(rtc_clock
, pxa2xx_rtc_swal1_tick
, s
);
1137 s
->rtc_swal2
= timer_new_ms(rtc_clock
, pxa2xx_rtc_swal2_tick
, s
);
1138 s
->rtc_pi
= timer_new_ms(rtc_clock
, pxa2xx_rtc_pi_tick
, s
);
1140 sysbus_init_irq(dev
, &s
->rtc_irq
);
1142 memory_region_init_io(&s
->iomem
, obj
, &pxa2xx_rtc_ops
, s
,
1143 "pxa2xx-rtc", 0x10000);
1144 sysbus_init_mmio(dev
, &s
->iomem
);
1147 static void pxa2xx_rtc_pre_save(void *opaque
)
1149 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1151 pxa2xx_rtc_hzupdate(s
);
1152 pxa2xx_rtc_piupdate(s
);
1153 pxa2xx_rtc_swupdate(s
);
1156 static int pxa2xx_rtc_post_load(void *opaque
, int version_id
)
1158 PXA2xxRTCState
*s
= (PXA2xxRTCState
*) opaque
;
1160 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1165 static const VMStateDescription vmstate_pxa2xx_rtc_regs
= {
1166 .name
= "pxa2xx_rtc",
1168 .minimum_version_id
= 0,
1169 .pre_save
= pxa2xx_rtc_pre_save
,
1170 .post_load
= pxa2xx_rtc_post_load
,
1171 .fields
= (VMStateField
[]) {
1172 VMSTATE_UINT32(rttr
, PXA2xxRTCState
),
1173 VMSTATE_UINT32(rtsr
, PXA2xxRTCState
),
1174 VMSTATE_UINT32(rtar
, PXA2xxRTCState
),
1175 VMSTATE_UINT32(rdar1
, PXA2xxRTCState
),
1176 VMSTATE_UINT32(rdar2
, PXA2xxRTCState
),
1177 VMSTATE_UINT32(ryar1
, PXA2xxRTCState
),
1178 VMSTATE_UINT32(ryar2
, PXA2xxRTCState
),
1179 VMSTATE_UINT32(swar1
, PXA2xxRTCState
),
1180 VMSTATE_UINT32(swar2
, PXA2xxRTCState
),
1181 VMSTATE_UINT32(piar
, PXA2xxRTCState
),
1182 VMSTATE_UINT32(last_rcnr
, PXA2xxRTCState
),
1183 VMSTATE_UINT32(last_rdcr
, PXA2xxRTCState
),
1184 VMSTATE_UINT32(last_rycr
, PXA2xxRTCState
),
1185 VMSTATE_UINT32(last_swcr
, PXA2xxRTCState
),
1186 VMSTATE_UINT32(last_rtcpicr
, PXA2xxRTCState
),
1187 VMSTATE_INT64(last_hz
, PXA2xxRTCState
),
1188 VMSTATE_INT64(last_sw
, PXA2xxRTCState
),
1189 VMSTATE_INT64(last_pi
, PXA2xxRTCState
),
1190 VMSTATE_END_OF_LIST(),
1194 static void pxa2xx_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
1196 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1198 dc
->desc
= "PXA2xx RTC Controller";
1199 dc
->vmsd
= &vmstate_pxa2xx_rtc_regs
;
1202 static const TypeInfo pxa2xx_rtc_sysbus_info
= {
1203 .name
= TYPE_PXA2XX_RTC
,
1204 .parent
= TYPE_SYS_BUS_DEVICE
,
1205 .instance_size
= sizeof(PXA2xxRTCState
),
1206 .instance_init
= pxa2xx_rtc_init
,
1207 .class_init
= pxa2xx_rtc_sysbus_class_init
,
1212 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1213 #define PXA2XX_I2C_SLAVE(obj) \
1214 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1216 typedef struct PXA2xxI2CSlaveState
{
1217 I2CSlave parent_obj
;
1219 PXA2xxI2CState
*host
;
1220 } PXA2xxI2CSlaveState
;
1222 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1223 #define PXA2XX_I2C(obj) \
1224 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1226 struct PXA2xxI2CState
{
1228 SysBusDevice parent_obj
;
1232 PXA2xxI2CSlaveState
*slave
;
1236 uint32_t region_size
;
1244 #define IBMR 0x80 /* I2C Bus Monitor register */
1245 #define IDBR 0x88 /* I2C Data Buffer register */
1246 #define ICR 0x90 /* I2C Control register */
1247 #define ISR 0x98 /* I2C Status register */
1248 #define ISAR 0xa0 /* I2C Slave Address register */
1250 static void pxa2xx_i2c_update(PXA2xxI2CState
*s
)
1253 level
|= s
->status
& s
->control
& (1 << 10); /* BED */
1254 level
|= (s
->status
& (1 << 7)) && (s
->control
& (1 << 9)); /* IRF */
1255 level
|= (s
->status
& (1 << 6)) && (s
->control
& (1 << 8)); /* ITE */
1256 level
|= s
->status
& (1 << 9); /* SAD */
1257 qemu_set_irq(s
->irq
, !!level
);
1260 /* These are only stubs now. */
1261 static int pxa2xx_i2c_event(I2CSlave
*i2c
, enum i2c_event event
)
1263 PXA2xxI2CSlaveState
*slave
= PXA2XX_I2C_SLAVE(i2c
);
1264 PXA2xxI2CState
*s
= slave
->host
;
1267 case I2C_START_SEND
:
1268 s
->status
|= (1 << 9); /* set SAD */
1269 s
->status
&= ~(1 << 0); /* clear RWM */
1271 case I2C_START_RECV
:
1272 s
->status
|= (1 << 9); /* set SAD */
1273 s
->status
|= 1 << 0; /* set RWM */
1276 s
->status
|= (1 << 4); /* set SSD */
1279 s
->status
|= 1 << 1; /* set ACKNAK */
1282 pxa2xx_i2c_update(s
);
1287 static int pxa2xx_i2c_rx(I2CSlave
*i2c
)
1289 PXA2xxI2CSlaveState
*slave
= PXA2XX_I2C_SLAVE(i2c
);
1290 PXA2xxI2CState
*s
= slave
->host
;
1292 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6))) {
1296 if (s
->status
& (1 << 0)) { /* RWM */
1297 s
->status
|= 1 << 6; /* set ITE */
1299 pxa2xx_i2c_update(s
);
1304 static int pxa2xx_i2c_tx(I2CSlave
*i2c
, uint8_t data
)
1306 PXA2xxI2CSlaveState
*slave
= PXA2XX_I2C_SLAVE(i2c
);
1307 PXA2xxI2CState
*s
= slave
->host
;
1309 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6))) {
1313 if (!(s
->status
& (1 << 0))) { /* RWM */
1314 s
->status
|= 1 << 7; /* set IRF */
1317 pxa2xx_i2c_update(s
);
1322 static uint64_t pxa2xx_i2c_read(void *opaque
, hwaddr addr
,
1325 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1333 return s
->status
| (i2c_bus_busy(s
->bus
) << 2);
1335 slave
= I2C_SLAVE(s
->slave
);
1336 return slave
->address
;
1340 if (s
->status
& (1 << 2))
1341 s
->ibmr
^= 3; /* Fake SCL and SDA pin changes */
1346 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1352 static void pxa2xx_i2c_write(void *opaque
, hwaddr addr
,
1353 uint64_t value64
, unsigned size
)
1355 PXA2xxI2CState
*s
= (PXA2xxI2CState
*) opaque
;
1356 uint32_t value
= value64
;
1362 s
->control
= value
& 0xfff7;
1363 if ((value
& (1 << 3)) && (value
& (1 << 6))) { /* TB and IUE */
1364 /* TODO: slave mode */
1365 if (value
& (1 << 0)) { /* START condition */
1367 s
->status
|= 1 << 0; /* set RWM */
1369 s
->status
&= ~(1 << 0); /* clear RWM */
1370 ack
= !i2c_start_transfer(s
->bus
, s
->data
>> 1, s
->data
& 1);
1372 if (s
->status
& (1 << 0)) { /* RWM */
1373 s
->data
= i2c_recv(s
->bus
);
1374 if (value
& (1 << 2)) /* ACKNAK */
1378 ack
= !i2c_send(s
->bus
, s
->data
);
1381 if (value
& (1 << 1)) /* STOP condition */
1382 i2c_end_transfer(s
->bus
);
1385 if (value
& (1 << 0)) /* START condition */
1386 s
->status
|= 1 << 6; /* set ITE */
1388 if (s
->status
& (1 << 0)) /* RWM */
1389 s
->status
|= 1 << 7; /* set IRF */
1391 s
->status
|= 1 << 6; /* set ITE */
1392 s
->status
&= ~(1 << 1); /* clear ACKNAK */
1394 s
->status
|= 1 << 6; /* set ITE */
1395 s
->status
|= 1 << 10; /* set BED */
1396 s
->status
|= 1 << 1; /* set ACKNAK */
1399 if (!(value
& (1 << 3)) && (value
& (1 << 6))) /* !TB and IUE */
1400 if (value
& (1 << 4)) /* MA */
1401 i2c_end_transfer(s
->bus
);
1402 pxa2xx_i2c_update(s
);
1406 s
->status
&= ~(value
& 0x07f0);
1407 pxa2xx_i2c_update(s
);
1411 i2c_set_slave_address(I2C_SLAVE(s
->slave
), value
& 0x7f);
1415 s
->data
= value
& 0xff;
1419 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1423 static const MemoryRegionOps pxa2xx_i2c_ops
= {
1424 .read
= pxa2xx_i2c_read
,
1425 .write
= pxa2xx_i2c_write
,
1426 .endianness
= DEVICE_NATIVE_ENDIAN
,
1429 static const VMStateDescription vmstate_pxa2xx_i2c_slave
= {
1430 .name
= "pxa2xx_i2c_slave",
1432 .minimum_version_id
= 1,
1433 .fields
= (VMStateField
[]) {
1434 VMSTATE_I2C_SLAVE(parent_obj
, PXA2xxI2CSlaveState
),
1435 VMSTATE_END_OF_LIST()
1439 static const VMStateDescription vmstate_pxa2xx_i2c
= {
1440 .name
= "pxa2xx_i2c",
1442 .minimum_version_id
= 1,
1443 .fields
= (VMStateField
[]) {
1444 VMSTATE_UINT16(control
, PXA2xxI2CState
),
1445 VMSTATE_UINT16(status
, PXA2xxI2CState
),
1446 VMSTATE_UINT8(ibmr
, PXA2xxI2CState
),
1447 VMSTATE_UINT8(data
, PXA2xxI2CState
),
1448 VMSTATE_STRUCT_POINTER(slave
, PXA2xxI2CState
,
1449 vmstate_pxa2xx_i2c_slave
, PXA2xxI2CSlaveState
),
1450 VMSTATE_END_OF_LIST()
1454 static void pxa2xx_i2c_slave_class_init(ObjectClass
*klass
, void *data
)
1456 I2CSlaveClass
*k
= I2C_SLAVE_CLASS(klass
);
1458 k
->event
= pxa2xx_i2c_event
;
1459 k
->recv
= pxa2xx_i2c_rx
;
1460 k
->send
= pxa2xx_i2c_tx
;
1463 static const TypeInfo pxa2xx_i2c_slave_info
= {
1464 .name
= TYPE_PXA2XX_I2C_SLAVE
,
1465 .parent
= TYPE_I2C_SLAVE
,
1466 .instance_size
= sizeof(PXA2xxI2CSlaveState
),
1467 .class_init
= pxa2xx_i2c_slave_class_init
,
1470 PXA2xxI2CState
*pxa2xx_i2c_init(hwaddr base
,
1471 qemu_irq irq
, uint32_t region_size
)
1474 SysBusDevice
*i2c_dev
;
1478 dev
= qdev_create(NULL
, TYPE_PXA2XX_I2C
);
1479 qdev_prop_set_uint32(dev
, "size", region_size
+ 1);
1480 qdev_prop_set_uint32(dev
, "offset", base
& region_size
);
1481 qdev_init_nofail(dev
);
1483 i2c_dev
= SYS_BUS_DEVICE(dev
);
1484 sysbus_mmio_map(i2c_dev
, 0, base
& ~region_size
);
1485 sysbus_connect_irq(i2c_dev
, 0, irq
);
1487 s
= PXA2XX_I2C(i2c_dev
);
1488 /* FIXME: Should the slave device really be on a separate bus? */
1489 i2cbus
= i2c_init_bus(dev
, "dummy");
1490 dev
= i2c_create_slave(i2cbus
, TYPE_PXA2XX_I2C_SLAVE
, 0);
1491 s
->slave
= PXA2XX_I2C_SLAVE(dev
);
1497 static void pxa2xx_i2c_initfn(Object
*obj
)
1499 DeviceState
*dev
= DEVICE(obj
);
1500 PXA2xxI2CState
*s
= PXA2XX_I2C(obj
);
1501 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1503 s
->bus
= i2c_init_bus(dev
, NULL
);
1505 memory_region_init_io(&s
->iomem
, obj
, &pxa2xx_i2c_ops
, s
,
1506 "pxa2xx-i2c", s
->region_size
);
1507 sysbus_init_mmio(sbd
, &s
->iomem
);
1508 sysbus_init_irq(sbd
, &s
->irq
);
1511 I2CBus
*pxa2xx_i2c_bus(PXA2xxI2CState
*s
)
1516 static Property pxa2xx_i2c_properties
[] = {
1517 DEFINE_PROP_UINT32("size", PXA2xxI2CState
, region_size
, 0x10000),
1518 DEFINE_PROP_UINT32("offset", PXA2xxI2CState
, offset
, 0),
1519 DEFINE_PROP_END_OF_LIST(),
1522 static void pxa2xx_i2c_class_init(ObjectClass
*klass
, void *data
)
1524 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1526 dc
->desc
= "PXA2xx I2C Bus Controller";
1527 dc
->vmsd
= &vmstate_pxa2xx_i2c
;
1528 dc
->props
= pxa2xx_i2c_properties
;
1531 static const TypeInfo pxa2xx_i2c_info
= {
1532 .name
= TYPE_PXA2XX_I2C
,
1533 .parent
= TYPE_SYS_BUS_DEVICE
,
1534 .instance_size
= sizeof(PXA2xxI2CState
),
1535 .instance_init
= pxa2xx_i2c_initfn
,
1536 .class_init
= pxa2xx_i2c_class_init
,
1539 /* PXA Inter-IC Sound Controller */
1540 static void pxa2xx_i2s_reset(PXA2xxI2SState
*i2s
)
1546 i2s
->control
[0] = 0x00;
1547 i2s
->control
[1] = 0x00;
1552 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1553 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1554 #define SACR_DREC(val) (val & (1 << 3))
1555 #define SACR_DPRL(val) (val & (1 << 4))
1557 static inline void pxa2xx_i2s_update(PXA2xxI2SState
*i2s
)
1560 rfs
= SACR_RFTH(i2s
->control
[0]) < i2s
->rx_len
&&
1561 !SACR_DREC(i2s
->control
[1]);
1562 tfs
= (i2s
->tx_len
|| i2s
->fifo_len
< SACR_TFTH(i2s
->control
[0])) &&
1563 i2s
->enable
&& !SACR_DPRL(i2s
->control
[1]);
1565 qemu_set_irq(i2s
->rx_dma
, rfs
);
1566 qemu_set_irq(i2s
->tx_dma
, tfs
);
1568 i2s
->status
&= 0xe0;
1569 if (i2s
->fifo_len
< 16 || !i2s
->enable
)
1570 i2s
->status
|= 1 << 0; /* TNF */
1572 i2s
->status
|= 1 << 1; /* RNE */
1574 i2s
->status
|= 1 << 2; /* BSY */
1576 i2s
->status
|= 1 << 3; /* TFS */
1578 i2s
->status
|= 1 << 4; /* RFS */
1579 if (!(i2s
->tx_len
&& i2s
->enable
))
1580 i2s
->status
|= i2s
->fifo_len
<< 8; /* TFL */
1581 i2s
->status
|= MAX(i2s
->rx_len
, 0xf) << 12; /* RFL */
1583 qemu_set_irq(i2s
->irq
, i2s
->status
& i2s
->mask
);
1586 #define SACR0 0x00 /* Serial Audio Global Control register */
1587 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1588 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1589 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1590 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1591 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1592 #define SADR 0x80 /* Serial Audio Data register */
1594 static uint64_t pxa2xx_i2s_read(void *opaque
, hwaddr addr
,
1597 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1601 return s
->control
[0];
1603 return s
->control
[1];
1613 if (s
->rx_len
> 0) {
1615 pxa2xx_i2s_update(s
);
1616 return s
->codec_in(s
->opaque
);
1620 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1626 static void pxa2xx_i2s_write(void *opaque
, hwaddr addr
,
1627 uint64_t value
, unsigned size
)
1629 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1634 if (value
& (1 << 3)) /* RST */
1635 pxa2xx_i2s_reset(s
);
1636 s
->control
[0] = value
& 0xff3d;
1637 if (!s
->enable
&& (value
& 1) && s
->tx_len
) { /* ENB */
1638 for (sample
= s
->fifo
; s
->fifo_len
> 0; s
->fifo_len
--, sample
++)
1639 s
->codec_out(s
->opaque
, *sample
);
1640 s
->status
&= ~(1 << 7); /* I2SOFF */
1642 if (value
& (1 << 4)) /* EFWR */
1643 printf("%s: Attempt to use special function\n", __FUNCTION__
);
1644 s
->enable
= (value
& 9) == 1; /* ENB && !RST*/
1645 pxa2xx_i2s_update(s
);
1648 s
->control
[1] = value
& 0x0039;
1649 if (value
& (1 << 5)) /* ENLBF */
1650 printf("%s: Attempt to use loopback function\n", __FUNCTION__
);
1651 if (value
& (1 << 4)) /* DPRL */
1653 pxa2xx_i2s_update(s
);
1656 s
->mask
= value
& 0x0078;
1657 pxa2xx_i2s_update(s
);
1660 s
->status
&= ~(value
& (3 << 5));
1661 pxa2xx_i2s_update(s
);
1664 s
->clk
= value
& 0x007f;
1667 if (s
->tx_len
&& s
->enable
) {
1669 pxa2xx_i2s_update(s
);
1670 s
->codec_out(s
->opaque
, value
);
1671 } else if (s
->fifo_len
< 16) {
1672 s
->fifo
[s
->fifo_len
++] = value
;
1673 pxa2xx_i2s_update(s
);
1677 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1681 static const MemoryRegionOps pxa2xx_i2s_ops
= {
1682 .read
= pxa2xx_i2s_read
,
1683 .write
= pxa2xx_i2s_write
,
1684 .endianness
= DEVICE_NATIVE_ENDIAN
,
1687 static const VMStateDescription vmstate_pxa2xx_i2s
= {
1688 .name
= "pxa2xx_i2s",
1690 .minimum_version_id
= 0,
1691 .fields
= (VMStateField
[]) {
1692 VMSTATE_UINT32_ARRAY(control
, PXA2xxI2SState
, 2),
1693 VMSTATE_UINT32(status
, PXA2xxI2SState
),
1694 VMSTATE_UINT32(mask
, PXA2xxI2SState
),
1695 VMSTATE_UINT32(clk
, PXA2xxI2SState
),
1696 VMSTATE_INT32(enable
, PXA2xxI2SState
),
1697 VMSTATE_INT32(rx_len
, PXA2xxI2SState
),
1698 VMSTATE_INT32(tx_len
, PXA2xxI2SState
),
1699 VMSTATE_INT32(fifo_len
, PXA2xxI2SState
),
1700 VMSTATE_END_OF_LIST()
1704 static void pxa2xx_i2s_data_req(void *opaque
, int tx
, int rx
)
1706 PXA2xxI2SState
*s
= (PXA2xxI2SState
*) opaque
;
1709 /* Signal FIFO errors */
1710 if (s
->enable
&& s
->tx_len
)
1711 s
->status
|= 1 << 5; /* TUR */
1712 if (s
->enable
&& s
->rx_len
)
1713 s
->status
|= 1 << 6; /* ROR */
1715 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1716 * handle the cases where it makes a difference. */
1717 s
->tx_len
= tx
- s
->fifo_len
;
1719 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1721 for (sample
= s
->fifo
; s
->fifo_len
; s
->fifo_len
--, sample
++)
1722 s
->codec_out(s
->opaque
, *sample
);
1723 pxa2xx_i2s_update(s
);
1726 static PXA2xxI2SState
*pxa2xx_i2s_init(MemoryRegion
*sysmem
,
1728 qemu_irq irq
, qemu_irq rx_dma
, qemu_irq tx_dma
)
1730 PXA2xxI2SState
*s
= g_new0(PXA2xxI2SState
, 1);
1735 s
->data_req
= pxa2xx_i2s_data_req
;
1737 pxa2xx_i2s_reset(s
);
1739 memory_region_init_io(&s
->iomem
, NULL
, &pxa2xx_i2s_ops
, s
,
1740 "pxa2xx-i2s", 0x100000);
1741 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);
1743 vmstate_register(NULL
, base
, &vmstate_pxa2xx_i2s
, s
);
1748 /* PXA Fast Infra-red Communications Port */
1749 #define TYPE_PXA2XX_FIR "pxa2xx-fir"
1750 #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
1752 struct PXA2xxFIrState
{
1754 SysBusDevice parent_obj
;
1769 uint8_t rx_fifo
[64];
1772 static void pxa2xx_fir_reset(DeviceState
*d
)
1774 PXA2xxFIrState
*s
= PXA2XX_FIR(d
);
1776 s
->control
[0] = 0x00;
1777 s
->control
[1] = 0x00;
1778 s
->control
[2] = 0x00;
1779 s
->status
[0] = 0x00;
1780 s
->status
[1] = 0x00;
1784 static inline void pxa2xx_fir_update(PXA2xxFIrState
*s
)
1786 static const int tresh
[4] = { 8, 16, 32, 0 };
1788 if ((s
->control
[0] & (1 << 4)) && /* RXE */
1789 s
->rx_len
>= tresh
[s
->control
[2] & 3]) /* TRIG */
1790 s
->status
[0] |= 1 << 4; /* RFS */
1792 s
->status
[0] &= ~(1 << 4); /* RFS */
1793 if (s
->control
[0] & (1 << 3)) /* TXE */
1794 s
->status
[0] |= 1 << 3; /* TFS */
1796 s
->status
[0] &= ~(1 << 3); /* TFS */
1798 s
->status
[1] |= 1 << 2; /* RNE */
1800 s
->status
[1] &= ~(1 << 2); /* RNE */
1801 if (s
->control
[0] & (1 << 4)) /* RXE */
1802 s
->status
[1] |= 1 << 0; /* RSY */
1804 s
->status
[1] &= ~(1 << 0); /* RSY */
1806 intr
|= (s
->control
[0] & (1 << 5)) && /* RIE */
1807 (s
->status
[0] & (1 << 4)); /* RFS */
1808 intr
|= (s
->control
[0] & (1 << 6)) && /* TIE */
1809 (s
->status
[0] & (1 << 3)); /* TFS */
1810 intr
|= (s
->control
[2] & (1 << 4)) && /* TRAIL */
1811 (s
->status
[0] & (1 << 6)); /* EOC */
1812 intr
|= (s
->control
[0] & (1 << 2)) && /* TUS */
1813 (s
->status
[0] & (1 << 1)); /* TUR */
1814 intr
|= s
->status
[0] & 0x25; /* FRE, RAB, EIF */
1816 qemu_set_irq(s
->rx_dma
, (s
->status
[0] >> 4) & 1);
1817 qemu_set_irq(s
->tx_dma
, (s
->status
[0] >> 3) & 1);
1819 qemu_set_irq(s
->irq
, intr
&& s
->enable
);
1822 #define ICCR0 0x00 /* FICP Control register 0 */
1823 #define ICCR1 0x04 /* FICP Control register 1 */
1824 #define ICCR2 0x08 /* FICP Control register 2 */
1825 #define ICDR 0x0c /* FICP Data register */
1826 #define ICSR0 0x14 /* FICP Status register 0 */
1827 #define ICSR1 0x18 /* FICP Status register 1 */
1828 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1830 static uint64_t pxa2xx_fir_read(void *opaque
, hwaddr addr
,
1833 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1838 return s
->control
[0];
1840 return s
->control
[1];
1842 return s
->control
[2];
1844 s
->status
[0] &= ~0x01;
1845 s
->status
[1] &= ~0x72;
1848 ret
= s
->rx_fifo
[s
->rx_start
++];
1850 pxa2xx_fir_update(s
);
1853 printf("%s: Rx FIFO underrun.\n", __FUNCTION__
);
1856 return s
->status
[0];
1858 return s
->status
[1] | (1 << 3); /* TNF */
1862 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1868 static void pxa2xx_fir_write(void *opaque
, hwaddr addr
,
1869 uint64_t value64
, unsigned size
)
1871 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1872 uint32_t value
= value64
;
1877 s
->control
[0] = value
;
1878 if (!(value
& (1 << 4))) /* RXE */
1879 s
->rx_len
= s
->rx_start
= 0;
1880 if (!(value
& (1 << 3))) { /* TXE */
1883 s
->enable
= value
& 1; /* ITR */
1886 pxa2xx_fir_update(s
);
1889 s
->control
[1] = value
;
1892 s
->control
[2] = value
& 0x3f;
1893 pxa2xx_fir_update(s
);
1896 if (s
->control
[2] & (1 << 2)) { /* TXP */
1901 if (s
->enable
&& (s
->control
[0] & (1 << 3))) { /* TXE */
1902 /* XXX this blocks entire thread. Rewrite to use
1903 * qemu_chr_fe_write and background I/O callbacks */
1904 qemu_chr_fe_write_all(&s
->chr
, &ch
, 1);
1908 s
->status
[0] &= ~(value
& 0x66);
1909 pxa2xx_fir_update(s
);
1914 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1918 static const MemoryRegionOps pxa2xx_fir_ops
= {
1919 .read
= pxa2xx_fir_read
,
1920 .write
= pxa2xx_fir_write
,
1921 .endianness
= DEVICE_NATIVE_ENDIAN
,
1924 static int pxa2xx_fir_is_empty(void *opaque
)
1926 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1927 return (s
->rx_len
< 64);
1930 static void pxa2xx_fir_rx(void *opaque
, const uint8_t *buf
, int size
)
1932 PXA2xxFIrState
*s
= (PXA2xxFIrState
*) opaque
;
1933 if (!(s
->control
[0] & (1 << 4))) /* RXE */
1937 s
->status
[1] |= 1 << 4; /* EOF */
1938 if (s
->rx_len
>= 64) {
1939 s
->status
[1] |= 1 << 6; /* ROR */
1943 if (s
->control
[2] & (1 << 3)) /* RXP */
1944 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = *(buf
++);
1946 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = ~*(buf
++);
1949 pxa2xx_fir_update(s
);
1952 static void pxa2xx_fir_event(void *opaque
, int event
)
1956 static void pxa2xx_fir_instance_init(Object
*obj
)
1958 PXA2xxFIrState
*s
= PXA2XX_FIR(obj
);
1959 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1961 memory_region_init_io(&s
->iomem
, obj
, &pxa2xx_fir_ops
, s
,
1962 "pxa2xx-fir", 0x1000);
1963 sysbus_init_mmio(sbd
, &s
->iomem
);
1964 sysbus_init_irq(sbd
, &s
->irq
);
1965 sysbus_init_irq(sbd
, &s
->rx_dma
);
1966 sysbus_init_irq(sbd
, &s
->tx_dma
);
1969 static void pxa2xx_fir_realize(DeviceState
*dev
, Error
**errp
)
1971 PXA2xxFIrState
*s
= PXA2XX_FIR(dev
);
1973 qemu_chr_fe_set_handlers(&s
->chr
, pxa2xx_fir_is_empty
,
1974 pxa2xx_fir_rx
, pxa2xx_fir_event
, s
, NULL
, true);
1977 static bool pxa2xx_fir_vmstate_validate(void *opaque
, int version_id
)
1979 PXA2xxFIrState
*s
= opaque
;
1981 return s
->rx_start
< ARRAY_SIZE(s
->rx_fifo
);
1984 static const VMStateDescription pxa2xx_fir_vmsd
= {
1985 .name
= "pxa2xx-fir",
1987 .minimum_version_id
= 1,
1988 .fields
= (VMStateField
[]) {
1989 VMSTATE_UINT32(enable
, PXA2xxFIrState
),
1990 VMSTATE_UINT8_ARRAY(control
, PXA2xxFIrState
, 3),
1991 VMSTATE_UINT8_ARRAY(status
, PXA2xxFIrState
, 2),
1992 VMSTATE_UINT32(rx_len
, PXA2xxFIrState
),
1993 VMSTATE_UINT32(rx_start
, PXA2xxFIrState
),
1994 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate
),
1995 VMSTATE_UINT8_ARRAY(rx_fifo
, PXA2xxFIrState
, 64),
1996 VMSTATE_END_OF_LIST()
2000 static Property pxa2xx_fir_properties
[] = {
2001 DEFINE_PROP_CHR("chardev", PXA2xxFIrState
, chr
),
2002 DEFINE_PROP_END_OF_LIST(),
2005 static void pxa2xx_fir_class_init(ObjectClass
*klass
, void *data
)
2007 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2009 dc
->realize
= pxa2xx_fir_realize
;
2010 dc
->vmsd
= &pxa2xx_fir_vmsd
;
2011 dc
->props
= pxa2xx_fir_properties
;
2012 dc
->reset
= pxa2xx_fir_reset
;
2015 static const TypeInfo pxa2xx_fir_info
= {
2016 .name
= TYPE_PXA2XX_FIR
,
2017 .parent
= TYPE_SYS_BUS_DEVICE
,
2018 .instance_size
= sizeof(PXA2xxFIrState
),
2019 .class_init
= pxa2xx_fir_class_init
,
2020 .instance_init
= pxa2xx_fir_instance_init
,
2023 static PXA2xxFIrState
*pxa2xx_fir_init(MemoryRegion
*sysmem
,
2025 qemu_irq irq
, qemu_irq rx_dma
,
2027 CharDriverState
*chr
)
2032 dev
= qdev_create(NULL
, TYPE_PXA2XX_FIR
);
2033 qdev_prop_set_chr(dev
, "chardev", chr
);
2034 qdev_init_nofail(dev
);
2035 sbd
= SYS_BUS_DEVICE(dev
);
2036 sysbus_mmio_map(sbd
, 0, base
);
2037 sysbus_connect_irq(sbd
, 0, irq
);
2038 sysbus_connect_irq(sbd
, 1, rx_dma
);
2039 sysbus_connect_irq(sbd
, 2, tx_dma
);
2040 return PXA2XX_FIR(dev
);
2043 static void pxa2xx_reset(void *opaque
, int line
, int level
)
2045 PXA2xxState
*s
= (PXA2xxState
*) opaque
;
2047 if (level
&& (s
->pm_regs
[PCFR
>> 2] & 0x10)) { /* GPR_EN */
2048 cpu_reset(CPU(s
->cpu
));
2049 /* TODO: reset peripherals */
2053 /* Initialise a PXA270 integrated chip (ARM based core). */
2054 PXA2xxState
*pxa270_init(MemoryRegion
*address_space
,
2055 unsigned int sdram_size
, const char *revision
)
2060 s
= g_new0(PXA2xxState
, 1);
2062 if (revision
&& strncmp(revision
, "pxa27", 5)) {
2063 fprintf(stderr
, "Machine requires a PXA27x processor.\n");
2067 revision
= "pxa270";
2069 s
->cpu
= cpu_arm_init(revision
);
2070 if (s
->cpu
== NULL
) {
2071 fprintf(stderr
, "Unable to find CPU definition\n");
2074 s
->reset
= qemu_allocate_irq(pxa2xx_reset
, s
, 0);
2076 /* SDRAM & Internal Memory Storage */
2077 memory_region_init_ram(&s
->sdram
, NULL
, "pxa270.sdram", sdram_size
,
2079 vmstate_register_ram_global(&s
->sdram
);
2080 memory_region_add_subregion(address_space
, PXA2XX_SDRAM_BASE
, &s
->sdram
);
2081 memory_region_init_ram(&s
->internal
, NULL
, "pxa270.internal", 0x40000,
2083 vmstate_register_ram_global(&s
->internal
);
2084 memory_region_add_subregion(address_space
, PXA2XX_INTERNAL_BASE
,
2087 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->cpu
);
2089 s
->dma
= pxa27x_dma_init(0x40000000,
2090 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_DMA
));
2092 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2093 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 0),
2094 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 1),
2095 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 2),
2096 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 3),
2097 qdev_get_gpio_in(s
->pic
, PXA27X_PIC_OST_4_11
),
2100 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->cpu
, s
->pic
, 121);
2102 dinfo
= drive_get(IF_SD
, 0, 0);
2104 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2107 s
->mmc
= pxa2xx_mmci_init(address_space
, 0x41100000,
2108 blk_by_legacy_dinfo(dinfo
),
2109 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_MMC
),
2110 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_MMCI
),
2111 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_MMCI
));
2113 for (i
= 0; pxa270_serial
[i
].io_base
; i
++) {
2114 if (serial_hds
[i
]) {
2115 serial_mm_init(address_space
, pxa270_serial
[i
].io_base
, 2,
2116 qdev_get_gpio_in(s
->pic
, pxa270_serial
[i
].irqn
),
2117 14857000 / 16, serial_hds
[i
],
2118 DEVICE_NATIVE_ENDIAN
);
2124 s
->fir
= pxa2xx_fir_init(address_space
, 0x40800000,
2125 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_ICP
),
2126 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_ICP
),
2127 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_ICP
),
2130 s
->lcd
= pxa2xx_lcdc_init(address_space
, 0x44000000,
2131 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_LCD
));
2133 s
->cm_base
= 0x41300000;
2134 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2135 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2136 memory_region_init_io(&s
->cm_iomem
, NULL
, &pxa2xx_cm_ops
, s
, "pxa2xx-cm", 0x1000);
2137 memory_region_add_subregion(address_space
, s
->cm_base
, &s
->cm_iomem
);
2138 vmstate_register(NULL
, 0, &vmstate_pxa2xx_cm
, s
);
2140 pxa2xx_setup_cp14(s
);
2142 s
->mm_base
= 0x48000000;
2143 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2144 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2145 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2146 memory_region_init_io(&s
->mm_iomem
, NULL
, &pxa2xx_mm_ops
, s
, "pxa2xx-mm", 0x1000);
2147 memory_region_add_subregion(address_space
, s
->mm_base
, &s
->mm_iomem
);
2148 vmstate_register(NULL
, 0, &vmstate_pxa2xx_mm
, s
);
2150 s
->pm_base
= 0x40f00000;
2151 memory_region_init_io(&s
->pm_iomem
, NULL
, &pxa2xx_pm_ops
, s
, "pxa2xx-pm", 0x100);
2152 memory_region_add_subregion(address_space
, s
->pm_base
, &s
->pm_iomem
);
2153 vmstate_register(NULL
, 0, &vmstate_pxa2xx_pm
, s
);
2155 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++);
2156 s
->ssp
= g_new0(SSIBus
*, i
);
2157 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++) {
2159 dev
= sysbus_create_simple(TYPE_PXA2XX_SSP
, pxa27x_ssp
[i
].io_base
,
2160 qdev_get_gpio_in(s
->pic
, pxa27x_ssp
[i
].irqn
));
2161 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2164 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2165 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_USBH1
));
2167 s
->pcmcia
[0] = pxa2xx_pcmcia_init(address_space
, 0x20000000);
2168 s
->pcmcia
[1] = pxa2xx_pcmcia_init(address_space
, 0x30000000);
2170 sysbus_create_simple(TYPE_PXA2XX_RTC
, 0x40900000,
2171 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_RTCALARM
));
2173 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600,
2174 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2C
), 0xffff);
2175 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100,
2176 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_PWRI2C
), 0xff);
2178 s
->i2s
= pxa2xx_i2s_init(address_space
, 0x40400000,
2179 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2S
),
2180 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_I2S
),
2181 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_I2S
));
2183 s
->kp
= pxa27x_keypad_init(address_space
, 0x41500000,
2184 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_KEYPAD
));
2186 /* GPIO1 resets the processor */
2187 /* The handler can be overridden by board-specific code */
2188 qdev_connect_gpio_out(s
->gpio
, 1, s
->reset
);
2192 /* Initialise a PXA255 integrated chip (ARM based core). */
2193 PXA2xxState
*pxa255_init(MemoryRegion
*address_space
, unsigned int sdram_size
)
2199 s
= g_new0(PXA2xxState
, 1);
2201 s
->cpu
= cpu_arm_init("pxa255");
2202 if (s
->cpu
== NULL
) {
2203 fprintf(stderr
, "Unable to find CPU definition\n");
2206 s
->reset
= qemu_allocate_irq(pxa2xx_reset
, s
, 0);
2208 /* SDRAM & Internal Memory Storage */
2209 memory_region_init_ram(&s
->sdram
, NULL
, "pxa255.sdram", sdram_size
,
2211 vmstate_register_ram_global(&s
->sdram
);
2212 memory_region_add_subregion(address_space
, PXA2XX_SDRAM_BASE
, &s
->sdram
);
2213 memory_region_init_ram(&s
->internal
, NULL
, "pxa255.internal",
2214 PXA2XX_INTERNAL_SIZE
, &error_fatal
);
2215 vmstate_register_ram_global(&s
->internal
);
2216 memory_region_add_subregion(address_space
, PXA2XX_INTERNAL_BASE
,
2219 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->cpu
);
2221 s
->dma
= pxa255_dma_init(0x40000000,
2222 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_DMA
));
2224 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2225 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 0),
2226 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 1),
2227 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 2),
2228 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_OST_0
+ 3),
2231 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->cpu
, s
->pic
, 85);
2233 dinfo
= drive_get(IF_SD
, 0, 0);
2235 fprintf(stderr
, "qemu: missing SecureDigital device\n");
2238 s
->mmc
= pxa2xx_mmci_init(address_space
, 0x41100000,
2239 blk_by_legacy_dinfo(dinfo
),
2240 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_MMC
),
2241 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_MMCI
),
2242 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_MMCI
));
2244 for (i
= 0; pxa255_serial
[i
].io_base
; i
++) {
2245 if (serial_hds
[i
]) {
2246 serial_mm_init(address_space
, pxa255_serial
[i
].io_base
, 2,
2247 qdev_get_gpio_in(s
->pic
, pxa255_serial
[i
].irqn
),
2248 14745600 / 16, serial_hds
[i
],
2249 DEVICE_NATIVE_ENDIAN
);
2255 s
->fir
= pxa2xx_fir_init(address_space
, 0x40800000,
2256 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_ICP
),
2257 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_ICP
),
2258 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_ICP
),
2261 s
->lcd
= pxa2xx_lcdc_init(address_space
, 0x44000000,
2262 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_LCD
));
2264 s
->cm_base
= 0x41300000;
2265 s
->cm_regs
[CCCR
>> 2] = 0x00000121; /* from datasheet */
2266 s
->cm_regs
[CKEN
>> 2] = 0x00017def; /* from datasheet */
2268 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2269 memory_region_init_io(&s
->cm_iomem
, NULL
, &pxa2xx_cm_ops
, s
, "pxa2xx-cm", 0x1000);
2270 memory_region_add_subregion(address_space
, s
->cm_base
, &s
->cm_iomem
);
2271 vmstate_register(NULL
, 0, &vmstate_pxa2xx_cm
, s
);
2273 pxa2xx_setup_cp14(s
);
2275 s
->mm_base
= 0x48000000;
2276 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2277 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2278 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2279 memory_region_init_io(&s
->mm_iomem
, NULL
, &pxa2xx_mm_ops
, s
, "pxa2xx-mm", 0x1000);
2280 memory_region_add_subregion(address_space
, s
->mm_base
, &s
->mm_iomem
);
2281 vmstate_register(NULL
, 0, &vmstate_pxa2xx_mm
, s
);
2283 s
->pm_base
= 0x40f00000;
2284 memory_region_init_io(&s
->pm_iomem
, NULL
, &pxa2xx_pm_ops
, s
, "pxa2xx-pm", 0x100);
2285 memory_region_add_subregion(address_space
, s
->pm_base
, &s
->pm_iomem
);
2286 vmstate_register(NULL
, 0, &vmstate_pxa2xx_pm
, s
);
2288 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++);
2289 s
->ssp
= g_new0(SSIBus
*, i
);
2290 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++) {
2292 dev
= sysbus_create_simple(TYPE_PXA2XX_SSP
, pxa255_ssp
[i
].io_base
,
2293 qdev_get_gpio_in(s
->pic
, pxa255_ssp
[i
].irqn
));
2294 s
->ssp
[i
] = (SSIBus
*)qdev_get_child_bus(dev
, "ssi");
2297 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2298 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_USBH1
));
2300 s
->pcmcia
[0] = pxa2xx_pcmcia_init(address_space
, 0x20000000);
2301 s
->pcmcia
[1] = pxa2xx_pcmcia_init(address_space
, 0x30000000);
2303 sysbus_create_simple(TYPE_PXA2XX_RTC
, 0x40900000,
2304 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_RTCALARM
));
2306 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600,
2307 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2C
), 0xffff);
2308 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100,
2309 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_PWRI2C
), 0xff);
2311 s
->i2s
= pxa2xx_i2s_init(address_space
, 0x40400000,
2312 qdev_get_gpio_in(s
->pic
, PXA2XX_PIC_I2S
),
2313 qdev_get_gpio_in(s
->dma
, PXA2XX_RX_RQ_I2S
),
2314 qdev_get_gpio_in(s
->dma
, PXA2XX_TX_RQ_I2S
));
2316 /* GPIO1 resets the processor */
2317 /* The handler can be overridden by board-specific code */
2318 qdev_connect_gpio_out(s
->gpio
, 1, s
->reset
);
2322 static void pxa2xx_ssp_class_init(ObjectClass
*klass
, void *data
)
2324 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
2325 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2327 sdc
->init
= pxa2xx_ssp_init
;
2328 dc
->reset
= pxa2xx_ssp_reset
;
2329 dc
->vmsd
= &vmstate_pxa2xx_ssp
;
2332 static const TypeInfo pxa2xx_ssp_info
= {
2333 .name
= TYPE_PXA2XX_SSP
,
2334 .parent
= TYPE_SYS_BUS_DEVICE
,
2335 .instance_size
= sizeof(PXA2xxSSPState
),
2336 .class_init
= pxa2xx_ssp_class_init
,
2339 static void pxa2xx_register_types(void)
2341 type_register_static(&pxa2xx_i2c_slave_info
);
2342 type_register_static(&pxa2xx_ssp_info
);
2343 type_register_static(&pxa2xx_i2c_info
);
2344 type_register_static(&pxa2xx_rtc_sysbus_info
);
2345 type_register_static(&pxa2xx_fir_info
);
2348 type_init(pxa2xx_register_types
)