2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg/tcg-op.h"
27 #include "tcg/tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "qemu/main-loop.h"
30 #include "exec/cpu_ldst.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
35 #include "trace-tcg.h"
36 #include "exec/translator.h"
38 #include "qemu/atomic128.h"
41 #define CPU_SINGLE_STEP 0x1
42 #define CPU_BRANCH_STEP 0x2
43 #define GDBSTUB_SINGLE_STEP 0x4
45 /* Include definitions for instructions classes and implementations flags */
46 /* #define PPC_DEBUG_DISAS */
47 /* #define DO_PPC_STATISTICS */
49 #ifdef PPC_DEBUG_DISAS
50 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
52 # define LOG_DISAS(...) do { } while (0)
54 /*****************************************************************************/
55 /* Code translation helpers */
57 /* global register indexes */
58 static char cpu_reg_names
[10 * 3 + 22 * 4 /* GPR */
59 + 10 * 4 + 22 * 5 /* SPE GPRh */
61 static TCGv cpu_gpr
[32];
62 static TCGv cpu_gprh
[32];
63 static TCGv_i32 cpu_crf
[8];
68 #if defined(TARGET_PPC64)
71 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
, cpu_ov32
, cpu_ca32
;
72 static TCGv cpu_reserve
;
73 static TCGv cpu_reserve_val
;
74 static TCGv cpu_fpscr
;
75 static TCGv_i32 cpu_access_type
;
77 #include "exec/gen-icount.h"
79 void ppc_translate_init(void)
83 size_t cpu_reg_names_size
;
86 cpu_reg_names_size
= sizeof(cpu_reg_names
);
88 for (i
= 0; i
< 8; i
++) {
89 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
90 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
91 offsetof(CPUPPCState
, crf
[i
]), p
);
93 cpu_reg_names_size
-= 5;
96 for (i
= 0; i
< 32; i
++) {
97 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
98 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
99 offsetof(CPUPPCState
, gpr
[i
]), p
);
100 p
+= (i
< 10) ? 3 : 4;
101 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
102 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
103 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
104 offsetof(CPUPPCState
, gprh
[i
]), p
);
105 p
+= (i
< 10) ? 4 : 5;
106 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
109 cpu_nip
= tcg_global_mem_new(cpu_env
,
110 offsetof(CPUPPCState
, nip
), "nip");
112 cpu_msr
= tcg_global_mem_new(cpu_env
,
113 offsetof(CPUPPCState
, msr
), "msr");
115 cpu_ctr
= tcg_global_mem_new(cpu_env
,
116 offsetof(CPUPPCState
, ctr
), "ctr");
118 cpu_lr
= tcg_global_mem_new(cpu_env
,
119 offsetof(CPUPPCState
, lr
), "lr");
121 #if defined(TARGET_PPC64)
122 cpu_cfar
= tcg_global_mem_new(cpu_env
,
123 offsetof(CPUPPCState
, cfar
), "cfar");
126 cpu_xer
= tcg_global_mem_new(cpu_env
,
127 offsetof(CPUPPCState
, xer
), "xer");
128 cpu_so
= tcg_global_mem_new(cpu_env
,
129 offsetof(CPUPPCState
, so
), "SO");
130 cpu_ov
= tcg_global_mem_new(cpu_env
,
131 offsetof(CPUPPCState
, ov
), "OV");
132 cpu_ca
= tcg_global_mem_new(cpu_env
,
133 offsetof(CPUPPCState
, ca
), "CA");
134 cpu_ov32
= tcg_global_mem_new(cpu_env
,
135 offsetof(CPUPPCState
, ov32
), "OV32");
136 cpu_ca32
= tcg_global_mem_new(cpu_env
,
137 offsetof(CPUPPCState
, ca32
), "CA32");
139 cpu_reserve
= tcg_global_mem_new(cpu_env
,
140 offsetof(CPUPPCState
, reserve_addr
),
142 cpu_reserve_val
= tcg_global_mem_new(cpu_env
,
143 offsetof(CPUPPCState
, reserve_val
),
146 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
147 offsetof(CPUPPCState
, fpscr
), "fpscr");
149 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
150 offsetof(CPUPPCState
, access_type
),
154 /* internal defines */
155 struct DisasContext
{
156 DisasContextBase base
;
159 /* Routine used to access memory */
160 bool pr
, hv
, dr
, le_mode
;
162 bool need_access_type
;
165 /* Translation flags */
166 MemOp default_tcg_memop_mask
;
167 #if defined(TARGET_PPC64)
172 bool altivec_enabled
;
178 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
179 int singlestep_enabled
;
181 uint64_t insns_flags
;
182 uint64_t insns_flags2
;
185 /* Return true iff byteswap is needed in a scalar memop */
186 static inline bool need_byteswap(const DisasContext
*ctx
)
188 #if defined(TARGET_WORDS_BIGENDIAN)
191 return !ctx
->le_mode
;
195 /* True when active word size < size of target_long. */
197 # define NARROW_MODE(C) (!(C)->sf_mode)
199 # define NARROW_MODE(C) 0
202 struct opc_handler_t
{
203 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
205 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
207 /* instruction type */
209 /* extended instruction type */
212 void (*handler
)(DisasContext
*ctx
);
213 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
216 #if defined(DO_PPC_STATISTICS)
221 /* SPR load/store helpers */
222 static inline void gen_load_spr(TCGv t
, int reg
)
224 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
227 static inline void gen_store_spr(int reg
, TCGv t
)
229 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
232 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
234 if (ctx
->need_access_type
&& ctx
->access_type
!= access_type
) {
235 tcg_gen_movi_i32(cpu_access_type
, access_type
);
236 ctx
->access_type
= access_type
;
240 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
242 if (NARROW_MODE(ctx
)) {
245 tcg_gen_movi_tl(cpu_nip
, nip
);
248 static void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
253 * These are all synchronous exceptions, we set the PC back to the
254 * faulting instruction
256 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
257 gen_update_nip(ctx
, ctx
->base
.pc_next
- 4);
259 t0
= tcg_const_i32(excp
);
260 t1
= tcg_const_i32(error
);
261 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
262 tcg_temp_free_i32(t0
);
263 tcg_temp_free_i32(t1
);
264 ctx
->exception
= (excp
);
267 static void gen_exception(DisasContext
*ctx
, uint32_t excp
)
272 * These are all synchronous exceptions, we set the PC back to the
273 * faulting instruction
275 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
276 gen_update_nip(ctx
, ctx
->base
.pc_next
- 4);
278 t0
= tcg_const_i32(excp
);
279 gen_helper_raise_exception(cpu_env
, t0
);
280 tcg_temp_free_i32(t0
);
281 ctx
->exception
= (excp
);
284 static void gen_exception_nip(DisasContext
*ctx
, uint32_t excp
,
289 gen_update_nip(ctx
, nip
);
290 t0
= tcg_const_i32(excp
);
291 gen_helper_raise_exception(cpu_env
, t0
);
292 tcg_temp_free_i32(t0
);
293 ctx
->exception
= (excp
);
297 * Tells the caller what is the appropriate exception to generate and prepares
298 * SPR registers for this exception.
300 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
301 * POWERPC_EXCP_DEBUG (on BookE).
303 static uint32_t gen_prep_dbgex(DisasContext
*ctx
)
305 if (ctx
->flags
& POWERPC_FLAG_DE
) {
306 target_ulong dbsr
= 0;
307 if (ctx
->singlestep_enabled
& CPU_SINGLE_STEP
) {
310 /* Must have been branch */
313 TCGv t0
= tcg_temp_new();
314 gen_load_spr(t0
, SPR_BOOKE_DBSR
);
315 tcg_gen_ori_tl(t0
, t0
, dbsr
);
316 gen_store_spr(SPR_BOOKE_DBSR
, t0
);
318 return POWERPC_EXCP_DEBUG
;
320 return POWERPC_EXCP_TRACE
;
324 static void gen_debug_exception(DisasContext
*ctx
)
329 * These are all synchronous exceptions, we set the PC back to the
330 * faulting instruction
332 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
333 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
334 gen_update_nip(ctx
, ctx
->base
.pc_next
);
336 t0
= tcg_const_i32(EXCP_DEBUG
);
337 gen_helper_raise_exception(cpu_env
, t0
);
338 tcg_temp_free_i32(t0
);
341 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
343 /* Will be converted to program check if needed */
344 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
347 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
349 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
352 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
354 /* Will be converted to program check if needed */
355 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
358 /* Stop translation */
359 static inline void gen_stop_exception(DisasContext
*ctx
)
361 gen_update_nip(ctx
, ctx
->base
.pc_next
);
362 ctx
->exception
= POWERPC_EXCP_STOP
;
365 #ifndef CONFIG_USER_ONLY
366 /* No need to update nip here, as execution flow will change */
367 static inline void gen_sync_exception(DisasContext
*ctx
)
369 ctx
->exception
= POWERPC_EXCP_SYNC
;
373 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
374 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
376 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
377 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
379 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
380 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
382 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
383 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
385 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
386 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
388 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
389 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
391 typedef struct opcode_t
{
392 unsigned char opc1
, opc2
, opc3
, opc4
;
393 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
394 unsigned char pad
[4];
396 opc_handler_t handler
;
400 /* Helpers for priv. check */
403 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
406 #if defined(CONFIG_USER_ONLY)
407 #define CHK_HV GEN_PRIV
408 #define CHK_SV GEN_PRIV
409 #define CHK_HVRM GEN_PRIV
413 if (unlikely(ctx->pr || !ctx->hv)) { \
419 if (unlikely(ctx->pr)) { \
425 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
433 /*****************************************************************************/
434 /* PowerPC instructions table */
436 #if defined(DO_PPC_STATISTICS)
437 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
447 .handler = &gen_##name, \
448 .oname = stringify(name), \
450 .oname = stringify(name), \
452 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
463 .handler = &gen_##name, \
464 .oname = stringify(name), \
466 .oname = stringify(name), \
468 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
478 .handler = &gen_##name, \
483 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
496 .oname = stringify(name), \
498 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
508 .handler = &gen_##name, \
514 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
524 .handler = &gen_##name, \
526 .oname = stringify(name), \
528 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
539 .handler = &gen_##name, \
541 .oname = stringify(name), \
543 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
553 .handler = &gen_##name, \
557 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
567 .handler = &gen_##name, \
569 .oname = stringify(name), \
571 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
581 .handler = &gen_##name, \
587 /* Invalid instruction */
588 static void gen_invalid(DisasContext
*ctx
)
590 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
593 static opc_handler_t invalid_handler
= {
594 .inval1
= 0xFFFFFFFF,
595 .inval2
= 0xFFFFFFFF,
598 .handler
= gen_invalid
,
601 /*** Integer comparison ***/
603 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
605 TCGv t0
= tcg_temp_new();
606 TCGv t1
= tcg_temp_new();
607 TCGv_i32 t
= tcg_temp_new_i32();
609 tcg_gen_movi_tl(t0
, CRF_EQ
);
610 tcg_gen_movi_tl(t1
, CRF_LT
);
611 tcg_gen_movcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
),
612 t0
, arg0
, arg1
, t1
, t0
);
613 tcg_gen_movi_tl(t1
, CRF_GT
);
614 tcg_gen_movcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
),
615 t0
, arg0
, arg1
, t1
, t0
);
617 tcg_gen_trunc_tl_i32(t
, t0
);
618 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
619 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t
);
623 tcg_temp_free_i32(t
);
626 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
628 TCGv t0
= tcg_const_tl(arg1
);
629 gen_op_cmp(arg0
, t0
, s
, crf
);
633 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
639 tcg_gen_ext32s_tl(t0
, arg0
);
640 tcg_gen_ext32s_tl(t1
, arg1
);
642 tcg_gen_ext32u_tl(t0
, arg0
);
643 tcg_gen_ext32u_tl(t1
, arg1
);
645 gen_op_cmp(t0
, t1
, s
, crf
);
650 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
652 TCGv t0
= tcg_const_tl(arg1
);
653 gen_op_cmp32(arg0
, t0
, s
, crf
);
657 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
659 if (NARROW_MODE(ctx
)) {
660 gen_op_cmpi32(reg
, 0, 1, 0);
662 gen_op_cmpi(reg
, 0, 1, 0);
667 static void gen_cmp(DisasContext
*ctx
)
669 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
670 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
671 1, crfD(ctx
->opcode
));
673 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
674 1, crfD(ctx
->opcode
));
679 static void gen_cmpi(DisasContext
*ctx
)
681 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
682 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
683 1, crfD(ctx
->opcode
));
685 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
686 1, crfD(ctx
->opcode
));
691 static void gen_cmpl(DisasContext
*ctx
)
693 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
694 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
695 0, crfD(ctx
->opcode
));
697 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
698 0, crfD(ctx
->opcode
));
703 static void gen_cmpli(DisasContext
*ctx
)
705 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
706 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
707 0, crfD(ctx
->opcode
));
709 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
710 0, crfD(ctx
->opcode
));
714 /* cmprb - range comparison: isupper, isaplha, islower*/
715 static void gen_cmprb(DisasContext
*ctx
)
717 TCGv_i32 src1
= tcg_temp_new_i32();
718 TCGv_i32 src2
= tcg_temp_new_i32();
719 TCGv_i32 src2lo
= tcg_temp_new_i32();
720 TCGv_i32 src2hi
= tcg_temp_new_i32();
721 TCGv_i32 crf
= cpu_crf
[crfD(ctx
->opcode
)];
723 tcg_gen_trunc_tl_i32(src1
, cpu_gpr
[rA(ctx
->opcode
)]);
724 tcg_gen_trunc_tl_i32(src2
, cpu_gpr
[rB(ctx
->opcode
)]);
726 tcg_gen_andi_i32(src1
, src1
, 0xFF);
727 tcg_gen_ext8u_i32(src2lo
, src2
);
728 tcg_gen_shri_i32(src2
, src2
, 8);
729 tcg_gen_ext8u_i32(src2hi
, src2
);
731 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
732 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
733 tcg_gen_and_i32(crf
, src2lo
, src2hi
);
735 if (ctx
->opcode
& 0x00200000) {
736 tcg_gen_shri_i32(src2
, src2
, 8);
737 tcg_gen_ext8u_i32(src2lo
, src2
);
738 tcg_gen_shri_i32(src2
, src2
, 8);
739 tcg_gen_ext8u_i32(src2hi
, src2
);
740 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
741 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
742 tcg_gen_and_i32(src2lo
, src2lo
, src2hi
);
743 tcg_gen_or_i32(crf
, crf
, src2lo
);
745 tcg_gen_shli_i32(crf
, crf
, CRF_GT_BIT
);
746 tcg_temp_free_i32(src1
);
747 tcg_temp_free_i32(src2
);
748 tcg_temp_free_i32(src2lo
);
749 tcg_temp_free_i32(src2hi
);
752 #if defined(TARGET_PPC64)
754 static void gen_cmpeqb(DisasContext
*ctx
)
756 gen_helper_cmpeqb(cpu_crf
[crfD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
757 cpu_gpr
[rB(ctx
->opcode
)]);
761 /* isel (PowerPC 2.03 specification) */
762 static void gen_isel(DisasContext
*ctx
)
764 uint32_t bi
= rC(ctx
->opcode
);
765 uint32_t mask
= 0x08 >> (bi
& 0x03);
766 TCGv t0
= tcg_temp_new();
769 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
770 tcg_gen_andi_tl(t0
, t0
, mask
);
772 zr
= tcg_const_tl(0);
773 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
774 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
775 cpu_gpr
[rB(ctx
->opcode
)]);
780 /* cmpb: PowerPC 2.05 specification */
781 static void gen_cmpb(DisasContext
*ctx
)
783 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
784 cpu_gpr
[rB(ctx
->opcode
)]);
787 /*** Integer arithmetic ***/
789 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
790 TCGv arg1
, TCGv arg2
, int sub
)
792 TCGv t0
= tcg_temp_new();
794 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
795 tcg_gen_xor_tl(t0
, arg1
, arg2
);
797 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
799 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
802 if (NARROW_MODE(ctx
)) {
803 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, 31, 1);
804 if (is_isa300(ctx
)) {
805 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
808 if (is_isa300(ctx
)) {
809 tcg_gen_extract_tl(cpu_ov32
, cpu_ov
, 31, 1);
811 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1, 1);
813 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
816 static inline void gen_op_arith_compute_ca32(DisasContext
*ctx
,
817 TCGv res
, TCGv arg0
, TCGv arg1
,
822 if (!is_isa300(ctx
)) {
828 tcg_gen_eqv_tl(t0
, arg0
, arg1
);
830 tcg_gen_xor_tl(t0
, arg0
, arg1
);
832 tcg_gen_xor_tl(t0
, t0
, res
);
833 tcg_gen_extract_tl(ca32
, t0
, 32, 1);
837 /* Common add function */
838 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
839 TCGv arg2
, TCGv ca
, TCGv ca32
,
840 bool add_ca
, bool compute_ca
,
841 bool compute_ov
, bool compute_rc0
)
845 if (compute_ca
|| compute_ov
) {
850 if (NARROW_MODE(ctx
)) {
852 * Caution: a non-obvious corner case of the spec is that
853 * we must produce the *entire* 64-bit addition, but
854 * produce the carry into bit 32.
856 TCGv t1
= tcg_temp_new();
857 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
858 tcg_gen_add_tl(t0
, arg1
, arg2
);
860 tcg_gen_add_tl(t0
, t0
, ca
);
862 tcg_gen_xor_tl(ca
, t0
, t1
); /* bits changed w/ carry */
864 tcg_gen_extract_tl(ca
, ca
, 32, 1);
865 if (is_isa300(ctx
)) {
866 tcg_gen_mov_tl(ca32
, ca
);
869 TCGv zero
= tcg_const_tl(0);
871 tcg_gen_add2_tl(t0
, ca
, arg1
, zero
, ca
, zero
);
872 tcg_gen_add2_tl(t0
, ca
, t0
, ca
, arg2
, zero
);
874 tcg_gen_add2_tl(t0
, ca
, arg1
, zero
, arg2
, zero
);
876 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, ca32
, 0);
880 tcg_gen_add_tl(t0
, arg1
, arg2
);
882 tcg_gen_add_tl(t0
, t0
, ca
);
887 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
889 if (unlikely(compute_rc0
)) {
890 gen_set_Rc0(ctx
, t0
);
894 tcg_gen_mov_tl(ret
, t0
);
898 /* Add functions with two operands */
899 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
900 static void glue(gen_, name)(DisasContext *ctx) \
902 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
903 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
905 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
907 /* Add functions with one operand and one immediate */
908 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
909 add_ca, compute_ca, compute_ov) \
910 static void glue(gen_, name)(DisasContext *ctx) \
912 TCGv t0 = tcg_const_tl(const_val); \
913 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
914 cpu_gpr[rA(ctx->opcode)], t0, \
916 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
920 /* add add. addo addo. */
921 GEN_INT_ARITH_ADD(add
, 0x08, cpu_ca
, 0, 0, 0)
922 GEN_INT_ARITH_ADD(addo
, 0x18, cpu_ca
, 0, 0, 1)
923 /* addc addc. addco addco. */
924 GEN_INT_ARITH_ADD(addc
, 0x00, cpu_ca
, 0, 1, 0)
925 GEN_INT_ARITH_ADD(addco
, 0x10, cpu_ca
, 0, 1, 1)
926 /* adde adde. addeo addeo. */
927 GEN_INT_ARITH_ADD(adde
, 0x04, cpu_ca
, 1, 1, 0)
928 GEN_INT_ARITH_ADD(addeo
, 0x14, cpu_ca
, 1, 1, 1)
929 /* addme addme. addmeo addmeo. */
930 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, cpu_ca
, 1, 1, 0)
931 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, cpu_ca
, 1, 1, 1)
933 GEN_INT_ARITH_ADD(addex
, 0x05, cpu_ov
, 1, 1, 0);
934 /* addze addze. addzeo addzeo.*/
935 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, cpu_ca
, 1, 1, 0)
936 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, cpu_ca
, 1, 1, 1)
938 static void gen_addi(DisasContext
*ctx
)
940 target_long simm
= SIMM(ctx
->opcode
);
942 if (rA(ctx
->opcode
) == 0) {
944 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
946 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
947 cpu_gpr
[rA(ctx
->opcode
)], simm
);
951 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
953 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
954 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
955 c
, cpu_ca
, cpu_ca32
, 0, 1, 0, compute_rc0
);
959 static void gen_addic(DisasContext
*ctx
)
961 gen_op_addic(ctx
, 0);
964 static void gen_addic_(DisasContext
*ctx
)
966 gen_op_addic(ctx
, 1);
970 static void gen_addis(DisasContext
*ctx
)
972 target_long simm
= SIMM(ctx
->opcode
);
974 if (rA(ctx
->opcode
) == 0) {
976 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
978 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
979 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
984 static void gen_addpcis(DisasContext
*ctx
)
986 target_long d
= DX(ctx
->opcode
);
988 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], ctx
->base
.pc_next
+ (d
<< 16));
991 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
992 TCGv arg2
, int sign
, int compute_ov
)
994 TCGv_i32 t0
= tcg_temp_new_i32();
995 TCGv_i32 t1
= tcg_temp_new_i32();
996 TCGv_i32 t2
= tcg_temp_new_i32();
997 TCGv_i32 t3
= tcg_temp_new_i32();
999 tcg_gen_trunc_tl_i32(t0
, arg1
);
1000 tcg_gen_trunc_tl_i32(t1
, arg2
);
1002 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1003 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1004 tcg_gen_and_i32(t2
, t2
, t3
);
1005 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1006 tcg_gen_or_i32(t2
, t2
, t3
);
1007 tcg_gen_movi_i32(t3
, 0);
1008 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1009 tcg_gen_div_i32(t3
, t0
, t1
);
1010 tcg_gen_extu_i32_tl(ret
, t3
);
1012 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t1
, 0);
1013 tcg_gen_movi_i32(t3
, 0);
1014 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1015 tcg_gen_divu_i32(t3
, t0
, t1
);
1016 tcg_gen_extu_i32_tl(ret
, t3
);
1019 tcg_gen_extu_i32_tl(cpu_ov
, t2
);
1020 if (is_isa300(ctx
)) {
1021 tcg_gen_extu_i32_tl(cpu_ov32
, t2
);
1023 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1025 tcg_temp_free_i32(t0
);
1026 tcg_temp_free_i32(t1
);
1027 tcg_temp_free_i32(t2
);
1028 tcg_temp_free_i32(t3
);
1030 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1031 gen_set_Rc0(ctx
, ret
);
1035 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1036 static void glue(gen_, name)(DisasContext *ctx) \
1038 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1039 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1040 sign, compute_ov); \
1042 /* divwu divwu. divwuo divwuo. */
1043 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1044 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1045 /* divw divw. divwo divwo. */
1046 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1047 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1049 /* div[wd]eu[o][.] */
1050 #define GEN_DIVE(name, hlpr, compute_ov) \
1051 static void gen_##name(DisasContext *ctx) \
1053 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1054 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1055 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1056 tcg_temp_free_i32(t0); \
1057 if (unlikely(Rc(ctx->opcode) != 0)) { \
1058 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1062 GEN_DIVE(divweu
, divweu
, 0);
1063 GEN_DIVE(divweuo
, divweu
, 1);
1064 GEN_DIVE(divwe
, divwe
, 0);
1065 GEN_DIVE(divweo
, divwe
, 1);
1067 #if defined(TARGET_PPC64)
1068 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1069 TCGv arg2
, int sign
, int compute_ov
)
1071 TCGv_i64 t0
= tcg_temp_new_i64();
1072 TCGv_i64 t1
= tcg_temp_new_i64();
1073 TCGv_i64 t2
= tcg_temp_new_i64();
1074 TCGv_i64 t3
= tcg_temp_new_i64();
1076 tcg_gen_mov_i64(t0
, arg1
);
1077 tcg_gen_mov_i64(t1
, arg2
);
1079 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1080 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1081 tcg_gen_and_i64(t2
, t2
, t3
);
1082 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1083 tcg_gen_or_i64(t2
, t2
, t3
);
1084 tcg_gen_movi_i64(t3
, 0);
1085 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1086 tcg_gen_div_i64(ret
, t0
, t1
);
1088 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t1
, 0);
1089 tcg_gen_movi_i64(t3
, 0);
1090 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1091 tcg_gen_divu_i64(ret
, t0
, t1
);
1094 tcg_gen_mov_tl(cpu_ov
, t2
);
1095 if (is_isa300(ctx
)) {
1096 tcg_gen_mov_tl(cpu_ov32
, t2
);
1098 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1100 tcg_temp_free_i64(t0
);
1101 tcg_temp_free_i64(t1
);
1102 tcg_temp_free_i64(t2
);
1103 tcg_temp_free_i64(t3
);
1105 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1106 gen_set_Rc0(ctx
, ret
);
1110 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1111 static void glue(gen_, name)(DisasContext *ctx) \
1113 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1114 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1115 sign, compute_ov); \
1117 /* divdu divdu. divduo divduo. */
1118 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1119 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1120 /* divd divd. divdo divdo. */
1121 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1122 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1124 GEN_DIVE(divdeu
, divdeu
, 0);
1125 GEN_DIVE(divdeuo
, divdeu
, 1);
1126 GEN_DIVE(divde
, divde
, 0);
1127 GEN_DIVE(divdeo
, divde
, 1);
1130 static inline void gen_op_arith_modw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1131 TCGv arg2
, int sign
)
1133 TCGv_i32 t0
= tcg_temp_new_i32();
1134 TCGv_i32 t1
= tcg_temp_new_i32();
1136 tcg_gen_trunc_tl_i32(t0
, arg1
);
1137 tcg_gen_trunc_tl_i32(t1
, arg2
);
1139 TCGv_i32 t2
= tcg_temp_new_i32();
1140 TCGv_i32 t3
= tcg_temp_new_i32();
1141 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1142 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1143 tcg_gen_and_i32(t2
, t2
, t3
);
1144 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1145 tcg_gen_or_i32(t2
, t2
, t3
);
1146 tcg_gen_movi_i32(t3
, 0);
1147 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1148 tcg_gen_rem_i32(t3
, t0
, t1
);
1149 tcg_gen_ext_i32_tl(ret
, t3
);
1150 tcg_temp_free_i32(t2
);
1151 tcg_temp_free_i32(t3
);
1153 TCGv_i32 t2
= tcg_const_i32(1);
1154 TCGv_i32 t3
= tcg_const_i32(0);
1155 tcg_gen_movcond_i32(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1156 tcg_gen_remu_i32(t3
, t0
, t1
);
1157 tcg_gen_extu_i32_tl(ret
, t3
);
1158 tcg_temp_free_i32(t2
);
1159 tcg_temp_free_i32(t3
);
1161 tcg_temp_free_i32(t0
);
1162 tcg_temp_free_i32(t1
);
1165 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1166 static void glue(gen_, name)(DisasContext *ctx) \
1168 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1169 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1173 GEN_INT_ARITH_MODW(moduw
, 0x08, 0);
1174 GEN_INT_ARITH_MODW(modsw
, 0x18, 1);
1176 #if defined(TARGET_PPC64)
1177 static inline void gen_op_arith_modd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1178 TCGv arg2
, int sign
)
1180 TCGv_i64 t0
= tcg_temp_new_i64();
1181 TCGv_i64 t1
= tcg_temp_new_i64();
1183 tcg_gen_mov_i64(t0
, arg1
);
1184 tcg_gen_mov_i64(t1
, arg2
);
1186 TCGv_i64 t2
= tcg_temp_new_i64();
1187 TCGv_i64 t3
= tcg_temp_new_i64();
1188 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1189 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1190 tcg_gen_and_i64(t2
, t2
, t3
);
1191 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1192 tcg_gen_or_i64(t2
, t2
, t3
);
1193 tcg_gen_movi_i64(t3
, 0);
1194 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1195 tcg_gen_rem_i64(ret
, t0
, t1
);
1196 tcg_temp_free_i64(t2
);
1197 tcg_temp_free_i64(t3
);
1199 TCGv_i64 t2
= tcg_const_i64(1);
1200 TCGv_i64 t3
= tcg_const_i64(0);
1201 tcg_gen_movcond_i64(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1202 tcg_gen_remu_i64(ret
, t0
, t1
);
1203 tcg_temp_free_i64(t2
);
1204 tcg_temp_free_i64(t3
);
1206 tcg_temp_free_i64(t0
);
1207 tcg_temp_free_i64(t1
);
1210 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1211 static void glue(gen_, name)(DisasContext *ctx) \
1213 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1214 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1218 GEN_INT_ARITH_MODD(modud
, 0x08, 0);
1219 GEN_INT_ARITH_MODD(modsd
, 0x18, 1);
1223 static void gen_mulhw(DisasContext
*ctx
)
1225 TCGv_i32 t0
= tcg_temp_new_i32();
1226 TCGv_i32 t1
= tcg_temp_new_i32();
1228 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1229 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1230 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1231 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1232 tcg_temp_free_i32(t0
);
1233 tcg_temp_free_i32(t1
);
1234 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1235 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1239 /* mulhwu mulhwu. */
1240 static void gen_mulhwu(DisasContext
*ctx
)
1242 TCGv_i32 t0
= tcg_temp_new_i32();
1243 TCGv_i32 t1
= tcg_temp_new_i32();
1245 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1246 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1247 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1248 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1249 tcg_temp_free_i32(t0
);
1250 tcg_temp_free_i32(t1
);
1251 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1252 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1257 static void gen_mullw(DisasContext
*ctx
)
1259 #if defined(TARGET_PPC64)
1261 t0
= tcg_temp_new_i64();
1262 t1
= tcg_temp_new_i64();
1263 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1264 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1265 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1269 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1270 cpu_gpr
[rB(ctx
->opcode
)]);
1272 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1273 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1277 /* mullwo mullwo. */
1278 static void gen_mullwo(DisasContext
*ctx
)
1280 TCGv_i32 t0
= tcg_temp_new_i32();
1281 TCGv_i32 t1
= tcg_temp_new_i32();
1283 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1284 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1285 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1286 #if defined(TARGET_PPC64)
1287 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1289 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1292 tcg_gen_sari_i32(t0
, t0
, 31);
1293 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1294 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1295 if (is_isa300(ctx
)) {
1296 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1298 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1300 tcg_temp_free_i32(t0
);
1301 tcg_temp_free_i32(t1
);
1302 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1303 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1308 static void gen_mulli(DisasContext
*ctx
)
1310 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1314 #if defined(TARGET_PPC64)
1316 static void gen_mulhd(DisasContext
*ctx
)
1318 TCGv lo
= tcg_temp_new();
1319 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1320 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1322 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1323 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1327 /* mulhdu mulhdu. */
1328 static void gen_mulhdu(DisasContext
*ctx
)
1330 TCGv lo
= tcg_temp_new();
1331 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1332 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1334 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1335 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1340 static void gen_mulld(DisasContext
*ctx
)
1342 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1343 cpu_gpr
[rB(ctx
->opcode
)]);
1344 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1345 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1349 /* mulldo mulldo. */
1350 static void gen_mulldo(DisasContext
*ctx
)
1352 TCGv_i64 t0
= tcg_temp_new_i64();
1353 TCGv_i64 t1
= tcg_temp_new_i64();
1355 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1356 cpu_gpr
[rB(ctx
->opcode
)]);
1357 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1359 tcg_gen_sari_i64(t0
, t0
, 63);
1360 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1361 if (is_isa300(ctx
)) {
1362 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1364 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1366 tcg_temp_free_i64(t0
);
1367 tcg_temp_free_i64(t1
);
1369 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1370 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1375 /* Common subf function */
1376 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1377 TCGv arg2
, bool add_ca
, bool compute_ca
,
1378 bool compute_ov
, bool compute_rc0
)
1382 if (compute_ca
|| compute_ov
) {
1383 t0
= tcg_temp_new();
1387 /* dest = ~arg1 + arg2 [+ ca]. */
1388 if (NARROW_MODE(ctx
)) {
1390 * Caution: a non-obvious corner case of the spec is that
1391 * we must produce the *entire* 64-bit addition, but
1392 * produce the carry into bit 32.
1394 TCGv inv1
= tcg_temp_new();
1395 TCGv t1
= tcg_temp_new();
1396 tcg_gen_not_tl(inv1
, arg1
);
1398 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1400 tcg_gen_addi_tl(t0
, arg2
, 1);
1402 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1403 tcg_gen_add_tl(t0
, t0
, inv1
);
1404 tcg_temp_free(inv1
);
1405 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1407 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
1408 if (is_isa300(ctx
)) {
1409 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
1411 } else if (add_ca
) {
1412 TCGv zero
, inv1
= tcg_temp_new();
1413 tcg_gen_not_tl(inv1
, arg1
);
1414 zero
= tcg_const_tl(0);
1415 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1416 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1417 gen_op_arith_compute_ca32(ctx
, t0
, inv1
, arg2
, cpu_ca32
, 0);
1418 tcg_temp_free(zero
);
1419 tcg_temp_free(inv1
);
1421 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1422 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1423 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, cpu_ca32
, 1);
1425 } else if (add_ca
) {
1427 * Since we're ignoring carry-out, we can simplify the
1428 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
1430 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1431 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1432 tcg_gen_subi_tl(t0
, t0
, 1);
1434 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1438 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1440 if (unlikely(compute_rc0
)) {
1441 gen_set_Rc0(ctx
, t0
);
1445 tcg_gen_mov_tl(ret
, t0
);
1449 /* Sub functions with Two operands functions */
1450 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1451 static void glue(gen_, name)(DisasContext *ctx) \
1453 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1454 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1455 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1457 /* Sub functions with one operand and one immediate */
1458 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1459 add_ca, compute_ca, compute_ov) \
1460 static void glue(gen_, name)(DisasContext *ctx) \
1462 TCGv t0 = tcg_const_tl(const_val); \
1463 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1464 cpu_gpr[rA(ctx->opcode)], t0, \
1465 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1466 tcg_temp_free(t0); \
1468 /* subf subf. subfo subfo. */
1469 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1470 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1471 /* subfc subfc. subfco subfco. */
1472 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1473 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1474 /* subfe subfe. subfeo subfo. */
1475 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1476 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1477 /* subfme subfme. subfmeo subfmeo. */
1478 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1479 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1480 /* subfze subfze. subfzeo subfzeo.*/
1481 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1482 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1485 static void gen_subfic(DisasContext
*ctx
)
1487 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1488 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1493 /* neg neg. nego nego. */
1494 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1496 TCGv zero
= tcg_const_tl(0);
1497 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1498 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1499 tcg_temp_free(zero
);
1502 static void gen_neg(DisasContext
*ctx
)
1504 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1505 if (unlikely(Rc(ctx
->opcode
))) {
1506 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1510 static void gen_nego(DisasContext
*ctx
)
1512 gen_op_arith_neg(ctx
, 1);
1515 /*** Integer logical ***/
1516 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1517 static void glue(gen_, name)(DisasContext *ctx) \
1519 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1520 cpu_gpr[rB(ctx->opcode)]); \
1521 if (unlikely(Rc(ctx->opcode) != 0)) \
1522 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1525 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1526 static void glue(gen_, name)(DisasContext *ctx) \
1528 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1529 if (unlikely(Rc(ctx->opcode) != 0)) \
1530 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1534 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1536 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1539 static void gen_andi_(DisasContext
*ctx
)
1541 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1543 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1547 static void gen_andis_(DisasContext
*ctx
)
1549 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1550 UIMM(ctx
->opcode
) << 16);
1551 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1555 static void gen_cntlzw(DisasContext
*ctx
)
1557 TCGv_i32 t
= tcg_temp_new_i32();
1559 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1560 tcg_gen_clzi_i32(t
, t
, 32);
1561 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1562 tcg_temp_free_i32(t
);
1564 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1565 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1570 static void gen_cnttzw(DisasContext
*ctx
)
1572 TCGv_i32 t
= tcg_temp_new_i32();
1574 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1575 tcg_gen_ctzi_i32(t
, t
, 32);
1576 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1577 tcg_temp_free_i32(t
);
1579 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1580 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1585 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1586 /* extsb & extsb. */
1587 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1588 /* extsh & extsh. */
1589 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1591 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1593 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1595 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1596 static void gen_pause(DisasContext
*ctx
)
1598 TCGv_i32 t0
= tcg_const_i32(0);
1599 tcg_gen_st_i32(t0
, cpu_env
,
1600 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1601 tcg_temp_free_i32(t0
);
1603 /* Stop translation, this gives other CPUs a chance to run */
1604 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
1606 #endif /* defined(TARGET_PPC64) */
1609 static void gen_or(DisasContext
*ctx
)
1613 rs
= rS(ctx
->opcode
);
1614 ra
= rA(ctx
->opcode
);
1615 rb
= rB(ctx
->opcode
);
1616 /* Optimisation for mr. ri case */
1617 if (rs
!= ra
|| rs
!= rb
) {
1619 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1621 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1623 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1624 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1626 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1627 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1628 #if defined(TARGET_PPC64)
1629 } else if (rs
!= 0) { /* 0 is nop */
1634 /* Set process priority to low */
1638 /* Set process priority to medium-low */
1642 /* Set process priority to normal */
1645 #if !defined(CONFIG_USER_ONLY)
1648 /* Set process priority to very low */
1654 /* Set process priority to medium-hight */
1660 /* Set process priority to high */
1665 if (ctx
->hv
&& !ctx
->pr
) {
1666 /* Set process priority to very high */
1675 TCGv t0
= tcg_temp_new();
1676 gen_load_spr(t0
, SPR_PPR
);
1677 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1678 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1679 gen_store_spr(SPR_PPR
, t0
);
1682 #if !defined(CONFIG_USER_ONLY)
1684 * Pause out of TCG otherwise spin loops with smt_low eat too
1685 * much CPU and the kernel hangs. This applies to all
1686 * encodings other than no-op, e.g., miso(rs=26), yield(27),
1687 * mdoio(29), mdoom(30), and all currently undefined.
1695 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1698 static void gen_xor(DisasContext
*ctx
)
1700 /* Optimisation for "set to zero" case */
1701 if (rS(ctx
->opcode
) != rB(ctx
->opcode
)) {
1702 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1703 cpu_gpr
[rB(ctx
->opcode
)]);
1705 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1707 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1708 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1713 static void gen_ori(DisasContext
*ctx
)
1715 target_ulong uimm
= UIMM(ctx
->opcode
);
1717 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1720 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1724 static void gen_oris(DisasContext
*ctx
)
1726 target_ulong uimm
= UIMM(ctx
->opcode
);
1728 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1732 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1737 static void gen_xori(DisasContext
*ctx
)
1739 target_ulong uimm
= UIMM(ctx
->opcode
);
1741 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1745 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1749 static void gen_xoris(DisasContext
*ctx
)
1751 target_ulong uimm
= UIMM(ctx
->opcode
);
1753 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1757 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1761 /* popcntb : PowerPC 2.03 specification */
1762 static void gen_popcntb(DisasContext
*ctx
)
1764 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1767 static void gen_popcntw(DisasContext
*ctx
)
1769 #if defined(TARGET_PPC64)
1770 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1772 tcg_gen_ctpop_i32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1776 #if defined(TARGET_PPC64)
1777 /* popcntd: PowerPC 2.06 specification */
1778 static void gen_popcntd(DisasContext
*ctx
)
1780 tcg_gen_ctpop_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1784 /* prtyw: PowerPC 2.05 specification */
1785 static void gen_prtyw(DisasContext
*ctx
)
1787 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1788 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1789 TCGv t0
= tcg_temp_new();
1790 tcg_gen_shri_tl(t0
, rs
, 16);
1791 tcg_gen_xor_tl(ra
, rs
, t0
);
1792 tcg_gen_shri_tl(t0
, ra
, 8);
1793 tcg_gen_xor_tl(ra
, ra
, t0
);
1794 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1798 #if defined(TARGET_PPC64)
1799 /* prtyd: PowerPC 2.05 specification */
1800 static void gen_prtyd(DisasContext
*ctx
)
1802 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1803 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1804 TCGv t0
= tcg_temp_new();
1805 tcg_gen_shri_tl(t0
, rs
, 32);
1806 tcg_gen_xor_tl(ra
, rs
, t0
);
1807 tcg_gen_shri_tl(t0
, ra
, 16);
1808 tcg_gen_xor_tl(ra
, ra
, t0
);
1809 tcg_gen_shri_tl(t0
, ra
, 8);
1810 tcg_gen_xor_tl(ra
, ra
, t0
);
1811 tcg_gen_andi_tl(ra
, ra
, 1);
1816 #if defined(TARGET_PPC64)
1818 static void gen_bpermd(DisasContext
*ctx
)
1820 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1821 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1825 #if defined(TARGET_PPC64)
1826 /* extsw & extsw. */
1827 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1830 static void gen_cntlzd(DisasContext
*ctx
)
1832 tcg_gen_clzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1833 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1834 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1839 static void gen_cnttzd(DisasContext
*ctx
)
1841 tcg_gen_ctzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1842 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1843 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1848 static void gen_darn(DisasContext
*ctx
)
1850 int l
= L(ctx
->opcode
);
1853 tcg_gen_movi_i64(cpu_gpr
[rD(ctx
->opcode
)], -1);
1855 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
1859 gen_helper_darn32(cpu_gpr
[rD(ctx
->opcode
)]);
1861 /* Return 64-bit random for both CRN and RRN */
1862 gen_helper_darn64(cpu_gpr
[rD(ctx
->opcode
)]);
1864 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
1865 gen_stop_exception(ctx
);
1871 /*** Integer rotate ***/
1873 /* rlwimi & rlwimi. */
1874 static void gen_rlwimi(DisasContext
*ctx
)
1876 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1877 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1878 uint32_t sh
= SH(ctx
->opcode
);
1879 uint32_t mb
= MB(ctx
->opcode
);
1880 uint32_t me
= ME(ctx
->opcode
);
1882 if (sh
== (31 - me
) && mb
<= me
) {
1883 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1886 bool mask_in_32b
= true;
1889 #if defined(TARGET_PPC64)
1893 mask
= MASK(mb
, me
);
1895 #if defined(TARGET_PPC64)
1896 if (mask
> 0xffffffffu
) {
1897 mask_in_32b
= false;
1900 t1
= tcg_temp_new();
1902 TCGv_i32 t0
= tcg_temp_new_i32();
1903 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1904 tcg_gen_rotli_i32(t0
, t0
, sh
);
1905 tcg_gen_extu_i32_tl(t1
, t0
);
1906 tcg_temp_free_i32(t0
);
1908 #if defined(TARGET_PPC64)
1909 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1910 tcg_gen_rotli_i64(t1
, t1
, sh
);
1912 g_assert_not_reached();
1916 tcg_gen_andi_tl(t1
, t1
, mask
);
1917 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1918 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1921 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1922 gen_set_Rc0(ctx
, t_ra
);
1926 /* rlwinm & rlwinm. */
1927 static void gen_rlwinm(DisasContext
*ctx
)
1929 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1930 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1931 int sh
= SH(ctx
->opcode
);
1932 int mb
= MB(ctx
->opcode
);
1933 int me
= ME(ctx
->opcode
);
1934 int len
= me
- mb
+ 1;
1935 int rsh
= (32 - sh
) & 31;
1937 if (sh
!= 0 && len
> 0 && me
== (31 - sh
)) {
1938 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
1939 } else if (me
== 31 && rsh
+ len
<= 32) {
1940 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
1943 bool mask_in_32b
= true;
1944 #if defined(TARGET_PPC64)
1948 mask
= MASK(mb
, me
);
1949 #if defined(TARGET_PPC64)
1950 if (mask
> 0xffffffffu
) {
1951 mask_in_32b
= false;
1956 tcg_gen_andi_tl(t_ra
, t_rs
, mask
);
1958 TCGv_i32 t0
= tcg_temp_new_i32();
1959 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1960 tcg_gen_rotli_i32(t0
, t0
, sh
);
1961 tcg_gen_andi_i32(t0
, t0
, mask
);
1962 tcg_gen_extu_i32_tl(t_ra
, t0
);
1963 tcg_temp_free_i32(t0
);
1966 #if defined(TARGET_PPC64)
1967 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1968 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1969 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1971 g_assert_not_reached();
1975 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1976 gen_set_Rc0(ctx
, t_ra
);
1980 /* rlwnm & rlwnm. */
1981 static void gen_rlwnm(DisasContext
*ctx
)
1983 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1984 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1985 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1986 uint32_t mb
= MB(ctx
->opcode
);
1987 uint32_t me
= ME(ctx
->opcode
);
1989 bool mask_in_32b
= true;
1991 #if defined(TARGET_PPC64)
1995 mask
= MASK(mb
, me
);
1997 #if defined(TARGET_PPC64)
1998 if (mask
> 0xffffffffu
) {
1999 mask_in_32b
= false;
2003 TCGv_i32 t0
= tcg_temp_new_i32();
2004 TCGv_i32 t1
= tcg_temp_new_i32();
2005 tcg_gen_trunc_tl_i32(t0
, t_rb
);
2006 tcg_gen_trunc_tl_i32(t1
, t_rs
);
2007 tcg_gen_andi_i32(t0
, t0
, 0x1f);
2008 tcg_gen_rotl_i32(t1
, t1
, t0
);
2009 tcg_gen_extu_i32_tl(t_ra
, t1
);
2010 tcg_temp_free_i32(t0
);
2011 tcg_temp_free_i32(t1
);
2013 #if defined(TARGET_PPC64)
2014 TCGv_i64 t0
= tcg_temp_new_i64();
2015 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
2016 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
2017 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
2018 tcg_temp_free_i64(t0
);
2020 g_assert_not_reached();
2024 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
2026 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2027 gen_set_Rc0(ctx
, t_ra
);
2031 #if defined(TARGET_PPC64)
2032 #define GEN_PPC64_R2(name, opc1, opc2) \
2033 static void glue(gen_, name##0)(DisasContext *ctx) \
2035 gen_##name(ctx, 0); \
2038 static void glue(gen_, name##1)(DisasContext *ctx) \
2040 gen_##name(ctx, 1); \
2042 #define GEN_PPC64_R4(name, opc1, opc2) \
2043 static void glue(gen_, name##0)(DisasContext *ctx) \
2045 gen_##name(ctx, 0, 0); \
2048 static void glue(gen_, name##1)(DisasContext *ctx) \
2050 gen_##name(ctx, 0, 1); \
2053 static void glue(gen_, name##2)(DisasContext *ctx) \
2055 gen_##name(ctx, 1, 0); \
2058 static void glue(gen_, name##3)(DisasContext *ctx) \
2060 gen_##name(ctx, 1, 1); \
2063 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
2065 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2066 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2067 int len
= me
- mb
+ 1;
2068 int rsh
= (64 - sh
) & 63;
2070 if (sh
!= 0 && len
> 0 && me
== (63 - sh
)) {
2071 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
2072 } else if (me
== 63 && rsh
+ len
<= 64) {
2073 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
2075 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
2076 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2078 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2079 gen_set_Rc0(ctx
, t_ra
);
2083 /* rldicl - rldicl. */
2084 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
2088 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2089 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2090 gen_rldinm(ctx
, mb
, 63, sh
);
2092 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
2094 /* rldicr - rldicr. */
2095 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
2099 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2100 me
= MB(ctx
->opcode
) | (men
<< 5);
2101 gen_rldinm(ctx
, 0, me
, sh
);
2103 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
2105 /* rldic - rldic. */
2106 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
2110 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2111 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2112 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
2114 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
2116 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
2118 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2119 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2120 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2123 t0
= tcg_temp_new();
2124 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
2125 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
2128 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2129 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2130 gen_set_Rc0(ctx
, t_ra
);
2134 /* rldcl - rldcl. */
2135 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
2139 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2140 gen_rldnm(ctx
, mb
, 63);
2142 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
2144 /* rldcr - rldcr. */
2145 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
2149 me
= MB(ctx
->opcode
) | (men
<< 5);
2150 gen_rldnm(ctx
, 0, me
);
2152 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
2154 /* rldimi - rldimi. */
2155 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
2157 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2158 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2159 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
2160 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2161 uint32_t me
= 63 - sh
;
2164 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2166 target_ulong mask
= MASK(mb
, me
);
2167 TCGv t1
= tcg_temp_new();
2169 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
2170 tcg_gen_andi_tl(t1
, t1
, mask
);
2171 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2172 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2175 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2176 gen_set_Rc0(ctx
, t_ra
);
2179 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
2182 /*** Integer shift ***/
2185 static void gen_slw(DisasContext
*ctx
)
2189 t0
= tcg_temp_new();
2190 /* AND rS with a mask that is 0 when rB >= 0x20 */
2191 #if defined(TARGET_PPC64)
2192 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2193 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2195 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2196 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2198 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2199 t1
= tcg_temp_new();
2200 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2201 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2204 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2205 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2206 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2211 static void gen_sraw(DisasContext
*ctx
)
2213 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2214 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2215 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2216 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2220 /* srawi & srawi. */
2221 static void gen_srawi(DisasContext
*ctx
)
2223 int sh
= SH(ctx
->opcode
);
2224 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2225 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2227 tcg_gen_ext32s_tl(dst
, src
);
2228 tcg_gen_movi_tl(cpu_ca
, 0);
2229 if (is_isa300(ctx
)) {
2230 tcg_gen_movi_tl(cpu_ca32
, 0);
2234 tcg_gen_ext32s_tl(dst
, src
);
2235 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2236 t0
= tcg_temp_new();
2237 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2238 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2240 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2241 if (is_isa300(ctx
)) {
2242 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2244 tcg_gen_sari_tl(dst
, dst
, sh
);
2246 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2247 gen_set_Rc0(ctx
, dst
);
2252 static void gen_srw(DisasContext
*ctx
)
2256 t0
= tcg_temp_new();
2257 /* AND rS with a mask that is 0 when rB >= 0x20 */
2258 #if defined(TARGET_PPC64)
2259 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2260 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2262 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2263 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2265 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2266 tcg_gen_ext32u_tl(t0
, t0
);
2267 t1
= tcg_temp_new();
2268 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2269 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2272 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2273 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2277 #if defined(TARGET_PPC64)
2279 static void gen_sld(DisasContext
*ctx
)
2283 t0
= tcg_temp_new();
2284 /* AND rS with a mask that is 0 when rB >= 0x40 */
2285 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2286 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2287 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2288 t1
= tcg_temp_new();
2289 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2290 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2293 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2294 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2299 static void gen_srad(DisasContext
*ctx
)
2301 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2302 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2303 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2304 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2307 /* sradi & sradi. */
2308 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2310 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2311 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2312 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2314 tcg_gen_mov_tl(dst
, src
);
2315 tcg_gen_movi_tl(cpu_ca
, 0);
2316 if (is_isa300(ctx
)) {
2317 tcg_gen_movi_tl(cpu_ca32
, 0);
2321 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2322 t0
= tcg_temp_new();
2323 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2324 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2326 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2327 if (is_isa300(ctx
)) {
2328 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2330 tcg_gen_sari_tl(dst
, src
, sh
);
2332 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2333 gen_set_Rc0(ctx
, dst
);
2337 static void gen_sradi0(DisasContext
*ctx
)
2342 static void gen_sradi1(DisasContext
*ctx
)
2347 /* extswsli & extswsli. */
2348 static inline void gen_extswsli(DisasContext
*ctx
, int n
)
2350 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2351 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2352 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2354 tcg_gen_ext32s_tl(dst
, src
);
2355 tcg_gen_shli_tl(dst
, dst
, sh
);
2356 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2357 gen_set_Rc0(ctx
, dst
);
2361 static void gen_extswsli0(DisasContext
*ctx
)
2363 gen_extswsli(ctx
, 0);
2366 static void gen_extswsli1(DisasContext
*ctx
)
2368 gen_extswsli(ctx
, 1);
2372 static void gen_srd(DisasContext
*ctx
)
2376 t0
= tcg_temp_new();
2377 /* AND rS with a mask that is 0 when rB >= 0x40 */
2378 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2379 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2380 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2381 t1
= tcg_temp_new();
2382 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2383 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2386 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2387 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2392 /*** Addressing modes ***/
2393 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2394 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2397 target_long simm
= SIMM(ctx
->opcode
);
2400 if (rA(ctx
->opcode
) == 0) {
2401 if (NARROW_MODE(ctx
)) {
2402 simm
= (uint32_t)simm
;
2404 tcg_gen_movi_tl(EA
, simm
);
2405 } else if (likely(simm
!= 0)) {
2406 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2407 if (NARROW_MODE(ctx
)) {
2408 tcg_gen_ext32u_tl(EA
, EA
);
2411 if (NARROW_MODE(ctx
)) {
2412 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2414 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2419 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2421 if (rA(ctx
->opcode
) == 0) {
2422 if (NARROW_MODE(ctx
)) {
2423 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2425 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2428 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2429 if (NARROW_MODE(ctx
)) {
2430 tcg_gen_ext32u_tl(EA
, EA
);
2435 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2437 if (rA(ctx
->opcode
) == 0) {
2438 tcg_gen_movi_tl(EA
, 0);
2439 } else if (NARROW_MODE(ctx
)) {
2440 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2442 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2446 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2449 tcg_gen_addi_tl(ret
, arg1
, val
);
2450 if (NARROW_MODE(ctx
)) {
2451 tcg_gen_ext32u_tl(ret
, ret
);
2455 static inline void gen_align_no_le(DisasContext
*ctx
)
2457 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
,
2458 (ctx
->opcode
& 0x03FF0000) | POWERPC_EXCP_ALIGN_LE
);
2461 /*** Integer load ***/
2462 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2463 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2465 #define GEN_QEMU_LOAD_TL(ldop, op) \
2466 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2470 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2473 GEN_QEMU_LOAD_TL(ld8u
, DEF_MEMOP(MO_UB
))
2474 GEN_QEMU_LOAD_TL(ld16u
, DEF_MEMOP(MO_UW
))
2475 GEN_QEMU_LOAD_TL(ld16s
, DEF_MEMOP(MO_SW
))
2476 GEN_QEMU_LOAD_TL(ld32u
, DEF_MEMOP(MO_UL
))
2477 GEN_QEMU_LOAD_TL(ld32s
, DEF_MEMOP(MO_SL
))
2479 GEN_QEMU_LOAD_TL(ld16ur
, BSWAP_MEMOP(MO_UW
))
2480 GEN_QEMU_LOAD_TL(ld32ur
, BSWAP_MEMOP(MO_UL
))
2482 #define GEN_QEMU_LOAD_64(ldop, op) \
2483 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2487 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2490 GEN_QEMU_LOAD_64(ld8u
, DEF_MEMOP(MO_UB
))
2491 GEN_QEMU_LOAD_64(ld16u
, DEF_MEMOP(MO_UW
))
2492 GEN_QEMU_LOAD_64(ld32u
, DEF_MEMOP(MO_UL
))
2493 GEN_QEMU_LOAD_64(ld32s
, DEF_MEMOP(MO_SL
))
2494 GEN_QEMU_LOAD_64(ld64
, DEF_MEMOP(MO_Q
))
2496 #if defined(TARGET_PPC64)
2497 GEN_QEMU_LOAD_64(ld64ur
, BSWAP_MEMOP(MO_Q
))
2500 #define GEN_QEMU_STORE_TL(stop, op) \
2501 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2505 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2508 GEN_QEMU_STORE_TL(st8
, DEF_MEMOP(MO_UB
))
2509 GEN_QEMU_STORE_TL(st16
, DEF_MEMOP(MO_UW
))
2510 GEN_QEMU_STORE_TL(st32
, DEF_MEMOP(MO_UL
))
2512 GEN_QEMU_STORE_TL(st16r
, BSWAP_MEMOP(MO_UW
))
2513 GEN_QEMU_STORE_TL(st32r
, BSWAP_MEMOP(MO_UL
))
2515 #define GEN_QEMU_STORE_64(stop, op) \
2516 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2520 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2523 GEN_QEMU_STORE_64(st8
, DEF_MEMOP(MO_UB
))
2524 GEN_QEMU_STORE_64(st16
, DEF_MEMOP(MO_UW
))
2525 GEN_QEMU_STORE_64(st32
, DEF_MEMOP(MO_UL
))
2526 GEN_QEMU_STORE_64(st64
, DEF_MEMOP(MO_Q
))
2528 #if defined(TARGET_PPC64)
2529 GEN_QEMU_STORE_64(st64r
, BSWAP_MEMOP(MO_Q
))
2532 #define GEN_LD(name, ldop, opc, type) \
2533 static void glue(gen_, name)(DisasContext *ctx) \
2536 gen_set_access_type(ctx, ACCESS_INT); \
2537 EA = tcg_temp_new(); \
2538 gen_addr_imm_index(ctx, EA, 0); \
2539 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2540 tcg_temp_free(EA); \
2543 #define GEN_LDU(name, ldop, opc, type) \
2544 static void glue(gen_, name##u)(DisasContext *ctx) \
2547 if (unlikely(rA(ctx->opcode) == 0 || \
2548 rA(ctx->opcode) == rD(ctx->opcode))) { \
2549 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2552 gen_set_access_type(ctx, ACCESS_INT); \
2553 EA = tcg_temp_new(); \
2554 if (type == PPC_64B) \
2555 gen_addr_imm_index(ctx, EA, 0x03); \
2557 gen_addr_imm_index(ctx, EA, 0); \
2558 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2559 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2560 tcg_temp_free(EA); \
2563 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2564 static void glue(gen_, name##ux)(DisasContext *ctx) \
2567 if (unlikely(rA(ctx->opcode) == 0 || \
2568 rA(ctx->opcode) == rD(ctx->opcode))) { \
2569 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2572 gen_set_access_type(ctx, ACCESS_INT); \
2573 EA = tcg_temp_new(); \
2574 gen_addr_reg_index(ctx, EA); \
2575 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2576 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2577 tcg_temp_free(EA); \
2580 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2581 static void glue(gen_, name##x)(DisasContext *ctx) \
2585 gen_set_access_type(ctx, ACCESS_INT); \
2586 EA = tcg_temp_new(); \
2587 gen_addr_reg_index(ctx, EA); \
2588 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2589 tcg_temp_free(EA); \
2592 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2593 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2595 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2596 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2598 #define GEN_LDS(name, ldop, op, type) \
2599 GEN_LD(name, ldop, op | 0x20, type); \
2600 GEN_LDU(name, ldop, op | 0x21, type); \
2601 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2602 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2604 /* lbz lbzu lbzux lbzx */
2605 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2606 /* lha lhau lhaux lhax */
2607 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2608 /* lhz lhzu lhzux lhzx */
2609 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2610 /* lwz lwzu lwzux lwzx */
2611 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2613 #define GEN_LDEPX(name, ldop, opc2, opc3) \
2614 static void glue(gen_, name##epx)(DisasContext *ctx) \
2618 gen_set_access_type(ctx, ACCESS_INT); \
2619 EA = tcg_temp_new(); \
2620 gen_addr_reg_index(ctx, EA); \
2621 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
2622 tcg_temp_free(EA); \
2625 GEN_LDEPX(lb
, DEF_MEMOP(MO_UB
), 0x1F, 0x02)
2626 GEN_LDEPX(lh
, DEF_MEMOP(MO_UW
), 0x1F, 0x08)
2627 GEN_LDEPX(lw
, DEF_MEMOP(MO_UL
), 0x1F, 0x00)
2628 #if defined(TARGET_PPC64)
2629 GEN_LDEPX(ld
, DEF_MEMOP(MO_Q
), 0x1D, 0x00)
2632 #if defined(TARGET_PPC64)
2634 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2636 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2638 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
);
2640 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
);
2642 /* CI load/store variants */
2643 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
2644 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x15, PPC_CILDST
)
2645 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
2646 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
2648 static void gen_ld(DisasContext
*ctx
)
2651 if (Rc(ctx
->opcode
)) {
2652 if (unlikely(rA(ctx
->opcode
) == 0 ||
2653 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2654 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2658 gen_set_access_type(ctx
, ACCESS_INT
);
2659 EA
= tcg_temp_new();
2660 gen_addr_imm_index(ctx
, EA
, 0x03);
2661 if (ctx
->opcode
& 0x02) {
2662 /* lwa (lwau is undefined) */
2663 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2666 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2668 if (Rc(ctx
->opcode
)) {
2669 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2675 static void gen_lq(DisasContext
*ctx
)
2680 /* lq is a legal user mode instruction starting in ISA 2.07 */
2681 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2682 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2684 if (!legal_in_user_mode
&& ctx
->pr
) {
2685 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2689 if (!le_is_supported
&& ctx
->le_mode
) {
2690 gen_align_no_le(ctx
);
2693 ra
= rA(ctx
->opcode
);
2694 rd
= rD(ctx
->opcode
);
2695 if (unlikely((rd
& 1) || rd
== ra
)) {
2696 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2700 gen_set_access_type(ctx
, ACCESS_INT
);
2701 EA
= tcg_temp_new();
2702 gen_addr_imm_index(ctx
, EA
, 0x0F);
2704 /* Note that the low part is always in RD+1, even in LE mode. */
2705 lo
= cpu_gpr
[rd
+ 1];
2708 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2709 if (HAVE_ATOMIC128
) {
2710 TCGv_i32 oi
= tcg_temp_new_i32();
2712 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
2713 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
2715 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
2716 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
2718 tcg_temp_free_i32(oi
);
2719 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
2721 /* Restart with exclusive lock. */
2722 gen_helper_exit_atomic(cpu_env
);
2723 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2725 } else if (ctx
->le_mode
) {
2726 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
2727 gen_addr_add(ctx
, EA
, EA
, 8);
2728 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
2730 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
2731 gen_addr_add(ctx
, EA
, EA
, 8);
2732 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
2738 /*** Integer store ***/
2739 #define GEN_ST(name, stop, opc, type) \
2740 static void glue(gen_, name)(DisasContext *ctx) \
2743 gen_set_access_type(ctx, ACCESS_INT); \
2744 EA = tcg_temp_new(); \
2745 gen_addr_imm_index(ctx, EA, 0); \
2746 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2747 tcg_temp_free(EA); \
2750 #define GEN_STU(name, stop, opc, type) \
2751 static void glue(gen_, stop##u)(DisasContext *ctx) \
2754 if (unlikely(rA(ctx->opcode) == 0)) { \
2755 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2758 gen_set_access_type(ctx, ACCESS_INT); \
2759 EA = tcg_temp_new(); \
2760 if (type == PPC_64B) \
2761 gen_addr_imm_index(ctx, EA, 0x03); \
2763 gen_addr_imm_index(ctx, EA, 0); \
2764 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2765 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2766 tcg_temp_free(EA); \
2769 #define GEN_STUX(name, stop, opc2, opc3, type) \
2770 static void glue(gen_, name##ux)(DisasContext *ctx) \
2773 if (unlikely(rA(ctx->opcode) == 0)) { \
2774 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2777 gen_set_access_type(ctx, ACCESS_INT); \
2778 EA = tcg_temp_new(); \
2779 gen_addr_reg_index(ctx, EA); \
2780 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2781 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2782 tcg_temp_free(EA); \
2785 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2786 static void glue(gen_, name##x)(DisasContext *ctx) \
2790 gen_set_access_type(ctx, ACCESS_INT); \
2791 EA = tcg_temp_new(); \
2792 gen_addr_reg_index(ctx, EA); \
2793 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2794 tcg_temp_free(EA); \
2796 #define GEN_STX(name, stop, opc2, opc3, type) \
2797 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2799 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2800 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2802 #define GEN_STS(name, stop, op, type) \
2803 GEN_ST(name, stop, op | 0x20, type); \
2804 GEN_STU(name, stop, op | 0x21, type); \
2805 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2806 GEN_STX(name, stop, 0x17, op | 0x00, type)
2808 /* stb stbu stbux stbx */
2809 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2810 /* sth sthu sthux sthx */
2811 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2812 /* stw stwu stwux stwx */
2813 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2815 #define GEN_STEPX(name, stop, opc2, opc3) \
2816 static void glue(gen_, name##epx)(DisasContext *ctx) \
2820 gen_set_access_type(ctx, ACCESS_INT); \
2821 EA = tcg_temp_new(); \
2822 gen_addr_reg_index(ctx, EA); \
2823 tcg_gen_qemu_st_tl( \
2824 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
2825 tcg_temp_free(EA); \
2828 GEN_STEPX(stb
, DEF_MEMOP(MO_UB
), 0x1F, 0x06)
2829 GEN_STEPX(sth
, DEF_MEMOP(MO_UW
), 0x1F, 0x0C)
2830 GEN_STEPX(stw
, DEF_MEMOP(MO_UL
), 0x1F, 0x04)
2831 #if defined(TARGET_PPC64)
2832 GEN_STEPX(std
, DEF_MEMOP(MO_Q
), 0x1d, 0x04)
2835 #if defined(TARGET_PPC64)
2836 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
);
2837 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
);
2838 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
2839 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
2840 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
2841 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
2843 static void gen_std(DisasContext
*ctx
)
2848 rs
= rS(ctx
->opcode
);
2849 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
2850 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2851 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2854 if (!(ctx
->insns_flags
& PPC_64BX
)) {
2855 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2858 if (!legal_in_user_mode
&& ctx
->pr
) {
2859 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2863 if (!le_is_supported
&& ctx
->le_mode
) {
2864 gen_align_no_le(ctx
);
2868 if (unlikely(rs
& 1)) {
2869 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2872 gen_set_access_type(ctx
, ACCESS_INT
);
2873 EA
= tcg_temp_new();
2874 gen_addr_imm_index(ctx
, EA
, 0x03);
2876 /* Note that the low part is always in RS+1, even in LE mode. */
2877 lo
= cpu_gpr
[rs
+ 1];
2880 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2881 if (HAVE_ATOMIC128
) {
2882 TCGv_i32 oi
= tcg_temp_new_i32();
2884 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
2885 gen_helper_stq_le_parallel(cpu_env
, EA
, lo
, hi
, oi
);
2887 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
2888 gen_helper_stq_be_parallel(cpu_env
, EA
, lo
, hi
, oi
);
2890 tcg_temp_free_i32(oi
);
2892 /* Restart with exclusive lock. */
2893 gen_helper_exit_atomic(cpu_env
);
2894 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2896 } else if (ctx
->le_mode
) {
2897 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
2898 gen_addr_add(ctx
, EA
, EA
, 8);
2899 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
2901 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
2902 gen_addr_add(ctx
, EA
, EA
, 8);
2903 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
2908 if (Rc(ctx
->opcode
)) {
2909 if (unlikely(rA(ctx
->opcode
) == 0)) {
2910 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2914 gen_set_access_type(ctx
, ACCESS_INT
);
2915 EA
= tcg_temp_new();
2916 gen_addr_imm_index(ctx
, EA
, 0x03);
2917 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2918 if (Rc(ctx
->opcode
)) {
2919 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2925 /*** Integer load and store with byte reverse ***/
2928 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2931 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2933 #if defined(TARGET_PPC64)
2935 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2937 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2938 #endif /* TARGET_PPC64 */
2941 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2943 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2945 /*** Integer load and store multiple ***/
2948 static void gen_lmw(DisasContext
*ctx
)
2954 gen_align_no_le(ctx
);
2957 gen_set_access_type(ctx
, ACCESS_INT
);
2958 t0
= tcg_temp_new();
2959 t1
= tcg_const_i32(rD(ctx
->opcode
));
2960 gen_addr_imm_index(ctx
, t0
, 0);
2961 gen_helper_lmw(cpu_env
, t0
, t1
);
2963 tcg_temp_free_i32(t1
);
2967 static void gen_stmw(DisasContext
*ctx
)
2973 gen_align_no_le(ctx
);
2976 gen_set_access_type(ctx
, ACCESS_INT
);
2977 t0
= tcg_temp_new();
2978 t1
= tcg_const_i32(rS(ctx
->opcode
));
2979 gen_addr_imm_index(ctx
, t0
, 0);
2980 gen_helper_stmw(cpu_env
, t0
, t1
);
2982 tcg_temp_free_i32(t1
);
2985 /*** Integer load and store strings ***/
2989 * PowerPC32 specification says we must generate an exception if rA is
2990 * in the range of registers to be loaded. In an other hand, IBM says
2991 * this is valid, but rA won't be loaded. For now, I'll follow the
2994 static void gen_lswi(DisasContext
*ctx
)
2998 int nb
= NB(ctx
->opcode
);
2999 int start
= rD(ctx
->opcode
);
3000 int ra
= rA(ctx
->opcode
);
3004 gen_align_no_le(ctx
);
3010 nr
= DIV_ROUND_UP(nb
, 4);
3011 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
3012 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3015 gen_set_access_type(ctx
, ACCESS_INT
);
3016 t0
= tcg_temp_new();
3017 gen_addr_register(ctx
, t0
);
3018 t1
= tcg_const_i32(nb
);
3019 t2
= tcg_const_i32(start
);
3020 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
3022 tcg_temp_free_i32(t1
);
3023 tcg_temp_free_i32(t2
);
3027 static void gen_lswx(DisasContext
*ctx
)
3030 TCGv_i32 t1
, t2
, t3
;
3033 gen_align_no_le(ctx
);
3036 gen_set_access_type(ctx
, ACCESS_INT
);
3037 t0
= tcg_temp_new();
3038 gen_addr_reg_index(ctx
, t0
);
3039 t1
= tcg_const_i32(rD(ctx
->opcode
));
3040 t2
= tcg_const_i32(rA(ctx
->opcode
));
3041 t3
= tcg_const_i32(rB(ctx
->opcode
));
3042 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
3044 tcg_temp_free_i32(t1
);
3045 tcg_temp_free_i32(t2
);
3046 tcg_temp_free_i32(t3
);
3050 static void gen_stswi(DisasContext
*ctx
)
3054 int nb
= NB(ctx
->opcode
);
3057 gen_align_no_le(ctx
);
3060 gen_set_access_type(ctx
, ACCESS_INT
);
3061 t0
= tcg_temp_new();
3062 gen_addr_register(ctx
, t0
);
3066 t1
= tcg_const_i32(nb
);
3067 t2
= tcg_const_i32(rS(ctx
->opcode
));
3068 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3070 tcg_temp_free_i32(t1
);
3071 tcg_temp_free_i32(t2
);
3075 static void gen_stswx(DisasContext
*ctx
)
3081 gen_align_no_le(ctx
);
3084 gen_set_access_type(ctx
, ACCESS_INT
);
3085 t0
= tcg_temp_new();
3086 gen_addr_reg_index(ctx
, t0
);
3087 t1
= tcg_temp_new_i32();
3088 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3089 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3090 t2
= tcg_const_i32(rS(ctx
->opcode
));
3091 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3093 tcg_temp_free_i32(t1
);
3094 tcg_temp_free_i32(t2
);
3097 /*** Memory synchronisation ***/
3099 static void gen_eieio(DisasContext
*ctx
)
3101 TCGBar bar
= TCG_MO_LD_ST
;
3104 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3105 * tell the CPU it is a store-forwarding barrier.
3107 if (ctx
->opcode
& 0x2000000) {
3109 * ISA says that "Reserved fields in instructions are ignored
3110 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3111 * as this is not an instruction software should be using,
3112 * complain to the user.
3114 if (!(ctx
->insns_flags2
& PPC2_ISA300
)) {
3115 qemu_log_mask(LOG_GUEST_ERROR
, "invalid eieio using bit 6 at @"
3116 TARGET_FMT_lx
"\n", ctx
->base
.pc_next
- 4);
3122 tcg_gen_mb(bar
| TCG_BAR_SC
);
3125 #if !defined(CONFIG_USER_ONLY)
3126 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
)
3131 if (!ctx
->lazy_tlb_flush
) {
3134 l
= gen_new_label();
3135 t
= tcg_temp_new_i32();
3136 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3137 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3139 gen_helper_check_tlb_flush_global(cpu_env
);
3141 gen_helper_check_tlb_flush_local(cpu_env
);
3144 tcg_temp_free_i32(t
);
3147 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
) { }
3151 static void gen_isync(DisasContext
*ctx
)
3154 * We need to check for a pending TLB flush. This can only happen in
3155 * kernel mode however so check MSR_PR
3158 gen_check_tlb_flush(ctx
, false);
3160 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3161 gen_stop_exception(ctx
);
3164 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3166 static void gen_load_locked(DisasContext
*ctx
, MemOp memop
)
3168 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3169 TCGv t0
= tcg_temp_new();
3171 gen_set_access_type(ctx
, ACCESS_RES
);
3172 gen_addr_reg_index(ctx
, t0
);
3173 tcg_gen_qemu_ld_tl(gpr
, t0
, ctx
->mem_idx
, memop
| MO_ALIGN
);
3174 tcg_gen_mov_tl(cpu_reserve
, t0
);
3175 tcg_gen_mov_tl(cpu_reserve_val
, gpr
);
3176 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3180 #define LARX(name, memop) \
3181 static void gen_##name(DisasContext *ctx) \
3183 gen_load_locked(ctx, memop); \
3187 LARX(lbarx
, DEF_MEMOP(MO_UB
))
3188 LARX(lharx
, DEF_MEMOP(MO_UW
))
3189 LARX(lwarx
, DEF_MEMOP(MO_UL
))
3191 static void gen_fetch_inc_conditional(DisasContext
*ctx
, MemOp memop
,
3192 TCGv EA
, TCGCond cond
, int addend
)
3194 TCGv t
= tcg_temp_new();
3195 TCGv t2
= tcg_temp_new();
3196 TCGv u
= tcg_temp_new();
3198 tcg_gen_qemu_ld_tl(t
, EA
, ctx
->mem_idx
, memop
);
3199 tcg_gen_addi_tl(t2
, EA
, MEMOP_GET_SIZE(memop
));
3200 tcg_gen_qemu_ld_tl(t2
, t2
, ctx
->mem_idx
, memop
);
3201 tcg_gen_addi_tl(u
, t
, addend
);
3203 /* E.g. for fetch and increment bounded... */
3204 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3205 tcg_gen_movcond_tl(cond
, u
, t
, t2
, u
, t
);
3206 tcg_gen_qemu_st_tl(u
, EA
, ctx
->mem_idx
, memop
);
3208 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3209 tcg_gen_movi_tl(u
, 1 << (MEMOP_GET_SIZE(memop
) * 8 - 1));
3210 tcg_gen_movcond_tl(cond
, cpu_gpr
[rD(ctx
->opcode
)], t
, t2
, t
, u
);
3217 static void gen_ld_atomic(DisasContext
*ctx
, MemOp memop
)
3219 uint32_t gpr_FC
= FC(ctx
->opcode
);
3220 TCGv EA
= tcg_temp_new();
3221 int rt
= rD(ctx
->opcode
);
3225 gen_addr_register(ctx
, EA
);
3227 src
= cpu_gpr
[(rt
+ 1) & 31];
3229 need_serial
= false;
3232 case 0: /* Fetch and add */
3233 tcg_gen_atomic_fetch_add_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3235 case 1: /* Fetch and xor */
3236 tcg_gen_atomic_fetch_xor_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3238 case 2: /* Fetch and or */
3239 tcg_gen_atomic_fetch_or_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3241 case 3: /* Fetch and 'and' */
3242 tcg_gen_atomic_fetch_and_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3244 case 4: /* Fetch and max unsigned */
3245 tcg_gen_atomic_fetch_umax_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3247 case 5: /* Fetch and max signed */
3248 tcg_gen_atomic_fetch_smax_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3250 case 6: /* Fetch and min unsigned */
3251 tcg_gen_atomic_fetch_umin_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3253 case 7: /* Fetch and min signed */
3254 tcg_gen_atomic_fetch_smin_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3257 tcg_gen_atomic_xchg_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3260 case 16: /* Compare and swap not equal */
3261 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3264 TCGv t0
= tcg_temp_new();
3265 TCGv t1
= tcg_temp_new();
3267 tcg_gen_qemu_ld_tl(t0
, EA
, ctx
->mem_idx
, memop
);
3268 if ((memop
& MO_SIZE
) == MO_64
|| TARGET_LONG_BITS
== 32) {
3269 tcg_gen_mov_tl(t1
, src
);
3271 tcg_gen_ext32u_tl(t1
, src
);
3273 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t0
, t1
,
3274 cpu_gpr
[(rt
+ 2) & 31], t0
);
3275 tcg_gen_qemu_st_tl(t1
, EA
, ctx
->mem_idx
, memop
);
3276 tcg_gen_mov_tl(dst
, t0
);
3283 case 24: /* Fetch and increment bounded */
3284 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3287 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_NE
, 1);
3290 case 25: /* Fetch and increment equal */
3291 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3294 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_EQ
, 1);
3297 case 28: /* Fetch and decrement bounded */
3298 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3301 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_NE
, -1);
3306 /* invoke data storage error handler */
3307 gen_exception_err(ctx
, POWERPC_EXCP_DSI
, POWERPC_EXCP_INVAL
);
3312 /* Restart with exclusive lock. */
3313 gen_helper_exit_atomic(cpu_env
);
3314 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3318 static void gen_lwat(DisasContext
*ctx
)
3320 gen_ld_atomic(ctx
, DEF_MEMOP(MO_UL
));
3324 static void gen_ldat(DisasContext
*ctx
)
3326 gen_ld_atomic(ctx
, DEF_MEMOP(MO_Q
));
3330 static void gen_st_atomic(DisasContext
*ctx
, MemOp memop
)
3332 uint32_t gpr_FC
= FC(ctx
->opcode
);
3333 TCGv EA
= tcg_temp_new();
3336 gen_addr_register(ctx
, EA
);
3337 src
= cpu_gpr
[rD(ctx
->opcode
)];
3338 discard
= tcg_temp_new();
3342 case 0: /* add and Store */
3343 tcg_gen_atomic_add_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3345 case 1: /* xor and Store */
3346 tcg_gen_atomic_xor_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3348 case 2: /* Or and Store */
3349 tcg_gen_atomic_or_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3351 case 3: /* 'and' and Store */
3352 tcg_gen_atomic_and_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3354 case 4: /* Store max unsigned */
3355 tcg_gen_atomic_umax_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3357 case 5: /* Store max signed */
3358 tcg_gen_atomic_smax_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3360 case 6: /* Store min unsigned */
3361 tcg_gen_atomic_umin_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3363 case 7: /* Store min signed */
3364 tcg_gen_atomic_smin_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3366 case 24: /* Store twin */
3367 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3368 /* Restart with exclusive lock. */
3369 gen_helper_exit_atomic(cpu_env
);
3370 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3372 TCGv t
= tcg_temp_new();
3373 TCGv t2
= tcg_temp_new();
3374 TCGv s
= tcg_temp_new();
3375 TCGv s2
= tcg_temp_new();
3376 TCGv ea_plus_s
= tcg_temp_new();
3378 tcg_gen_qemu_ld_tl(t
, EA
, ctx
->mem_idx
, memop
);
3379 tcg_gen_addi_tl(ea_plus_s
, EA
, MEMOP_GET_SIZE(memop
));
3380 tcg_gen_qemu_ld_tl(t2
, ea_plus_s
, ctx
->mem_idx
, memop
);
3381 tcg_gen_movcond_tl(TCG_COND_EQ
, s
, t
, t2
, src
, t
);
3382 tcg_gen_movcond_tl(TCG_COND_EQ
, s2
, t
, t2
, src
, t2
);
3383 tcg_gen_qemu_st_tl(s
, EA
, ctx
->mem_idx
, memop
);
3384 tcg_gen_qemu_st_tl(s2
, ea_plus_s
, ctx
->mem_idx
, memop
);
3386 tcg_temp_free(ea_plus_s
);
3394 /* invoke data storage error handler */
3395 gen_exception_err(ctx
, POWERPC_EXCP_DSI
, POWERPC_EXCP_INVAL
);
3397 tcg_temp_free(discard
);
3401 static void gen_stwat(DisasContext
*ctx
)
3403 gen_st_atomic(ctx
, DEF_MEMOP(MO_UL
));
3407 static void gen_stdat(DisasContext
*ctx
)
3409 gen_st_atomic(ctx
, DEF_MEMOP(MO_Q
));
3413 static void gen_conditional_store(DisasContext
*ctx
, MemOp memop
)
3415 TCGLabel
*l1
= gen_new_label();
3416 TCGLabel
*l2
= gen_new_label();
3417 TCGv t0
= tcg_temp_new();
3418 int reg
= rS(ctx
->opcode
);
3420 gen_set_access_type(ctx
, ACCESS_RES
);
3421 gen_addr_reg_index(ctx
, t0
);
3422 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3425 t0
= tcg_temp_new();
3426 tcg_gen_atomic_cmpxchg_tl(t0
, cpu_reserve
, cpu_reserve_val
,
3427 cpu_gpr
[reg
], ctx
->mem_idx
,
3428 DEF_MEMOP(memop
) | MO_ALIGN
);
3429 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, t0
, cpu_reserve_val
);
3430 tcg_gen_shli_tl(t0
, t0
, CRF_EQ_BIT
);
3431 tcg_gen_or_tl(t0
, t0
, cpu_so
);
3432 tcg_gen_trunc_tl_i32(cpu_crf
[0], t0
);
3439 * Address mismatch implies failure. But we still need to provide
3440 * the memory barrier semantics of the instruction.
3442 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3443 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3446 tcg_gen_movi_tl(cpu_reserve
, -1);
3449 #define STCX(name, memop) \
3450 static void gen_##name(DisasContext *ctx) \
3452 gen_conditional_store(ctx, memop); \
3455 STCX(stbcx_
, DEF_MEMOP(MO_UB
))
3456 STCX(sthcx_
, DEF_MEMOP(MO_UW
))
3457 STCX(stwcx_
, DEF_MEMOP(MO_UL
))
3459 #if defined(TARGET_PPC64)
3461 LARX(ldarx
, DEF_MEMOP(MO_Q
))
3463 STCX(stdcx_
, DEF_MEMOP(MO_Q
))
3466 static void gen_lqarx(DisasContext
*ctx
)
3468 int rd
= rD(ctx
->opcode
);
3471 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3472 (rd
== rB(ctx
->opcode
)))) {
3473 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3477 gen_set_access_type(ctx
, ACCESS_RES
);
3478 EA
= tcg_temp_new();
3479 gen_addr_reg_index(ctx
, EA
);
3481 /* Note that the low part is always in RD+1, even in LE mode. */
3482 lo
= cpu_gpr
[rd
+ 1];
3485 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3486 if (HAVE_ATOMIC128
) {
3487 TCGv_i32 oi
= tcg_temp_new_i32();
3489 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
| MO_ALIGN_16
,
3491 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
3493 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
| MO_ALIGN_16
,
3495 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
3497 tcg_temp_free_i32(oi
);
3498 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
3500 /* Restart with exclusive lock. */
3501 gen_helper_exit_atomic(cpu_env
);
3502 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3506 } else if (ctx
->le_mode
) {
3507 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
| MO_ALIGN_16
);
3508 tcg_gen_mov_tl(cpu_reserve
, EA
);
3509 gen_addr_add(ctx
, EA
, EA
, 8);
3510 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
3512 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
| MO_ALIGN_16
);
3513 tcg_gen_mov_tl(cpu_reserve
, EA
);
3514 gen_addr_add(ctx
, EA
, EA
, 8);
3515 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
3519 tcg_gen_st_tl(hi
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3520 tcg_gen_st_tl(lo
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3524 static void gen_stqcx_(DisasContext
*ctx
)
3526 int rs
= rS(ctx
->opcode
);
3529 if (unlikely(rs
& 1)) {
3530 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3534 gen_set_access_type(ctx
, ACCESS_RES
);
3535 EA
= tcg_temp_new();
3536 gen_addr_reg_index(ctx
, EA
);
3538 /* Note that the low part is always in RS+1, even in LE mode. */
3539 lo
= cpu_gpr
[rs
+ 1];
3542 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3543 if (HAVE_CMPXCHG128
) {
3544 TCGv_i32 oi
= tcg_const_i32(DEF_MEMOP(MO_Q
) | MO_ALIGN_16
);
3546 gen_helper_stqcx_le_parallel(cpu_crf
[0], cpu_env
,
3549 gen_helper_stqcx_be_parallel(cpu_crf
[0], cpu_env
,
3552 tcg_temp_free_i32(oi
);
3554 /* Restart with exclusive lock. */
3555 gen_helper_exit_atomic(cpu_env
);
3556 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3560 TCGLabel
*lab_fail
= gen_new_label();
3561 TCGLabel
*lab_over
= gen_new_label();
3562 TCGv_i64 t0
= tcg_temp_new_i64();
3563 TCGv_i64 t1
= tcg_temp_new_i64();
3565 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, lab_fail
);
3568 gen_qemu_ld64_i64(ctx
, t0
, cpu_reserve
);
3569 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
3570 ? offsetof(CPUPPCState
, reserve_val2
)
3571 : offsetof(CPUPPCState
, reserve_val
)));
3572 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
3574 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
3575 gen_qemu_ld64_i64(ctx
, t0
, t0
);
3576 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
3577 ? offsetof(CPUPPCState
, reserve_val
)
3578 : offsetof(CPUPPCState
, reserve_val2
)));
3579 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
3582 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? lo
: hi
, cpu_reserve
);
3583 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
3584 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? hi
: lo
, t0
);
3586 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3587 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
3588 tcg_gen_br(lab_over
);
3590 gen_set_label(lab_fail
);
3591 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3593 gen_set_label(lab_over
);
3594 tcg_gen_movi_tl(cpu_reserve
, -1);
3595 tcg_temp_free_i64(t0
);
3596 tcg_temp_free_i64(t1
);
3599 #endif /* defined(TARGET_PPC64) */
3602 static void gen_sync(DisasContext
*ctx
)
3604 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3607 * We may need to check for a pending TLB flush.
3609 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3611 * Additionally, this can only happen in kernel mode however so
3612 * check MSR_PR as well.
3614 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3615 gen_check_tlb_flush(ctx
, true);
3617 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3621 static void gen_wait(DisasContext
*ctx
)
3623 TCGv_i32 t0
= tcg_const_i32(1);
3624 tcg_gen_st_i32(t0
, cpu_env
,
3625 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3626 tcg_temp_free_i32(t0
);
3627 /* Stop translation, as the CPU is supposed to sleep from now */
3628 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3631 #if defined(TARGET_PPC64)
3632 static void gen_doze(DisasContext
*ctx
)
3634 #if defined(CONFIG_USER_ONLY)
3640 t
= tcg_const_i32(PPC_PM_DOZE
);
3641 gen_helper_pminsn(cpu_env
, t
);
3642 tcg_temp_free_i32(t
);
3643 /* Stop translation, as the CPU is supposed to sleep from now */
3644 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3645 #endif /* defined(CONFIG_USER_ONLY) */
3648 static void gen_nap(DisasContext
*ctx
)
3650 #if defined(CONFIG_USER_ONLY)
3656 t
= tcg_const_i32(PPC_PM_NAP
);
3657 gen_helper_pminsn(cpu_env
, t
);
3658 tcg_temp_free_i32(t
);
3659 /* Stop translation, as the CPU is supposed to sleep from now */
3660 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3661 #endif /* defined(CONFIG_USER_ONLY) */
3664 static void gen_stop(DisasContext
*ctx
)
3666 #if defined(CONFIG_USER_ONLY)
3672 t
= tcg_const_i32(PPC_PM_STOP
);
3673 gen_helper_pminsn(cpu_env
, t
);
3674 tcg_temp_free_i32(t
);
3675 /* Stop translation, as the CPU is supposed to sleep from now */
3676 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3677 #endif /* defined(CONFIG_USER_ONLY) */
3680 static void gen_sleep(DisasContext
*ctx
)
3682 #if defined(CONFIG_USER_ONLY)
3688 t
= tcg_const_i32(PPC_PM_SLEEP
);
3689 gen_helper_pminsn(cpu_env
, t
);
3690 tcg_temp_free_i32(t
);
3691 /* Stop translation, as the CPU is supposed to sleep from now */
3692 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3693 #endif /* defined(CONFIG_USER_ONLY) */
3696 static void gen_rvwinkle(DisasContext
*ctx
)
3698 #if defined(CONFIG_USER_ONLY)
3704 t
= tcg_const_i32(PPC_PM_RVWINKLE
);
3705 gen_helper_pminsn(cpu_env
, t
);
3706 tcg_temp_free_i32(t
);
3707 /* Stop translation, as the CPU is supposed to sleep from now */
3708 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3709 #endif /* defined(CONFIG_USER_ONLY) */
3711 #endif /* #if defined(TARGET_PPC64) */
3713 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3715 #if defined(TARGET_PPC64)
3716 if (ctx
->has_cfar
) {
3717 tcg_gen_movi_tl(cpu_cfar
, nip
);
3722 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3724 if (unlikely(ctx
->singlestep_enabled
)) {
3728 #ifndef CONFIG_USER_ONLY
3729 return (ctx
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3735 static void gen_lookup_and_goto_ptr(DisasContext
*ctx
)
3737 int sse
= ctx
->singlestep_enabled
;
3738 if (unlikely(sse
)) {
3739 if (sse
& GDBSTUB_SINGLE_STEP
) {
3740 gen_debug_exception(ctx
);
3741 } else if (sse
& (CPU_SINGLE_STEP
| CPU_BRANCH_STEP
)) {
3742 uint32_t excp
= gen_prep_dbgex(ctx
);
3743 gen_exception(ctx
, excp
);
3745 tcg_gen_exit_tb(NULL
, 0);
3747 tcg_gen_lookup_and_goto_ptr();
3752 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3754 if (NARROW_MODE(ctx
)) {
3755 dest
= (uint32_t) dest
;
3757 if (use_goto_tb(ctx
, dest
)) {
3759 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3760 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
3762 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3763 gen_lookup_and_goto_ptr(ctx
);
3767 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3769 if (NARROW_MODE(ctx
)) {
3770 nip
= (uint32_t)nip
;
3772 tcg_gen_movi_tl(cpu_lr
, nip
);
3776 static void gen_b(DisasContext
*ctx
)
3778 target_ulong li
, target
;
3780 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3781 /* sign extend LI */
3782 li
= LI(ctx
->opcode
);
3783 li
= (li
^ 0x02000000) - 0x02000000;
3784 if (likely(AA(ctx
->opcode
) == 0)) {
3785 target
= ctx
->base
.pc_next
+ li
- 4;
3789 if (LK(ctx
->opcode
)) {
3790 gen_setlr(ctx
, ctx
->base
.pc_next
);
3792 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3793 gen_goto_tb(ctx
, 0, target
);
3801 static void gen_bcond(DisasContext
*ctx
, int type
)
3803 uint32_t bo
= BO(ctx
->opcode
);
3806 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3808 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3809 target
= tcg_temp_local_new();
3810 if (type
== BCOND_CTR
) {
3811 tcg_gen_mov_tl(target
, cpu_ctr
);
3812 } else if (type
== BCOND_TAR
) {
3813 gen_load_spr(target
, SPR_TAR
);
3815 tcg_gen_mov_tl(target
, cpu_lr
);
3820 if (LK(ctx
->opcode
)) {
3821 gen_setlr(ctx
, ctx
->base
.pc_next
);
3823 l1
= gen_new_label();
3824 if ((bo
& 0x4) == 0) {
3825 /* Decrement and test CTR */
3826 TCGv temp
= tcg_temp_new();
3828 if (type
== BCOND_CTR
) {
3830 * All ISAs up to v3 describe this form of bcctr as invalid but
3831 * some processors, ie. 64-bit server processors compliant with
3832 * arch 2.x, do implement a "test and decrement" logic instead,
3833 * as described in their respective UMs. This logic involves CTR
3834 * to act as both the branch target and a counter, which makes
3835 * it basically useless and thus never used in real code.
3837 * This form was hence chosen to trigger extra micro-architectural
3838 * side-effect on real HW needed for the Spectre v2 workaround.
3839 * It is up to guests that implement such workaround, ie. linux, to
3840 * use this form in a way it just triggers the side-effect without
3841 * doing anything else harmful.
3843 if (unlikely(!is_book3s_arch2x(ctx
))) {
3844 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3845 tcg_temp_free(temp
);
3846 tcg_temp_free(target
);
3850 if (NARROW_MODE(ctx
)) {
3851 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3853 tcg_gen_mov_tl(temp
, cpu_ctr
);
3856 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3858 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3860 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3862 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3863 if (NARROW_MODE(ctx
)) {
3864 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3866 tcg_gen_mov_tl(temp
, cpu_ctr
);
3869 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3871 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3874 tcg_temp_free(temp
);
3876 if ((bo
& 0x10) == 0) {
3878 uint32_t bi
= BI(ctx
->opcode
);
3879 uint32_t mask
= 0x08 >> (bi
& 0x03);
3880 TCGv_i32 temp
= tcg_temp_new_i32();
3883 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3884 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3886 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3887 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3889 tcg_temp_free_i32(temp
);
3891 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3892 if (type
== BCOND_IM
) {
3893 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3894 if (likely(AA(ctx
->opcode
) == 0)) {
3895 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ li
- 4);
3897 gen_goto_tb(ctx
, 0, li
);
3900 if (NARROW_MODE(ctx
)) {
3901 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3903 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3905 gen_lookup_and_goto_ptr(ctx
);
3906 tcg_temp_free(target
);
3908 if ((bo
& 0x14) != 0x14) {
3909 /* fallthrough case */
3911 gen_goto_tb(ctx
, 1, ctx
->base
.pc_next
);
3915 static void gen_bc(DisasContext
*ctx
)
3917 gen_bcond(ctx
, BCOND_IM
);
3920 static void gen_bcctr(DisasContext
*ctx
)
3922 gen_bcond(ctx
, BCOND_CTR
);
3925 static void gen_bclr(DisasContext
*ctx
)
3927 gen_bcond(ctx
, BCOND_LR
);
3930 static void gen_bctar(DisasContext
*ctx
)
3932 gen_bcond(ctx
, BCOND_TAR
);
3935 /*** Condition register logical ***/
3936 #define GEN_CRLOGIC(name, tcg_op, opc) \
3937 static void glue(gen_, name)(DisasContext *ctx) \
3942 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3943 t0 = tcg_temp_new_i32(); \
3945 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3947 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3949 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3950 t1 = tcg_temp_new_i32(); \
3951 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3953 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3955 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3957 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3958 tcg_op(t0, t0, t1); \
3959 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3960 tcg_gen_andi_i32(t0, t0, bitmask); \
3961 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3962 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3963 tcg_temp_free_i32(t0); \
3964 tcg_temp_free_i32(t1); \
3968 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3970 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3972 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3974 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3976 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3978 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3980 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3982 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3985 static void gen_mcrf(DisasContext
*ctx
)
3987 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3990 /*** System linkage ***/
3992 /* rfi (supervisor only) */
3993 static void gen_rfi(DisasContext
*ctx
)
3995 #if defined(CONFIG_USER_ONLY)
3999 * This instruction doesn't exist anymore on 64-bit server
4000 * processors compliant with arch 2.x
4002 if (is_book3s_arch2x(ctx
)) {
4003 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4006 /* Restore CPU state */
4008 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4011 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
4012 gen_helper_rfi(cpu_env
);
4013 gen_sync_exception(ctx
);
4017 #if defined(TARGET_PPC64)
4018 static void gen_rfid(DisasContext
*ctx
)
4020 #if defined(CONFIG_USER_ONLY)
4023 /* Restore CPU state */
4025 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4028 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
4029 gen_helper_rfid(cpu_env
);
4030 gen_sync_exception(ctx
);
4034 #if !defined(CONFIG_USER_ONLY)
4035 static void gen_rfscv(DisasContext
*ctx
)
4037 #if defined(CONFIG_USER_ONLY)
4040 /* Restore CPU state */
4042 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4045 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
4046 gen_helper_rfscv(cpu_env
);
4047 gen_sync_exception(ctx
);
4052 static void gen_hrfid(DisasContext
*ctx
)
4054 #if defined(CONFIG_USER_ONLY)
4057 /* Restore CPU state */
4059 gen_helper_hrfid(cpu_env
);
4060 gen_sync_exception(ctx
);
4066 #if defined(CONFIG_USER_ONLY)
4067 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4069 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4070 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED
4072 static void gen_sc(DisasContext
*ctx
)
4076 lev
= (ctx
->opcode
>> 5) & 0x7F;
4077 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
4080 #if defined(TARGET_PPC64)
4081 #if !defined(CONFIG_USER_ONLY)
4082 static void gen_scv(DisasContext
*ctx
)
4086 if (unlikely(!ctx
->scv_enabled
)) {
4087 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_SCV
);
4091 lev
= (ctx
->opcode
>> 5) & 0x7F;
4092 gen_exception_err(ctx
, POWERPC_SYSCALL_VECTORED
, lev
);
4099 /* Check for unconditional traps (always or never) */
4100 static bool check_unconditional_trap(DisasContext
*ctx
)
4103 if (TO(ctx
->opcode
) == 0) {
4107 if (TO(ctx
->opcode
) == 31) {
4108 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
4115 static void gen_tw(DisasContext
*ctx
)
4119 if (check_unconditional_trap(ctx
)) {
4122 t0
= tcg_const_i32(TO(ctx
->opcode
));
4123 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4125 tcg_temp_free_i32(t0
);
4129 static void gen_twi(DisasContext
*ctx
)
4134 if (check_unconditional_trap(ctx
)) {
4137 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4138 t1
= tcg_const_i32(TO(ctx
->opcode
));
4139 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4141 tcg_temp_free_i32(t1
);
4144 #if defined(TARGET_PPC64)
4146 static void gen_td(DisasContext
*ctx
)
4150 if (check_unconditional_trap(ctx
)) {
4153 t0
= tcg_const_i32(TO(ctx
->opcode
));
4154 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4156 tcg_temp_free_i32(t0
);
4160 static void gen_tdi(DisasContext
*ctx
)
4165 if (check_unconditional_trap(ctx
)) {
4168 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4169 t1
= tcg_const_i32(TO(ctx
->opcode
));
4170 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4172 tcg_temp_free_i32(t1
);
4176 /*** Processor control ***/
4178 static void gen_read_xer(DisasContext
*ctx
, TCGv dst
)
4180 TCGv t0
= tcg_temp_new();
4181 TCGv t1
= tcg_temp_new();
4182 TCGv t2
= tcg_temp_new();
4183 tcg_gen_mov_tl(dst
, cpu_xer
);
4184 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
4185 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
4186 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
4187 tcg_gen_or_tl(t0
, t0
, t1
);
4188 tcg_gen_or_tl(dst
, dst
, t2
);
4189 tcg_gen_or_tl(dst
, dst
, t0
);
4190 if (is_isa300(ctx
)) {
4191 tcg_gen_shli_tl(t0
, cpu_ov32
, XER_OV32
);
4192 tcg_gen_or_tl(dst
, dst
, t0
);
4193 tcg_gen_shli_tl(t0
, cpu_ca32
, XER_CA32
);
4194 tcg_gen_or_tl(dst
, dst
, t0
);
4201 static void gen_write_xer(TCGv src
)
4203 /* Write all flags, while reading back check for isa300 */
4204 tcg_gen_andi_tl(cpu_xer
, src
,
4206 (1u << XER_OV
) | (1u << XER_OV32
) |
4207 (1u << XER_CA
) | (1u << XER_CA32
)));
4208 tcg_gen_extract_tl(cpu_ov32
, src
, XER_OV32
, 1);
4209 tcg_gen_extract_tl(cpu_ca32
, src
, XER_CA32
, 1);
4210 tcg_gen_extract_tl(cpu_so
, src
, XER_SO
, 1);
4211 tcg_gen_extract_tl(cpu_ov
, src
, XER_OV
, 1);
4212 tcg_gen_extract_tl(cpu_ca
, src
, XER_CA
, 1);
4216 static void gen_mcrxr(DisasContext
*ctx
)
4218 TCGv_i32 t0
= tcg_temp_new_i32();
4219 TCGv_i32 t1
= tcg_temp_new_i32();
4220 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4222 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
4223 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
4224 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
4225 tcg_gen_shli_i32(t0
, t0
, 3);
4226 tcg_gen_shli_i32(t1
, t1
, 2);
4227 tcg_gen_shli_i32(dst
, dst
, 1);
4228 tcg_gen_or_i32(dst
, dst
, t0
);
4229 tcg_gen_or_i32(dst
, dst
, t1
);
4230 tcg_temp_free_i32(t0
);
4231 tcg_temp_free_i32(t1
);
4233 tcg_gen_movi_tl(cpu_so
, 0);
4234 tcg_gen_movi_tl(cpu_ov
, 0);
4235 tcg_gen_movi_tl(cpu_ca
, 0);
4240 static void gen_mcrxrx(DisasContext
*ctx
)
4242 TCGv t0
= tcg_temp_new();
4243 TCGv t1
= tcg_temp_new();
4244 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4246 /* copy OV and OV32 */
4247 tcg_gen_shli_tl(t0
, cpu_ov
, 1);
4248 tcg_gen_or_tl(t0
, t0
, cpu_ov32
);
4249 tcg_gen_shli_tl(t0
, t0
, 2);
4250 /* copy CA and CA32 */
4251 tcg_gen_shli_tl(t1
, cpu_ca
, 1);
4252 tcg_gen_or_tl(t1
, t1
, cpu_ca32
);
4253 tcg_gen_or_tl(t0
, t0
, t1
);
4254 tcg_gen_trunc_tl_i32(dst
, t0
);
4261 static void gen_mfcr(DisasContext
*ctx
)
4265 if (likely(ctx
->opcode
& 0x00100000)) {
4266 crm
= CRM(ctx
->opcode
);
4267 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
4269 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
4270 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
4271 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
4274 TCGv_i32 t0
= tcg_temp_new_i32();
4275 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
4276 tcg_gen_shli_i32(t0
, t0
, 4);
4277 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
4278 tcg_gen_shli_i32(t0
, t0
, 4);
4279 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
4280 tcg_gen_shli_i32(t0
, t0
, 4);
4281 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
4282 tcg_gen_shli_i32(t0
, t0
, 4);
4283 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
4284 tcg_gen_shli_i32(t0
, t0
, 4);
4285 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
4286 tcg_gen_shli_i32(t0
, t0
, 4);
4287 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
4288 tcg_gen_shli_i32(t0
, t0
, 4);
4289 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
4290 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4291 tcg_temp_free_i32(t0
);
4296 static void gen_mfmsr(DisasContext
*ctx
)
4299 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
4302 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
4305 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
4306 printf("ERROR: try to access SPR %d !\n", sprn
);
4309 #define SPR_NOACCESS (&spr_noaccess)
4312 static inline void gen_op_mfspr(DisasContext
*ctx
)
4314 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
4315 uint32_t sprn
= SPR(ctx
->opcode
);
4317 #if defined(CONFIG_USER_ONLY)
4318 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4321 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4322 } else if (ctx
->hv
) {
4323 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
4325 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
4328 if (likely(read_cb
!= NULL
)) {
4329 if (likely(read_cb
!= SPR_NOACCESS
)) {
4330 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
4332 /* Privilege exception */
4334 * This is a hack to avoid warnings when running Linux:
4335 * this OS breaks the PowerPC virtualisation model,
4336 * allowing userland application to read the PVR
4338 if (sprn
!= SPR_PVR
) {
4339 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to read privileged spr "
4340 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
4341 ctx
->base
.pc_next
- 4);
4343 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4346 /* ISA 2.07 defines these as no-ops */
4347 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4348 (sprn
>= 808 && sprn
<= 811)) {
4353 qemu_log_mask(LOG_GUEST_ERROR
,
4354 "Trying to read invalid spr %d (0x%03x) at "
4355 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->base
.pc_next
- 4);
4358 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4359 * generate a priv, a hv emu or a no-op
4363 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4366 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
4367 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4373 static void gen_mfspr(DisasContext
*ctx
)
4379 static void gen_mftb(DisasContext
*ctx
)
4385 static void gen_mtcrf(DisasContext
*ctx
)
4389 crm
= CRM(ctx
->opcode
);
4390 if (likely((ctx
->opcode
& 0x00100000))) {
4391 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4392 TCGv_i32 temp
= tcg_temp_new_i32();
4394 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4395 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4396 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4397 tcg_temp_free_i32(temp
);
4400 TCGv_i32 temp
= tcg_temp_new_i32();
4401 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4402 for (crn
= 0 ; crn
< 8 ; crn
++) {
4403 if (crm
& (1 << crn
)) {
4404 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4405 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4408 tcg_temp_free_i32(temp
);
4413 #if defined(TARGET_PPC64)
4414 static void gen_mtmsrd(DisasContext
*ctx
)
4418 #if !defined(CONFIG_USER_ONLY)
4419 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4422 if (ctx
->opcode
& 0x00010000) {
4423 /* L=1 form only updates EE and RI */
4424 TCGv t0
= tcg_temp_new();
4425 TCGv t1
= tcg_temp_new();
4426 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)],
4427 (1 << MSR_RI
) | (1 << MSR_EE
));
4428 tcg_gen_andi_tl(t1
, cpu_msr
,
4429 ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4430 tcg_gen_or_tl(t1
, t1
, t0
);
4432 gen_helper_store_msr(cpu_env
, t1
);
4438 * XXX: we need to update nip before the store if we enter
4439 * power saving mode, we will exit the loop directly from
4442 gen_update_nip(ctx
, ctx
->base
.pc_next
);
4443 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4445 /* Must stop the translation as machine state (may have) changed */
4446 gen_stop_exception(ctx
);
4447 #endif /* !defined(CONFIG_USER_ONLY) */
4449 #endif /* defined(TARGET_PPC64) */
4451 static void gen_mtmsr(DisasContext
*ctx
)
4455 #if !defined(CONFIG_USER_ONLY)
4456 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4459 if (ctx
->opcode
& 0x00010000) {
4460 /* L=1 form only updates EE and RI */
4461 TCGv t0
= tcg_temp_new();
4462 TCGv t1
= tcg_temp_new();
4463 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)],
4464 (1 << MSR_RI
) | (1 << MSR_EE
));
4465 tcg_gen_andi_tl(t1
, cpu_msr
,
4466 ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4467 tcg_gen_or_tl(t1
, t1
, t0
);
4469 gen_helper_store_msr(cpu_env
, t1
);
4474 TCGv msr
= tcg_temp_new();
4477 * XXX: we need to update nip before the store if we enter
4478 * power saving mode, we will exit the loop directly from
4481 gen_update_nip(ctx
, ctx
->base
.pc_next
);
4482 #if defined(TARGET_PPC64)
4483 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4485 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4487 gen_helper_store_msr(cpu_env
, msr
);
4490 /* Must stop the translation as machine state (may have) changed */
4491 gen_stop_exception(ctx
);
4496 static void gen_mtspr(DisasContext
*ctx
)
4498 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4499 uint32_t sprn
= SPR(ctx
->opcode
);
4501 #if defined(CONFIG_USER_ONLY)
4502 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4505 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4506 } else if (ctx
->hv
) {
4507 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4509 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4512 if (likely(write_cb
!= NULL
)) {
4513 if (likely(write_cb
!= SPR_NOACCESS
)) {
4514 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4516 /* Privilege exception */
4517 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to write privileged spr "
4518 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
4519 ctx
->base
.pc_next
- 4);
4520 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4523 /* ISA 2.07 defines these as no-ops */
4524 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4525 (sprn
>= 808 && sprn
<= 811)) {
4531 qemu_log_mask(LOG_GUEST_ERROR
,
4532 "Trying to write invalid spr %d (0x%03x) at "
4533 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->base
.pc_next
- 4);
4537 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4538 * generate a priv, a hv emu or a no-op
4542 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4545 if (ctx
->pr
|| sprn
== 0) {
4546 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4552 #if defined(TARGET_PPC64)
4554 static void gen_setb(DisasContext
*ctx
)
4556 TCGv_i32 t0
= tcg_temp_new_i32();
4557 TCGv_i32 t8
= tcg_temp_new_i32();
4558 TCGv_i32 tm1
= tcg_temp_new_i32();
4559 int crf
= crfS(ctx
->opcode
);
4561 tcg_gen_setcondi_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], 4);
4562 tcg_gen_movi_i32(t8
, 8);
4563 tcg_gen_movi_i32(tm1
, -1);
4564 tcg_gen_movcond_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], t8
, tm1
, t0
);
4565 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4567 tcg_temp_free_i32(t0
);
4568 tcg_temp_free_i32(t8
);
4569 tcg_temp_free_i32(tm1
);
4573 /*** Cache management ***/
4576 static void gen_dcbf(DisasContext
*ctx
)
4578 /* XXX: specification says this is treated as a load by the MMU */
4580 gen_set_access_type(ctx
, ACCESS_CACHE
);
4581 t0
= tcg_temp_new();
4582 gen_addr_reg_index(ctx
, t0
);
4583 gen_qemu_ld8u(ctx
, t0
, t0
);
4587 /* dcbfep (external PID dcbf) */
4588 static void gen_dcbfep(DisasContext
*ctx
)
4590 /* XXX: specification says this is treated as a load by the MMU */
4593 gen_set_access_type(ctx
, ACCESS_CACHE
);
4594 t0
= tcg_temp_new();
4595 gen_addr_reg_index(ctx
, t0
);
4596 tcg_gen_qemu_ld_tl(t0
, t0
, PPC_TLB_EPID_LOAD
, DEF_MEMOP(MO_UB
));
4600 /* dcbi (Supervisor only) */
4601 static void gen_dcbi(DisasContext
*ctx
)
4603 #if defined(CONFIG_USER_ONLY)
4609 EA
= tcg_temp_new();
4610 gen_set_access_type(ctx
, ACCESS_CACHE
);
4611 gen_addr_reg_index(ctx
, EA
);
4612 val
= tcg_temp_new();
4613 /* XXX: specification says this should be treated as a store by the MMU */
4614 gen_qemu_ld8u(ctx
, val
, EA
);
4615 gen_qemu_st8(ctx
, val
, EA
);
4618 #endif /* defined(CONFIG_USER_ONLY) */
4622 static void gen_dcbst(DisasContext
*ctx
)
4624 /* XXX: specification say this is treated as a load by the MMU */
4626 gen_set_access_type(ctx
, ACCESS_CACHE
);
4627 t0
= tcg_temp_new();
4628 gen_addr_reg_index(ctx
, t0
);
4629 gen_qemu_ld8u(ctx
, t0
, t0
);
4633 /* dcbstep (dcbstep External PID version) */
4634 static void gen_dcbstep(DisasContext
*ctx
)
4636 /* XXX: specification say this is treated as a load by the MMU */
4638 gen_set_access_type(ctx
, ACCESS_CACHE
);
4639 t0
= tcg_temp_new();
4640 gen_addr_reg_index(ctx
, t0
);
4641 tcg_gen_qemu_ld_tl(t0
, t0
, PPC_TLB_EPID_LOAD
, DEF_MEMOP(MO_UB
));
4646 static void gen_dcbt(DisasContext
*ctx
)
4649 * interpreted as no-op
4650 * XXX: specification say this is treated as a load by the MMU but
4651 * does not generate any exception
4656 static void gen_dcbtep(DisasContext
*ctx
)
4659 * interpreted as no-op
4660 * XXX: specification say this is treated as a load by the MMU but
4661 * does not generate any exception
4666 static void gen_dcbtst(DisasContext
*ctx
)
4669 * interpreted as no-op
4670 * XXX: specification say this is treated as a load by the MMU but
4671 * does not generate any exception
4676 static void gen_dcbtstep(DisasContext
*ctx
)
4679 * interpreted as no-op
4680 * XXX: specification say this is treated as a load by the MMU but
4681 * does not generate any exception
4686 static void gen_dcbtls(DisasContext
*ctx
)
4688 /* Always fails locking the cache */
4689 TCGv t0
= tcg_temp_new();
4690 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4691 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4692 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4697 static void gen_dcbz(DisasContext
*ctx
)
4702 gen_set_access_type(ctx
, ACCESS_CACHE
);
4703 tcgv_addr
= tcg_temp_new();
4704 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
4705 gen_addr_reg_index(ctx
, tcgv_addr
);
4706 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_op
);
4707 tcg_temp_free(tcgv_addr
);
4708 tcg_temp_free_i32(tcgv_op
);
4712 static void gen_dcbzep(DisasContext
*ctx
)
4717 gen_set_access_type(ctx
, ACCESS_CACHE
);
4718 tcgv_addr
= tcg_temp_new();
4719 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
4720 gen_addr_reg_index(ctx
, tcgv_addr
);
4721 gen_helper_dcbzep(cpu_env
, tcgv_addr
, tcgv_op
);
4722 tcg_temp_free(tcgv_addr
);
4723 tcg_temp_free_i32(tcgv_op
);
4727 static void gen_dst(DisasContext
*ctx
)
4729 if (rA(ctx
->opcode
) == 0) {
4730 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4732 /* interpreted as no-op */
4737 static void gen_dstst(DisasContext
*ctx
)
4739 if (rA(ctx
->opcode
) == 0) {
4740 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4742 /* interpreted as no-op */
4748 static void gen_dss(DisasContext
*ctx
)
4750 /* interpreted as no-op */
4754 static void gen_icbi(DisasContext
*ctx
)
4757 gen_set_access_type(ctx
, ACCESS_CACHE
);
4758 t0
= tcg_temp_new();
4759 gen_addr_reg_index(ctx
, t0
);
4760 gen_helper_icbi(cpu_env
, t0
);
4765 static void gen_icbiep(DisasContext
*ctx
)
4768 gen_set_access_type(ctx
, ACCESS_CACHE
);
4769 t0
= tcg_temp_new();
4770 gen_addr_reg_index(ctx
, t0
);
4771 gen_helper_icbiep(cpu_env
, t0
);
4777 static void gen_dcba(DisasContext
*ctx
)
4780 * interpreted as no-op
4781 * XXX: specification say this is treated as a store by the MMU
4782 * but does not generate any exception
4786 /*** Segment register manipulation ***/
4787 /* Supervisor only: */
4790 static void gen_mfsr(DisasContext
*ctx
)
4792 #if defined(CONFIG_USER_ONLY)
4798 t0
= tcg_const_tl(SR(ctx
->opcode
));
4799 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4801 #endif /* defined(CONFIG_USER_ONLY) */
4805 static void gen_mfsrin(DisasContext
*ctx
)
4807 #if defined(CONFIG_USER_ONLY)
4813 t0
= tcg_temp_new();
4814 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4815 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4817 #endif /* defined(CONFIG_USER_ONLY) */
4821 static void gen_mtsr(DisasContext
*ctx
)
4823 #if defined(CONFIG_USER_ONLY)
4829 t0
= tcg_const_tl(SR(ctx
->opcode
));
4830 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4832 #endif /* defined(CONFIG_USER_ONLY) */
4836 static void gen_mtsrin(DisasContext
*ctx
)
4838 #if defined(CONFIG_USER_ONLY)
4844 t0
= tcg_temp_new();
4845 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4846 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4848 #endif /* defined(CONFIG_USER_ONLY) */
4851 #if defined(TARGET_PPC64)
4852 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4855 static void gen_mfsr_64b(DisasContext
*ctx
)
4857 #if defined(CONFIG_USER_ONLY)
4863 t0
= tcg_const_tl(SR(ctx
->opcode
));
4864 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4866 #endif /* defined(CONFIG_USER_ONLY) */
4870 static void gen_mfsrin_64b(DisasContext
*ctx
)
4872 #if defined(CONFIG_USER_ONLY)
4878 t0
= tcg_temp_new();
4879 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4880 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4882 #endif /* defined(CONFIG_USER_ONLY) */
4886 static void gen_mtsr_64b(DisasContext
*ctx
)
4888 #if defined(CONFIG_USER_ONLY)
4894 t0
= tcg_const_tl(SR(ctx
->opcode
));
4895 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4897 #endif /* defined(CONFIG_USER_ONLY) */
4901 static void gen_mtsrin_64b(DisasContext
*ctx
)
4903 #if defined(CONFIG_USER_ONLY)
4909 t0
= tcg_temp_new();
4910 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4911 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4913 #endif /* defined(CONFIG_USER_ONLY) */
4917 static void gen_slbmte(DisasContext
*ctx
)
4919 #if defined(CONFIG_USER_ONLY)
4924 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4925 cpu_gpr
[rS(ctx
->opcode
)]);
4926 #endif /* defined(CONFIG_USER_ONLY) */
4929 static void gen_slbmfee(DisasContext
*ctx
)
4931 #if defined(CONFIG_USER_ONLY)
4936 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4937 cpu_gpr
[rB(ctx
->opcode
)]);
4938 #endif /* defined(CONFIG_USER_ONLY) */
4941 static void gen_slbmfev(DisasContext
*ctx
)
4943 #if defined(CONFIG_USER_ONLY)
4948 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4949 cpu_gpr
[rB(ctx
->opcode
)]);
4950 #endif /* defined(CONFIG_USER_ONLY) */
4953 static void gen_slbfee_(DisasContext
*ctx
)
4955 #if defined(CONFIG_USER_ONLY)
4956 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4960 if (unlikely(ctx
->pr
)) {
4961 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4964 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4965 cpu_gpr
[rB(ctx
->opcode
)]);
4966 l1
= gen_new_label();
4967 l2
= gen_new_label();
4968 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4969 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4970 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
4973 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4977 #endif /* defined(TARGET_PPC64) */
4979 /*** Lookaside buffer management ***/
4980 /* Optional & supervisor only: */
4983 static void gen_tlbia(DisasContext
*ctx
)
4985 #if defined(CONFIG_USER_ONLY)
4990 gen_helper_tlbia(cpu_env
);
4991 #endif /* defined(CONFIG_USER_ONLY) */
4995 static void gen_tlbiel(DisasContext
*ctx
)
4997 #if defined(CONFIG_USER_ONLY)
5002 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5003 #endif /* defined(CONFIG_USER_ONLY) */
5007 static void gen_tlbie(DisasContext
*ctx
)
5009 #if defined(CONFIG_USER_ONLY)
5015 CHK_SV
; /* If gtse is set then tlbie is supervisor privileged */
5017 CHK_HV
; /* Else hypervisor privileged */
5020 if (NARROW_MODE(ctx
)) {
5021 TCGv t0
= tcg_temp_new();
5022 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
5023 gen_helper_tlbie(cpu_env
, t0
);
5026 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5028 t1
= tcg_temp_new_i32();
5029 tcg_gen_ld_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
5030 tcg_gen_ori_i32(t1
, t1
, TLB_NEED_GLOBAL_FLUSH
);
5031 tcg_gen_st_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
5032 tcg_temp_free_i32(t1
);
5033 #endif /* defined(CONFIG_USER_ONLY) */
5037 static void gen_tlbsync(DisasContext
*ctx
)
5039 #if defined(CONFIG_USER_ONLY)
5044 CHK_SV
; /* If gtse is set then tlbsync is supervisor privileged */
5046 CHK_HV
; /* Else hypervisor privileged */
5049 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
5050 if (ctx
->insns_flags
& PPC_BOOKE
) {
5051 gen_check_tlb_flush(ctx
, true);
5053 #endif /* defined(CONFIG_USER_ONLY) */
5056 #if defined(TARGET_PPC64)
5058 static void gen_slbia(DisasContext
*ctx
)
5060 #if defined(CONFIG_USER_ONLY)
5063 uint32_t ih
= (ctx
->opcode
>> 21) & 0x7;
5064 TCGv_i32 t0
= tcg_const_i32(ih
);
5068 gen_helper_slbia(cpu_env
, t0
);
5069 tcg_temp_free_i32(t0
);
5070 #endif /* defined(CONFIG_USER_ONLY) */
5074 static void gen_slbie(DisasContext
*ctx
)
5076 #if defined(CONFIG_USER_ONLY)
5081 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5082 #endif /* defined(CONFIG_USER_ONLY) */
5086 static void gen_slbieg(DisasContext
*ctx
)
5088 #if defined(CONFIG_USER_ONLY)
5093 gen_helper_slbieg(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5094 #endif /* defined(CONFIG_USER_ONLY) */
5098 static void gen_slbsync(DisasContext
*ctx
)
5100 #if defined(CONFIG_USER_ONLY)
5104 gen_check_tlb_flush(ctx
, true);
5105 #endif /* defined(CONFIG_USER_ONLY) */
5108 #endif /* defined(TARGET_PPC64) */
5110 /*** External control ***/
5114 static void gen_eciwx(DisasContext
*ctx
)
5117 /* Should check EAR[E] ! */
5118 gen_set_access_type(ctx
, ACCESS_EXT
);
5119 t0
= tcg_temp_new();
5120 gen_addr_reg_index(ctx
, t0
);
5121 tcg_gen_qemu_ld_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, ctx
->mem_idx
,
5122 DEF_MEMOP(MO_UL
| MO_ALIGN
));
5127 static void gen_ecowx(DisasContext
*ctx
)
5130 /* Should check EAR[E] ! */
5131 gen_set_access_type(ctx
, ACCESS_EXT
);
5132 t0
= tcg_temp_new();
5133 gen_addr_reg_index(ctx
, t0
);
5134 tcg_gen_qemu_st_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, ctx
->mem_idx
,
5135 DEF_MEMOP(MO_UL
| MO_ALIGN
));
5139 /* PowerPC 601 specific instructions */
5142 static void gen_abs(DisasContext
*ctx
)
5144 TCGv d
= cpu_gpr
[rD(ctx
->opcode
)];
5145 TCGv a
= cpu_gpr
[rA(ctx
->opcode
)];
5147 tcg_gen_abs_tl(d
, a
);
5148 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5149 gen_set_Rc0(ctx
, d
);
5154 static void gen_abso(DisasContext
*ctx
)
5156 TCGv d
= cpu_gpr
[rD(ctx
->opcode
)];
5157 TCGv a
= cpu_gpr
[rA(ctx
->opcode
)];
5159 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_ov
, a
, 0x80000000);
5160 tcg_gen_abs_tl(d
, a
);
5161 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
5162 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5163 gen_set_Rc0(ctx
, d
);
5168 static void gen_clcs(DisasContext
*ctx
)
5170 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
5171 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5172 tcg_temp_free_i32(t0
);
5173 /* Rc=1 sets CR0 to an undefined state */
5177 static void gen_div(DisasContext
*ctx
)
5179 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5180 cpu_gpr
[rB(ctx
->opcode
)]);
5181 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5182 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5187 static void gen_divo(DisasContext
*ctx
)
5189 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5190 cpu_gpr
[rB(ctx
->opcode
)]);
5191 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5192 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5197 static void gen_divs(DisasContext
*ctx
)
5199 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5200 cpu_gpr
[rB(ctx
->opcode
)]);
5201 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5202 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5206 /* divso - divso. */
5207 static void gen_divso(DisasContext
*ctx
)
5209 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5210 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5211 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5212 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5217 static void gen_doz(DisasContext
*ctx
)
5219 TCGLabel
*l1
= gen_new_label();
5220 TCGLabel
*l2
= gen_new_label();
5221 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)],
5222 cpu_gpr
[rA(ctx
->opcode
)], l1
);
5223 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
5224 cpu_gpr
[rA(ctx
->opcode
)]);
5227 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5229 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5230 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5235 static void gen_dozo(DisasContext
*ctx
)
5237 TCGLabel
*l1
= gen_new_label();
5238 TCGLabel
*l2
= gen_new_label();
5239 TCGv t0
= tcg_temp_new();
5240 TCGv t1
= tcg_temp_new();
5241 TCGv t2
= tcg_temp_new();
5242 /* Start with XER OV disabled, the most likely case */
5243 tcg_gen_movi_tl(cpu_ov
, 0);
5244 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)],
5245 cpu_gpr
[rA(ctx
->opcode
)], l1
);
5246 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5247 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5248 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
5249 tcg_gen_andc_tl(t1
, t1
, t2
);
5250 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5251 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5252 tcg_gen_movi_tl(cpu_ov
, 1);
5253 tcg_gen_movi_tl(cpu_so
, 1);
5256 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5261 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5262 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5267 static void gen_dozi(DisasContext
*ctx
)
5269 target_long simm
= SIMM(ctx
->opcode
);
5270 TCGLabel
*l1
= gen_new_label();
5271 TCGLabel
*l2
= gen_new_label();
5272 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
5273 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
5276 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5278 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5279 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5283 /* lscbx - lscbx. */
5284 static void gen_lscbx(DisasContext
*ctx
)
5286 TCGv t0
= tcg_temp_new();
5287 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
5288 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
5289 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
5291 gen_addr_reg_index(ctx
, t0
);
5292 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
5293 tcg_temp_free_i32(t1
);
5294 tcg_temp_free_i32(t2
);
5295 tcg_temp_free_i32(t3
);
5296 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
5297 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
5298 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5299 gen_set_Rc0(ctx
, t0
);
5304 /* maskg - maskg. */
5305 static void gen_maskg(DisasContext
*ctx
)
5307 TCGLabel
*l1
= gen_new_label();
5308 TCGv t0
= tcg_temp_new();
5309 TCGv t1
= tcg_temp_new();
5310 TCGv t2
= tcg_temp_new();
5311 TCGv t3
= tcg_temp_new();
5312 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
5313 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5314 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
5315 tcg_gen_addi_tl(t2
, t0
, 1);
5316 tcg_gen_shr_tl(t2
, t3
, t2
);
5317 tcg_gen_shr_tl(t3
, t3
, t1
);
5318 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
5319 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
5320 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5326 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5327 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5331 /* maskir - maskir. */
5332 static void gen_maskir(DisasContext
*ctx
)
5334 TCGv t0
= tcg_temp_new();
5335 TCGv t1
= tcg_temp_new();
5336 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5337 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5338 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5341 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5342 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5347 static void gen_mul(DisasContext
*ctx
)
5349 TCGv_i64 t0
= tcg_temp_new_i64();
5350 TCGv_i64 t1
= tcg_temp_new_i64();
5351 TCGv t2
= tcg_temp_new();
5352 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5353 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5354 tcg_gen_mul_i64(t0
, t0
, t1
);
5355 tcg_gen_trunc_i64_tl(t2
, t0
);
5356 gen_store_spr(SPR_MQ
, t2
);
5357 tcg_gen_shri_i64(t1
, t0
, 32);
5358 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5359 tcg_temp_free_i64(t0
);
5360 tcg_temp_free_i64(t1
);
5362 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5363 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5368 static void gen_mulo(DisasContext
*ctx
)
5370 TCGLabel
*l1
= gen_new_label();
5371 TCGv_i64 t0
= tcg_temp_new_i64();
5372 TCGv_i64 t1
= tcg_temp_new_i64();
5373 TCGv t2
= tcg_temp_new();
5374 /* Start with XER OV disabled, the most likely case */
5375 tcg_gen_movi_tl(cpu_ov
, 0);
5376 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5377 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5378 tcg_gen_mul_i64(t0
, t0
, t1
);
5379 tcg_gen_trunc_i64_tl(t2
, t0
);
5380 gen_store_spr(SPR_MQ
, t2
);
5381 tcg_gen_shri_i64(t1
, t0
, 32);
5382 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5383 tcg_gen_ext32s_i64(t1
, t0
);
5384 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
5385 tcg_gen_movi_tl(cpu_ov
, 1);
5386 tcg_gen_movi_tl(cpu_so
, 1);
5388 tcg_temp_free_i64(t0
);
5389 tcg_temp_free_i64(t1
);
5391 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5392 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5397 static void gen_nabs(DisasContext
*ctx
)
5399 TCGv d
= cpu_gpr
[rD(ctx
->opcode
)];
5400 TCGv a
= cpu_gpr
[rA(ctx
->opcode
)];
5402 tcg_gen_abs_tl(d
, a
);
5403 tcg_gen_neg_tl(d
, d
);
5404 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5405 gen_set_Rc0(ctx
, d
);
5409 /* nabso - nabso. */
5410 static void gen_nabso(DisasContext
*ctx
)
5412 TCGv d
= cpu_gpr
[rD(ctx
->opcode
)];
5413 TCGv a
= cpu_gpr
[rA(ctx
->opcode
)];
5415 tcg_gen_abs_tl(d
, a
);
5416 tcg_gen_neg_tl(d
, d
);
5417 /* nabs never overflows */
5418 tcg_gen_movi_tl(cpu_ov
, 0);
5419 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5420 gen_set_Rc0(ctx
, d
);
5425 static void gen_rlmi(DisasContext
*ctx
)
5427 uint32_t mb
= MB(ctx
->opcode
);
5428 uint32_t me
= ME(ctx
->opcode
);
5429 TCGv t0
= tcg_temp_new();
5430 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5431 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5432 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
5433 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
5435 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
5437 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5438 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5443 static void gen_rrib(DisasContext
*ctx
)
5445 TCGv t0
= tcg_temp_new();
5446 TCGv t1
= tcg_temp_new();
5447 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5448 tcg_gen_movi_tl(t1
, 0x80000000);
5449 tcg_gen_shr_tl(t1
, t1
, t0
);
5450 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5451 tcg_gen_and_tl(t0
, t0
, t1
);
5452 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
5453 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5456 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5457 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5462 static void gen_sle(DisasContext
*ctx
)
5464 TCGv t0
= tcg_temp_new();
5465 TCGv t1
= tcg_temp_new();
5466 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5467 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5468 tcg_gen_subfi_tl(t1
, 32, t1
);
5469 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5470 tcg_gen_or_tl(t1
, t0
, t1
);
5471 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5472 gen_store_spr(SPR_MQ
, t1
);
5475 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5476 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5481 static void gen_sleq(DisasContext
*ctx
)
5483 TCGv t0
= tcg_temp_new();
5484 TCGv t1
= tcg_temp_new();
5485 TCGv t2
= tcg_temp_new();
5486 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5487 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5488 tcg_gen_shl_tl(t2
, t2
, t0
);
5489 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5490 gen_load_spr(t1
, SPR_MQ
);
5491 gen_store_spr(SPR_MQ
, t0
);
5492 tcg_gen_and_tl(t0
, t0
, t2
);
5493 tcg_gen_andc_tl(t1
, t1
, t2
);
5494 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5498 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5499 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5504 static void gen_sliq(DisasContext
*ctx
)
5506 int sh
= SH(ctx
->opcode
);
5507 TCGv t0
= tcg_temp_new();
5508 TCGv t1
= tcg_temp_new();
5509 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5510 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5511 tcg_gen_or_tl(t1
, t0
, t1
);
5512 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5513 gen_store_spr(SPR_MQ
, t1
);
5516 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5517 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5521 /* slliq - slliq. */
5522 static void gen_slliq(DisasContext
*ctx
)
5524 int sh
= SH(ctx
->opcode
);
5525 TCGv t0
= tcg_temp_new();
5526 TCGv t1
= tcg_temp_new();
5527 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5528 gen_load_spr(t1
, SPR_MQ
);
5529 gen_store_spr(SPR_MQ
, t0
);
5530 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5531 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5532 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5535 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5536 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5541 static void gen_sllq(DisasContext
*ctx
)
5543 TCGLabel
*l1
= gen_new_label();
5544 TCGLabel
*l2
= gen_new_label();
5545 TCGv t0
= tcg_temp_local_new();
5546 TCGv t1
= tcg_temp_local_new();
5547 TCGv t2
= tcg_temp_local_new();
5548 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5549 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5550 tcg_gen_shl_tl(t1
, t1
, t2
);
5551 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5552 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5553 gen_load_spr(t0
, SPR_MQ
);
5554 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5557 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5558 gen_load_spr(t2
, SPR_MQ
);
5559 tcg_gen_andc_tl(t1
, t2
, t1
);
5560 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5565 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5566 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5571 static void gen_slq(DisasContext
*ctx
)
5573 TCGLabel
*l1
= gen_new_label();
5574 TCGv t0
= tcg_temp_new();
5575 TCGv t1
= tcg_temp_new();
5576 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5577 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5578 tcg_gen_subfi_tl(t1
, 32, t1
);
5579 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5580 tcg_gen_or_tl(t1
, t0
, t1
);
5581 gen_store_spr(SPR_MQ
, t1
);
5582 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5583 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5584 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5585 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5589 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5590 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5594 /* sraiq - sraiq. */
5595 static void gen_sraiq(DisasContext
*ctx
)
5597 int sh
= SH(ctx
->opcode
);
5598 TCGLabel
*l1
= gen_new_label();
5599 TCGv t0
= tcg_temp_new();
5600 TCGv t1
= tcg_temp_new();
5601 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5602 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5603 tcg_gen_or_tl(t0
, t0
, t1
);
5604 gen_store_spr(SPR_MQ
, t0
);
5605 tcg_gen_movi_tl(cpu_ca
, 0);
5606 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5607 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5608 tcg_gen_movi_tl(cpu_ca
, 1);
5610 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5613 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5614 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5619 static void gen_sraq(DisasContext
*ctx
)
5621 TCGLabel
*l1
= gen_new_label();
5622 TCGLabel
*l2
= gen_new_label();
5623 TCGv t0
= tcg_temp_new();
5624 TCGv t1
= tcg_temp_local_new();
5625 TCGv t2
= tcg_temp_local_new();
5626 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5627 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5628 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5629 tcg_gen_subfi_tl(t2
, 32, t2
);
5630 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5631 tcg_gen_or_tl(t0
, t0
, t2
);
5632 gen_store_spr(SPR_MQ
, t0
);
5633 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5634 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5635 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5636 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5639 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5640 tcg_gen_movi_tl(cpu_ca
, 0);
5641 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5642 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5643 tcg_gen_movi_tl(cpu_ca
, 1);
5647 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5648 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5653 static void gen_sre(DisasContext
*ctx
)
5655 TCGv t0
= tcg_temp_new();
5656 TCGv t1
= tcg_temp_new();
5657 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5658 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5659 tcg_gen_subfi_tl(t1
, 32, t1
);
5660 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5661 tcg_gen_or_tl(t1
, t0
, t1
);
5662 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5663 gen_store_spr(SPR_MQ
, t1
);
5666 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5667 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5672 static void gen_srea(DisasContext
*ctx
)
5674 TCGv t0
= tcg_temp_new();
5675 TCGv t1
= tcg_temp_new();
5676 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5677 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5678 gen_store_spr(SPR_MQ
, t0
);
5679 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5682 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5683 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5688 static void gen_sreq(DisasContext
*ctx
)
5690 TCGv t0
= tcg_temp_new();
5691 TCGv t1
= tcg_temp_new();
5692 TCGv t2
= tcg_temp_new();
5693 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5694 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5695 tcg_gen_shr_tl(t1
, t1
, t0
);
5696 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5697 gen_load_spr(t2
, SPR_MQ
);
5698 gen_store_spr(SPR_MQ
, t0
);
5699 tcg_gen_and_tl(t0
, t0
, t1
);
5700 tcg_gen_andc_tl(t2
, t2
, t1
);
5701 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5705 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5706 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5711 static void gen_sriq(DisasContext
*ctx
)
5713 int sh
= SH(ctx
->opcode
);
5714 TCGv t0
= tcg_temp_new();
5715 TCGv t1
= tcg_temp_new();
5716 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5717 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5718 tcg_gen_or_tl(t1
, t0
, t1
);
5719 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5720 gen_store_spr(SPR_MQ
, t1
);
5723 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5724 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5729 static void gen_srliq(DisasContext
*ctx
)
5731 int sh
= SH(ctx
->opcode
);
5732 TCGv t0
= tcg_temp_new();
5733 TCGv t1
= tcg_temp_new();
5734 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5735 gen_load_spr(t1
, SPR_MQ
);
5736 gen_store_spr(SPR_MQ
, t0
);
5737 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5738 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5739 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5742 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5743 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5748 static void gen_srlq(DisasContext
*ctx
)
5750 TCGLabel
*l1
= gen_new_label();
5751 TCGLabel
*l2
= gen_new_label();
5752 TCGv t0
= tcg_temp_local_new();
5753 TCGv t1
= tcg_temp_local_new();
5754 TCGv t2
= tcg_temp_local_new();
5755 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5756 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5757 tcg_gen_shr_tl(t2
, t1
, t2
);
5758 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5759 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5760 gen_load_spr(t0
, SPR_MQ
);
5761 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5764 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5765 tcg_gen_and_tl(t0
, t0
, t2
);
5766 gen_load_spr(t1
, SPR_MQ
);
5767 tcg_gen_andc_tl(t1
, t1
, t2
);
5768 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5773 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5774 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5779 static void gen_srq(DisasContext
*ctx
)
5781 TCGLabel
*l1
= gen_new_label();
5782 TCGv t0
= tcg_temp_new();
5783 TCGv t1
= tcg_temp_new();
5784 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5785 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5786 tcg_gen_subfi_tl(t1
, 32, t1
);
5787 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5788 tcg_gen_or_tl(t1
, t0
, t1
);
5789 gen_store_spr(SPR_MQ
, t1
);
5790 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5791 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5792 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5793 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5797 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5798 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5802 /* PowerPC 602 specific instructions */
5805 static void gen_dsa(DisasContext
*ctx
)
5808 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5812 static void gen_esa(DisasContext
*ctx
)
5815 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5819 static void gen_mfrom(DisasContext
*ctx
)
5821 #if defined(CONFIG_USER_ONLY)
5825 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5826 #endif /* defined(CONFIG_USER_ONLY) */
5829 /* 602 - 603 - G2 TLB management */
5832 static void gen_tlbld_6xx(DisasContext
*ctx
)
5834 #if defined(CONFIG_USER_ONLY)
5838 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5839 #endif /* defined(CONFIG_USER_ONLY) */
5843 static void gen_tlbli_6xx(DisasContext
*ctx
)
5845 #if defined(CONFIG_USER_ONLY)
5849 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5850 #endif /* defined(CONFIG_USER_ONLY) */
5853 /* 74xx TLB management */
5856 static void gen_tlbld_74xx(DisasContext
*ctx
)
5858 #if defined(CONFIG_USER_ONLY)
5862 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5863 #endif /* defined(CONFIG_USER_ONLY) */
5867 static void gen_tlbli_74xx(DisasContext
*ctx
)
5869 #if defined(CONFIG_USER_ONLY)
5873 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5874 #endif /* defined(CONFIG_USER_ONLY) */
5877 /* POWER instructions not in PowerPC 601 */
5880 static void gen_clf(DisasContext
*ctx
)
5882 /* Cache line flush: implemented as no-op */
5886 static void gen_cli(DisasContext
*ctx
)
5888 #if defined(CONFIG_USER_ONLY)
5891 /* Cache line invalidate: privileged and treated as no-op */
5893 #endif /* defined(CONFIG_USER_ONLY) */
5897 static void gen_dclst(DisasContext
*ctx
)
5899 /* Data cache line store: treated as no-op */
5902 static void gen_mfsri(DisasContext
*ctx
)
5904 #if defined(CONFIG_USER_ONLY)
5907 int ra
= rA(ctx
->opcode
);
5908 int rd
= rD(ctx
->opcode
);
5912 t0
= tcg_temp_new();
5913 gen_addr_reg_index(ctx
, t0
);
5914 tcg_gen_extract_tl(t0
, t0
, 28, 4);
5915 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5917 if (ra
!= 0 && ra
!= rd
) {
5918 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5920 #endif /* defined(CONFIG_USER_ONLY) */
5923 static void gen_rac(DisasContext
*ctx
)
5925 #if defined(CONFIG_USER_ONLY)
5931 t0
= tcg_temp_new();
5932 gen_addr_reg_index(ctx
, t0
);
5933 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5935 #endif /* defined(CONFIG_USER_ONLY) */
5938 static void gen_rfsvc(DisasContext
*ctx
)
5940 #if defined(CONFIG_USER_ONLY)
5945 gen_helper_rfsvc(cpu_env
);
5946 gen_sync_exception(ctx
);
5947 #endif /* defined(CONFIG_USER_ONLY) */
5950 /* svc is not implemented for now */
5952 /* BookE specific instructions */
5954 /* XXX: not implemented on 440 ? */
5955 static void gen_mfapidi(DisasContext
*ctx
)
5958 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5961 /* XXX: not implemented on 440 ? */
5962 static void gen_tlbiva(DisasContext
*ctx
)
5964 #if defined(CONFIG_USER_ONLY)
5970 t0
= tcg_temp_new();
5971 gen_addr_reg_index(ctx
, t0
);
5972 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5974 #endif /* defined(CONFIG_USER_ONLY) */
5977 /* All 405 MAC instructions are translated here */
5978 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5979 int ra
, int rb
, int rt
, int Rc
)
5983 t0
= tcg_temp_local_new();
5984 t1
= tcg_temp_local_new();
5986 switch (opc3
& 0x0D) {
5988 /* macchw - macchw. - macchwo - macchwo. */
5989 /* macchws - macchws. - macchwso - macchwso. */
5990 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5991 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5992 /* mulchw - mulchw. */
5993 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5994 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5995 tcg_gen_ext16s_tl(t1
, t1
);
5998 /* macchwu - macchwu. - macchwuo - macchwuo. */
5999 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6000 /* mulchwu - mulchwu. */
6001 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
6002 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
6003 tcg_gen_ext16u_tl(t1
, t1
);
6006 /* machhw - machhw. - machhwo - machhwo. */
6007 /* machhws - machhws. - machhwso - machhwso. */
6008 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6009 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6010 /* mulhhw - mulhhw. */
6011 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
6012 tcg_gen_ext16s_tl(t0
, t0
);
6013 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
6014 tcg_gen_ext16s_tl(t1
, t1
);
6017 /* machhwu - machhwu. - machhwuo - machhwuo. */
6018 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6019 /* mulhhwu - mulhhwu. */
6020 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
6021 tcg_gen_ext16u_tl(t0
, t0
);
6022 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
6023 tcg_gen_ext16u_tl(t1
, t1
);
6026 /* maclhw - maclhw. - maclhwo - maclhwo. */
6027 /* maclhws - maclhws. - maclhwso - maclhwso. */
6028 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6029 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6030 /* mullhw - mullhw. */
6031 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
6032 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
6035 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6036 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6037 /* mullhwu - mullhwu. */
6038 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
6039 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
6043 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6044 tcg_gen_mul_tl(t1
, t0
, t1
);
6046 /* nmultiply-and-accumulate (0x0E) */
6047 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
6049 /* multiply-and-accumulate (0x0C) */
6050 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
6054 /* Check overflow and/or saturate */
6055 TCGLabel
*l1
= gen_new_label();
6058 /* Start with XER OV disabled, the most likely case */
6059 tcg_gen_movi_tl(cpu_ov
, 0);
6063 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
6064 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
6065 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
6066 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
6069 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
6070 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
6074 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
6077 tcg_gen_movi_tl(t0
, UINT32_MAX
);
6081 /* Check overflow */
6082 tcg_gen_movi_tl(cpu_ov
, 1);
6083 tcg_gen_movi_tl(cpu_so
, 1);
6086 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
6089 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
6093 if (unlikely(Rc
) != 0) {
6095 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
6099 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6100 static void glue(gen_, name)(DisasContext *ctx) \
6102 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6103 rD(ctx->opcode), Rc(ctx->opcode)); \
6106 /* macchw - macchw. */
6107 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
6108 /* macchwo - macchwo. */
6109 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
6110 /* macchws - macchws. */
6111 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
6112 /* macchwso - macchwso. */
6113 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
6114 /* macchwsu - macchwsu. */
6115 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
6116 /* macchwsuo - macchwsuo. */
6117 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
6118 /* macchwu - macchwu. */
6119 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
6120 /* macchwuo - macchwuo. */
6121 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
6122 /* machhw - machhw. */
6123 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
6124 /* machhwo - machhwo. */
6125 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
6126 /* machhws - machhws. */
6127 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
6128 /* machhwso - machhwso. */
6129 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
6130 /* machhwsu - machhwsu. */
6131 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
6132 /* machhwsuo - machhwsuo. */
6133 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
6134 /* machhwu - machhwu. */
6135 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
6136 /* machhwuo - machhwuo. */
6137 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
6138 /* maclhw - maclhw. */
6139 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
6140 /* maclhwo - maclhwo. */
6141 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
6142 /* maclhws - maclhws. */
6143 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
6144 /* maclhwso - maclhwso. */
6145 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
6146 /* maclhwu - maclhwu. */
6147 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
6148 /* maclhwuo - maclhwuo. */
6149 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
6150 /* maclhwsu - maclhwsu. */
6151 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
6152 /* maclhwsuo - maclhwsuo. */
6153 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
6154 /* nmacchw - nmacchw. */
6155 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
6156 /* nmacchwo - nmacchwo. */
6157 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
6158 /* nmacchws - nmacchws. */
6159 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
6160 /* nmacchwso - nmacchwso. */
6161 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
6162 /* nmachhw - nmachhw. */
6163 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
6164 /* nmachhwo - nmachhwo. */
6165 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
6166 /* nmachhws - nmachhws. */
6167 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
6168 /* nmachhwso - nmachhwso. */
6169 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
6170 /* nmaclhw - nmaclhw. */
6171 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
6172 /* nmaclhwo - nmaclhwo. */
6173 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
6174 /* nmaclhws - nmaclhws. */
6175 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
6176 /* nmaclhwso - nmaclhwso. */
6177 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
6179 /* mulchw - mulchw. */
6180 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
6181 /* mulchwu - mulchwu. */
6182 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
6183 /* mulhhw - mulhhw. */
6184 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
6185 /* mulhhwu - mulhhwu. */
6186 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
6187 /* mullhw - mullhw. */
6188 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
6189 /* mullhwu - mullhwu. */
6190 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
6193 static void gen_mfdcr(DisasContext
*ctx
)
6195 #if defined(CONFIG_USER_ONLY)
6201 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6202 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
6203 tcg_temp_free(dcrn
);
6204 #endif /* defined(CONFIG_USER_ONLY) */
6208 static void gen_mtdcr(DisasContext
*ctx
)
6210 #if defined(CONFIG_USER_ONLY)
6216 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6217 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
6218 tcg_temp_free(dcrn
);
6219 #endif /* defined(CONFIG_USER_ONLY) */
6223 /* XXX: not implemented on 440 ? */
6224 static void gen_mfdcrx(DisasContext
*ctx
)
6226 #if defined(CONFIG_USER_ONLY)
6230 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6231 cpu_gpr
[rA(ctx
->opcode
)]);
6232 /* Note: Rc update flag set leads to undefined state of Rc0 */
6233 #endif /* defined(CONFIG_USER_ONLY) */
6237 /* XXX: not implemented on 440 ? */
6238 static void gen_mtdcrx(DisasContext
*ctx
)
6240 #if defined(CONFIG_USER_ONLY)
6244 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6245 cpu_gpr
[rS(ctx
->opcode
)]);
6246 /* Note: Rc update flag set leads to undefined state of Rc0 */
6247 #endif /* defined(CONFIG_USER_ONLY) */
6250 /* mfdcrux (PPC 460) : user-mode access to DCR */
6251 static void gen_mfdcrux(DisasContext
*ctx
)
6253 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6254 cpu_gpr
[rA(ctx
->opcode
)]);
6255 /* Note: Rc update flag set leads to undefined state of Rc0 */
6258 /* mtdcrux (PPC 460) : user-mode access to DCR */
6259 static void gen_mtdcrux(DisasContext
*ctx
)
6261 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6262 cpu_gpr
[rS(ctx
->opcode
)]);
6263 /* Note: Rc update flag set leads to undefined state of Rc0 */
6267 static void gen_dccci(DisasContext
*ctx
)
6270 /* interpreted as no-op */
6274 static void gen_dcread(DisasContext
*ctx
)
6276 #if defined(CONFIG_USER_ONLY)
6282 gen_set_access_type(ctx
, ACCESS_CACHE
);
6283 EA
= tcg_temp_new();
6284 gen_addr_reg_index(ctx
, EA
);
6285 val
= tcg_temp_new();
6286 gen_qemu_ld32u(ctx
, val
, EA
);
6288 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
6290 #endif /* defined(CONFIG_USER_ONLY) */
6294 static void gen_icbt_40x(DisasContext
*ctx
)
6297 * interpreted as no-op
6298 * XXX: specification say this is treated as a load by the MMU but
6299 * does not generate any exception
6304 static void gen_iccci(DisasContext
*ctx
)
6307 /* interpreted as no-op */
6311 static void gen_icread(DisasContext
*ctx
)
6314 /* interpreted as no-op */
6317 /* rfci (supervisor only) */
6318 static void gen_rfci_40x(DisasContext
*ctx
)
6320 #if defined(CONFIG_USER_ONLY)
6324 /* Restore CPU state */
6325 gen_helper_40x_rfci(cpu_env
);
6326 gen_sync_exception(ctx
);
6327 #endif /* defined(CONFIG_USER_ONLY) */
6330 static void gen_rfci(DisasContext
*ctx
)
6332 #if defined(CONFIG_USER_ONLY)
6336 /* Restore CPU state */
6337 gen_helper_rfci(cpu_env
);
6338 gen_sync_exception(ctx
);
6339 #endif /* defined(CONFIG_USER_ONLY) */
6342 /* BookE specific */
6344 /* XXX: not implemented on 440 ? */
6345 static void gen_rfdi(DisasContext
*ctx
)
6347 #if defined(CONFIG_USER_ONLY)
6351 /* Restore CPU state */
6352 gen_helper_rfdi(cpu_env
);
6353 gen_sync_exception(ctx
);
6354 #endif /* defined(CONFIG_USER_ONLY) */
6357 /* XXX: not implemented on 440 ? */
6358 static void gen_rfmci(DisasContext
*ctx
)
6360 #if defined(CONFIG_USER_ONLY)
6364 /* Restore CPU state */
6365 gen_helper_rfmci(cpu_env
);
6366 gen_sync_exception(ctx
);
6367 #endif /* defined(CONFIG_USER_ONLY) */
6370 /* TLB management - PowerPC 405 implementation */
6373 static void gen_tlbre_40x(DisasContext
*ctx
)
6375 #if defined(CONFIG_USER_ONLY)
6379 switch (rB(ctx
->opcode
)) {
6381 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6382 cpu_gpr
[rA(ctx
->opcode
)]);
6385 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6386 cpu_gpr
[rA(ctx
->opcode
)]);
6389 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6392 #endif /* defined(CONFIG_USER_ONLY) */
6395 /* tlbsx - tlbsx. */
6396 static void gen_tlbsx_40x(DisasContext
*ctx
)
6398 #if defined(CONFIG_USER_ONLY)
6404 t0
= tcg_temp_new();
6405 gen_addr_reg_index(ctx
, t0
);
6406 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6408 if (Rc(ctx
->opcode
)) {
6409 TCGLabel
*l1
= gen_new_label();
6410 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6411 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6412 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6415 #endif /* defined(CONFIG_USER_ONLY) */
6419 static void gen_tlbwe_40x(DisasContext
*ctx
)
6421 #if defined(CONFIG_USER_ONLY)
6426 switch (rB(ctx
->opcode
)) {
6428 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6429 cpu_gpr
[rS(ctx
->opcode
)]);
6432 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6433 cpu_gpr
[rS(ctx
->opcode
)]);
6436 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6439 #endif /* defined(CONFIG_USER_ONLY) */
6442 /* TLB management - PowerPC 440 implementation */
6445 static void gen_tlbre_440(DisasContext
*ctx
)
6447 #if defined(CONFIG_USER_ONLY)
6452 switch (rB(ctx
->opcode
)) {
6457 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6458 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6459 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6460 tcg_temp_free_i32(t0
);
6464 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6467 #endif /* defined(CONFIG_USER_ONLY) */
6470 /* tlbsx - tlbsx. */
6471 static void gen_tlbsx_440(DisasContext
*ctx
)
6473 #if defined(CONFIG_USER_ONLY)
6479 t0
= tcg_temp_new();
6480 gen_addr_reg_index(ctx
, t0
);
6481 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6483 if (Rc(ctx
->opcode
)) {
6484 TCGLabel
*l1
= gen_new_label();
6485 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6486 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6487 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6490 #endif /* defined(CONFIG_USER_ONLY) */
6494 static void gen_tlbwe_440(DisasContext
*ctx
)
6496 #if defined(CONFIG_USER_ONLY)
6500 switch (rB(ctx
->opcode
)) {
6505 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6506 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6507 cpu_gpr
[rS(ctx
->opcode
)]);
6508 tcg_temp_free_i32(t0
);
6512 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6515 #endif /* defined(CONFIG_USER_ONLY) */
6518 /* TLB management - PowerPC BookE 2.06 implementation */
6521 static void gen_tlbre_booke206(DisasContext
*ctx
)
6523 #if defined(CONFIG_USER_ONLY)
6527 gen_helper_booke206_tlbre(cpu_env
);
6528 #endif /* defined(CONFIG_USER_ONLY) */
6531 /* tlbsx - tlbsx. */
6532 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6534 #if defined(CONFIG_USER_ONLY)
6540 if (rA(ctx
->opcode
)) {
6541 t0
= tcg_temp_new();
6542 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6544 t0
= tcg_const_tl(0);
6547 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6548 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6550 #endif /* defined(CONFIG_USER_ONLY) */
6554 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6556 #if defined(CONFIG_USER_ONLY)
6560 gen_helper_booke206_tlbwe(cpu_env
);
6561 #endif /* defined(CONFIG_USER_ONLY) */
6564 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6566 #if defined(CONFIG_USER_ONLY)
6572 t0
= tcg_temp_new();
6573 gen_addr_reg_index(ctx
, t0
);
6574 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6576 #endif /* defined(CONFIG_USER_ONLY) */
6579 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6581 #if defined(CONFIG_USER_ONLY)
6587 t0
= tcg_temp_new();
6588 gen_addr_reg_index(ctx
, t0
);
6590 switch ((ctx
->opcode
>> 21) & 0x3) {
6592 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6595 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6598 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6601 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6606 #endif /* defined(CONFIG_USER_ONLY) */
6611 static void gen_wrtee(DisasContext
*ctx
)
6613 #if defined(CONFIG_USER_ONLY)
6619 t0
= tcg_temp_new();
6620 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6621 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6622 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6625 * Stop translation to have a chance to raise an exception if we
6626 * just set msr_ee to 1
6628 gen_stop_exception(ctx
);
6629 #endif /* defined(CONFIG_USER_ONLY) */
6633 static void gen_wrteei(DisasContext
*ctx
)
6635 #if defined(CONFIG_USER_ONLY)
6639 if (ctx
->opcode
& 0x00008000) {
6640 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6641 /* Stop translation to have a chance to raise an exception */
6642 gen_stop_exception(ctx
);
6644 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6646 #endif /* defined(CONFIG_USER_ONLY) */
6649 /* PowerPC 440 specific instructions */
6652 static void gen_dlmzb(DisasContext
*ctx
)
6654 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6655 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6656 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6657 tcg_temp_free_i32(t0
);
6660 /* mbar replaces eieio on 440 */
6661 static void gen_mbar(DisasContext
*ctx
)
6663 /* interpreted as no-op */
6666 /* msync replaces sync on 440 */
6667 static void gen_msync_4xx(DisasContext
*ctx
)
6669 /* Only e500 seems to treat reserved bits as invalid */
6670 if ((ctx
->insns_flags2
& PPC2_BOOKE206
) &&
6671 (ctx
->opcode
& 0x03FFF801)) {
6672 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6674 /* otherwise interpreted as no-op */
6678 static void gen_icbt_440(DisasContext
*ctx
)
6681 * interpreted as no-op
6682 * XXX: specification say this is treated as a load by the MMU but
6683 * does not generate any exception
6687 /* Embedded.Processor Control */
6689 static void gen_msgclr(DisasContext
*ctx
)
6691 #if defined(CONFIG_USER_ONLY)
6695 if (is_book3s_arch2x(ctx
)) {
6696 gen_helper_book3s_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6698 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6700 #endif /* defined(CONFIG_USER_ONLY) */
6703 static void gen_msgsnd(DisasContext
*ctx
)
6705 #if defined(CONFIG_USER_ONLY)
6709 if (is_book3s_arch2x(ctx
)) {
6710 gen_helper_book3s_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6712 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6714 #endif /* defined(CONFIG_USER_ONLY) */
6717 #if defined(TARGET_PPC64)
6718 static void gen_msgclrp(DisasContext
*ctx
)
6720 #if defined(CONFIG_USER_ONLY)
6724 gen_helper_book3s_msgclrp(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6725 #endif /* defined(CONFIG_USER_ONLY) */
6728 static void gen_msgsndp(DisasContext
*ctx
)
6730 #if defined(CONFIG_USER_ONLY)
6734 gen_helper_book3s_msgsndp(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6735 #endif /* defined(CONFIG_USER_ONLY) */
6739 static void gen_msgsync(DisasContext
*ctx
)
6741 #if defined(CONFIG_USER_ONLY)
6745 #endif /* defined(CONFIG_USER_ONLY) */
6746 /* interpreted as no-op */
6749 #if defined(TARGET_PPC64)
6750 static void gen_maddld(DisasContext
*ctx
)
6752 TCGv_i64 t1
= tcg_temp_new_i64();
6754 tcg_gen_mul_i64(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6755 tcg_gen_add_i64(cpu_gpr
[rD(ctx
->opcode
)], t1
, cpu_gpr
[rC(ctx
->opcode
)]);
6756 tcg_temp_free_i64(t1
);
6759 /* maddhd maddhdu */
6760 static void gen_maddhd_maddhdu(DisasContext
*ctx
)
6762 TCGv_i64 lo
= tcg_temp_new_i64();
6763 TCGv_i64 hi
= tcg_temp_new_i64();
6764 TCGv_i64 t1
= tcg_temp_new_i64();
6766 if (Rc(ctx
->opcode
)) {
6767 tcg_gen_mulu2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6768 cpu_gpr
[rB(ctx
->opcode
)]);
6769 tcg_gen_movi_i64(t1
, 0);
6771 tcg_gen_muls2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6772 cpu_gpr
[rB(ctx
->opcode
)]);
6773 tcg_gen_sari_i64(t1
, cpu_gpr
[rC(ctx
->opcode
)], 63);
6775 tcg_gen_add2_i64(t1
, cpu_gpr
[rD(ctx
->opcode
)], lo
, hi
,
6776 cpu_gpr
[rC(ctx
->opcode
)], t1
);
6777 tcg_temp_free_i64(lo
);
6778 tcg_temp_free_i64(hi
);
6779 tcg_temp_free_i64(t1
);
6781 #endif /* defined(TARGET_PPC64) */
6783 static void gen_tbegin(DisasContext
*ctx
)
6785 if (unlikely(!ctx
->tm_enabled
)) {
6786 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6789 gen_helper_tbegin(cpu_env
);
6792 #define GEN_TM_NOOP(name) \
6793 static inline void gen_##name(DisasContext *ctx) \
6795 if (unlikely(!ctx->tm_enabled)) { \
6796 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6800 * Because tbegin always fails in QEMU, these user \
6801 * space instructions all have a simple implementation: \
6803 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6804 * = 0b0 || 0b00 || 0b0 \
6806 tcg_gen_movi_i32(cpu_crf[0], 0); \
6810 GEN_TM_NOOP(tabort
);
6811 GEN_TM_NOOP(tabortwc
);
6812 GEN_TM_NOOP(tabortwci
);
6813 GEN_TM_NOOP(tabortdc
);
6814 GEN_TM_NOOP(tabortdci
);
6817 static inline void gen_cp_abort(DisasContext
*ctx
)
6822 #define GEN_CP_PASTE_NOOP(name) \
6823 static inline void gen_##name(DisasContext *ctx) \
6826 * Generate invalid exception until we have an \
6827 * implementation of the copy paste facility \
6832 GEN_CP_PASTE_NOOP(copy
)
6833 GEN_CP_PASTE_NOOP(paste
)
6835 static void gen_tcheck(DisasContext
*ctx
)
6837 if (unlikely(!ctx
->tm_enabled
)) {
6838 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6842 * Because tbegin always fails, the tcheck implementation is
6845 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6846 * = 0b1 || 0b00 || 0b0
6848 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
6851 #if defined(CONFIG_USER_ONLY)
6852 #define GEN_TM_PRIV_NOOP(name) \
6853 static inline void gen_##name(DisasContext *ctx) \
6855 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6860 #define GEN_TM_PRIV_NOOP(name) \
6861 static inline void gen_##name(DisasContext *ctx) \
6864 if (unlikely(!ctx->tm_enabled)) { \
6865 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6869 * Because tbegin always fails, the implementation is \
6872 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6873 * = 0b0 || 0b00 | 0b0 \
6875 tcg_gen_movi_i32(cpu_crf[0], 0); \
6880 GEN_TM_PRIV_NOOP(treclaim
);
6881 GEN_TM_PRIV_NOOP(trechkpt
);
6883 static inline void get_fpr(TCGv_i64 dst
, int regno
)
6885 tcg_gen_ld_i64(dst
, cpu_env
, fpr_offset(regno
));
6888 static inline void set_fpr(int regno
, TCGv_i64 src
)
6890 tcg_gen_st_i64(src
, cpu_env
, fpr_offset(regno
));
6893 static inline void get_avr64(TCGv_i64 dst
, int regno
, bool high
)
6895 tcg_gen_ld_i64(dst
, cpu_env
, avr64_offset(regno
, high
));
6898 static inline void set_avr64(int regno
, TCGv_i64 src
, bool high
)
6900 tcg_gen_st_i64(src
, cpu_env
, avr64_offset(regno
, high
));
6903 #include "translate/fp-impl.inc.c"
6905 #include "translate/vmx-impl.inc.c"
6907 #include "translate/vsx-impl.inc.c"
6909 #include "translate/dfp-impl.inc.c"
6911 #include "translate/spe-impl.inc.c"
6913 /* Handles lfdp, lxsd, lxssp */
6914 static void gen_dform39(DisasContext
*ctx
)
6916 switch (ctx
->opcode
& 0x3) {
6918 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6919 return gen_lfdp(ctx
);
6923 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6924 return gen_lxsd(ctx
);
6928 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6929 return gen_lxssp(ctx
);
6933 return gen_invalid(ctx
);
6936 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6937 static void gen_dform3D(DisasContext
*ctx
)
6939 if ((ctx
->opcode
& 3) == 1) { /* DQ-FORM */
6940 switch (ctx
->opcode
& 0x7) {
6942 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6943 return gen_lxv(ctx
);
6947 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6948 return gen_stxv(ctx
);
6952 } else { /* DS-FORM */
6953 switch (ctx
->opcode
& 0x3) {
6955 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6956 return gen_stfdp(ctx
);
6960 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6961 return gen_stxsd(ctx
);
6964 case 3: /* stxssp */
6965 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6966 return gen_stxssp(ctx
);
6971 return gen_invalid(ctx
);
6974 static opcode_t opcodes
[] = {
6975 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
6976 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
6977 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6978 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER
),
6979 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6980 #if defined(TARGET_PPC64)
6981 GEN_HANDLER_E(cmpeqb
, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE
, PPC2_ISA300
),
6983 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
6984 GEN_HANDLER_E(cmprb
, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE
, PPC2_ISA300
),
6985 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
6986 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6987 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6988 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6989 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6990 GEN_HANDLER_E(addpcis
, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6991 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
6992 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
6993 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
6994 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
6995 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6996 #if defined(TARGET_PPC64)
6997 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
6999 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
7000 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
7001 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7002 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7003 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7004 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
7005 GEN_HANDLER_E(cnttzw
, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7006 GEN_HANDLER_E(copy
, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE
, PPC2_ISA300
),
7007 GEN_HANDLER_E(cp_abort
, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
7008 GEN_HANDLER_E(paste
, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE
, PPC2_ISA300
),
7009 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
7010 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
7011 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7012 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7013 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7014 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7015 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
7016 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
7017 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
7018 #if defined(TARGET_PPC64)
7019 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
7020 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
7021 GEN_HANDLER_E(cnttzd
, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7022 GEN_HANDLER_E(darn
, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE
, PPC2_ISA300
),
7023 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
7024 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
7026 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7027 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7028 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7029 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
7030 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
7031 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
7032 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
7033 #if defined(TARGET_PPC64)
7034 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
7035 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
7036 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
7037 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
7038 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
7039 GEN_HANDLER2_E(extswsli0
, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
7040 PPC_NONE
, PPC2_ISA300
),
7041 GEN_HANDLER2_E(extswsli1
, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
7042 PPC_NONE
, PPC2_ISA300
),
7044 #if defined(TARGET_PPC64)
7045 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
7046 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
7047 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
7049 /* handles lfdp, lxsd, lxssp */
7050 GEN_HANDLER_E(dform39
, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
7051 /* handles stfdp, lxv, stxsd, stxssp, stxv */
7052 GEN_HANDLER_E(dform3D
, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
7053 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7054 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7055 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
7056 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
7057 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
7058 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
7059 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO
),
7060 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
7061 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
7062 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
7063 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
7064 GEN_HANDLER_E(lwat
, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7065 GEN_HANDLER_E(stwat
, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7066 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
7067 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
7068 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
7069 #if defined(TARGET_PPC64)
7070 GEN_HANDLER_E(ldat
, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7071 GEN_HANDLER_E(stdat
, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7072 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
7073 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
7074 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
7075 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
7077 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
7078 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
7079 GEN_HANDLER_E(wait
, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE
, PPC2_ISA300
),
7080 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
7081 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
7082 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
7083 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
7084 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE
, PPC2_BCTAR_ISA207
),
7085 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
7086 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
7087 #if defined(TARGET_PPC64)
7088 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
7089 #if !defined(CONFIG_USER_ONLY)
7090 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
7091 GEN_HANDLER_E(scv
, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE
, PPC2_ISA300
),
7092 GEN_HANDLER_E(scv
, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE
, PPC2_ISA300
),
7093 GEN_HANDLER_E(rfscv
, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE
, PPC2_ISA300
),
7095 GEN_HANDLER_E(stop
, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
7096 GEN_HANDLER_E(doze
, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7097 GEN_HANDLER_E(nap
, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7098 GEN_HANDLER_E(sleep
, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7099 GEN_HANDLER_E(rvwinkle
, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7100 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
7102 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
7103 GEN_HANDLER(sc
, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW
),
7104 GEN_HANDLER(sc
, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW
),
7105 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
7106 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
7107 #if defined(TARGET_PPC64)
7108 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
7109 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
7111 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
7112 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
7113 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
7114 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
7115 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
7116 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
7117 #if defined(TARGET_PPC64)
7118 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
7119 GEN_HANDLER_E(setb
, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE
, PPC2_ISA300
),
7120 GEN_HANDLER_E(mcrxrx
, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE
, PPC2_ISA300
),
7122 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
7123 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
7124 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
7125 GEN_HANDLER_E(dcbfep
, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE
, PPC2_BOOKE206
),
7126 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
7127 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
7128 GEN_HANDLER_E(dcbstep
, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE
, PPC2_BOOKE206
),
7129 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
7130 GEN_HANDLER_E(dcbtep
, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE
, PPC2_BOOKE206
),
7131 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
7132 GEN_HANDLER_E(dcbtstep
, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE
, PPC2_BOOKE206
),
7133 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
7134 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
7135 GEN_HANDLER_E(dcbzep
, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE
, PPC2_BOOKE206
),
7136 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
7137 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC
),
7138 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
7139 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
7140 GEN_HANDLER_E(icbiep
, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE
, PPC2_BOOKE206
),
7141 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
7142 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
7143 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
7144 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
7145 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
7146 #if defined(TARGET_PPC64)
7147 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
7148 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
7150 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
7151 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
7153 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
7154 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
7155 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
7156 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
7158 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
7160 * XXX Those instructions will need to be handled differently for
7161 * different ISA versions
7163 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
7164 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
7165 GEN_HANDLER_E(tlbiel
, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE
, PPC2_ISA300
),
7166 GEN_HANDLER_E(tlbie
, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE
, PPC2_ISA300
),
7167 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
7168 #if defined(TARGET_PPC64)
7169 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
7170 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
7171 GEN_HANDLER_E(slbieg
, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE
, PPC2_ISA300
),
7172 GEN_HANDLER_E(slbsync
, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
7174 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
7175 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
7176 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
7177 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
7178 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
7179 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
7180 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
7181 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
7182 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
7183 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
7184 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
7185 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
7186 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
7187 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
7188 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
7189 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
7190 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
7191 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
7192 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
7193 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
7194 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
7195 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
7196 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
7197 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
7198 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
7199 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
7200 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
7201 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
7202 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
7203 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
7204 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
7205 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
7206 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
7207 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
7208 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
7209 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
7210 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
7211 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
7212 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
7213 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
7214 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
7215 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
7216 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
7217 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
7218 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
7219 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
7220 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
7221 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
7222 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
7223 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7224 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7225 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
7226 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
7227 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7228 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7229 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
7230 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
7231 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
7232 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
7233 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
7234 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
7235 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
7236 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
7237 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
7238 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
7239 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
7240 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
7241 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
7242 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
7243 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
7244 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
7245 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
7246 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
7247 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
7248 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
7249 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
7250 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
7251 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
7252 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
7253 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
7254 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7255 PPC_NONE
, PPC2_BOOKE206
),
7256 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7257 PPC_NONE
, PPC2_BOOKE206
),
7258 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7259 PPC_NONE
, PPC2_BOOKE206
),
7260 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7261 PPC_NONE
, PPC2_BOOKE206
),
7262 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7263 PPC_NONE
, PPC2_BOOKE206
),
7264 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7265 PPC_NONE
, PPC2_PRCNTL
),
7266 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7267 PPC_NONE
, PPC2_PRCNTL
),
7268 GEN_HANDLER2_E(msgsync
, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
7269 PPC_NONE
, PPC2_PRCNTL
),
7270 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
7271 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
7272 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
7273 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
7274 PPC_BOOKE
, PPC2_BOOKE206
),
7275 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE
),
7276 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7277 PPC_BOOKE
, PPC2_BOOKE206
),
7278 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
7280 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
7281 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
7282 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
7283 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
7284 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
7285 #if defined(TARGET_PPC64)
7286 GEN_HANDLER_E(maddhd_maddhdu
, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE
,
7288 GEN_HANDLER_E(maddld
, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7289 GEN_HANDLER2_E(msgsndp
, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001,
7290 PPC_NONE
, PPC2_ISA207S
),
7291 GEN_HANDLER2_E(msgclrp
, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001,
7292 PPC_NONE
, PPC2_ISA207S
),
7295 #undef GEN_INT_ARITH_ADD
7296 #undef GEN_INT_ARITH_ADD_CONST
7297 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7298 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7299 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7300 add_ca, compute_ca, compute_ov) \
7301 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7302 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
7303 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
7304 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
7305 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
7306 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
7307 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
7308 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
7309 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
7310 GEN_HANDLER_E(addex
, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7311 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
7312 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
7314 #undef GEN_INT_ARITH_DIVW
7315 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7316 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7317 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
7318 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
7319 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
7320 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
7321 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7322 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7323 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7324 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7325 GEN_HANDLER_E(modsw
, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7326 GEN_HANDLER_E(moduw
, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7328 #if defined(TARGET_PPC64)
7329 #undef GEN_INT_ARITH_DIVD
7330 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7331 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7332 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
7333 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
7334 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
7335 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
7337 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7338 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7339 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7340 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7341 GEN_HANDLER_E(modsd
, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7342 GEN_HANDLER_E(modud
, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7344 #undef GEN_INT_ARITH_MUL_HELPER
7345 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7346 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7347 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
7348 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
7349 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
7352 #undef GEN_INT_ARITH_SUBF
7353 #undef GEN_INT_ARITH_SUBF_CONST
7354 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7355 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7356 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7357 add_ca, compute_ca, compute_ov) \
7358 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7359 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
7360 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
7361 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
7362 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
7363 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
7364 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
7365 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
7366 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
7367 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
7368 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
7372 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
7373 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7374 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
7375 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7376 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
7377 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
7378 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
7379 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
7380 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
7381 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
7382 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
7383 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
7384 #if defined(TARGET_PPC64)
7385 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
7388 #if defined(TARGET_PPC64)
7391 #define GEN_PPC64_R2(name, opc1, opc2) \
7392 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7393 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7395 #define GEN_PPC64_R4(name, opc1, opc2) \
7396 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7397 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
7399 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7401 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
7403 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
7404 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
7405 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
7406 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
7407 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
7408 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
7416 #define GEN_LD(name, ldop, opc, type) \
7417 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7418 #define GEN_LDU(name, ldop, opc, type) \
7419 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
7420 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
7421 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7422 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
7423 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7424 #define GEN_LDS(name, ldop, op, type) \
7425 GEN_LD(name, ldop, op | 0x20, type) \
7426 GEN_LDU(name, ldop, op | 0x21, type) \
7427 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
7428 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
7430 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
7431 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
7432 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
7433 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
7434 #if defined(TARGET_PPC64)
7435 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
7436 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
7437 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
)
7438 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
)
7439 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
7441 /* HV/P7 and later only */
7442 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
7443 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x18, PPC_CILDST
)
7444 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
7445 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
7447 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
7448 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
7450 /* External PID based load */
7452 #define GEN_LDEPX(name, ldop, opc2, opc3) \
7453 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7454 0x00000001, PPC_NONE, PPC2_BOOKE206),
7456 GEN_LDEPX(lb
, DEF_MEMOP(MO_UB
), 0x1F, 0x02)
7457 GEN_LDEPX(lh
, DEF_MEMOP(MO_UW
), 0x1F, 0x08)
7458 GEN_LDEPX(lw
, DEF_MEMOP(MO_UL
), 0x1F, 0x00)
7459 #if defined(TARGET_PPC64)
7460 GEN_LDEPX(ld
, DEF_MEMOP(MO_Q
), 0x1D, 0x00)
7468 #define GEN_ST(name, stop, opc, type) \
7469 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7470 #define GEN_STU(name, stop, opc, type) \
7471 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
7472 #define GEN_STUX(name, stop, opc2, opc3, type) \
7473 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7474 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
7475 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
7476 #define GEN_STS(name, stop, op, type) \
7477 GEN_ST(name, stop, op | 0x20, type) \
7478 GEN_STU(name, stop, op | 0x21, type) \
7479 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
7480 GEN_STX(name, stop, 0x17, op | 0x00, type)
7482 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
7483 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
7484 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
7485 #if defined(TARGET_PPC64)
7486 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
)
7487 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
)
7488 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
7489 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
7490 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
7491 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
7492 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
7494 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
7495 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
7498 #define GEN_STEPX(name, ldop, opc2, opc3) \
7499 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7500 0x00000001, PPC_NONE, PPC2_BOOKE206),
7502 GEN_STEPX(stb
, DEF_MEMOP(MO_UB
), 0x1F, 0x06)
7503 GEN_STEPX(sth
, DEF_MEMOP(MO_UW
), 0x1F, 0x0C)
7504 GEN_STEPX(stw
, DEF_MEMOP(MO_UL
), 0x1F, 0x04)
7505 #if defined(TARGET_PPC64)
7506 GEN_STEPX(std
, DEF_MEMOP(MO_Q
), 0x1D, 0x04)
7510 #define GEN_CRLOGIC(name, tcg_op, opc) \
7511 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
7512 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
7513 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
7514 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
7515 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
7516 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
7517 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
7518 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
7519 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
7521 #undef GEN_MAC_HANDLER
7522 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7523 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7524 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
7525 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
7526 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
7527 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
7528 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
7529 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
7530 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
7531 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
7532 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
7533 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
7534 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
7535 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
7536 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
7537 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
7538 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
7539 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
7540 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
7541 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
7542 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
7543 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
7544 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
7545 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
7546 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
7547 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
7548 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
7549 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
7550 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
7551 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
7552 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
7553 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
7554 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
7555 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
7556 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
7557 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
7558 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
7559 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
7560 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
7561 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
7562 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
7563 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
7564 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
7565 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
7567 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7569 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7571 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7573 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7575 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7577 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7579 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7581 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7583 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7585 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7587 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7590 #include "translate/fp-ops.inc.c"
7592 #include "translate/vmx-ops.inc.c"
7594 #include "translate/vsx-ops.inc.c"
7596 #include "translate/dfp-ops.inc.c"
7598 #include "translate/spe-ops.inc.c"
7601 #include "helper_regs.h"
7602 #include "translate_init.inc.c"
7604 /*****************************************************************************/
7605 /* Misc PowerPC helpers */
7606 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
7611 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7612 CPUPPCState
*env
= &cpu
->env
;
7615 qemu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
7616 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
7617 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
7619 qemu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
7620 TARGET_FMT_lx
" iidx %d didx %d\n",
7621 env
->msr
, env
->spr
[SPR_HID0
],
7622 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
7623 #if !defined(NO_TIMER_DUMP)
7624 qemu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
7625 #if !defined(CONFIG_USER_ONLY)
7626 " DECR " TARGET_FMT_lu
7629 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
7630 #if !defined(CONFIG_USER_ONLY)
7631 , cpu_ppc_load_decr(env
)
7635 for (i
= 0; i
< 32; i
++) {
7636 if ((i
& (RGPL
- 1)) == 0) {
7637 qemu_fprintf(f
, "GPR%02d", i
);
7639 qemu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
7640 if ((i
& (RGPL
- 1)) == (RGPL
- 1)) {
7641 qemu_fprintf(f
, "\n");
7644 qemu_fprintf(f
, "CR ");
7645 for (i
= 0; i
< 8; i
++)
7646 qemu_fprintf(f
, "%01x", env
->crf
[i
]);
7647 qemu_fprintf(f
, " [");
7648 for (i
= 0; i
< 8; i
++) {
7650 if (env
->crf
[i
] & 0x08) {
7652 } else if (env
->crf
[i
] & 0x04) {
7654 } else if (env
->crf
[i
] & 0x02) {
7657 qemu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
7659 qemu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
7662 if (flags
& CPU_DUMP_FPU
) {
7663 for (i
= 0; i
< 32; i
++) {
7664 if ((i
& (RFPL
- 1)) == 0) {
7665 qemu_fprintf(f
, "FPR%02d", i
);
7667 qemu_fprintf(f
, " %016" PRIx64
, *cpu_fpr_ptr(env
, i
));
7668 if ((i
& (RFPL
- 1)) == (RFPL
- 1)) {
7669 qemu_fprintf(f
, "\n");
7672 qemu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
7675 #if !defined(CONFIG_USER_ONLY)
7676 qemu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
7677 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
7678 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
7679 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
7681 qemu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
7682 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
7683 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
7684 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
7686 qemu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
7687 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
7688 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
7689 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
7691 #if defined(TARGET_PPC64)
7692 if (env
->excp_model
== POWERPC_EXCP_POWER7
||
7693 env
->excp_model
== POWERPC_EXCP_POWER8
||
7694 env
->excp_model
== POWERPC_EXCP_POWER9
) {
7695 qemu_fprintf(f
, "HSRR0 " TARGET_FMT_lx
" HSRR1 " TARGET_FMT_lx
"\n",
7696 env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
7699 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
7700 qemu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
7701 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
7702 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
7703 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
7705 qemu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
7706 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
7707 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
7708 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
7710 qemu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
7711 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
7712 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
7713 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
7715 qemu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
7716 " EPR " TARGET_FMT_lx
"\n",
7717 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
7718 env
->spr
[SPR_BOOKE_EPR
]);
7721 qemu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
7722 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
7723 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
7724 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
7727 * IVORs are left out as they are large and do not change often --
7728 * they can be read with "p $ivor0", "p $ivor1", etc.
7732 #if defined(TARGET_PPC64)
7733 if (env
->flags
& POWERPC_FLAG_CFAR
) {
7734 qemu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
7738 if (env
->spr_cb
[SPR_LPCR
].name
) {
7739 qemu_fprintf(f
, " LPCR " TARGET_FMT_lx
"\n", env
->spr
[SPR_LPCR
]);
7742 switch (env
->mmu_model
) {
7743 case POWERPC_MMU_32B
:
7744 case POWERPC_MMU_601
:
7745 case POWERPC_MMU_SOFT_6xx
:
7746 case POWERPC_MMU_SOFT_74xx
:
7747 #if defined(TARGET_PPC64)
7748 case POWERPC_MMU_64B
:
7749 case POWERPC_MMU_2_03
:
7750 case POWERPC_MMU_2_06
:
7751 case POWERPC_MMU_2_07
:
7752 case POWERPC_MMU_3_00
:
7754 if (env
->spr_cb
[SPR_SDR1
].name
) { /* SDR1 Exists */
7755 qemu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" ", env
->spr
[SPR_SDR1
]);
7757 if (env
->spr_cb
[SPR_PTCR
].name
) { /* PTCR Exists */
7758 qemu_fprintf(f
, " PTCR " TARGET_FMT_lx
" ", env
->spr
[SPR_PTCR
]);
7760 qemu_fprintf(f
, " DAR " TARGET_FMT_lx
" DSISR " TARGET_FMT_lx
"\n",
7761 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
7763 case POWERPC_MMU_BOOKE206
:
7764 qemu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
7765 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
7766 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
7767 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
7769 qemu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
7770 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
7771 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
7772 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
7774 qemu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
7775 " TLB1CFG " TARGET_FMT_lx
"\n",
7776 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
7777 env
->spr
[SPR_BOOKE_TLB1CFG
]);
7788 void ppc_cpu_dump_statistics(CPUState
*cs
, int flags
)
7790 #if defined(DO_PPC_STATISTICS)
7791 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7792 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
7795 t1
= cpu
->env
.opcodes
;
7796 for (op1
= 0; op1
< 64; op1
++) {
7798 if (is_indirect_opcode(handler
)) {
7799 t2
= ind_table(handler
);
7800 for (op2
= 0; op2
< 32; op2
++) {
7802 if (is_indirect_opcode(handler
)) {
7803 t3
= ind_table(handler
);
7804 for (op3
= 0; op3
< 32; op3
++) {
7806 if (handler
->count
== 0) {
7809 qemu_printf("%02x %02x %02x (%02x %04d) %16s: "
7810 "%016" PRIx64
" %" PRId64
"\n",
7811 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
7813 handler
->count
, handler
->count
);
7816 if (handler
->count
== 0) {
7819 qemu_printf("%02x %02x (%02x %04d) %16s: "
7820 "%016" PRIx64
" %" PRId64
"\n",
7821 op1
, op2
, op1
, op2
, handler
->oname
,
7822 handler
->count
, handler
->count
);
7826 if (handler
->count
== 0) {
7829 qemu_printf("%02x (%02x ) %16s: %016" PRIx64
7831 op1
, op1
, handler
->oname
,
7832 handler
->count
, handler
->count
);
7838 static void ppc_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
7840 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7841 CPUPPCState
*env
= cs
->env_ptr
;
7844 ctx
->exception
= POWERPC_EXCP_NONE
;
7845 ctx
->spr_cb
= env
->spr_cb
;
7847 ctx
->mem_idx
= env
->dmmu_idx
;
7849 #if !defined(CONFIG_USER_ONLY)
7850 ctx
->hv
= msr_hv
|| !env
->has_hv_mode
;
7852 ctx
->insns_flags
= env
->insns_flags
;
7853 ctx
->insns_flags2
= env
->insns_flags2
;
7854 ctx
->access_type
= -1;
7855 ctx
->need_access_type
= !(env
->mmu_model
& POWERPC_MMU_64B
);
7856 ctx
->le_mode
= !!(env
->hflags
& (1 << MSR_LE
));
7857 ctx
->default_tcg_memop_mask
= ctx
->le_mode
? MO_LE
: MO_BE
;
7858 ctx
->flags
= env
->flags
;
7859 #if defined(TARGET_PPC64)
7860 ctx
->sf_mode
= msr_is_64bit(env
, env
->msr
);
7861 ctx
->has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
7863 ctx
->lazy_tlb_flush
= env
->mmu_model
== POWERPC_MMU_32B
7864 || env
->mmu_model
== POWERPC_MMU_601
7865 || (env
->mmu_model
& POWERPC_MMU_64B
);
7867 ctx
->fpu_enabled
= !!msr_fp
;
7868 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
) {
7869 ctx
->spe_enabled
= !!msr_spe
;
7871 ctx
->spe_enabled
= false;
7873 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
) {
7874 ctx
->altivec_enabled
= !!msr_vr
;
7876 ctx
->altivec_enabled
= false;
7878 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
7879 ctx
->vsx_enabled
= !!msr_vsx
;
7881 ctx
->vsx_enabled
= false;
7883 if ((env
->flags
& POWERPC_FLAG_SCV
)
7884 && (env
->spr
[SPR_FSCR
] & (1ull << FSCR_SCV
))) {
7885 ctx
->scv_enabled
= true;
7887 ctx
->scv_enabled
= false;
7889 #if defined(TARGET_PPC64)
7890 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
7891 ctx
->tm_enabled
= !!msr_tm
;
7893 ctx
->tm_enabled
= false;
7896 ctx
->gtse
= !!(env
->spr
[SPR_LPCR
] & LPCR_GTSE
);
7897 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
) {
7898 ctx
->singlestep_enabled
= CPU_SINGLE_STEP
;
7900 ctx
->singlestep_enabled
= 0;
7902 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
) {
7903 ctx
->singlestep_enabled
|= CPU_BRANCH_STEP
;
7905 if ((env
->flags
& POWERPC_FLAG_DE
) && msr_de
) {
7906 ctx
->singlestep_enabled
= 0;
7907 target_ulong dbcr0
= env
->spr
[SPR_BOOKE_DBCR0
];
7908 if (dbcr0
& DBCR0_ICMP
) {
7909 ctx
->singlestep_enabled
|= CPU_SINGLE_STEP
;
7911 if (dbcr0
& DBCR0_BRT
) {
7912 ctx
->singlestep_enabled
|= CPU_BRANCH_STEP
;
7916 if (unlikely(ctx
->base
.singlestep_enabled
)) {
7917 ctx
->singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
7919 #if defined(DO_SINGLE_STEP) && 0
7920 /* Single step trace mode */
7924 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
7925 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
7928 static void ppc_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
7932 static void ppc_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
7934 tcg_gen_insn_start(dcbase
->pc_next
);
7937 static bool ppc_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
7938 const CPUBreakpoint
*bp
)
7940 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7942 gen_debug_exception(ctx
);
7943 dcbase
->is_jmp
= DISAS_NORETURN
;
7945 * The address covered by the breakpoint must be included in
7946 * [tb->pc, tb->pc + tb->size) in order to for it to be properly
7947 * cleared -- thus we increment the PC here so that the logic
7948 * setting tb->size below does the right thing.
7950 ctx
->base
.pc_next
+= 4;
7954 static void ppc_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
7956 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7957 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7958 CPUPPCState
*env
= cs
->env_ptr
;
7959 opc_handler_t
**table
, *handler
;
7961 LOG_DISAS("----------------\n");
7962 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
7963 ctx
->base
.pc_next
, ctx
->mem_idx
, (int)msr_ir
);
7965 ctx
->opcode
= translator_ldl_swap(env
, ctx
->base
.pc_next
,
7966 need_byteswap(ctx
));
7968 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7969 ctx
->opcode
, opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7970 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7971 ctx
->le_mode
? "little" : "big");
7972 ctx
->base
.pc_next
+= 4;
7973 table
= cpu
->opcodes
;
7974 handler
= table
[opc1(ctx
->opcode
)];
7975 if (is_indirect_opcode(handler
)) {
7976 table
= ind_table(handler
);
7977 handler
= table
[opc2(ctx
->opcode
)];
7978 if (is_indirect_opcode(handler
)) {
7979 table
= ind_table(handler
);
7980 handler
= table
[opc3(ctx
->opcode
)];
7981 if (is_indirect_opcode(handler
)) {
7982 table
= ind_table(handler
);
7983 handler
= table
[opc4(ctx
->opcode
)];
7987 /* Is opcode *REALLY* valid ? */
7988 if (unlikely(handler
->handler
== &gen_invalid
)) {
7989 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
7990 "%02x - %02x - %02x - %02x (%08x) "
7991 TARGET_FMT_lx
" %d\n",
7992 opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7993 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7994 ctx
->opcode
, ctx
->base
.pc_next
- 4, (int)msr_ir
);
7998 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
)
7999 && Rc(ctx
->opcode
))) {
8000 inval
= handler
->inval2
;
8002 inval
= handler
->inval1
;
8005 if (unlikely((ctx
->opcode
& inval
) != 0)) {
8006 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
8007 "%02x - %02x - %02x - %02x (%08x) "
8008 TARGET_FMT_lx
"\n", ctx
->opcode
& inval
,
8009 opc1(ctx
->opcode
), opc2(ctx
->opcode
),
8010 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
8011 ctx
->opcode
, ctx
->base
.pc_next
- 4);
8012 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
8013 ctx
->base
.is_jmp
= DISAS_NORETURN
;
8017 (*(handler
->handler
))(ctx
);
8018 #if defined(DO_PPC_STATISTICS)
8021 /* Check trace mode exceptions */
8022 if (unlikely(ctx
->singlestep_enabled
& CPU_SINGLE_STEP
&&
8023 (ctx
->base
.pc_next
<= 0x100 || ctx
->base
.pc_next
> 0xF00) &&
8024 ctx
->exception
!= POWERPC_SYSCALL
&&
8025 ctx
->exception
!= POWERPC_EXCP_TRAP
&&
8026 ctx
->exception
!= POWERPC_EXCP_BRANCH
)) {
8027 uint32_t excp
= gen_prep_dbgex(ctx
);
8028 gen_exception_nip(ctx
, excp
, ctx
->base
.pc_next
);
8031 if (tcg_check_temp_count()) {
8032 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
8033 "temporaries\n", opc1(ctx
->opcode
), opc2(ctx
->opcode
),
8034 opc3(ctx
->opcode
), opc4(ctx
->opcode
), ctx
->opcode
);
8037 ctx
->base
.is_jmp
= ctx
->exception
== POWERPC_EXCP_NONE
?
8038 DISAS_NEXT
: DISAS_NORETURN
;
8041 static void ppc_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
8043 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
8045 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
8046 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
8047 } else if (ctx
->exception
!= POWERPC_EXCP_BRANCH
) {
8048 if (unlikely(ctx
->base
.singlestep_enabled
)) {
8049 gen_debug_exception(ctx
);
8051 /* Generate the return instruction */
8052 tcg_gen_exit_tb(NULL
, 0);
8056 static void ppc_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
8058 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
8059 log_target_disas(cs
, dcbase
->pc_first
, dcbase
->tb
->size
);
8062 static const TranslatorOps ppc_tr_ops
= {
8063 .init_disas_context
= ppc_tr_init_disas_context
,
8064 .tb_start
= ppc_tr_tb_start
,
8065 .insn_start
= ppc_tr_insn_start
,
8066 .breakpoint_check
= ppc_tr_breakpoint_check
,
8067 .translate_insn
= ppc_tr_translate_insn
,
8068 .tb_stop
= ppc_tr_tb_stop
,
8069 .disas_log
= ppc_tr_disas_log
,
8072 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
8076 translator_loop(&ppc_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
8079 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,