hw/ppc/pnv_psi.c

   1 /*
   2  * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
   3  *
   4  * Copyright (c) 2015-2017, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/hw.h"
  22 #include "target/ppc/cpu.h"
  23 #include "qemu/log.h"
  24 #include "qapi/error.h"
  25
  26 #include "exec/address-spaces.h"
  27
  28 #include "hw/ppc/fdt.h"
  29 #include "hw/ppc/pnv.h"
  30 #include "hw/ppc/pnv_xscom.h"
  31 #include "hw/ppc/pnv_psi.h"
  32
  33 #include <libfdt.h>
  34
  35 #define PSIHB_XSCOM_FIR_RW      0x00
  36 #define PSIHB_XSCOM_FIR_AND     0x01
  37 #define PSIHB_XSCOM_FIR_OR      0x02
  38 #define PSIHB_XSCOM_FIRMASK_RW  0x03
  39 #define PSIHB_XSCOM_FIRMASK_AND 0x04
  40 #define PSIHB_XSCOM_FIRMASK_OR  0x05
  41 #define PSIHB_XSCOM_FIRACT0     0x06
  42 #define PSIHB_XSCOM_FIRACT1     0x07
  43
  44 /* Host Bridge Base Address Register */
  45 #define PSIHB_XSCOM_BAR         0x0a
  46 #define   PSIHB_BAR_EN                  0x0000000000000001ull
  47
  48 /* FSP Base Address Register */
  49 #define PSIHB_XSCOM_FSPBAR      0x0b
  50
  51 /* PSI Host Bridge Control/Status Register */
  52 #define PSIHB_XSCOM_CR          0x0e
  53 #define   PSIHB_CR_FSP_CMD_ENABLE       0x8000000000000000ull
  54 #define   PSIHB_CR_FSP_MMIO_ENABLE      0x4000000000000000ull
  55 #define   PSIHB_CR_FSP_IRQ_ENABLE       0x1000000000000000ull
  56 #define   PSIHB_CR_FSP_ERR_RSP_ENABLE   0x0800000000000000ull
  57 #define   PSIHB_CR_PSI_LINK_ENABLE      0x0400000000000000ull
  58 #define   PSIHB_CR_FSP_RESET            0x0200000000000000ull
  59 #define   PSIHB_CR_PSIHB_RESET          0x0100000000000000ull
  60 #define   PSIHB_CR_PSI_IRQ              0x0000800000000000ull
  61 #define   PSIHB_CR_FSP_IRQ              0x0000400000000000ull
  62 #define   PSIHB_CR_FSP_LINK_ACTIVE      0x0000200000000000ull
  63 #define   PSIHB_CR_IRQ_CMD_EXPECT       0x0000010000000000ull
  64           /* and more ... */
  65
  66 /* PSIHB Status / Error Mask Register */
  67 #define PSIHB_XSCOM_SEMR        0x0f
  68
  69 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
  70 #define PSIHB_XSCOM_XIVR_FSP    0x10
  71 #define   PSIHB_XIVR_SERVER_SH          40
  72 #define   PSIHB_XIVR_SERVER_MSK         (0xffffull << PSIHB_XIVR_SERVER_SH)
  73 #define   PSIHB_XIVR_PRIO_SH            32
  74 #define   PSIHB_XIVR_PRIO_MSK           (0xffull << PSIHB_XIVR_PRIO_SH)
  75 #define   PSIHB_XIVR_SRC_SH             29
  76 #define   PSIHB_XIVR_SRC_MSK            (0x7ull << PSIHB_XIVR_SRC_SH)
  77 #define   PSIHB_XIVR_PENDING            0x01000000ull
  78
  79 /* PSI Host Bridge Set Control/ Status Register */
  80 #define PSIHB_XSCOM_SCR         0x12
  81
  82 /* PSI Host Bridge Clear Control/ Status Register */
  83 #define PSIHB_XSCOM_CCR         0x13
  84
  85 /* DMA Upper Address Register */
  86 #define PSIHB_XSCOM_DMA_UPADD   0x14
  87
  88 /* Interrupt Status */
  89 #define PSIHB_XSCOM_IRQ_STAT    0x15
  90 #define   PSIHB_IRQ_STAT_OCC            0x0000001000000000ull
  91 #define   PSIHB_IRQ_STAT_FSI            0x0000000800000000ull
  92 #define   PSIHB_IRQ_STAT_LPCI2C         0x0000000400000000ull
  93 #define   PSIHB_IRQ_STAT_LOCERR         0x0000000200000000ull
  94 #define   PSIHB_IRQ_STAT_EXT            0x0000000100000000ull
  95
  96 /* remaining XIVR */
  97 #define PSIHB_XSCOM_XIVR_OCC    0x16
  98 #define PSIHB_XSCOM_XIVR_FSI    0x17
  99 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18
 100 #define PSIHB_XSCOM_XIVR_LOCERR 0x19
 101 #define PSIHB_XSCOM_XIVR_EXT    0x1a
 102
 103 /* Interrupt Requester Source Compare Register */
 104 #define PSIHB_XSCOM_IRSN        0x1b
 105 #define   PSIHB_IRSN_COMP_SH            45
 106 #define   PSIHB_IRSN_COMP_MSK           (0x7ffffull << PSIHB_IRSN_COMP_SH)
 107 #define   PSIHB_IRSN_IRQ_MUX            0x0000000800000000ull
 108 #define   PSIHB_IRSN_IRQ_RESET          0x0000000400000000ull
 109 #define   PSIHB_IRSN_DOWNSTREAM_EN      0x0000000200000000ull
 110 #define   PSIHB_IRSN_UPSTREAM_EN        0x0000000100000000ull
 111 #define   PSIHB_IRSN_COMPMASK_SH        13
 112 #define   PSIHB_IRSN_COMPMASK_MSK       (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
 113
 114 #define PSIHB_BAR_MASK                  0x0003fffffff00000ull
 115 #define PSIHB_FSPBAR_MASK               0x0003ffff00000000ull
 116
 117 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
 118
 119 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
 120 {
 121     MemoryRegion *sysmem = get_system_memory();
 122     uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
 123
 124     psi->regs[PSIHB_XSCOM_BAR] = bar & (PSIHB_BAR_MASK | PSIHB_BAR_EN);
 125
 126     /* Update MR, always remove it first */
 127     if (old & PSIHB_BAR_EN) {
 128         memory_region_del_subregion(sysmem, &psi->regs_mr);
 129     }
 130
 131     /* Then add it back if needed */
 132     if (bar & PSIHB_BAR_EN) {
 133         uint64_t addr = bar & PSIHB_BAR_MASK;
 134         memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
 135     }
 136 }
 137
 138 static void pnv_psi_update_fsp_mr(PnvPsi *psi)
 139 {
 140     /* TODO: Update FSP MR if/when we support FSP BAR */
 141 }
 142
 143 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
 144 {
 145     uint64_t old = psi->regs[PSIHB_XSCOM_CR];
 146
 147     psi->regs[PSIHB_XSCOM_CR] = cr;
 148
 149     /* Check some bit changes */
 150     if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
 151         pnv_psi_update_fsp_mr(psi);
 152     }
 153 }
 154
 155 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
 156 {
 157     ICSState *ics = &psi->ics;
 158
 159     /* In this model we ignore the up/down enable bits for now
 160      * as SW doesn't use them (other than setting them at boot).
 161      * We ignore IRQ_MUX, its meaning isn't clear and we don't use
 162      * it and finally we ignore reset (XXX fix that ?)
 163      */
 164     psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
 165                                          PSIHB_IRSN_IRQ_MUX |
 166                                          PSIHB_IRSN_IRQ_RESET |
 167                                          PSIHB_IRSN_DOWNSTREAM_EN |
 168                                          PSIHB_IRSN_UPSTREAM_EN);
 169
 170     /* We ignore the compare mask as well, our ICS emulation is too
 171      * simplistic to make any use if it, and we extract the offset
 172      * from the compare value
 173      */
 174     ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
 175 }
 176
 177 /*
 178  * FSP and PSI interrupts are muxed under the same number.
 179  */
 180 static const uint32_t xivr_regs[] = {
 181     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_XIVR_FSP,
 182     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_XIVR_FSP,
 183     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_XIVR_OCC,
 184     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_XIVR_FSI,
 185     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_XIVR_LPCI2C,
 186     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
 187     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_XIVR_EXT,
 188 };
 189
 190 static const uint32_t stat_regs[] = {
 191     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_CR,
 192     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_CR,
 193     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_IRQ_STAT,
 194     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_IRQ_STAT,
 195     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_IRQ_STAT,
 196     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
 197     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_IRQ_STAT,
 198 };
 199
 200 static const uint64_t stat_bits[] = {
 201     [PSIHB_IRQ_PSI]       = PSIHB_CR_PSI_IRQ,
 202     [PSIHB_IRQ_FSP]       = PSIHB_CR_FSP_IRQ,
 203     [PSIHB_IRQ_OCC]       = PSIHB_IRQ_STAT_OCC,
 204     [PSIHB_IRQ_FSI]       = PSIHB_IRQ_STAT_FSI,
 205     [PSIHB_IRQ_LPC_I2C]   = PSIHB_IRQ_STAT_LPCI2C,
 206     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
 207     [PSIHB_IRQ_EXTERNAL]  = PSIHB_IRQ_STAT_EXT,
 208 };
 209
 210 void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state)
 211 {
 212     uint32_t xivr_reg;
 213     uint32_t stat_reg;
 214     uint32_t src;
 215     bool masked;
 216
 217     if (irq > PSIHB_IRQ_EXTERNAL) {
 218         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
 219         return;
 220     }
 221
 222     xivr_reg = xivr_regs[irq];
 223     stat_reg = stat_regs[irq];
 224
 225     src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 226     if (state) {
 227         psi->regs[stat_reg] |= stat_bits[irq];
 228         /* TODO: optimization, check mask here. That means
 229          * re-evaluating when unmasking
 230          */
 231         qemu_irq_raise(psi->qirqs[src]);
 232     } else {
 233         psi->regs[stat_reg] &= ~stat_bits[irq];
 234
 235         /* FSP and PSI are muxed so don't lower if either is still set */
 236         if (stat_reg != PSIHB_XSCOM_CR ||
 237             !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
 238             qemu_irq_lower(psi->qirqs[src]);
 239         } else {
 240             state = true;
 241         }
 242     }
 243
 244     /* Note about the emulation of the pending bit: This isn't
 245      * entirely correct. The pending bit should be cleared when the
 246      * EOI has been received. However, we don't have callbacks on EOI
 247      * (especially not under KVM) so no way to emulate that properly,
 248      * so instead we just set that bit as the logical "output" of the
 249      * XIVR (ie pending & !masked)
 250      *
 251      * CLG: We could define a new ICS object with a custom eoi()
 252      * handler to clear the pending bit. But I am not sure this would
 253      * be useful for the software anyhow.
 254      */
 255     masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
 256     if (state && !masked) {
 257         psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
 258     } else {
 259         psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
 260     }
 261 }
 262
 263 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
 264 {
 265     ICSState *ics = &psi->ics;
 266     uint16_t server;
 267     uint8_t prio;
 268     uint8_t src;
 269
 270     psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
 271             (val & (PSIHB_XIVR_SERVER_MSK |
 272                     PSIHB_XIVR_PRIO_MSK |
 273                     PSIHB_XIVR_SRC_MSK));
 274     val = psi->regs[reg];
 275     server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
 276     prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
 277     src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 278
 279     if (src >= PSI_NUM_INTERRUPTS) {
 280         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
 281         return;
 282     }
 283
 284     /* Remove pending bit if the IRQ is masked */
 285     if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
 286         psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
 287     }
 288
 289     /* The low order 2 bits are the link pointer (Type II interrupts).
 290      * Shift back to get a valid IRQ server.
 291      */
 292     server >>= 2;
 293
 294     /* Now because of source remapping, weird things can happen
 295      * if you change the source number dynamically, our simple ICS
 296      * doesn't deal with remapping. So we just poke a different
 297      * ICS entry based on what source number was written. This will
 298      * do for now but a more accurate implementation would instead
 299      * use a fixed server/prio and a remapper of the generated irq.
 300      */
 301     ics_simple_write_xive(ics, src, server, prio, prio);
 302 }
 303
 304 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
 305 {
 306     uint64_t val = 0xffffffffffffffffull;
 307
 308     switch (offset) {
 309     case PSIHB_XSCOM_FIR_RW:
 310     case PSIHB_XSCOM_FIRACT0:
 311     case PSIHB_XSCOM_FIRACT1:
 312     case PSIHB_XSCOM_BAR:
 313     case PSIHB_XSCOM_FSPBAR:
 314     case PSIHB_XSCOM_CR:
 315     case PSIHB_XSCOM_XIVR_FSP:
 316     case PSIHB_XSCOM_XIVR_OCC:
 317     case PSIHB_XSCOM_XIVR_FSI:
 318     case PSIHB_XSCOM_XIVR_LPCI2C:
 319     case PSIHB_XSCOM_XIVR_LOCERR:
 320     case PSIHB_XSCOM_XIVR_EXT:
 321     case PSIHB_XSCOM_IRQ_STAT:
 322     case PSIHB_XSCOM_SEMR:
 323     case PSIHB_XSCOM_DMA_UPADD:
 324     case PSIHB_XSCOM_IRSN:
 325         val = psi->regs[offset];
 326         break;
 327     default:
 328         qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
 329     }
 330     return val;
 331 }
 332
 333 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
 334                               bool mmio)
 335 {
 336     switch (offset) {
 337     case PSIHB_XSCOM_FIR_RW:
 338     case PSIHB_XSCOM_FIRACT0:
 339     case PSIHB_XSCOM_FIRACT1:
 340     case PSIHB_XSCOM_SEMR:
 341     case PSIHB_XSCOM_DMA_UPADD:
 342         psi->regs[offset] = val;
 343         break;
 344     case PSIHB_XSCOM_FIR_OR:
 345         psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
 346         break;
 347     case PSIHB_XSCOM_FIR_AND:
 348         psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
 349         break;
 350     case PSIHB_XSCOM_BAR:
 351         /* Only XSCOM can write this one */
 352         if (!mmio) {
 353             pnv_psi_set_bar(psi, val);
 354         } else {
 355             qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
 356         }
 357         break;
 358     case PSIHB_XSCOM_FSPBAR:
 359         psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
 360         pnv_psi_update_fsp_mr(psi);
 361         break;
 362     case PSIHB_XSCOM_CR:
 363         pnv_psi_set_cr(psi, val);
 364         break;
 365     case PSIHB_XSCOM_SCR:
 366         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
 367         break;
 368     case PSIHB_XSCOM_CCR:
 369         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
 370         break;
 371     case PSIHB_XSCOM_XIVR_FSP:
 372     case PSIHB_XSCOM_XIVR_OCC:
 373     case PSIHB_XSCOM_XIVR_FSI:
 374     case PSIHB_XSCOM_XIVR_LPCI2C:
 375     case PSIHB_XSCOM_XIVR_LOCERR:
 376     case PSIHB_XSCOM_XIVR_EXT:
 377         pnv_psi_set_xivr(psi, offset, val);
 378         break;
 379     case PSIHB_XSCOM_IRQ_STAT:
 380         /* Read only */
 381         qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
 382         break;
 383     case PSIHB_XSCOM_IRSN:
 384         pnv_psi_set_irsn(psi, val);
 385         break;
 386     default:
 387         qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
 388     }
 389 }
 390
 391 /*
 392  * The values of the registers when accessed through the MMIO region
 393  * follow the relation : xscom = (mmio + 0x50) >> 3
 394  */
 395 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
 396 {
 397     return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
 398 }
 399
 400 static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
 401                               uint64_t val, unsigned size)
 402 {
 403     pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
 404 }
 405
 406 static const MemoryRegionOps psi_mmio_ops = {
 407     .read = pnv_psi_mmio_read,
 408     .write = pnv_psi_mmio_write,
 409     .endianness = DEVICE_BIG_ENDIAN,
 410     .valid = {
 411         .min_access_size = 8,
 412         .max_access_size = 8,
 413     },
 414     .impl = {
 415         .min_access_size = 8,
 416         .max_access_size = 8,
 417     },
 418 };
 419
 420 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
 421 {
 422     return pnv_psi_reg_read(opaque, addr >> 3, false);
 423 }
 424
 425 static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
 426                                 uint64_t val, unsigned size)
 427 {
 428     pnv_psi_reg_write(opaque, addr >> 3, val, false);
 429 }
 430
 431 static const MemoryRegionOps pnv_psi_xscom_ops = {
 432     .read = pnv_psi_xscom_read,
 433     .write = pnv_psi_xscom_write,
 434     .endianness = DEVICE_BIG_ENDIAN,
 435     .valid = {
 436         .min_access_size = 8,
 437         .max_access_size = 8,
 438     },
 439     .impl = {
 440         .min_access_size = 8,
 441         .max_access_size = 8,
 442     }
 443 };
 444
 445 static void pnv_psi_init(Object *obj)
 446 {
 447     PnvPsi *psi = PNV_PSI(obj);
 448
 449     object_initialize_child(obj, "ics-psi",  &psi->ics, sizeof(psi->ics),
 450                             TYPE_ICS_SIMPLE, &error_abort, NULL);
 451 }
 452
 453 static const uint8_t irq_to_xivr[] = {
 454     PSIHB_XSCOM_XIVR_FSP,
 455     PSIHB_XSCOM_XIVR_OCC,
 456     PSIHB_XSCOM_XIVR_FSI,
 457     PSIHB_XSCOM_XIVR_LPCI2C,
 458     PSIHB_XSCOM_XIVR_LOCERR,
 459     PSIHB_XSCOM_XIVR_EXT,
 460 };
 461
 462 static void pnv_psi_realize(DeviceState *dev, Error **errp)
 463 {
 464     PnvPsi *psi = PNV_PSI(dev);
 465     ICSState *ics = &psi->ics;
 466     Object *obj;
 467     Error *err = NULL;
 468     unsigned int i;
 469
 470     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 471     if (!obj) {
 472         error_setg(errp, "%s: required link 'xics' not found: %s",
 473                    __func__, error_get_pretty(err));
 474         return;
 475     }
 476
 477     /* Create PSI interrupt control source */
 478     object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj,
 479                                    &error_abort);
 480     object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
 481     if (err) {
 482         error_propagate(errp, err);
 483         return;
 484     }
 485     object_property_set_bool(OBJECT(ics), true, "realized",  &err);
 486     if (err) {
 487         error_propagate(errp, err);
 488         return;
 489     }
 490
 491     for (i = 0; i < ics->nr_irqs; i++) {
 492         ics_set_irq_type(ics, i, true);
 493     }
 494
 495     psi->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
 496
 497     /* XSCOM region for PSI registers */
 498     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
 499                 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
 500
 501     /* Initialize MMIO region */
 502     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
 503                           "psihb", PNV_PSIHB_SIZE);
 504
 505     /* Default BAR for MMIO region */
 506     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
 507
 508     /* Default sources in XIVR */
 509     for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
 510         uint8_t xivr = irq_to_xivr[i];
 511         psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
 512             ((uint64_t) i << PSIHB_XIVR_SRC_SH);
 513     }
 514 }
 515
 516 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
 517 {
 518     const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
 519     char *name;
 520     int offset;
 521     uint32_t lpc_pcba = PNV_XSCOM_PSIHB_BASE;
 522     uint32_t reg[] = {
 523         cpu_to_be32(lpc_pcba),
 524         cpu_to_be32(PNV_XSCOM_PSIHB_SIZE)
 525     };
 526
 527     name = g_strdup_printf("psihb@%x", lpc_pcba);
 528     offset = fdt_add_subnode(fdt, xscom_offset, name);
 529     _FDT(offset);
 530     g_free(name);
 531
 532     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 533
 534     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
 535     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
 536     _FDT((fdt_setprop(fdt, offset, "compatible", compat,
 537                       sizeof(compat))));
 538     return 0;
 539 }
 540
 541 static Property pnv_psi_properties[] = {
 542     DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
 543     DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
 544     DEFINE_PROP_END_OF_LIST(),
 545 };
 546
 547 static void pnv_psi_class_init(ObjectClass *klass, void *data)
 548 {
 549     DeviceClass *dc = DEVICE_CLASS(klass);
 550     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 551
 552     xdc->dt_xscom = pnv_psi_dt_xscom;
 553
 554     dc->realize = pnv_psi_realize;
 555     dc->props = pnv_psi_properties;
 556 }
 557
 558 static const TypeInfo pnv_psi_info = {
 559     .name          = TYPE_PNV_PSI,
 560     .parent        = TYPE_SYS_BUS_DEVICE,
 561     .instance_size = sizeof(PnvPsi),
 562     .instance_init = pnv_psi_init,
 563     .class_init    = pnv_psi_class_init,
 564     .interfaces    = (InterfaceInfo[]) {
 565         { TYPE_PNV_XSCOM_INTERFACE },
 566         { }
 567     }
 568 };
 569
 570 static void pnv_psi_register_types(void)
 571 {
 572     type_register_static(&pnv_psi_info);
 573 }
 574
 575 type_init(pnv_psi_register_types)