user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "tcg.h"
  23 #include "qemu/bitops.h"
  24
  25 #undef EAX
  26 #undef ECX
  27 #undef EDX
  28 #undef EBX
  29 #undef ESP
  30 #undef EBP
  31 #undef ESI
  32 #undef EDI
  33 #undef EIP
  34 #include <signal.h>
  35 #ifdef __linux__
  36 #include <sys/ucontext.h>
  37 #endif
  38
  39 //#define DEBUG_SIGNAL
  40
  41 static void exception_action(CPUState *cpu)
  42 {
  43 #if defined(TARGET_I386)
  44     X86CPU *x86_cpu = X86_CPU(cpu);
  45     CPUX86State *env1 = &x86_cpu->env;
  46
  47     raise_exception_err(env1, cpu->exception_index, env1->error_code);
  48 #else
  49     cpu_loop_exit(cpu);
  50 #endif
  51 }
  52
  53 /* exit the current TB from a signal handler. The host registers are
  54    restored in a state compatible with the CPU emulator
  55  */
  56 void cpu_resume_from_signal(CPUState *cpu, void *puc)
  57 {
  58 #ifdef __linux__
  59     struct ucontext *uc = puc;
  60 #elif defined(__OpenBSD__)
  61     struct sigcontext *uc = puc;
  62 #endif
  63
  64     if (puc) {
  65         /* XXX: use siglongjmp ? */
  66 #ifdef __linux__
  67 #ifdef __ia64
  68         sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
  69 #else
  70         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  71 #endif
  72 #elif defined(__OpenBSD__)
  73         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  74 #endif
  75     }
  76     cpu->exception_index = -1;
  77     siglongjmp(cpu->jmp_env, 1);
  78 }
  79
  80 /* 'pc' is the host PC at which the exception was raised. 'address' is
  81    the effective address of the memory exception. 'is_write' is 1 if a
  82    write caused the exception and otherwise 0'. 'old_set' is the
  83    signal set which should be restored */
  84 static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
  85                                     int is_write, sigset_t *old_set,
  86                                     void *puc)
  87 {
  88     CPUState *cpu;
  89     CPUClass *cc;
  90     int ret;
  91
  92 #if defined(DEBUG_SIGNAL)
  93     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  94                 pc, address, is_write, *(unsigned long *)old_set);
  95 #endif
  96     /* XXX: locking issue */
  97     if (is_write && h2g_valid(address)
  98         && page_unprotect(h2g(address), pc, puc)) {
  99         return 1;
 100     }
 101
 102     /* Convert forcefully to guest address space, invalid addresses
 103        are still valid segv ones */
 104     address = h2g_nocheck(address);
 105
 106     cpu = current_cpu;
 107     cc = CPU_GET_CLASS(cpu);
 108     /* see if it is an MMU fault */
 109     g_assert(cc->handle_mmu_fault);
 110     ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
 111     if (ret < 0) {
 112         return 0; /* not an MMU fault */
 113     }
 114     if (ret == 0) {
 115         return 1; /* the MMU fault was handled without causing real CPU fault */
 116     }
 117     /* now we have a real cpu fault */
 118     cpu_restore_state(cpu, pc);
 119
 120     /* we restore the process signal mask as the sigreturn should
 121        do it (XXX: use sigsetjmp) */
 122     sigprocmask(SIG_SETMASK, old_set, NULL);
 123     exception_action(cpu);
 124
 125     /* never comes here */
 126     return 1;
 127 }
 128
 129 #if defined(__i386__)
 130
 131 #if defined(__APPLE__)
 132 #include <sys/ucontext.h>
 133
 134 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
 135 #define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
 136 #define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
 137 #define MASK_sig(context)    ((context)->uc_sigmask)
 138 #elif defined(__NetBSD__)
 139 #include <ucontext.h>
 140
 141 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 142 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 143 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 144 #define MASK_sig(context)    ((context)->uc_sigmask)
 145 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 146 #include <ucontext.h>
 147
 148 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 149 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 150 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 151 #define MASK_sig(context)    ((context)->uc_sigmask)
 152 #elif defined(__OpenBSD__)
 153 #define EIP_sig(context)     ((context)->sc_eip)
 154 #define TRAP_sig(context)    ((context)->sc_trapno)
 155 #define ERROR_sig(context)   ((context)->sc_err)
 156 #define MASK_sig(context)    ((context)->sc_mask)
 157 #else
 158 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 159 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 160 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 161 #define MASK_sig(context)    ((context)->uc_sigmask)
 162 #endif
 163
 164 int cpu_signal_handler(int host_signum, void *pinfo,
 165                        void *puc)
 166 {
 167     siginfo_t *info = pinfo;
 168 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 169     ucontext_t *uc = puc;
 170 #elif defined(__OpenBSD__)
 171     struct sigcontext *uc = puc;
 172 #else
 173     struct ucontext *uc = puc;
 174 #endif
 175     unsigned long pc;
 176     int trapno;
 177
 178 #ifndef REG_EIP
 179 /* for glibc 2.1 */
 180 #define REG_EIP    EIP
 181 #define REG_ERR    ERR
 182 #define REG_TRAPNO TRAPNO
 183 #endif
 184     pc = EIP_sig(uc);
 185     trapno = TRAP_sig(uc);
 186     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 187                              trapno == 0xe ?
 188                              (ERROR_sig(uc) >> 1) & 1 : 0,
 189                              &MASK_sig(uc), puc);
 190 }
 191
 192 #elif defined(__x86_64__)
 193
 194 #ifdef __NetBSD__
 195 #define PC_sig(context)       _UC_MACHINE_PC(context)
 196 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 197 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 198 #define MASK_sig(context)     ((context)->uc_sigmask)
 199 #elif defined(__OpenBSD__)
 200 #define PC_sig(context)       ((context)->sc_rip)
 201 #define TRAP_sig(context)     ((context)->sc_trapno)
 202 #define ERROR_sig(context)    ((context)->sc_err)
 203 #define MASK_sig(context)     ((context)->sc_mask)
 204 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 205 #include <ucontext.h>
 206
 207 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 208 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 209 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 210 #define MASK_sig(context)     ((context)->uc_sigmask)
 211 #else
 212 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 213 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 214 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 215 #define MASK_sig(context)     ((context)->uc_sigmask)
 216 #endif
 217
 218 int cpu_signal_handler(int host_signum, void *pinfo,
 219                        void *puc)
 220 {
 221     siginfo_t *info = pinfo;
 222     unsigned long pc;
 223 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 224     ucontext_t *uc = puc;
 225 #elif defined(__OpenBSD__)
 226     struct sigcontext *uc = puc;
 227 #else
 228     struct ucontext *uc = puc;
 229 #endif
 230
 231     pc = PC_sig(uc);
 232     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 233                              TRAP_sig(uc) == 0xe ?
 234                              (ERROR_sig(uc) >> 1) & 1 : 0,
 235                              &MASK_sig(uc), puc);
 236 }
 237
 238 #elif defined(_ARCH_PPC)
 239
 240 /***********************************************************************
 241  * signal context platform-specific definitions
 242  * From Wine
 243  */
 244 #ifdef linux
 245 /* All Registers access - only for local access */
 246 #define REG_sig(reg_name, context)              \
 247     ((context)->uc_mcontext.regs->reg_name)
 248 /* Gpr Registers access  */
 249 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 250 /* Program counter */
 251 #define IAR_sig(context)                       REG_sig(nip, context)
 252 /* Machine State Register (Supervisor) */
 253 #define MSR_sig(context)                       REG_sig(msr, context)
 254 /* Count register */
 255 #define CTR_sig(context)                       REG_sig(ctr, context)
 256 /* User's integer exception register */
 257 #define XER_sig(context)                       REG_sig(xer, context)
 258 /* Link register */
 259 #define LR_sig(context)                        REG_sig(link, context)
 260 /* Condition register */
 261 #define CR_sig(context)                        REG_sig(ccr, context)
 262
 263 /* Float Registers access  */
 264 #define FLOAT_sig(reg_num, context)                                     \
 265     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 266 #define FPSCR_sig(context) \
 267     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 268 /* Exception Registers access */
 269 #define DAR_sig(context)                       REG_sig(dar, context)
 270 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 271 #define TRAP_sig(context)                      REG_sig(trap, context)
 272 #endif /* linux */
 273
 274 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 275 #include <ucontext.h>
 276 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 277 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 278 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 279 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 280 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 281 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 282 /* Exception Registers access */
 283 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 284 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 285 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 286 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 287
 288 #ifdef __APPLE__
 289 #include <sys/ucontext.h>
 290 typedef struct ucontext SIGCONTEXT;
 291 /* All Registers access - only for local access */
 292 #define REG_sig(reg_name, context)              \
 293     ((context)->uc_mcontext->ss.reg_name)
 294 #define FLOATREG_sig(reg_name, context)         \
 295     ((context)->uc_mcontext->fs.reg_name)
 296 #define EXCEPREG_sig(reg_name, context)         \
 297     ((context)->uc_mcontext->es.reg_name)
 298 #define VECREG_sig(reg_name, context)           \
 299     ((context)->uc_mcontext->vs.reg_name)
 300 /* Gpr Registers access */
 301 #define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
 302 /* Program counter */
 303 #define IAR_sig(context)                       REG_sig(srr0, context)
 304 /* Machine State Register (Supervisor) */
 305 #define MSR_sig(context)                       REG_sig(srr1, context)
 306 #define CTR_sig(context)                       REG_sig(ctr, context)
 307 /* Link register */
 308 #define XER_sig(context)                       REG_sig(xer, context)
 309 /* User's integer exception register */
 310 #define LR_sig(context)                        REG_sig(lr, context)
 311 /* Condition register */
 312 #define CR_sig(context)                        REG_sig(cr, context)
 313 /* Float Registers access */
 314 #define FLOAT_sig(reg_num, context)             \
 315     FLOATREG_sig(fpregs[reg_num], context)
 316 #define FPSCR_sig(context)                      \
 317     ((double)FLOATREG_sig(fpscr, context))
 318 /* Exception Registers access */
 319 /* Fault registers for coredump */
 320 #define DAR_sig(context)                       EXCEPREG_sig(dar, context)
 321 #define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
 322 /* number of powerpc exception taken */
 323 #define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
 324 #endif /* __APPLE__ */
 325
 326 int cpu_signal_handler(int host_signum, void *pinfo,
 327                        void *puc)
 328 {
 329     siginfo_t *info = pinfo;
 330 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 331     ucontext_t *uc = puc;
 332 #else
 333     struct ucontext *uc = puc;
 334 #endif
 335     unsigned long pc;
 336     int is_write;
 337
 338     pc = IAR_sig(uc);
 339     is_write = 0;
 340 #if 0
 341     /* ppc 4xx case */
 342     if (DSISR_sig(uc) & 0x00800000) {
 343         is_write = 1;
 344     }
 345 #else
 346     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 347         is_write = 1;
 348     }
 349 #endif
 350     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 351                              is_write, &uc->uc_sigmask, puc);
 352 }
 353
 354 #elif defined(__alpha__)
 355
 356 int cpu_signal_handler(int host_signum, void *pinfo,
 357                            void *puc)
 358 {
 359     siginfo_t *info = pinfo;
 360     struct ucontext *uc = puc;
 361     uint32_t *pc = uc->uc_mcontext.sc_pc;
 362     uint32_t insn = *pc;
 363     int is_write = 0;
 364
 365     /* XXX: need kernel patch to get write flag faster */
 366     switch (insn >> 26) {
 367     case 0x0d: /* stw */
 368     case 0x0e: /* stb */
 369     case 0x0f: /* stq_u */
 370     case 0x24: /* stf */
 371     case 0x25: /* stg */
 372     case 0x26: /* sts */
 373     case 0x27: /* stt */
 374     case 0x2c: /* stl */
 375     case 0x2d: /* stq */
 376     case 0x2e: /* stl_c */
 377     case 0x2f: /* stq_c */
 378         is_write = 1;
 379     }
 380
 381     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 382                              is_write, &uc->uc_sigmask, puc);
 383 }
 384 #elif defined(__sparc__)
 385
 386 int cpu_signal_handler(int host_signum, void *pinfo,
 387                        void *puc)
 388 {
 389     siginfo_t *info = pinfo;
 390     int is_write;
 391     uint32_t insn;
 392 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 393     uint32_t *regs = (uint32_t *)(info + 1);
 394     void *sigmask = (regs + 20);
 395     /* XXX: is there a standard glibc define ? */
 396     unsigned long pc = regs[1];
 397 #else
 398 #ifdef __linux__
 399     struct sigcontext *sc = puc;
 400     unsigned long pc = sc->sigc_regs.tpc;
 401     void *sigmask = (void *)sc->sigc_mask;
 402 #elif defined(__OpenBSD__)
 403     struct sigcontext *uc = puc;
 404     unsigned long pc = uc->sc_pc;
 405     void *sigmask = (void *)(long)uc->sc_mask;
 406 #endif
 407 #endif
 408
 409     /* XXX: need kernel patch to get write flag faster */
 410     is_write = 0;
 411     insn = *(uint32_t *)pc;
 412     if ((insn >> 30) == 3) {
 413         switch ((insn >> 19) & 0x3f) {
 414         case 0x05: /* stb */
 415         case 0x15: /* stba */
 416         case 0x06: /* sth */
 417         case 0x16: /* stha */
 418         case 0x04: /* st */
 419         case 0x14: /* sta */
 420         case 0x07: /* std */
 421         case 0x17: /* stda */
 422         case 0x0e: /* stx */
 423         case 0x1e: /* stxa */
 424         case 0x24: /* stf */
 425         case 0x34: /* stfa */
 426         case 0x27: /* stdf */
 427         case 0x37: /* stdfa */
 428         case 0x26: /* stqf */
 429         case 0x36: /* stqfa */
 430         case 0x25: /* stfsr */
 431         case 0x3c: /* casa */
 432         case 0x3e: /* casxa */
 433             is_write = 1;
 434             break;
 435         }
 436     }
 437     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 438                              is_write, sigmask, NULL);
 439 }
 440
 441 #elif defined(__arm__)
 442
 443 int cpu_signal_handler(int host_signum, void *pinfo,
 444                        void *puc)
 445 {
 446     siginfo_t *info = pinfo;
 447     struct ucontext *uc = puc;
 448     unsigned long pc;
 449     int is_write;
 450
 451 #if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 452     pc = uc->uc_mcontext.gregs[R15];
 453 #else
 454     pc = uc->uc_mcontext.arm_pc;
 455 #endif
 456
 457     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 458      * later processor; on v5 we will always report this as a read).
 459      */
 460     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 461     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 462                              is_write,
 463                              &uc->uc_sigmask, puc);
 464 }
 465
 466 #elif defined(__aarch64__)
 467
 468 int cpu_signal_handler(int host_signum, void *pinfo,
 469                        void *puc)
 470 {
 471     siginfo_t *info = pinfo;
 472     struct ucontext *uc = puc;
 473     uint64_t pc;
 474     int is_write = 0; /* XXX how to determine? */
 475
 476     pc = uc->uc_mcontext.pc;
 477     return handle_cpu_signal(pc, (uint64_t)info->si_addr,
 478                              is_write, &uc->uc_sigmask, puc);
 479 }
 480
 481 #elif defined(__mc68000)
 482
 483 int cpu_signal_handler(int host_signum, void *pinfo,
 484                        void *puc)
 485 {
 486     siginfo_t *info = pinfo;
 487     struct ucontext *uc = puc;
 488     unsigned long pc;
 489     int is_write;
 490
 491     pc = uc->uc_mcontext.gregs[16];
 492     /* XXX: compute is_write */
 493     is_write = 0;
 494     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 495                              is_write,
 496                              &uc->uc_sigmask, puc);
 497 }
 498
 499 #elif defined(__ia64)
 500
 501 #ifndef __ISR_VALID
 502   /* This ought to be in <bits/siginfo.h>... */
 503 # define __ISR_VALID    1
 504 #endif
 505
 506 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 507 {
 508     siginfo_t *info = pinfo;
 509     struct ucontext *uc = puc;
 510     unsigned long ip;
 511     int is_write = 0;
 512
 513     ip = uc->uc_mcontext.sc_ip;
 514     switch (host_signum) {
 515     case SIGILL:
 516     case SIGFPE:
 517     case SIGSEGV:
 518     case SIGBUS:
 519     case SIGTRAP:
 520         if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
 521             /* ISR.W (write-access) is bit 33:  */
 522             is_write = (info->si_isr >> 33) & 1;
 523         }
 524         break;
 525
 526     default:
 527         break;
 528     }
 529     return handle_cpu_signal(ip, (unsigned long)info->si_addr,
 530                              is_write,
 531                              (sigset_t *)&uc->uc_sigmask, puc);
 532 }
 533
 534 #elif defined(__s390__)
 535
 536 int cpu_signal_handler(int host_signum, void *pinfo,
 537                        void *puc)
 538 {
 539     siginfo_t *info = pinfo;
 540     struct ucontext *uc = puc;
 541     unsigned long pc;
 542     uint16_t *pinsn;
 543     int is_write = 0;
 544
 545     pc = uc->uc_mcontext.psw.addr;
 546
 547     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 548        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 549        from the hardware which does in fact contain the is_write value.
 550        The rt signal handler, as far as I can tell, does not give this value
 551        at all.  Not that we could get to it from here even if it were.  */
 552     /* ??? This is not even close to complete, since it ignores all
 553        of the read-modify-write instructions.  */
 554     pinsn = (uint16_t *)pc;
 555     switch (pinsn[0] >> 8) {
 556     case 0x50: /* ST */
 557     case 0x42: /* STC */
 558     case 0x40: /* STH */
 559         is_write = 1;
 560         break;
 561     case 0xc4: /* RIL format insns */
 562         switch (pinsn[0] & 0xf) {
 563         case 0xf: /* STRL */
 564         case 0xb: /* STGRL */
 565         case 0x7: /* STHRL */
 566             is_write = 1;
 567         }
 568         break;
 569     case 0xe3: /* RXY format insns */
 570         switch (pinsn[2] & 0xff) {
 571         case 0x50: /* STY */
 572         case 0x24: /* STG */
 573         case 0x72: /* STCY */
 574         case 0x70: /* STHY */
 575         case 0x8e: /* STPQ */
 576         case 0x3f: /* STRVH */
 577         case 0x3e: /* STRV */
 578         case 0x2f: /* STRVG */
 579             is_write = 1;
 580         }
 581         break;
 582     }
 583     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 584                              is_write, &uc->uc_sigmask, puc);
 585 }
 586
 587 #elif defined(__mips__)
 588
 589 int cpu_signal_handler(int host_signum, void *pinfo,
 590                        void *puc)
 591 {
 592     siginfo_t *info = pinfo;
 593     struct ucontext *uc = puc;
 594     greg_t pc = uc->uc_mcontext.pc;
 595     int is_write;
 596
 597     /* XXX: compute is_write */
 598     is_write = 0;
 599     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 600                              is_write, &uc->uc_sigmask, puc);
 601 }
 602
 603 #elif defined(__hppa__)
 604
 605 int cpu_signal_handler(int host_signum, void *pinfo,
 606                        void *puc)
 607 {
 608     siginfo_t *info = pinfo;
 609     struct ucontext *uc = puc;
 610     unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
 611     uint32_t insn = *(uint32_t *)pc;
 612     int is_write = 0;
 613
 614     /* XXX: need kernel patch to get write flag faster.  */
 615     switch (insn >> 26) {
 616     case 0x1a: /* STW */
 617     case 0x19: /* STH */
 618     case 0x18: /* STB */
 619     case 0x1b: /* STWM */
 620         is_write = 1;
 621         break;
 622
 623     case 0x09: /* CSTWX, FSTWX, FSTWS */
 624     case 0x0b: /* CSTDX, FSTDX, FSTDS */
 625         /* Distinguish from coprocessor load ... */
 626         is_write = (insn >> 9) & 1;
 627         break;
 628
 629     case 0x03:
 630         switch ((insn >> 6) & 15) {
 631         case 0xa: /* STWS */
 632         case 0x9: /* STHS */
 633         case 0x8: /* STBS */
 634         case 0xe: /* STWAS */
 635         case 0xc: /* STBYS */
 636             is_write = 1;
 637         }
 638         break;
 639     }
 640
 641     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 642                              is_write, &uc->uc_sigmask, puc);
 643 }
 644
 645 #else
 646
 647 #error host CPU specific signal handler needed
 648
 649 #endif