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target/mips: Remove access_type arg from get_segctl_physical_address()
[qemu/ar7.git] / target / mips / tlb_helper.c
blobd89ad87cb9db6837d92026b4794079f2ba86c036
1 /*
2 * MIPS TLB (Translation lookaside buffer) helpers.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/log.h"
26 #include "hw/mips/cpudevs.h"
27
28 enum {
29 TLBRET_XI = -6,
30 TLBRET_RI = -5,
31 TLBRET_DIRTY = -4,
32 TLBRET_INVALID = -3,
33 TLBRET_NOMATCH = -2,
34 TLBRET_BADADDR = -1,
35 TLBRET_MATCH = 0
36 };
37
38 #if !defined(CONFIG_USER_ONLY)
39
40 /* no MMU emulation */
41 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
42 target_ulong address, int rw)
43 {
44 *physical = address;
45 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
46 return TLBRET_MATCH;
47 }
48
49 /* fixed mapping MMU emulation */
50 int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
51 target_ulong address, int rw)
52 {
53 if (address <= (int32_t)0x7FFFFFFFUL) {
54 if (!(env->CP0_Status & (1 << CP0St_ERL))) {
55 *physical = address + 0x40000000UL;
56 } else {
57 *physical = address;
58 }
59 } else if (address <= (int32_t)0xBFFFFFFFUL) {
60 *physical = address & 0x1FFFFFFF;
61 } else {
62 *physical = address;
63 }
64
65 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
66 return TLBRET_MATCH;
67 }
68
69 /* MIPS32/MIPS64 R4000-style MMU emulation */
70 int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
71 target_ulong address, int rw)
72 {
73 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
74 uint32_t MMID = env->CP0_MemoryMapID;
75 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
76 uint32_t tlb_mmid;
77 int i;
78
79 MMID = mi ? MMID : (uint32_t) ASID;
80
81 for (i = 0; i < env->tlb->tlb_in_use; i++) {
82 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
83 /* 1k pages are not supported. */
84 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
85 target_ulong tag = address & ~mask;
86 target_ulong VPN = tlb->VPN & ~mask;
87 #if defined(TARGET_MIPS64)
88 tag &= env->SEGMask;
89 #endif
90
91 /* Check ASID/MMID, virtual page number & size */
92 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
93 if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) {
94 /* TLB match */
95 int n = !!(address & mask & ~(mask >> 1));
96 /* Check access rights */
97 if (!(n ? tlb->V1 : tlb->V0)) {
98 return TLBRET_INVALID;
99 }
100 if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
101 return TLBRET_XI;
102 }
103 if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
104 return TLBRET_RI;
105 }
106 if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
107 *physical = tlb->PFN[n] | (address & (mask >> 1));
108 *prot = PAGE_READ;
109 if (n ? tlb->D1 : tlb->D0) {
110 *prot |= PAGE_WRITE;
111 }
112 if (!(n ? tlb->XI1 : tlb->XI0)) {
113 *prot |= PAGE_EXEC;
114 }
115 return TLBRET_MATCH;
116 }
117 return TLBRET_DIRTY;
118 }
119 }
120 return TLBRET_NOMATCH;
121 }
122
123 static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
124 {
125 env->tlb->nb_tlb = 1;
126 env->tlb->map_address = &no_mmu_map_address;
127 }
128
129 static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
130 {
131 env->tlb->nb_tlb = 1;
132 env->tlb->map_address = &fixed_mmu_map_address;
133 }
134
135 static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
136 {
137 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
138 env->tlb->map_address = &r4k_map_address;
139 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
140 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
141 env->tlb->helper_tlbp = r4k_helper_tlbp;
142 env->tlb->helper_tlbr = r4k_helper_tlbr;
143 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
144 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
145 }
146
147 void mmu_init(CPUMIPSState *env, const mips_def_t *def)
148 {
149 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
150
151 switch (def->mmu_type) {
152 case MMU_TYPE_NONE:
153 no_mmu_init(env, def);
154 break;
155 case MMU_TYPE_R4000:
156 r4k_mmu_init(env, def);
157 break;
158 case MMU_TYPE_FMT:
159 fixed_mmu_init(env, def);
160 break;
161 case MMU_TYPE_R3000:
162 case MMU_TYPE_R6000:
163 case MMU_TYPE_R8000:
164 default:
165 cpu_abort(env_cpu(env), "MMU type not supported\n");
166 }
167 }
168
169 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
170 {
171 /*
172 * Interpret access control mode and mmu_idx.
173 * AdE? TLB?
174 * AM K S U E K S U E
175 * UK 0 0 1 1 0 0 - - 0
176 * MK 1 0 1 1 0 1 - - !eu
177 * MSK 2 0 0 1 0 1 1 - !eu
178 * MUSK 3 0 0 0 0 1 1 1 !eu
179 * MUSUK 4 0 0 0 0 0 1 1 0
180 * USK 5 0 0 1 0 0 0 - 0
181 * - 6 - - - - - - - -
182 * UUSK 7 0 0 0 0 0 0 0 0
183 */
184 int32_t adetlb_mask;
185
186 switch (mmu_idx) {
187 case 3: /* ERL */
188 /* If EU is set, always unmapped */
189 if (eu) {
190 return 0;
191 }
192 /* fall through */
193 case MIPS_HFLAG_KM:
194 /* Never AdE, TLB mapped if AM={1,2,3} */
195 adetlb_mask = 0x70000000;
196 goto check_tlb;
197
198 case MIPS_HFLAG_SM:
199 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
200 adetlb_mask = 0xc0380000;
201 goto check_ade;
202
203 case MIPS_HFLAG_UM:
204 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
205 adetlb_mask = 0xe4180000;
206 /* fall through */
207 check_ade:
208 /* does this AM cause AdE in current execution mode */
209 if ((adetlb_mask << am) < 0) {
210 return TLBRET_BADADDR;
211 }
212 adetlb_mask <<= 8;
213 /* fall through */
214 check_tlb:
215 /* is this AM mapped in current execution mode */
216 return ((adetlb_mask << am) < 0);
217 default:
218 assert(0);
219 return TLBRET_BADADDR;
220 };
221 }
222
223 static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
224 int *prot, target_ulong real_address,
225 int rw, int mmu_idx,
226 unsigned int am, bool eu,
227 target_ulong segmask,
228 hwaddr physical_base)
229 {
230 int mapped = is_seg_am_mapped(am, eu, mmu_idx);
231
232 if (mapped < 0) {
233 /* is_seg_am_mapped can report TLBRET_BADADDR */
234 return mapped;
235 } else if (mapped) {
236 /* The segment is TLB mapped */
237 return env->tlb->map_address(env, physical, prot, real_address, rw);
238 } else {
239 /* The segment is unmapped */
240 *physical = physical_base | (real_address & segmask);
241 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
242 return TLBRET_MATCH;
243 }
244 }
245
246 static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
247 int *prot, target_ulong real_address,
248 int rw, int mmu_idx,
249 uint16_t segctl, target_ulong segmask)
250 {
251 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
252 bool eu = (segctl >> CP0SC_EU) & 1;
253 hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
254
255 return get_seg_physical_address(env, physical, prot, real_address, rw,
256 mmu_idx, am, eu, segmask,
257 pa & ~(hwaddr)segmask);
258 }
259
260 static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
261 int *prot, target_ulong real_address,
262 int rw, int access_type, int mmu_idx)
263 {
264 /* User mode can only access useg/xuseg */
265 #if defined(TARGET_MIPS64)
266 int user_mode = mmu_idx == MIPS_HFLAG_UM;
267 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
268 int kernel_mode = !user_mode && !supervisor_mode;
269 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
270 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
271 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
272 #endif
273 int ret = TLBRET_MATCH;
274 /* effective address (modified for KVM T&E kernel segments) */
275 target_ulong address = real_address;
276
277 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
278 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
279 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
280 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
281 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
282
283 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
284 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
285
286 if (mips_um_ksegs_enabled()) {
287 /* KVM T&E adds guest kernel segments in useg */
288 if (real_address >= KVM_KSEG0_BASE) {
289 if (real_address < KVM_KSEG2_BASE) {
290 /* kseg0 */
291 address += KSEG0_BASE - KVM_KSEG0_BASE;
292 } else if (real_address <= USEG_LIMIT) {
293 /* kseg2/3 */
294 address += KSEG2_BASE - KVM_KSEG2_BASE;
295 }
296 }
297 }
298
299 if (address <= USEG_LIMIT) {
300 /* useg */
301 uint16_t segctl;
302
303 if (address >= 0x40000000UL) {
304 segctl = env->CP0_SegCtl2;
305 } else {
306 segctl = env->CP0_SegCtl2 >> 16;
307 }
308 ret = get_segctl_physical_address(env, physical, prot,
309 real_address, rw,
310 mmu_idx, segctl, 0x3FFFFFFF);
311 #if defined(TARGET_MIPS64)
312 } else if (address < 0x4000000000000000ULL) {
313 /* xuseg */
314 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
315 ret = env->tlb->map_address(env, physical, prot,
316 real_address, rw);
317 } else {
318 ret = TLBRET_BADADDR;
319 }
320 } else if (address < 0x8000000000000000ULL) {
321 /* xsseg */
322 if ((supervisor_mode || kernel_mode) &&
323 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
324 ret = env->tlb->map_address(env, physical, prot,
325 real_address, rw);
326 } else {
327 ret = TLBRET_BADADDR;
328 }
329 } else if (address < 0xC000000000000000ULL) {
330 /* xkphys */
331 if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
332 /* KX/SX/UX bit to check for each xkphys EVA access mode */
333 static const uint8_t am_ksux[8] = {
334 [CP0SC_AM_UK] = (1u << CP0St_KX),
335 [CP0SC_AM_MK] = (1u << CP0St_KX),
336 [CP0SC_AM_MSK] = (1u << CP0St_SX),
337 [CP0SC_AM_MUSK] = (1u << CP0St_UX),
338 [CP0SC_AM_MUSUK] = (1u << CP0St_UX),
339 [CP0SC_AM_USK] = (1u << CP0St_SX),
340 [6] = (1u << CP0St_KX),
341 [CP0SC_AM_UUSK] = (1u << CP0St_UX),
342 };
343 unsigned int am = CP0SC_AM_UK;
344 unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
345
346 if (xr & (1 << ((address >> 59) & 0x7))) {
347 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
348 }
349 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */
350 if (env->CP0_Status & am_ksux[am]) {
351 ret = get_seg_physical_address(env, physical, prot,
352 real_address, rw,
353 mmu_idx, am, false, env->PAMask,
354 0);
355 } else {
356 ret = TLBRET_BADADDR;
357 }
358 } else {
359 ret = TLBRET_BADADDR;
360 }
361 } else if (address < 0xFFFFFFFF80000000ULL) {
362 /* xkseg */
363 if (kernel_mode && KX &&
364 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
365 ret = env->tlb->map_address(env, physical, prot,
366 real_address, rw);
367 } else {
368 ret = TLBRET_BADADDR;
369 }
370 #endif
371 } else if (address < KSEG1_BASE) {
372 /* kseg0 */
373 ret = get_segctl_physical_address(env, physical, prot, real_address,
374 rw, mmu_idx,
375 env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
376 } else if (address < KSEG2_BASE) {
377 /* kseg1 */
378 ret = get_segctl_physical_address(env, physical, prot, real_address,
379 rw, mmu_idx,
380 env->CP0_SegCtl1, 0x1FFFFFFF);
381 } else if (address < KSEG3_BASE) {
382 /* sseg (kseg2) */
383 ret = get_segctl_physical_address(env, physical, prot, real_address,
384 rw, mmu_idx,
385 env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
386 } else {
387 /*
388 * kseg3
389 * XXX: debug segment is not emulated
390 */
391 ret = get_segctl_physical_address(env, physical, prot, real_address,
392 rw, mmu_idx,
393 env->CP0_SegCtl0, 0x1FFFFFFF);
394 }
395 return ret;
396 }
397
398 void cpu_mips_tlb_flush(CPUMIPSState *env)
399 {
400 /* Flush qemu's TLB and discard all shadowed entries. */
401 tlb_flush(env_cpu(env));
402 env->tlb->tlb_in_use = env->tlb->nb_tlb;
403 }
404
405 #endif /* !CONFIG_USER_ONLY */
406
407 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
408 int rw, int tlb_error)
409 {
410 CPUState *cs = env_cpu(env);
411 int exception = 0, error_code = 0;
412
413 if (rw == MMU_INST_FETCH) {
414 error_code |= EXCP_INST_NOTAVAIL;
415 }
416
417 switch (tlb_error) {
418 default:
419 case TLBRET_BADADDR:
420 /* Reference to kernel address from user mode or supervisor mode */
421 /* Reference to supervisor address from user mode */
422 if (rw == MMU_DATA_STORE) {
423 exception = EXCP_AdES;
424 } else {
425 exception = EXCP_AdEL;
426 }
427 break;
428 case TLBRET_NOMATCH:
429 /* No TLB match for a mapped address */
430 if (rw == MMU_DATA_STORE) {
431 exception = EXCP_TLBS;
432 } else {
433 exception = EXCP_TLBL;
434 }
435 error_code |= EXCP_TLB_NOMATCH;
436 break;
437 case TLBRET_INVALID:
438 /* TLB match with no valid bit */
439 if (rw == MMU_DATA_STORE) {
440 exception = EXCP_TLBS;
441 } else {
442 exception = EXCP_TLBL;
443 }
444 break;
445 case TLBRET_DIRTY:
446 /* TLB match but 'D' bit is cleared */
447 exception = EXCP_LTLBL;
448 break;
449 case TLBRET_XI:
450 /* Execute-Inhibit Exception */
451 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
452 exception = EXCP_TLBXI;
453 } else {
454 exception = EXCP_TLBL;
455 }
456 break;
457 case TLBRET_RI:
458 /* Read-Inhibit Exception */
459 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
460 exception = EXCP_TLBRI;
461 } else {
462 exception = EXCP_TLBL;
463 }
464 break;
465 }
466 /* Raise exception */
467 if (!(env->hflags & MIPS_HFLAG_DM)) {
468 env->CP0_BadVAddr = address;
469 }
470 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
471 ((address >> 9) & 0x007ffff0);
472 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
473 (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
474 (address & (TARGET_PAGE_MASK << 1));
475 #if defined(TARGET_MIPS64)
476 env->CP0_EntryHi &= env->SEGMask;
477 env->CP0_XContext =
478 (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */
479 (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */
480 (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */
481 #endif
482 cs->exception_index = exception;
483 env->error_code = error_code;
484 }
485
486 #if !defined(CONFIG_USER_ONLY)
487
488 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
489 {
490 MIPSCPU *cpu = MIPS_CPU(cs);
491 CPUMIPSState *env = &cpu->env;
492 hwaddr phys_addr;
493 int prot;
494
495 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT,
496 cpu_mmu_index(env, false)) != 0) {
497 return -1;
498 }
499 return phys_addr;
500 }
501
502 #if !defined(TARGET_MIPS64)
503
504 /*
505 * Perform hardware page table walk
506 *
507 * Memory accesses are performed using the KERNEL privilege level.
508 * Synchronous exceptions detected on memory accesses cause a silent exit
509 * from page table walking, resulting in a TLB or XTLB Refill exception.
510 *
511 * Implementations are not required to support page table walk memory
512 * accesses from mapped memory regions. When an unsupported access is
513 * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
514 * exception.
515 *
516 * Note that if an exception is caused by AddressTranslation or LoadMemory
517 * functions, the exception is not taken, a silent exit is taken,
518 * resulting in a TLB or XTLB Refill exception.
519 */
520
521 static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size,
522 uint64_t *pte)
523 {
524 if ((vaddr & ((entry_size >> 3) - 1)) != 0) {
525 return false;
526 }
527 if (entry_size == 64) {
528 *pte = cpu_ldq_code(env, vaddr);
529 } else {
530 *pte = cpu_ldl_code(env, vaddr);
531 }
532 return true;
533 }
534
535 static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry,
536 int entry_size, int ptei)
537 {
538 uint64_t result = entry;
539 uint64_t rixi;
540 if (ptei > entry_size) {
541 ptei -= 32;
542 }
543 result >>= (ptei - 2);
544 rixi = result & 3;
545 result >>= 2;
546 result |= rixi << CP0EnLo_XI;
547 return result;
548 }
549
550 static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
551 int directory_index, bool *huge_page, bool *hgpg_directory_hit,
552 uint64_t *pw_entrylo0, uint64_t *pw_entrylo1)
553 {
554 int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
555 int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
556 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
557 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
558 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
559 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
560 int directory_shift = (ptew > 1) ? -1 :
561 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
562 int leaf_shift = (ptew > 1) ? -1 :
563 (ptew == 1) ? native_shift + 1 : native_shift;
564 uint32_t direntry_size = 1 << (directory_shift + 3);
565 uint32_t leafentry_size = 1 << (leaf_shift + 3);
566 uint64_t entry;
567 uint64_t paddr;
568 int prot;
569 uint64_t lsb = 0;
570 uint64_t w = 0;
571
572 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD,
573 ACCESS_INT, cpu_mmu_index(env, false)) !=
574 TLBRET_MATCH) {
575 /* wrong base address */
576 return 0;
577 }
578 if (!get_pte(env, *vaddr, direntry_size, &entry)) {
579 return 0;
580 }
581
582 if ((entry & (1 << psn)) && hugepg) {
583 *huge_page = true;
584 *hgpg_directory_hit = true;
585 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
586 w = directory_index - 1;
587 if (directory_index & 0x1) {
588 /* Generate adjacent page from same PTE for odd TLB page */
589 lsb = (1 << w) >> 6;
590 *pw_entrylo0 = entry & ~lsb; /* even page */
591 *pw_entrylo1 = entry | lsb; /* odd page */
592 } else if (dph) {
593 int oddpagebit = 1 << leaf_shift;
594 uint64_t vaddr2 = *vaddr ^ oddpagebit;
595 if (*vaddr & oddpagebit) {
596 *pw_entrylo1 = entry;
597 } else {
598 *pw_entrylo0 = entry;
599 }
600 if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD,
601 ACCESS_INT, cpu_mmu_index(env, false)) !=
602 TLBRET_MATCH) {
603 return 0;
604 }
605 if (!get_pte(env, vaddr2, leafentry_size, &entry)) {
606 return 0;
607 }
608 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
609 if (*vaddr & oddpagebit) {
610 *pw_entrylo0 = entry;
611 } else {
612 *pw_entrylo1 = entry;
613 }
614 } else {
615 return 0;
616 }
617 return 1;
618 } else {
619 *vaddr = entry;
620 return 2;
621 }
622 }
623
624 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int rw,
625 int mmu_idx)
626 {
627 int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F;
628 int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F;
629 int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F;
630 int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F;
631 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
632
633 /* Initial values */
634 bool huge_page = false;
635 bool hgpg_bdhit = false;
636 bool hgpg_gdhit = false;
637 bool hgpg_udhit = false;
638 bool hgpg_mdhit = false;
639
640 int32_t pw_pagemask = 0;
641 target_ulong pw_entryhi = 0;
642 uint64_t pw_entrylo0 = 0;
643 uint64_t pw_entrylo1 = 0;
644
645 /* Native pointer size */
646 /*For the 32-bit architectures, this bit is fixed to 0.*/
647 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
648
649 /* Indices from PWField */
650 int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F;
651 int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F;
652 int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F;
653 int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F;
654 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
655
656 /* Indices computed from faulting address */
657 int gindex = (address >> pf_gdw) & ((1 << gdw) - 1);
658 int uindex = (address >> pf_udw) & ((1 << udw) - 1);
659 int mindex = (address >> pf_mdw) & ((1 << mdw) - 1);
660 int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1);
661
662 /* Other HTW configs */
663 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
664
665 /* HTW Shift values (depend on entry size) */
666 int directory_shift = (ptew > 1) ? -1 :
667 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
668 int leaf_shift = (ptew > 1) ? -1 :
669 (ptew == 1) ? native_shift + 1 : native_shift;
670
671 /* Offsets into tables */
672 int goffset = gindex << directory_shift;
673 int uoffset = uindex << directory_shift;
674 int moffset = mindex << directory_shift;
675 int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
676 int ptoffset1 = ptoffset0 | (1 << (leaf_shift));
677
678 uint32_t leafentry_size = 1 << (leaf_shift + 3);
679
680 /* Starting address - Page Table Base */
681 uint64_t vaddr = env->CP0_PWBase;
682
683 uint64_t dir_entry;
684 uint64_t paddr;
685 int prot;
686 int m;
687
688 if (!(env->CP0_Config3 & (1 << CP0C3_PW))) {
689 /* walker is unimplemented */
690 return false;
691 }
692 if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) {
693 /* walker is disabled */
694 return false;
695 }
696 if (!(gdw > 0 || udw > 0 || mdw > 0)) {
697 /* no structure to walk */
698 return false;
699 }
700 if ((directory_shift == -1) || (leaf_shift == -1)) {
701 return false;
702 }
703
704 /* Global Directory */
705 if (gdw > 0) {
706 vaddr |= goffset;
707 switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit,
708 &pw_entrylo0, &pw_entrylo1))
709 {
710 case 0:
711 return false;
712 case 1:
713 goto refill;
714 case 2:
715 default:
716 break;
717 }
718 }
719
720 /* Upper directory */
721 if (udw > 0) {
722 vaddr |= uoffset;
723 switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit,
724 &pw_entrylo0, &pw_entrylo1))
725 {
726 case 0:
727 return false;
728 case 1:
729 goto refill;
730 case 2:
731 default:
732 break;
733 }
734 }
735
736 /* Middle directory */
737 if (mdw > 0) {
738 vaddr |= moffset;
739 switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit,
740 &pw_entrylo0, &pw_entrylo1))
741 {
742 case 0:
743 return false;
744 case 1:
745 goto refill;
746 case 2:
747 default:
748 break;
749 }
750 }
751
752 /* Leaf Level Page Table - First half of PTE pair */
753 vaddr |= ptoffset0;
754 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
755 ACCESS_INT, cpu_mmu_index(env, false)) !=
756 TLBRET_MATCH) {
757 return false;
758 }
759 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
760 return false;
761 }
762 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
763 pw_entrylo0 = dir_entry;
764
765 /* Leaf Level Page Table - Second half of PTE pair */
766 vaddr |= ptoffset1;
767 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
768 ACCESS_INT, cpu_mmu_index(env, false)) !=
769 TLBRET_MATCH) {
770 return false;
771 }
772 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
773 return false;
774 }
775 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
776 pw_entrylo1 = dir_entry;
777
778 refill:
779
780 m = (1 << pf_ptw) - 1;
781
782 if (huge_page) {
783 switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 |
784 hgpg_mdhit)
785 {
786 case 4:
787 m = (1 << pf_gdw) - 1;
788 if (pf_gdw & 1) {
789 m >>= 1;
790 }
791 break;
792 case 2:
793 m = (1 << pf_udw) - 1;
794 if (pf_udw & 1) {
795 m >>= 1;
796 }
797 break;
798 case 1:
799 m = (1 << pf_mdw) - 1;
800 if (pf_mdw & 1) {
801 m >>= 1;
802 }
803 break;
804 }
805 }
806 pw_pagemask = m >> TARGET_PAGE_BITS_MIN;
807 update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask);
808 pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
809 {
810 target_ulong tmp_entryhi = env->CP0_EntryHi;
811 int32_t tmp_pagemask = env->CP0_PageMask;
812 uint64_t tmp_entrylo0 = env->CP0_EntryLo0;
813 uint64_t tmp_entrylo1 = env->CP0_EntryLo1;
814
815 env->CP0_EntryHi = pw_entryhi;
816 env->CP0_PageMask = pw_pagemask;
817 env->CP0_EntryLo0 = pw_entrylo0;
818 env->CP0_EntryLo1 = pw_entrylo1;
819
820 /*
821 * The hardware page walker inserts a page into the TLB in a manner
822 * identical to a TLBWR instruction as executed by the software refill
823 * handler.
824 */
825 r4k_helper_tlbwr(env);
826
827 env->CP0_EntryHi = tmp_entryhi;
828 env->CP0_PageMask = tmp_pagemask;
829 env->CP0_EntryLo0 = tmp_entrylo0;
830 env->CP0_EntryLo1 = tmp_entrylo1;
831 }
832 return true;
833 }
834 #endif
835 #endif /* !CONFIG_USER_ONLY */
836
837 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
838 MMUAccessType access_type, int mmu_idx,
839 bool probe, uintptr_t retaddr)
840 {
841 MIPSCPU *cpu = MIPS_CPU(cs);
842 CPUMIPSState *env = &cpu->env;
843 #if !defined(CONFIG_USER_ONLY)
844 hwaddr physical;
845 int prot;
846 int mips_access_type;
847 #endif
848 int ret = TLBRET_BADADDR;
849
850 /* data access */
851 #if !defined(CONFIG_USER_ONLY)
852 /* XXX: put correct access by using cpu_restore_state() correctly */
853 mips_access_type = ACCESS_INT;
854 ret = get_physical_address(env, &physical, &prot, address,
855 access_type, mips_access_type, mmu_idx);
856 switch (ret) {
857 case TLBRET_MATCH:
858 qemu_log_mask(CPU_LOG_MMU,
859 "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
860 " prot %d\n", __func__, address, physical, prot);
861 break;
862 default:
863 qemu_log_mask(CPU_LOG_MMU,
864 "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
865 ret);
866 break;
867 }
868 if (ret == TLBRET_MATCH) {
869 tlb_set_page(cs, address & TARGET_PAGE_MASK,
870 physical & TARGET_PAGE_MASK, prot,
871 mmu_idx, TARGET_PAGE_SIZE);
872 return true;
873 }
874 #if !defined(TARGET_MIPS64)
875 if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
876 /*
877 * Memory reads during hardware page table walking are performed
878 * as if they were kernel-mode load instructions.
879 */
880 int mode = (env->hflags & MIPS_HFLAG_KSU);
881 bool ret_walker;
882 env->hflags &= ~MIPS_HFLAG_KSU;
883 ret_walker = page_table_walk_refill(env, address, access_type, mmu_idx);
884 env->hflags |= mode;
885 if (ret_walker) {
886 ret = get_physical_address(env, &physical, &prot, address,
887 access_type, mips_access_type, mmu_idx);
888 if (ret == TLBRET_MATCH) {
889 tlb_set_page(cs, address & TARGET_PAGE_MASK,
890 physical & TARGET_PAGE_MASK, prot,
891 mmu_idx, TARGET_PAGE_SIZE);
892 return true;
893 }
894 }
895 }
896 #endif
897 if (probe) {
898 return false;
899 }
900 #endif
901
902 raise_mmu_exception(env, address, access_type, ret);
903 do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
904 }
905
906 #ifndef CONFIG_USER_ONLY
907 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
908 int rw)
909 {
910 hwaddr physical;
911 int prot;
912 int access_type;
913 int ret = 0;
914
915 /* data access */
916 access_type = ACCESS_INT;
917 ret = get_physical_address(env, &physical, &prot, address, rw, access_type,
918 cpu_mmu_index(env, false));
919 if (ret != TLBRET_MATCH) {
920 raise_mmu_exception(env, address, rw, ret);
921 return -1LL;
922 } else {
923 return physical;
924 }
925 }
926
927 static void set_hflags_for_handler(CPUMIPSState *env)
928 {
929 /* Exception handlers are entered in 32-bit mode. */
930 env->hflags &= ~(MIPS_HFLAG_M16);
931 /* ...except that microMIPS lets you choose. */
932 if (env->insn_flags & ASE_MICROMIPS) {
933 env->hflags |= (!!(env->CP0_Config3 &
934 (1 << CP0C3_ISA_ON_EXC))
935 << MIPS_HFLAG_M16_SHIFT);
936 }
937 }
938
939 static inline void set_badinstr_registers(CPUMIPSState *env)
940 {
941 if (env->insn_flags & ISA_NANOMIPS32) {
942 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
943 uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
944 if ((instr & 0x10000000) == 0) {
945 instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
946 }
947 env->CP0_BadInstr = instr;
948
949 if ((instr & 0xFC000000) == 0x60000000) {
950 instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
951 env->CP0_BadInstrX = instr;
952 }
953 }
954 return;
955 }
956
957 if (env->hflags & MIPS_HFLAG_M16) {
958 /* TODO: add BadInstr support for microMIPS */
959 return;
960 }
961 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
962 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
963 }
964 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
965 (env->hflags & MIPS_HFLAG_BMASK)) {
966 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
967 }
968 }
969
970 #endif /* !CONFIG_USER_ONLY */
971
972 void mips_cpu_do_interrupt(CPUState *cs)
973 {
974 #if !defined(CONFIG_USER_ONLY)
975 MIPSCPU *cpu = MIPS_CPU(cs);
976 CPUMIPSState *env = &cpu->env;
977 bool update_badinstr = 0;
978 target_ulong offset;
979 int cause = -1;
980
981 if (qemu_loglevel_mask(CPU_LOG_INT)
982 && cs->exception_index != EXCP_EXT_INTERRUPT) {
983 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
984 " %s exception\n",
985 __func__, env->active_tc.PC, env->CP0_EPC,
986 mips_exception_name(cs->exception_index));
987 }
988 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
989 (env->hflags & MIPS_HFLAG_DM)) {
990 cs->exception_index = EXCP_DINT;
991 }
992 offset = 0x180;
993 switch (cs->exception_index) {
994 case EXCP_DSS:
995 env->CP0_Debug |= 1 << CP0DB_DSS;
996 /*
997 * Debug single step cannot be raised inside a delay slot and
998 * resume will always occur on the next instruction
999 * (but we assume the pc has always been updated during
1000 * code translation).
1001 */
1002 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
1003 goto enter_debug_mode;
1004 case EXCP_DINT:
1005 env->CP0_Debug |= 1 << CP0DB_DINT;
1006 goto set_DEPC;
1007 case EXCP_DIB:
1008 env->CP0_Debug |= 1 << CP0DB_DIB;
1009 goto set_DEPC;
1010 case EXCP_DBp:
1011 env->CP0_Debug |= 1 << CP0DB_DBp;
1012 /* Setup DExcCode - SDBBP instruction */
1013 env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |
1014 (9 << CP0DB_DEC);
1015 goto set_DEPC;
1016 case EXCP_DDBS:
1017 env->CP0_Debug |= 1 << CP0DB_DDBS;
1018 goto set_DEPC;
1019 case EXCP_DDBL:
1020 env->CP0_Debug |= 1 << CP0DB_DDBL;
1021 set_DEPC:
1022 env->CP0_DEPC = exception_resume_pc(env);
1023 env->hflags &= ~MIPS_HFLAG_BMASK;
1024 enter_debug_mode:
1025 if (env->insn_flags & ISA_MIPS3) {
1026 env->hflags |= MIPS_HFLAG_64;
1027 if (!(env->insn_flags & ISA_MIPS_R6) ||
1028 env->CP0_Status & (1 << CP0St_KX)) {
1029 env->hflags &= ~MIPS_HFLAG_AWRAP;
1030 }
1031 }
1032 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
1033 env->hflags &= ~(MIPS_HFLAG_KSU);
1034 /* EJTAG probe trap enable is not implemented... */
1035 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1036 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1037 }
1038 env->active_tc.PC = env->exception_base + 0x480;
1039 set_hflags_for_handler(env);
1040 break;
1041 case EXCP_RESET:
1042 cpu_reset(CPU(cpu));
1043 break;
1044 case EXCP_SRESET:
1045 env->CP0_Status |= (1 << CP0St_SR);
1046 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
1047 goto set_error_EPC;
1048 case EXCP_NMI:
1049 env->CP0_Status |= (1 << CP0St_NMI);
1050 set_error_EPC:
1051 env->CP0_ErrorEPC = exception_resume_pc(env);
1052 env->hflags &= ~MIPS_HFLAG_BMASK;
1053 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
1054 if (env->insn_flags & ISA_MIPS3) {
1055 env->hflags |= MIPS_HFLAG_64;
1056 if (!(env->insn_flags & ISA_MIPS_R6) ||
1057 env->CP0_Status & (1 << CP0St_KX)) {
1058 env->hflags &= ~MIPS_HFLAG_AWRAP;
1059 }
1060 }
1061 env->hflags |= MIPS_HFLAG_CP0;
1062 env->hflags &= ~(MIPS_HFLAG_KSU);
1063 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1064 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1065 }
1066 env->active_tc.PC = env->exception_base;
1067 set_hflags_for_handler(env);
1068 break;
1069 case EXCP_EXT_INTERRUPT:
1070 cause = 0;
1071 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
1072 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
1073
1074 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
1075 offset = 0x200;
1076 } else {
1077 uint32_t vector = 0;
1078 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
1079
1080 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
1081 /*
1082 * For VEIC mode, the external interrupt controller feeds
1083 * the vector through the CP0Cause IP lines.
1084 */
1085 vector = pending;
1086 } else {
1087 /*
1088 * Vectored Interrupts
1089 * Mask with Status.IM7-IM0 to get enabled interrupts.
1090 */
1091 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
1092 /* Find the highest-priority interrupt. */
1093 while (pending >>= 1) {
1094 vector++;
1095 }
1096 }
1097 offset = 0x200 + (vector * (spacing << 5));
1098 }
1099 }
1100 goto set_EPC;
1101 case EXCP_LTLBL:
1102 cause = 1;
1103 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1104 goto set_EPC;
1105 case EXCP_TLBL:
1106 cause = 2;
1107 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1108 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1109 !(env->CP0_Status & (1 << CP0St_EXL))) {
1110 #if defined(TARGET_MIPS64)
1111 int R = env->CP0_BadVAddr >> 62;
1112 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1113 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1114
1115 if ((R != 0 || UX) && (R != 3 || KX) &&
1116 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1117 offset = 0x080;
1118 } else {
1119 #endif
1120 offset = 0x000;
1121 #if defined(TARGET_MIPS64)
1122 }
1123 #endif
1124 }
1125 goto set_EPC;
1126 case EXCP_TLBS:
1127 cause = 3;
1128 update_badinstr = 1;
1129 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1130 !(env->CP0_Status & (1 << CP0St_EXL))) {
1131 #if defined(TARGET_MIPS64)
1132 int R = env->CP0_BadVAddr >> 62;
1133 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1134 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1135
1136 if ((R != 0 || UX) && (R != 3 || KX) &&
1137 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1138 offset = 0x080;
1139 } else {
1140 #endif
1141 offset = 0x000;
1142 #if defined(TARGET_MIPS64)
1143 }
1144 #endif
1145 }
1146 goto set_EPC;
1147 case EXCP_AdEL:
1148 cause = 4;
1149 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1150 goto set_EPC;
1151 case EXCP_AdES:
1152 cause = 5;
1153 update_badinstr = 1;
1154 goto set_EPC;
1155 case EXCP_IBE:
1156 cause = 6;
1157 goto set_EPC;
1158 case EXCP_DBE:
1159 cause = 7;
1160 goto set_EPC;
1161 case EXCP_SYSCALL:
1162 cause = 8;
1163 update_badinstr = 1;
1164 goto set_EPC;
1165 case EXCP_BREAK:
1166 cause = 9;
1167 update_badinstr = 1;
1168 goto set_EPC;
1169 case EXCP_RI:
1170 cause = 10;
1171 update_badinstr = 1;
1172 goto set_EPC;
1173 case EXCP_CpU:
1174 cause = 11;
1175 update_badinstr = 1;
1176 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
1177 (env->error_code << CP0Ca_CE);
1178 goto set_EPC;
1179 case EXCP_OVERFLOW:
1180 cause = 12;
1181 update_badinstr = 1;
1182 goto set_EPC;
1183 case EXCP_TRAP:
1184 cause = 13;
1185 update_badinstr = 1;
1186 goto set_EPC;
1187 case EXCP_MSAFPE:
1188 cause = 14;
1189 update_badinstr = 1;
1190 goto set_EPC;
1191 case EXCP_FPE:
1192 cause = 15;
1193 update_badinstr = 1;
1194 goto set_EPC;
1195 case EXCP_C2E:
1196 cause = 18;
1197 goto set_EPC;
1198 case EXCP_TLBRI:
1199 cause = 19;
1200 update_badinstr = 1;
1201 goto set_EPC;
1202 case EXCP_TLBXI:
1203 cause = 20;
1204 goto set_EPC;
1205 case EXCP_MSADIS:
1206 cause = 21;
1207 update_badinstr = 1;
1208 goto set_EPC;
1209 case EXCP_MDMX:
1210 cause = 22;
1211 goto set_EPC;
1212 case EXCP_DWATCH:
1213 cause = 23;
1214 /* XXX: TODO: manage deferred watch exceptions */
1215 goto set_EPC;
1216 case EXCP_MCHECK:
1217 cause = 24;
1218 goto set_EPC;
1219 case EXCP_THREAD:
1220 cause = 25;
1221 goto set_EPC;
1222 case EXCP_DSPDIS:
1223 cause = 26;
1224 goto set_EPC;
1225 case EXCP_CACHE:
1226 cause = 30;
1227 offset = 0x100;
1228 set_EPC:
1229 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1230 env->CP0_EPC = exception_resume_pc(env);
1231 if (update_badinstr) {
1232 set_badinstr_registers(env);
1233 }
1234 if (env->hflags & MIPS_HFLAG_BMASK) {
1235 env->CP0_Cause |= (1U << CP0Ca_BD);
1236 } else {
1237 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1238 }
1239 env->CP0_Status |= (1 << CP0St_EXL);
1240 if (env->insn_flags & ISA_MIPS3) {
1241 env->hflags |= MIPS_HFLAG_64;
1242 if (!(env->insn_flags & ISA_MIPS_R6) ||
1243 env->CP0_Status & (1 << CP0St_KX)) {
1244 env->hflags &= ~MIPS_HFLAG_AWRAP;
1245 }
1246 }
1247 env->hflags |= MIPS_HFLAG_CP0;
1248 env->hflags &= ~(MIPS_HFLAG_KSU);
1249 }
1250 env->hflags &= ~MIPS_HFLAG_BMASK;
1251 if (env->CP0_Status & (1 << CP0St_BEV)) {
1252 env->active_tc.PC = env->exception_base + 0x200;
1253 } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
1254 env->CP0_Config5 & (1 << CP0C5_CV))) {
1255 /* Force KSeg1 for cache errors */
1256 env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
1257 } else {
1258 env->active_tc.PC = env->CP0_EBase & ~0xfff;
1259 }
1260
1261 env->active_tc.PC += offset;
1262 set_hflags_for_handler(env);
1263 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |
1264 (cause << CP0Ca_EC);
1265 break;
1266 default:
1267 abort();
1268 }
1269 if (qemu_loglevel_mask(CPU_LOG_INT)
1270 && cs->exception_index != EXCP_EXT_INTERRUPT) {
1271 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
1272 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
1273 __func__, env->active_tc.PC, env->CP0_EPC, cause,
1274 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
1275 env->CP0_DEPC);
1276 }
1277 #endif
1278 cs->exception_index = EXCP_NONE;
1279 }
1280
1281 #if !defined(CONFIG_USER_ONLY)
1282 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
1283 {
1284 CPUState *cs = env_cpu(env);
1285 r4k_tlb_t *tlb;
1286 target_ulong addr;
1287 target_ulong end;
1288 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
1289 uint32_t MMID = env->CP0_MemoryMapID;
1290 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
1291 uint32_t tlb_mmid;
1292 target_ulong mask;
1293
1294 MMID = mi ? MMID : (uint32_t) ASID;
1295
1296 tlb = &env->tlb->mmu.r4k.tlb[idx];
1297 /*
1298 * The qemu TLB is flushed when the ASID/MMID changes, so no need to
1299 * flush these entries again.
1300 */
1301 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
1302 if (tlb->G == 0 && tlb_mmid != MMID) {
1303 return;
1304 }
1305
1306 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
1307 /*
1308 * For tlbwr, we can shadow the discarded entry into
1309 * a new (fake) TLB entry, as long as the guest can not
1310 * tell that it's there.
1311 */
1312 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
1313 env->tlb->tlb_in_use++;
1314 return;
1315 }
1316
1317 /* 1k pages are not supported. */
1318 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1319 if (tlb->V0) {
1320 addr = tlb->VPN & ~mask;
1321 #if defined(TARGET_MIPS64)
1322 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1323 addr |= 0x3FFFFF0000000000ULL;
1324 }
1325 #endif
1326 end = addr | (mask >> 1);
1327 while (addr < end) {
1328 tlb_flush_page(cs, addr);
1329 addr += TARGET_PAGE_SIZE;
1330 }
1331 }
1332 if (tlb->V1) {
1333 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
1334 #if defined(TARGET_MIPS64)
1335 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1336 addr |= 0x3FFFFF0000000000ULL;
1337 }
1338 #endif
1339 end = addr | mask;
1340 while (addr - 1 < end) {
1341 tlb_flush_page(cs, addr);
1342 addr += TARGET_PAGE_SIZE;
1343 }
1344 }
1345 }
1346 #endif /* !CONFIG_USER_ONLY */
AR7 emulation for QEMU