4 * Copyright (c) 2008 Shin-ichiro KAWASAKI
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/cutils.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
31 #include "hw/char/serial.h"
32 #include "ui/console.h"
33 #include "hw/devices.h"
34 #include "hw/sysbus.h"
35 #include "hw/pci/pci.h"
36 #include "qemu/range.h"
37 #include "ui/pixel_ops.h"
38 #include "exec/address-spaces.h"
42 * - Minimum implementation for Linux console : mmio regs and CRT layer.
43 * - 2D graphics acceleration partially supported : only fill rectangle.
47 * - Touch panel support
50 * - More 2D graphics engine support
51 * - Performance tuning
54 /*#define DEBUG_SM501*/
55 /*#define DEBUG_BITBLT*/
58 #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
60 #define SM501_DPRINTF(fmt, ...) do {} while (0)
63 #define MMIO_BASE_OFFSET 0x3e00000
64 #define MMIO_SIZE 0x200000
66 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
68 /* System Configuration area */
69 /* System config base */
70 #define SM501_SYS_CONFIG (0x000000)
73 #define SM501_SYSTEM_CONTROL (0x000000)
75 #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0)
76 #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1)
77 #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2)
79 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4)
80 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4)
81 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4)
82 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4)
83 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4)
85 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6)
86 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7)
87 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11)
88 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15)
90 /* miscellaneous control */
92 #define SM501_MISC_CONTROL (0x000004)
94 #define SM501_MISC_BUS_SH (0x0)
95 #define SM501_MISC_BUS_PCI (0x1)
96 #define SM501_MISC_BUS_XSCALE (0x2)
97 #define SM501_MISC_BUS_NEC (0x6)
98 #define SM501_MISC_BUS_MASK (0x7)
100 #define SM501_MISC_VR_62MB (1 << 3)
101 #define SM501_MISC_CDR_RESET (1 << 7)
102 #define SM501_MISC_USB_LB (1 << 8)
103 #define SM501_MISC_USB_SLAVE (1 << 9)
104 #define SM501_MISC_BL_1 (1 << 10)
105 #define SM501_MISC_MC (1 << 11)
106 #define SM501_MISC_DAC_POWER (1 << 12)
107 #define SM501_MISC_IRQ_INVERT (1 << 16)
108 #define SM501_MISC_SH (1 << 17)
110 #define SM501_MISC_HOLD_EMPTY (0 << 18)
111 #define SM501_MISC_HOLD_8 (1 << 18)
112 #define SM501_MISC_HOLD_16 (2 << 18)
113 #define SM501_MISC_HOLD_24 (3 << 18)
114 #define SM501_MISC_HOLD_32 (4 << 18)
115 #define SM501_MISC_HOLD_MASK (7 << 18)
117 #define SM501_MISC_FREQ_12 (1 << 24)
118 #define SM501_MISC_PNL_24BIT (1 << 25)
119 #define SM501_MISC_8051_LE (1 << 26)
123 #define SM501_GPIO31_0_CONTROL (0x000008)
124 #define SM501_GPIO63_32_CONTROL (0x00000C)
125 #define SM501_DRAM_CONTROL (0x000010)
128 #define SM501_ARBTRTN_CONTROL (0x000014)
131 #define SM501_COMMAND_LIST_STATUS (0x000024)
133 /* interrupt debug */
134 #define SM501_RAW_IRQ_STATUS (0x000028)
135 #define SM501_RAW_IRQ_CLEAR (0x000028)
136 #define SM501_IRQ_STATUS (0x00002C)
137 #define SM501_IRQ_MASK (0x000030)
138 #define SM501_DEBUG_CONTROL (0x000034)
140 /* power management */
141 #define SM501_POWERMODE_P2X_SRC (1 << 29)
142 #define SM501_POWERMODE_V2X_SRC (1 << 20)
143 #define SM501_POWERMODE_M_SRC (1 << 12)
144 #define SM501_POWERMODE_M1_SRC (1 << 4)
146 #define SM501_CURRENT_GATE (0x000038)
147 #define SM501_CURRENT_CLOCK (0x00003C)
148 #define SM501_POWER_MODE_0_GATE (0x000040)
149 #define SM501_POWER_MODE_0_CLOCK (0x000044)
150 #define SM501_POWER_MODE_1_GATE (0x000048)
151 #define SM501_POWER_MODE_1_CLOCK (0x00004C)
152 #define SM501_SLEEP_MODE_GATE (0x000050)
153 #define SM501_POWER_MODE_CONTROL (0x000054)
155 /* power gates for units within the 501 */
156 #define SM501_GATE_HOST (0)
157 #define SM501_GATE_MEMORY (1)
158 #define SM501_GATE_DISPLAY (2)
159 #define SM501_GATE_2D_ENGINE (3)
160 #define SM501_GATE_CSC (4)
161 #define SM501_GATE_ZVPORT (5)
162 #define SM501_GATE_GPIO (6)
163 #define SM501_GATE_UART0 (7)
164 #define SM501_GATE_UART1 (8)
165 #define SM501_GATE_SSP (10)
166 #define SM501_GATE_USB_HOST (11)
167 #define SM501_GATE_USB_GADGET (12)
168 #define SM501_GATE_UCONTROLLER (17)
169 #define SM501_GATE_AC97 (18)
172 #define SM501_CLOCK_P2XCLK (24)
174 #define SM501_CLOCK_V2XCLK (16)
176 #define SM501_CLOCK_MCLK (8)
177 /* SDRAM controller clock */
178 #define SM501_CLOCK_M1XCLK (0)
181 #define SM501_PCI_MASTER_BASE (0x000058)
182 #define SM501_ENDIAN_CONTROL (0x00005C)
183 #define SM501_DEVICEID (0x000060)
186 #define SM501_DEVICEID_SM501 (0x05010000)
187 #define SM501_DEVICEID_IDMASK (0xffff0000)
188 #define SM501_DEVICEID_REVMASK (0x000000ff)
190 #define SM501_PLLCLOCK_COUNT (0x000064)
191 #define SM501_MISC_TIMING (0x000068)
192 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
194 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
197 #define SM501_GPIO (0x010000)
198 #define SM501_GPIO_DATA_LOW (0x00)
199 #define SM501_GPIO_DATA_HIGH (0x04)
200 #define SM501_GPIO_DDR_LOW (0x08)
201 #define SM501_GPIO_DDR_HIGH (0x0C)
202 #define SM501_GPIO_IRQ_SETUP (0x10)
203 #define SM501_GPIO_IRQ_STATUS (0x14)
204 #define SM501_GPIO_IRQ_RESET (0x14)
206 /* I2C controller base */
207 #define SM501_I2C (0x010040)
208 #define SM501_I2C_BYTE_COUNT (0x00)
209 #define SM501_I2C_CONTROL (0x01)
210 #define SM501_I2C_STATUS (0x02)
211 #define SM501_I2C_RESET (0x02)
212 #define SM501_I2C_SLAVE_ADDRESS (0x03)
213 #define SM501_I2C_DATA (0x04)
216 #define SM501_SSP (0x020000)
219 #define SM501_UART0 (0x030000)
222 #define SM501_UART1 (0x030020)
224 /* USB host port base */
225 #define SM501_USB_HOST (0x040000)
227 /* USB slave/gadget base */
228 #define SM501_USB_GADGET (0x060000)
230 /* USB slave/gadget data port base */
231 #define SM501_USB_GADGET_DATA (0x070000)
233 /* Display controller/video engine base */
234 #define SM501_DC (0x080000)
236 /* common defines for the SM501 address registers */
237 #define SM501_ADDR_FLIP (1 << 31)
238 #define SM501_ADDR_EXT (1 << 27)
239 #define SM501_ADDR_CS1 (1 << 26)
240 #define SM501_ADDR_MASK (0x3f << 26)
242 #define SM501_FIFO_MASK (0x3 << 16)
243 #define SM501_FIFO_1 (0x0 << 16)
244 #define SM501_FIFO_3 (0x1 << 16)
245 #define SM501_FIFO_7 (0x2 << 16)
246 #define SM501_FIFO_11 (0x3 << 16)
248 /* common registers for panel and the crt */
249 #define SM501_OFF_DC_H_TOT (0x000)
250 #define SM501_OFF_DC_V_TOT (0x008)
251 #define SM501_OFF_DC_H_SYNC (0x004)
252 #define SM501_OFF_DC_V_SYNC (0x00C)
254 #define SM501_DC_PANEL_CONTROL (0x000)
256 #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27)
257 #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26)
258 #define SM501_DC_PANEL_CONTROL_DATA (1 << 25)
259 #define SM501_DC_PANEL_CONTROL_VDD (1 << 24)
260 #define SM501_DC_PANEL_CONTROL_DP (1 << 23)
262 #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21)
263 #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21)
264 #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21)
266 #define SM501_DC_PANEL_CONTROL_DE (1 << 20)
268 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18)
269 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18)
270 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18)
272 #define SM501_DC_PANEL_CONTROL_CP (1 << 14)
273 #define SM501_DC_PANEL_CONTROL_VSP (1 << 13)
274 #define SM501_DC_PANEL_CONTROL_HSP (1 << 12)
275 #define SM501_DC_PANEL_CONTROL_CK (1 << 9)
276 #define SM501_DC_PANEL_CONTROL_TE (1 << 8)
277 #define SM501_DC_PANEL_CONTROL_VPD (1 << 7)
278 #define SM501_DC_PANEL_CONTROL_VP (1 << 6)
279 #define SM501_DC_PANEL_CONTROL_HPD (1 << 5)
280 #define SM501_DC_PANEL_CONTROL_HP (1 << 4)
281 #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3)
282 #define SM501_DC_PANEL_CONTROL_EN (1 << 2)
284 #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0)
285 #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0)
286 #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0)
289 #define SM501_DC_PANEL_PANNING_CONTROL (0x004)
290 #define SM501_DC_PANEL_COLOR_KEY (0x008)
291 #define SM501_DC_PANEL_FB_ADDR (0x00C)
292 #define SM501_DC_PANEL_FB_OFFSET (0x010)
293 #define SM501_DC_PANEL_FB_WIDTH (0x014)
294 #define SM501_DC_PANEL_FB_HEIGHT (0x018)
295 #define SM501_DC_PANEL_TL_LOC (0x01C)
296 #define SM501_DC_PANEL_BR_LOC (0x020)
297 #define SM501_DC_PANEL_H_TOT (0x024)
298 #define SM501_DC_PANEL_H_SYNC (0x028)
299 #define SM501_DC_PANEL_V_TOT (0x02C)
300 #define SM501_DC_PANEL_V_SYNC (0x030)
301 #define SM501_DC_PANEL_CUR_LINE (0x034)
303 #define SM501_DC_VIDEO_CONTROL (0x040)
304 #define SM501_DC_VIDEO_FB0_ADDR (0x044)
305 #define SM501_DC_VIDEO_FB_WIDTH (0x048)
306 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
307 #define SM501_DC_VIDEO_TL_LOC (0x050)
308 #define SM501_DC_VIDEO_BR_LOC (0x054)
309 #define SM501_DC_VIDEO_SCALE (0x058)
310 #define SM501_DC_VIDEO_INIT_SCALE (0x05C)
311 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
312 #define SM501_DC_VIDEO_FB1_ADDR (0x064)
313 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
315 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
316 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
317 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
318 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
319 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
320 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
321 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
322 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
323 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
324 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
326 #define SM501_DC_PANEL_HWC_BASE (0x0F0)
327 #define SM501_DC_PANEL_HWC_ADDR (0x0F0)
328 #define SM501_DC_PANEL_HWC_LOC (0x0F4)
329 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
330 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
332 #define SM501_HWC_EN (1 << 31)
334 #define SM501_OFF_HWC_ADDR (0x00)
335 #define SM501_OFF_HWC_LOC (0x04)
336 #define SM501_OFF_HWC_COLOR_1_2 (0x08)
337 #define SM501_OFF_HWC_COLOR_3 (0x0C)
339 #define SM501_DC_ALPHA_CONTROL (0x100)
340 #define SM501_DC_ALPHA_FB_ADDR (0x104)
341 #define SM501_DC_ALPHA_FB_OFFSET (0x108)
342 #define SM501_DC_ALPHA_TL_LOC (0x10C)
343 #define SM501_DC_ALPHA_BR_LOC (0x110)
344 #define SM501_DC_ALPHA_CHROMA_KEY (0x114)
345 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
347 #define SM501_DC_CRT_CONTROL (0x200)
349 #define SM501_DC_CRT_CONTROL_TVP (1 << 15)
350 #define SM501_DC_CRT_CONTROL_CP (1 << 14)
351 #define SM501_DC_CRT_CONTROL_VSP (1 << 13)
352 #define SM501_DC_CRT_CONTROL_HSP (1 << 12)
353 #define SM501_DC_CRT_CONTROL_VS (1 << 11)
354 #define SM501_DC_CRT_CONTROL_BLANK (1 << 10)
355 #define SM501_DC_CRT_CONTROL_SEL (1 << 9)
356 #define SM501_DC_CRT_CONTROL_TE (1 << 8)
357 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
358 #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3)
359 #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2)
361 #define SM501_DC_CRT_CONTROL_8BPP (0 << 0)
362 #define SM501_DC_CRT_CONTROL_16BPP (1 << 0)
363 #define SM501_DC_CRT_CONTROL_32BPP (2 << 0)
365 #define SM501_DC_CRT_FB_ADDR (0x204)
366 #define SM501_DC_CRT_FB_OFFSET (0x208)
367 #define SM501_DC_CRT_H_TOT (0x20C)
368 #define SM501_DC_CRT_H_SYNC (0x210)
369 #define SM501_DC_CRT_V_TOT (0x214)
370 #define SM501_DC_CRT_V_SYNC (0x218)
371 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
372 #define SM501_DC_CRT_CUR_LINE (0x220)
373 #define SM501_DC_CRT_MONITOR_DETECT (0x224)
375 #define SM501_DC_CRT_HWC_BASE (0x230)
376 #define SM501_DC_CRT_HWC_ADDR (0x230)
377 #define SM501_DC_CRT_HWC_LOC (0x234)
378 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
379 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
381 #define SM501_DC_PANEL_PALETTE (0x400)
383 #define SM501_DC_VIDEO_PALETTE (0x800)
385 #define SM501_DC_CRT_PALETTE (0xC00)
387 /* Zoom Video port base */
388 #define SM501_ZVPORT (0x090000)
391 #define SM501_AC97 (0x0A0000)
393 /* 8051 micro controller base */
394 #define SM501_UCONTROLLER (0x0B0000)
396 /* 8051 micro controller SRAM base */
397 #define SM501_UCONTROLLER_SRAM (0x0C0000)
400 #define SM501_DMA (0x0D0000)
403 #define SM501_2D_ENGINE (0x100000)
404 #define SM501_2D_SOURCE (0x00)
405 #define SM501_2D_DESTINATION (0x04)
406 #define SM501_2D_DIMENSION (0x08)
407 #define SM501_2D_CONTROL (0x0C)
408 #define SM501_2D_PITCH (0x10)
409 #define SM501_2D_FOREGROUND (0x14)
410 #define SM501_2D_BACKGROUND (0x18)
411 #define SM501_2D_STRETCH (0x1C)
412 #define SM501_2D_COLOR_COMPARE (0x20)
413 #define SM501_2D_COLOR_COMPARE_MASK (0x24)
414 #define SM501_2D_MASK (0x28)
415 #define SM501_2D_CLIP_TL (0x2C)
416 #define SM501_2D_CLIP_BR (0x30)
417 #define SM501_2D_MONO_PATTERN_LOW (0x34)
418 #define SM501_2D_MONO_PATTERN_HIGH (0x38)
419 #define SM501_2D_WINDOW_WIDTH (0x3C)
420 #define SM501_2D_SOURCE_BASE (0x40)
421 #define SM501_2D_DESTINATION_BASE (0x44)
422 #define SM501_2D_ALPHA (0x48)
423 #define SM501_2D_WRAP (0x4C)
424 #define SM501_2D_STATUS (0x50)
426 #define SM501_CSC_Y_SOURCE_BASE (0xC8)
427 #define SM501_CSC_CONSTANTS (0xCC)
428 #define SM501_CSC_Y_SOURCE_X (0xD0)
429 #define SM501_CSC_Y_SOURCE_Y (0xD4)
430 #define SM501_CSC_U_SOURCE_BASE (0xD8)
431 #define SM501_CSC_V_SOURCE_BASE (0xDC)
432 #define SM501_CSC_SOURCE_DIMENSION (0xE0)
433 #define SM501_CSC_SOURCE_PITCH (0xE4)
434 #define SM501_CSC_DESTINATION (0xE8)
435 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
436 #define SM501_CSC_DESTINATION_PITCH (0xF0)
437 #define SM501_CSC_SCALE_FACTOR (0xF4)
438 #define SM501_CSC_DESTINATION_BASE (0xF8)
439 #define SM501_CSC_CONTROL (0xFC)
441 /* 2d engine data port base */
442 #define SM501_2D_ENGINE_DATA (0x110000)
444 /* end of register definitions */
446 #define SM501_HWC_WIDTH (64)
447 #define SM501_HWC_HEIGHT (64)
449 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
450 static const uint32_t sm501_mem_local_size
[] = {
458 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
460 typedef struct SM501State
{
461 /* graphic console status */
464 /* status & internal resources */
465 uint32_t local_mem_size_index
;
467 MemoryRegion local_mem_region
;
468 MemoryRegion mmio_region
;
469 MemoryRegion system_config_region
;
470 MemoryRegion disp_ctrl_region
;
471 MemoryRegion twoD_engine_region
;
473 uint32_t last_height
;
476 uint32_t system_control
;
477 uint32_t misc_control
;
478 uint32_t gpio_31_0_control
;
479 uint32_t gpio_63_32_control
;
480 uint32_t dram_control
;
481 uint32_t arbitration_control
;
483 uint32_t misc_timing
;
484 uint32_t power_mode_control
;
491 uint8_t dc_palette
[0x400 * 3];
493 uint32_t dc_panel_control
;
494 uint32_t dc_panel_panning_control
;
495 uint32_t dc_panel_fb_addr
;
496 uint32_t dc_panel_fb_offset
;
497 uint32_t dc_panel_fb_width
;
498 uint32_t dc_panel_fb_height
;
499 uint32_t dc_panel_tl_location
;
500 uint32_t dc_panel_br_location
;
501 uint32_t dc_panel_h_total
;
502 uint32_t dc_panel_h_sync
;
503 uint32_t dc_panel_v_total
;
504 uint32_t dc_panel_v_sync
;
506 uint32_t dc_panel_hwc_addr
;
507 uint32_t dc_panel_hwc_location
;
508 uint32_t dc_panel_hwc_color_1_2
;
509 uint32_t dc_panel_hwc_color_3
;
511 uint32_t dc_crt_control
;
512 uint32_t dc_crt_fb_addr
;
513 uint32_t dc_crt_fb_offset
;
514 uint32_t dc_crt_h_total
;
515 uint32_t dc_crt_h_sync
;
516 uint32_t dc_crt_v_total
;
517 uint32_t dc_crt_v_sync
;
519 uint32_t dc_crt_hwc_addr
;
520 uint32_t dc_crt_hwc_location
;
521 uint32_t dc_crt_hwc_color_1_2
;
522 uint32_t dc_crt_hwc_color_3
;
524 uint32_t twoD_source
;
525 uint32_t twoD_destination
;
526 uint32_t twoD_dimension
;
527 uint32_t twoD_control
;
529 uint32_t twoD_foreground
;
530 uint32_t twoD_stretch
;
531 uint32_t twoD_color_compare_mask
;
533 uint32_t twoD_window_width
;
534 uint32_t twoD_source_base
;
535 uint32_t twoD_destination_base
;
539 static uint32_t get_local_mem_size_index(uint32_t size
)
541 uint32_t norm_size
= 0;
544 for (i
= 0; i
< ARRAY_SIZE(sm501_mem_local_size
); i
++) {
545 uint32_t new_size
= sm501_mem_local_size
[i
];
546 if (new_size
>= size
) {
547 if (norm_size
== 0 || norm_size
> new_size
) {
548 norm_size
= new_size
;
557 static inline int get_width(SM501State
*s
, int crt
)
559 int width
= crt
? s
->dc_crt_h_total
: s
->dc_panel_h_total
;
560 return (width
& 0x00000FFF) + 1;
563 static inline int get_height(SM501State
*s
, int crt
)
565 int height
= crt
? s
->dc_crt_v_total
: s
->dc_panel_v_total
;
566 return (height
& 0x00000FFF) + 1;
569 static inline int get_bpp(SM501State
*s
, int crt
)
571 int bpp
= crt
? s
->dc_crt_control
: s
->dc_panel_control
;
572 return 1 << (bpp
& 3);
576 * Check the availability of hardware cursor.
577 * @param crt 0 for PANEL, 1 for CRT.
579 static inline int is_hwc_enabled(SM501State
*state
, int crt
)
581 uint32_t addr
= crt
? state
->dc_crt_hwc_addr
: state
->dc_panel_hwc_addr
;
582 return addr
& SM501_HWC_EN
;
586 * Get the address which holds cursor pattern data.
587 * @param crt 0 for PANEL, 1 for CRT.
589 static inline uint8_t *get_hwc_address(SM501State
*state
, int crt
)
591 uint32_t addr
= crt
? state
->dc_crt_hwc_addr
: state
->dc_panel_hwc_addr
;
592 return state
->local_mem
+ (addr
& 0x03FFFFF0);
596 * Get the cursor position in y coordinate.
597 * @param crt 0 for PANEL, 1 for CRT.
599 static inline uint32_t get_hwc_y(SM501State
*state
, int crt
)
601 uint32_t location
= crt
? state
->dc_crt_hwc_location
602 : state
->dc_panel_hwc_location
;
603 return (location
& 0x07FF0000) >> 16;
607 * Get the cursor position in x coordinate.
608 * @param crt 0 for PANEL, 1 for CRT.
610 static inline uint32_t get_hwc_x(SM501State
*state
, int crt
)
612 uint32_t location
= crt
? state
->dc_crt_hwc_location
613 : state
->dc_panel_hwc_location
;
614 return location
& 0x000007FF;
618 * Get the hardware cursor palette.
619 * @param crt 0 for PANEL, 1 for CRT.
620 * @param palette pointer to a [3 * 3] array to store color values in
622 static inline void get_hwc_palette(SM501State
*state
, int crt
, uint8_t *palette
)
628 for (i
= 0; i
< 3; i
++) {
630 color_reg
= crt
? state
->dc_crt_hwc_color_3
631 : state
->dc_panel_hwc_color_3
;
633 color_reg
= crt
? state
->dc_crt_hwc_color_1_2
634 : state
->dc_panel_hwc_color_1_2
;
638 rgb565
= (color_reg
>> 16) & 0xFFFF;
640 rgb565
= color_reg
& 0xFFFF;
642 palette
[i
* 3 + 0] = (rgb565
<< 3) & 0xf8; /* red */
643 palette
[i
* 3 + 1] = (rgb565
>> 3) & 0xfc; /* green */
644 palette
[i
* 3 + 2] = (rgb565
>> 8) & 0xf8; /* blue */
648 static inline void hwc_invalidate(SM501State
*s
, int crt
)
650 int w
= get_width(s
, crt
);
651 int h
= get_height(s
, crt
);
652 int bpp
= get_bpp(s
, crt
);
653 int start
= get_hwc_y(s
, crt
);
654 int end
= MIN(h
, start
+ SM501_HWC_HEIGHT
) + 1;
659 memory_region_set_dirty(&s
->local_mem_region
, start
, end
- start
);
662 static void sm501_2d_operation(SM501State
*s
)
664 /* obtain operation parameters */
665 int operation
= (s
->twoD_control
>> 16) & 0x1f;
666 int rtl
= s
->twoD_control
& 0x8000000;
667 int src_x
= (s
->twoD_source
>> 16) & 0x01FFF;
668 int src_y
= s
->twoD_source
& 0xFFFF;
669 int dst_x
= (s
->twoD_destination
>> 16) & 0x01FFF;
670 int dst_y
= s
->twoD_destination
& 0xFFFF;
671 int operation_width
= (s
->twoD_dimension
>> 16) & 0x1FFF;
672 int operation_height
= s
->twoD_dimension
& 0xFFFF;
673 uint32_t color
= s
->twoD_foreground
;
674 int format_flags
= (s
->twoD_stretch
>> 20) & 0x3;
675 int addressing
= (s
->twoD_stretch
>> 16) & 0xF;
677 /* get frame buffer info */
678 uint8_t *src
= s
->local_mem
+ (s
->twoD_source_base
& 0x03FFFFFF);
679 uint8_t *dst
= s
->local_mem
+ (s
->twoD_destination_base
& 0x03FFFFFF);
680 int src_width
= (s
->dc_crt_h_total
& 0x00000FFF) + 1;
681 int dst_width
= (s
->dc_crt_h_total
& 0x00000FFF) + 1;
683 if (addressing
!= 0x0) {
684 printf("%s: only XY addressing is supported.\n", __func__
);
688 if ((s
->twoD_source_base
& 0x08000000) ||
689 (s
->twoD_destination_base
& 0x08000000)) {
690 printf("%s: only local memory is supported.\n", __func__
);
695 case 0x00: /* copy area */
696 #define COPY_AREA(_bpp, _pixel_type, rtl) { \
697 int y, x, index_d, index_s; \
698 for (y = 0; y < operation_height; y++) { \
699 for (x = 0; x < operation_width; x++) { \
701 index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
702 index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
704 index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
705 index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
707 *(_pixel_type *)&dst[index_d] = *(_pixel_type *)&src[index_s];\
711 switch (format_flags
) {
713 COPY_AREA(1, uint8_t, rtl
);
716 COPY_AREA(2, uint16_t, rtl
);
719 COPY_AREA(4, uint32_t, rtl
);
724 case 0x01: /* fill rectangle */
725 #define FILL_RECT(_bpp, _pixel_type) { \
727 for (y = 0; y < operation_height; y++) { \
728 for (x = 0; x < operation_width; x++) { \
729 int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
730 *(_pixel_type *)&dst[index] = (_pixel_type)color; \
735 switch (format_flags
) {
737 FILL_RECT(1, uint8_t);
740 FILL_RECT(2, uint16_t);
743 FILL_RECT(4, uint32_t);
749 printf("non-implemented SM501 2D operation. %d\n", operation
);
755 static uint64_t sm501_system_config_read(void *opaque
, hwaddr addr
,
758 SM501State
*s
= (SM501State
*)opaque
;
760 SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr
);
763 case SM501_SYSTEM_CONTROL
:
764 ret
= s
->system_control
;
766 case SM501_MISC_CONTROL
:
767 ret
= s
->misc_control
;
769 case SM501_GPIO31_0_CONTROL
:
770 ret
= s
->gpio_31_0_control
;
772 case SM501_GPIO63_32_CONTROL
:
773 ret
= s
->gpio_63_32_control
;
778 case SM501_DRAM_CONTROL
:
779 ret
= (s
->dram_control
& 0x07F107C0) | s
->local_mem_size_index
<< 13;
781 case SM501_ARBTRTN_CONTROL
:
782 ret
= s
->arbitration_control
;
787 case SM501_MISC_TIMING
:
788 /* TODO : simulate gate control */
789 ret
= s
->misc_timing
;
791 case SM501_CURRENT_GATE
:
792 /* TODO : simulate gate control */
795 case SM501_CURRENT_CLOCK
:
798 case SM501_POWER_MODE_CONTROL
:
799 ret
= s
->power_mode_control
;
803 printf("sm501 system config : not implemented register read."
804 " addr=%x\n", (int)addr
);
811 static void sm501_system_config_write(void *opaque
, hwaddr addr
,
812 uint64_t value
, unsigned size
)
814 SM501State
*s
= (SM501State
*)opaque
;
815 SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
816 (uint32_t)addr
, (uint32_t)value
);
819 case SM501_SYSTEM_CONTROL
:
820 s
->system_control
= value
& 0xE300B8F7;
822 case SM501_MISC_CONTROL
:
823 s
->misc_control
= value
& 0xFF7FFF20;
825 case SM501_GPIO31_0_CONTROL
:
826 s
->gpio_31_0_control
= value
;
828 case SM501_GPIO63_32_CONTROL
:
829 s
->gpio_63_32_control
= value
;
831 case SM501_DRAM_CONTROL
:
832 s
->local_mem_size_index
= (value
>> 13) & 0x7;
833 /* TODO : check validity of size change */
834 s
->dram_control
|= value
& 0x7FFFFFC3;
836 case SM501_ARBTRTN_CONTROL
:
837 s
->arbitration_control
= value
& 0x37777777;
842 case SM501_MISC_TIMING
:
843 s
->misc_timing
= value
& 0xF31F1FFF;
845 case SM501_POWER_MODE_0_GATE
:
846 case SM501_POWER_MODE_1_GATE
:
847 case SM501_POWER_MODE_0_CLOCK
:
848 case SM501_POWER_MODE_1_CLOCK
:
849 /* TODO : simulate gate & clock control */
851 case SM501_POWER_MODE_CONTROL
:
852 s
->power_mode_control
= value
& 0x00000003;
856 printf("sm501 system config : not implemented register write."
857 " addr=%x, val=%x\n", (int)addr
, (uint32_t)value
);
862 static const MemoryRegionOps sm501_system_config_ops
= {
863 .read
= sm501_system_config_read
,
864 .write
= sm501_system_config_write
,
866 .min_access_size
= 4,
867 .max_access_size
= 4,
869 .endianness
= DEVICE_LITTLE_ENDIAN
,
872 static uint32_t sm501_palette_read(void *opaque
, hwaddr addr
)
874 SM501State
*s
= (SM501State
*)opaque
;
875 SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr
);
877 /* TODO : consider BYTE/WORD access */
878 /* TODO : consider endian */
880 assert(range_covers_byte(0, 0x400 * 3, addr
));
881 return *(uint32_t *)&s
->dc_palette
[addr
];
884 static void sm501_palette_write(void *opaque
, hwaddr addr
,
887 SM501State
*s
= (SM501State
*)opaque
;
888 SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
891 /* TODO : consider BYTE/WORD access */
892 /* TODO : consider endian */
894 assert(range_covers_byte(0, 0x400 * 3, addr
));
895 *(uint32_t *)&s
->dc_palette
[addr
] = value
;
898 static uint64_t sm501_disp_ctrl_read(void *opaque
, hwaddr addr
,
901 SM501State
*s
= (SM501State
*)opaque
;
903 SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr
);
907 case SM501_DC_PANEL_CONTROL
:
908 ret
= s
->dc_panel_control
;
910 case SM501_DC_PANEL_PANNING_CONTROL
:
911 ret
= s
->dc_panel_panning_control
;
913 case SM501_DC_PANEL_FB_ADDR
:
914 ret
= s
->dc_panel_fb_addr
;
916 case SM501_DC_PANEL_FB_OFFSET
:
917 ret
= s
->dc_panel_fb_offset
;
919 case SM501_DC_PANEL_FB_WIDTH
:
920 ret
= s
->dc_panel_fb_width
;
922 case SM501_DC_PANEL_FB_HEIGHT
:
923 ret
= s
->dc_panel_fb_height
;
925 case SM501_DC_PANEL_TL_LOC
:
926 ret
= s
->dc_panel_tl_location
;
928 case SM501_DC_PANEL_BR_LOC
:
929 ret
= s
->dc_panel_br_location
;
932 case SM501_DC_PANEL_H_TOT
:
933 ret
= s
->dc_panel_h_total
;
935 case SM501_DC_PANEL_H_SYNC
:
936 ret
= s
->dc_panel_h_sync
;
938 case SM501_DC_PANEL_V_TOT
:
939 ret
= s
->dc_panel_v_total
;
941 case SM501_DC_PANEL_V_SYNC
:
942 ret
= s
->dc_panel_v_sync
;
945 case SM501_DC_CRT_CONTROL
:
946 ret
= s
->dc_crt_control
;
948 case SM501_DC_CRT_FB_ADDR
:
949 ret
= s
->dc_crt_fb_addr
;
951 case SM501_DC_CRT_FB_OFFSET
:
952 ret
= s
->dc_crt_fb_offset
;
954 case SM501_DC_CRT_H_TOT
:
955 ret
= s
->dc_crt_h_total
;
957 case SM501_DC_CRT_H_SYNC
:
958 ret
= s
->dc_crt_h_sync
;
960 case SM501_DC_CRT_V_TOT
:
961 ret
= s
->dc_crt_v_total
;
963 case SM501_DC_CRT_V_SYNC
:
964 ret
= s
->dc_crt_v_sync
;
967 case SM501_DC_CRT_HWC_ADDR
:
968 ret
= s
->dc_crt_hwc_addr
;
970 case SM501_DC_CRT_HWC_LOC
:
971 ret
= s
->dc_crt_hwc_location
;
973 case SM501_DC_CRT_HWC_COLOR_1_2
:
974 ret
= s
->dc_crt_hwc_color_1_2
;
976 case SM501_DC_CRT_HWC_COLOR_3
:
977 ret
= s
->dc_crt_hwc_color_3
;
980 case SM501_DC_PANEL_PALETTE
... SM501_DC_PANEL_PALETTE
+ 0x400 * 3 - 4:
981 ret
= sm501_palette_read(opaque
, addr
- SM501_DC_PANEL_PALETTE
);
985 printf("sm501 disp ctrl : not implemented register read."
986 " addr=%x\n", (int)addr
);
993 static void sm501_disp_ctrl_write(void *opaque
, hwaddr addr
,
994 uint64_t value
, unsigned size
)
996 SM501State
*s
= (SM501State
*)opaque
;
997 SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
998 (unsigned)addr
, (unsigned)value
);
1001 case SM501_DC_PANEL_CONTROL
:
1002 s
->dc_panel_control
= value
& 0x0FFF73FF;
1004 case SM501_DC_PANEL_PANNING_CONTROL
:
1005 s
->dc_panel_panning_control
= value
& 0xFF3FFF3F;
1007 case SM501_DC_PANEL_FB_ADDR
:
1008 s
->dc_panel_fb_addr
= value
& 0x8FFFFFF0;
1010 case SM501_DC_PANEL_FB_OFFSET
:
1011 s
->dc_panel_fb_offset
= value
& 0x3FF03FF0;
1013 case SM501_DC_PANEL_FB_WIDTH
:
1014 s
->dc_panel_fb_width
= value
& 0x0FFF0FFF;
1016 case SM501_DC_PANEL_FB_HEIGHT
:
1017 s
->dc_panel_fb_height
= value
& 0x0FFF0FFF;
1019 case SM501_DC_PANEL_TL_LOC
:
1020 s
->dc_panel_tl_location
= value
& 0x07FF07FF;
1022 case SM501_DC_PANEL_BR_LOC
:
1023 s
->dc_panel_br_location
= value
& 0x07FF07FF;
1026 case SM501_DC_PANEL_H_TOT
:
1027 s
->dc_panel_h_total
= value
& 0x0FFF0FFF;
1029 case SM501_DC_PANEL_H_SYNC
:
1030 s
->dc_panel_h_sync
= value
& 0x00FF0FFF;
1032 case SM501_DC_PANEL_V_TOT
:
1033 s
->dc_panel_v_total
= value
& 0x0FFF0FFF;
1035 case SM501_DC_PANEL_V_SYNC
:
1036 s
->dc_panel_v_sync
= value
& 0x003F0FFF;
1039 case SM501_DC_PANEL_HWC_ADDR
:
1040 value
&= 0x8FFFFFF0;
1041 if (value
!= s
->dc_panel_hwc_addr
) {
1042 hwc_invalidate(s
, 0);
1043 s
->dc_panel_hwc_addr
= value
;
1046 case SM501_DC_PANEL_HWC_LOC
:
1047 value
&= 0x0FFF0FFF;
1048 if (value
!= s
->dc_panel_hwc_location
) {
1049 hwc_invalidate(s
, 0);
1050 s
->dc_panel_hwc_location
= value
;
1053 case SM501_DC_PANEL_HWC_COLOR_1_2
:
1054 s
->dc_panel_hwc_color_1_2
= value
;
1056 case SM501_DC_PANEL_HWC_COLOR_3
:
1057 s
->dc_panel_hwc_color_3
= value
& 0x0000FFFF;
1060 case SM501_DC_CRT_CONTROL
:
1061 s
->dc_crt_control
= value
& 0x0003FFFF;
1063 case SM501_DC_CRT_FB_ADDR
:
1064 s
->dc_crt_fb_addr
= value
& 0x8FFFFFF0;
1066 case SM501_DC_CRT_FB_OFFSET
:
1067 s
->dc_crt_fb_offset
= value
& 0x3FF03FF0;
1069 case SM501_DC_CRT_H_TOT
:
1070 s
->dc_crt_h_total
= value
& 0x0FFF0FFF;
1072 case SM501_DC_CRT_H_SYNC
:
1073 s
->dc_crt_h_sync
= value
& 0x00FF0FFF;
1075 case SM501_DC_CRT_V_TOT
:
1076 s
->dc_crt_v_total
= value
& 0x0FFF0FFF;
1078 case SM501_DC_CRT_V_SYNC
:
1079 s
->dc_crt_v_sync
= value
& 0x003F0FFF;
1082 case SM501_DC_CRT_HWC_ADDR
:
1083 value
&= 0x8FFFFFF0;
1084 if (value
!= s
->dc_crt_hwc_addr
) {
1085 hwc_invalidate(s
, 1);
1086 s
->dc_crt_hwc_addr
= value
;
1089 case SM501_DC_CRT_HWC_LOC
:
1090 value
&= 0x0FFF0FFF;
1091 if (value
!= s
->dc_crt_hwc_location
) {
1092 hwc_invalidate(s
, 1);
1093 s
->dc_crt_hwc_location
= value
;
1096 case SM501_DC_CRT_HWC_COLOR_1_2
:
1097 s
->dc_crt_hwc_color_1_2
= value
;
1099 case SM501_DC_CRT_HWC_COLOR_3
:
1100 s
->dc_crt_hwc_color_3
= value
& 0x0000FFFF;
1103 case SM501_DC_PANEL_PALETTE
... SM501_DC_PANEL_PALETTE
+ 0x400 * 3 - 4:
1104 sm501_palette_write(opaque
, addr
- SM501_DC_PANEL_PALETTE
, value
);
1108 printf("sm501 disp ctrl : not implemented register write."
1109 " addr=%x, val=%x\n", (int)addr
, (unsigned)value
);
1114 static const MemoryRegionOps sm501_disp_ctrl_ops
= {
1115 .read
= sm501_disp_ctrl_read
,
1116 .write
= sm501_disp_ctrl_write
,
1118 .min_access_size
= 4,
1119 .max_access_size
= 4,
1121 .endianness
= DEVICE_LITTLE_ENDIAN
,
1124 static uint64_t sm501_2d_engine_read(void *opaque
, hwaddr addr
,
1127 SM501State
*s
= (SM501State
*)opaque
;
1129 SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr
);
1132 case SM501_2D_SOURCE_BASE
:
1133 ret
= s
->twoD_source_base
;
1136 printf("sm501 disp ctrl : not implemented register read."
1137 " addr=%x\n", (int)addr
);
1144 static void sm501_2d_engine_write(void *opaque
, hwaddr addr
,
1145 uint64_t value
, unsigned size
)
1147 SM501State
*s
= (SM501State
*)opaque
;
1148 SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
1149 (unsigned)addr
, (unsigned)value
);
1152 case SM501_2D_SOURCE
:
1153 s
->twoD_source
= value
;
1155 case SM501_2D_DESTINATION
:
1156 s
->twoD_destination
= value
;
1158 case SM501_2D_DIMENSION
:
1159 s
->twoD_dimension
= value
;
1161 case SM501_2D_CONTROL
:
1162 s
->twoD_control
= value
;
1164 /* do 2d operation if start flag is set. */
1165 if (value
& 0x80000000) {
1166 sm501_2d_operation(s
);
1167 s
->twoD_control
&= ~0x80000000; /* start flag down */
1171 case SM501_2D_PITCH
:
1172 s
->twoD_pitch
= value
;
1174 case SM501_2D_FOREGROUND
:
1175 s
->twoD_foreground
= value
;
1177 case SM501_2D_STRETCH
:
1178 s
->twoD_stretch
= value
;
1180 case SM501_2D_COLOR_COMPARE_MASK
:
1181 s
->twoD_color_compare_mask
= value
;
1184 s
->twoD_mask
= value
;
1186 case SM501_2D_WINDOW_WIDTH
:
1187 s
->twoD_window_width
= value
;
1189 case SM501_2D_SOURCE_BASE
:
1190 s
->twoD_source_base
= value
;
1192 case SM501_2D_DESTINATION_BASE
:
1193 s
->twoD_destination_base
= value
;
1196 printf("sm501 2d engine : not implemented register write."
1197 " addr=%x, val=%x\n", (int)addr
, (unsigned)value
);
1202 static const MemoryRegionOps sm501_2d_engine_ops
= {
1203 .read
= sm501_2d_engine_read
,
1204 .write
= sm501_2d_engine_write
,
1206 .min_access_size
= 4,
1207 .max_access_size
= 4,
1209 .endianness
= DEVICE_LITTLE_ENDIAN
,
1212 /* draw line functions for all console modes */
1214 typedef void draw_line_func(uint8_t *d
, const uint8_t *s
,
1215 int width
, const uint32_t *pal
);
1217 typedef void draw_hwc_line_func(uint8_t *d
, const uint8_t *s
,
1218 int width
, const uint8_t *palette
,
1222 #include "sm501_template.h"
1225 #include "sm501_template.h"
1229 #include "sm501_template.h"
1232 #include "sm501_template.h"
1236 #include "sm501_template.h"
1239 #include "sm501_template.h"
1243 #include "sm501_template.h"
1245 static draw_line_func
*draw_line8_funcs
[] = {
1255 static draw_line_func
*draw_line16_funcs
[] = {
1265 static draw_line_func
*draw_line32_funcs
[] = {
1275 static draw_hwc_line_func
*draw_hwc_line_funcs
[] = {
1280 draw_hwc_line_32bgr
,
1281 draw_hwc_line_15bgr
,
1282 draw_hwc_line_16bgr
,
1285 static inline int get_depth_index(DisplaySurface
*surface
)
1287 switch (surface_bits_per_pixel(surface
)) {
1296 if (is_surface_bgr(surface
)) {
1304 static void sm501_draw_crt(SM501State
*s
)
1306 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1307 int y
, c_x
= 0, c_y
= 0;
1308 uint8_t *hwc_src
= NULL
, *src
= s
->local_mem
;
1309 int width
= get_width(s
, 1);
1310 int height
= get_height(s
, 1);
1311 int src_bpp
= get_bpp(s
, 1);
1312 int dst_bpp
= surface_bytes_per_pixel(surface
);
1313 uint32_t *palette
= (uint32_t *)&s
->dc_palette
[SM501_DC_CRT_PALETTE
-
1314 SM501_DC_PANEL_PALETTE
];
1315 uint8_t hwc_palette
[3 * 3];
1316 int dst_depth_index
= get_depth_index(surface
);
1317 draw_line_func
*draw_line
= NULL
;
1318 draw_hwc_line_func
*draw_hwc_line
= NULL
;
1319 int full_update
= 0;
1321 ram_addr_t page_min
= ~0l;
1322 ram_addr_t page_max
= 0l;
1323 ram_addr_t offset
= 0;
1325 /* choose draw_line function */
1328 draw_line
= draw_line8_funcs
[dst_depth_index
];
1331 draw_line
= draw_line16_funcs
[dst_depth_index
];
1334 draw_line
= draw_line32_funcs
[dst_depth_index
];
1337 printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
1343 /* set up to draw hardware cursor */
1344 if (is_hwc_enabled(s
, 1)) {
1345 /* choose cursor draw line function */
1346 draw_hwc_line
= draw_hwc_line_funcs
[dst_depth_index
];
1347 hwc_src
= get_hwc_address(s
, 1);
1348 c_x
= get_hwc_x(s
, 1);
1349 c_y
= get_hwc_y(s
, 1);
1350 get_hwc_palette(s
, 1, hwc_palette
);
1353 /* adjust console size */
1354 if (s
->last_width
!= width
|| s
->last_height
!= height
) {
1355 qemu_console_resize(s
->con
, width
, height
);
1356 surface
= qemu_console_surface(s
->con
);
1357 s
->last_width
= width
;
1358 s
->last_height
= height
;
1362 /* draw each line according to conditions */
1363 memory_region_sync_dirty_bitmap(&s
->local_mem_region
);
1364 for (y
= 0; y
< height
; y
++) {
1365 int update
, update_hwc
;
1366 ram_addr_t page0
= offset
;
1367 ram_addr_t page1
= offset
+ width
* src_bpp
- 1;
1369 /* check if hardware cursor is enabled and we're within its range */
1370 update_hwc
= draw_hwc_line
&& c_y
<= y
&& y
< c_y
+ SM501_HWC_HEIGHT
;
1371 update
= full_update
|| update_hwc
;
1372 /* check dirty flags for each line */
1373 update
|= memory_region_get_dirty(&s
->local_mem_region
, page0
,
1374 page1
- page0
, DIRTY_MEMORY_VGA
);
1376 /* draw line and change status */
1378 uint8_t *d
= surface_data(surface
);
1379 d
+= y
* width
* dst_bpp
;
1381 /* draw graphics layer */
1382 draw_line(d
, src
, width
, palette
);
1384 /* draw hardware cursor */
1386 draw_hwc_line(d
, hwc_src
, width
, hwc_palette
, c_x
, y
- c_y
);
1392 if (page0
< page_min
) {
1395 if (page1
> page_max
) {
1400 /* flush to display */
1401 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
1406 src
+= width
* src_bpp
;
1407 offset
+= width
* src_bpp
;
1410 /* complete flush to display */
1412 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
1415 /* clear dirty flags */
1416 if (page_min
!= ~0l) {
1417 memory_region_reset_dirty(&s
->local_mem_region
,
1418 page_min
, page_max
+ TARGET_PAGE_SIZE
,
1423 static void sm501_update_display(void *opaque
)
1425 SM501State
*s
= (SM501State
*)opaque
;
1427 if (s
->dc_crt_control
& SM501_DC_CRT_CONTROL_ENABLE
) {
1432 static const GraphicHwOps sm501_ops
= {
1433 .gfx_update
= sm501_update_display
,
1436 static void sm501_reset(SM501State
*s
)
1438 s
->system_control
= 0x00100000; /* 2D engine FIFO empty */
1439 /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
1440 * to be determined at reset by GPIO lines which set config bits.
1442 * SH = 0 : Hitachi Ready Polarity == Active Low
1443 * CDR = 0 : do not reset clock divider
1444 * TEST = 0 : Normal mode (not testing the silicon)
1445 * BUS = 0 : Hitachi SH3/SH4
1447 s
->misc_control
= SM501_MISC_DAC_POWER
;
1448 s
->gpio_31_0_control
= 0;
1449 s
->gpio_63_32_control
= 0;
1450 s
->dram_control
= 0;
1451 s
->arbitration_control
= 0x05146732;
1454 s
->power_mode_control
= 0;
1455 s
->dc_panel_control
= 0x00010000; /* FIFO level 3 */
1456 s
->dc_crt_control
= 0x00010000;
1457 s
->twoD_control
= 0;
1460 static void sm501_init(SM501State
*s
, DeviceState
*dev
,
1461 uint32_t local_mem_bytes
)
1463 s
->local_mem_size_index
= get_local_mem_size_index(local_mem_bytes
);
1464 SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s
),
1465 s
->local_mem_size_index
);
1468 memory_region_init_ram(&s
->local_mem_region
, OBJECT(dev
), "sm501.local",
1469 get_local_mem_size(s
), &error_fatal
);
1470 vmstate_register_ram_global(&s
->local_mem_region
);
1471 memory_region_set_log(&s
->local_mem_region
, true, DIRTY_MEMORY_VGA
);
1472 s
->local_mem
= memory_region_get_ram_ptr(&s
->local_mem_region
);
1475 memory_region_init(&s
->mmio_region
, OBJECT(dev
), "sm501.mmio", MMIO_SIZE
);
1476 memory_region_init_io(&s
->system_config_region
, OBJECT(dev
),
1477 &sm501_system_config_ops
, s
,
1478 "sm501-system-config", 0x6c);
1479 memory_region_add_subregion(&s
->mmio_region
, SM501_SYS_CONFIG
,
1480 &s
->system_config_region
);
1481 memory_region_init_io(&s
->disp_ctrl_region
, OBJECT(dev
),
1482 &sm501_disp_ctrl_ops
, s
,
1483 "sm501-disp-ctrl", 0x1000);
1484 memory_region_add_subregion(&s
->mmio_region
, SM501_DC
,
1485 &s
->disp_ctrl_region
);
1486 memory_region_init_io(&s
->twoD_engine_region
, OBJECT(dev
),
1487 &sm501_2d_engine_ops
, s
,
1488 "sm501-2d-engine", 0x54);
1489 memory_region_add_subregion(&s
->mmio_region
, SM501_2D_ENGINE
,
1490 &s
->twoD_engine_region
);
1492 /* create qemu graphic console */
1493 s
->con
= graphic_console_init(DEVICE(dev
), 0, &sm501_ops
, s
);
1496 #define TYPE_SYSBUS_SM501 "sysbus-sm501"
1497 #define SYSBUS_SM501(obj) \
1498 OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501)
1502 SysBusDevice parent_obj
;
1510 static void sm501_realize_sysbus(DeviceState
*dev
, Error
**errp
)
1512 SM501SysBusState
*s
= SYSBUS_SM501(dev
);
1513 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1514 DeviceState
*usb_dev
;
1516 sm501_init(&s
->state
, dev
, s
->vram_size
);
1517 if (get_local_mem_size(&s
->state
) != s
->vram_size
) {
1518 error_setg(errp
, "Invalid VRAM size, nearest valid size is %" PRIu32
,
1519 get_local_mem_size(&s
->state
));
1522 sysbus_init_mmio(sbd
, &s
->state
.local_mem_region
);
1523 sysbus_init_mmio(sbd
, &s
->state
.mmio_region
);
1525 /* bridge to usb host emulation module */
1526 usb_dev
= qdev_create(NULL
, "sysbus-ohci");
1527 qdev_prop_set_uint32(usb_dev
, "num-ports", 2);
1528 qdev_prop_set_uint64(usb_dev
, "dma-offset", s
->base
);
1529 qdev_init_nofail(usb_dev
);
1530 memory_region_add_subregion(&s
->state
.mmio_region
, SM501_USB_HOST
,
1531 sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev
), 0));
1532 sysbus_pass_irq(sbd
, SYS_BUS_DEVICE(usb_dev
));
1534 /* bridge to serial emulation module */
1536 serial_mm_init(&s
->state
.mmio_region
, SM501_UART0
, 2,
1537 NULL
, /* TODO : chain irq to IRL */
1538 115200, s
->chr_state
, DEVICE_LITTLE_ENDIAN
);
1542 static Property sm501_sysbus_properties
[] = {
1543 DEFINE_PROP_UINT32("vram-size", SM501SysBusState
, vram_size
, 0),
1544 DEFINE_PROP_UINT32("base", SM501SysBusState
, base
, 0),
1545 DEFINE_PROP_PTR("chr-state", SM501SysBusState
, chr_state
),
1546 DEFINE_PROP_END_OF_LIST(),
1549 static void sm501_reset_sysbus(DeviceState
*dev
)
1551 SM501SysBusState
*s
= SYSBUS_SM501(dev
);
1552 sm501_reset(&s
->state
);
1555 static void sm501_sysbus_class_init(ObjectClass
*klass
, void *data
)
1557 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1559 dc
->realize
= sm501_realize_sysbus
;
1560 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
1561 dc
->desc
= "SM501 Multimedia Companion";
1562 dc
->props
= sm501_sysbus_properties
;
1563 dc
->reset
= sm501_reset_sysbus
;
1564 /* Note: pointer property "chr-state" may remain null, thus
1565 * no need for dc->cannot_instantiate_with_device_add_yet = true;
1569 static const TypeInfo sm501_sysbus_info
= {
1570 .name
= TYPE_SYSBUS_SM501
,
1571 .parent
= TYPE_SYS_BUS_DEVICE
,
1572 .instance_size
= sizeof(SM501SysBusState
),
1573 .class_init
= sm501_sysbus_class_init
,
1576 #define TYPE_PCI_SM501 "sm501"
1577 #define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501)
1581 PCIDevice parent_obj
;
1587 static void sm501_realize_pci(PCIDevice
*dev
, Error
**errp
)
1589 SM501PCIState
*s
= PCI_SM501(dev
);
1591 sm501_init(&s
->state
, DEVICE(dev
), s
->vram_size
);
1592 if (get_local_mem_size(&s
->state
) != s
->vram_size
) {
1593 error_setg(errp
, "Invalid VRAM size, nearest valid size is %" PRIu32
,
1594 get_local_mem_size(&s
->state
));
1597 pci_register_bar(dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1598 &s
->state
.local_mem_region
);
1599 pci_register_bar(dev
, 1, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1600 &s
->state
.mmio_region
);
1603 static Property sm501_pci_properties
[] = {
1604 DEFINE_PROP_UINT32("vram-size", SM501PCIState
, vram_size
, 64 * M_BYTE
),
1605 DEFINE_PROP_END_OF_LIST(),
1608 static void sm501_reset_pci(DeviceState
*dev
)
1610 SM501PCIState
*s
= PCI_SM501(dev
);
1611 sm501_reset(&s
->state
);
1612 /* Bits 2:0 of misc_control register is 001 for PCI */
1613 s
->state
.misc_control
|= 1;
1616 static void sm501_pci_class_init(ObjectClass
*klass
, void *data
)
1618 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1619 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1621 k
->realize
= sm501_realize_pci
;
1622 k
->vendor_id
= PCI_VENDOR_ID_SILICON_MOTION
;
1623 k
->device_id
= PCI_DEVICE_ID_SM501
;
1624 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
1625 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
1626 dc
->desc
= "SM501 Display Controller";
1627 dc
->props
= sm501_pci_properties
;
1628 dc
->reset
= sm501_reset_pci
;
1629 dc
->hotpluggable
= false;
1632 static const TypeInfo sm501_pci_info
= {
1633 .name
= TYPE_PCI_SM501
,
1634 .parent
= TYPE_PCI_DEVICE
,
1635 .instance_size
= sizeof(SM501PCIState
),
1636 .class_init
= sm501_pci_class_init
,
1639 static void sm501_register_types(void)
1641 type_register_static(&sm501_sysbus_info
);
1642 type_register_static(&sm501_pci_info
);
1645 type_init(sm501_register_types
)