4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2011 Alexander Graf
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "exec/gdbstub.h"
25 #include "qemu/timer.h"
26 #include "exec/exec-all.h"
27 #include "hw/s390x/ioinst.h"
28 #include "sysemu/hw_accel.h"
29 #ifndef CONFIG_USER_ONLY
30 #include "sysemu/sysemu.h"
33 #ifndef CONFIG_USER_ONLY
34 void s390x_tod_timer(void *opaque
)
36 cpu_inject_clock_comparator((S390CPU
*) opaque
);
39 void s390x_cpu_timer(void *opaque
)
41 cpu_inject_cpu_timer((S390CPU
*) opaque
);
45 #ifndef CONFIG_USER_ONLY
47 hwaddr
s390_cpu_get_phys_page_debug(CPUState
*cs
, vaddr vaddr
)
49 S390CPU
*cpu
= S390_CPU(cs
);
50 CPUS390XState
*env
= &cpu
->env
;
53 uint64_t asc
= env
->psw
.mask
& PSW_MASK_ASC
;
56 if (!(env
->psw
.mask
& PSW_MASK_64
)) {
60 if (mmu_translate(env
, vaddr
, MMU_INST_FETCH
, asc
, &raddr
, &prot
, false)) {
66 hwaddr
s390_cpu_get_phys_addr_debug(CPUState
*cs
, vaddr vaddr
)
71 page
= vaddr
& TARGET_PAGE_MASK
;
72 phys_addr
= cpu_get_phys_page_debug(cs
, page
);
73 phys_addr
+= (vaddr
& ~TARGET_PAGE_MASK
);
78 static inline bool is_special_wait_psw(uint64_t psw_addr
)
81 return psw_addr
== 0xfffUL
;
84 void s390_handle_wait(S390CPU
*cpu
)
86 CPUState
*cs
= CPU(cpu
);
88 if (s390_cpu_halt(cpu
) == 0) {
89 #ifndef CONFIG_USER_ONLY
90 if (is_special_wait_psw(cpu
->env
.psw
.addr
)) {
91 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
93 cpu
->env
.crash_reason
= S390_CRASH_REASON_DISABLED_WAIT
;
94 qemu_system_guest_panicked(cpu_get_crash_info(cs
));
100 void load_psw(CPUS390XState
*env
, uint64_t mask
, uint64_t addr
)
102 uint64_t old_mask
= env
->psw
.mask
;
104 env
->psw
.addr
= addr
;
105 env
->psw
.mask
= mask
;
107 env
->cc_op
= (mask
>> 44) & 3;
110 if ((old_mask
^ mask
) & PSW_MASK_PER
) {
111 s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env
)));
114 /* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */
115 if (tcg_enabled() && (mask
& PSW_MASK_WAIT
)) {
116 s390_handle_wait(s390_env_get_cpu(env
));
120 uint64_t get_psw_mask(CPUS390XState
*env
)
122 uint64_t r
= env
->psw
.mask
;
125 env
->cc_op
= calc_cc(env
, env
->cc_op
, env
->cc_src
, env
->cc_dst
,
129 assert(!(env
->cc_op
& ~3));
130 r
|= (uint64_t)env
->cc_op
<< 44;
136 LowCore
*cpu_map_lowcore(CPUS390XState
*env
)
138 S390CPU
*cpu
= s390_env_get_cpu(env
);
140 hwaddr len
= sizeof(LowCore
);
142 lowcore
= cpu_physical_memory_map(env
->psa
, &len
, 1);
144 if (len
< sizeof(LowCore
)) {
145 cpu_abort(CPU(cpu
), "Could not map lowcore\n");
151 void cpu_unmap_lowcore(LowCore
*lowcore
)
153 cpu_physical_memory_unmap(lowcore
, sizeof(LowCore
), 1, sizeof(LowCore
));
156 void do_restart_interrupt(CPUS390XState
*env
)
161 lowcore
= cpu_map_lowcore(env
);
163 lowcore
->restart_old_psw
.mask
= cpu_to_be64(get_psw_mask(env
));
164 lowcore
->restart_old_psw
.addr
= cpu_to_be64(env
->psw
.addr
);
165 mask
= be64_to_cpu(lowcore
->restart_new_psw
.mask
);
166 addr
= be64_to_cpu(lowcore
->restart_new_psw
.addr
);
168 cpu_unmap_lowcore(lowcore
);
169 env
->pending_int
&= ~INTERRUPT_RESTART
;
171 load_psw(env
, mask
, addr
);
174 void s390_cpu_recompute_watchpoints(CPUState
*cs
)
176 const int wp_flags
= BP_CPU
| BP_MEM_WRITE
| BP_STOP_BEFORE_ACCESS
;
177 S390CPU
*cpu
= S390_CPU(cs
);
178 CPUS390XState
*env
= &cpu
->env
;
180 /* We are called when the watchpoints have changed. First
182 cpu_watchpoint_remove_all(cs
, BP_CPU
);
184 /* Return if PER is not enabled */
185 if (!(env
->psw
.mask
& PSW_MASK_PER
)) {
189 /* Return if storage-alteration event is not enabled. */
190 if (!(env
->cregs
[9] & PER_CR9_EVENT_STORE
)) {
194 if (env
->cregs
[10] == 0 && env
->cregs
[11] == -1LL) {
195 /* We can't create a watchoint spanning the whole memory range, so
196 split it in two parts. */
197 cpu_watchpoint_insert(cs
, 0, 1ULL << 63, wp_flags
, NULL
);
198 cpu_watchpoint_insert(cs
, 1ULL << 63, 1ULL << 63, wp_flags
, NULL
);
199 } else if (env
->cregs
[10] > env
->cregs
[11]) {
200 /* The address range loops, create two watchpoints. */
201 cpu_watchpoint_insert(cs
, env
->cregs
[10], -env
->cregs
[10],
203 cpu_watchpoint_insert(cs
, 0, env
->cregs
[11] + 1, wp_flags
, NULL
);
206 /* Default case, create a single watchpoint. */
207 cpu_watchpoint_insert(cs
, env
->cregs
[10],
208 env
->cregs
[11] - env
->cregs
[10] + 1,
213 struct sigp_save_area
{
214 uint64_t fprs
[16]; /* 0x0000 */
215 uint64_t grs
[16]; /* 0x0080 */
216 PSW psw
; /* 0x0100 */
217 uint8_t pad_0x0110
[0x0118 - 0x0110]; /* 0x0110 */
218 uint32_t prefix
; /* 0x0118 */
219 uint32_t fpc
; /* 0x011c */
220 uint8_t pad_0x0120
[0x0124 - 0x0120]; /* 0x0120 */
221 uint32_t todpr
; /* 0x0124 */
222 uint64_t cputm
; /* 0x0128 */
223 uint64_t ckc
; /* 0x0130 */
224 uint8_t pad_0x0138
[0x0140 - 0x0138]; /* 0x0138 */
225 uint32_t ars
[16]; /* 0x0140 */
226 uint64_t crs
[16]; /* 0x0384 */
228 QEMU_BUILD_BUG_ON(sizeof(struct sigp_save_area
) != 512);
230 int s390_store_status(S390CPU
*cpu
, hwaddr addr
, bool store_arch
)
232 static const uint8_t ar_id
= 1;
233 struct sigp_save_area
*sa
;
234 hwaddr len
= sizeof(*sa
);
237 sa
= cpu_physical_memory_map(addr
, &len
, 1);
241 if (len
!= sizeof(*sa
)) {
242 cpu_physical_memory_unmap(sa
, len
, 1, 0);
247 cpu_physical_memory_write(offsetof(LowCore
, ar_access_id
), &ar_id
, 1);
249 for (i
= 0; i
< 16; ++i
) {
250 sa
->fprs
[i
] = cpu_to_be64(get_freg(&cpu
->env
, i
)->ll
);
252 for (i
= 0; i
< 16; ++i
) {
253 sa
->grs
[i
] = cpu_to_be64(cpu
->env
.regs
[i
]);
255 sa
->psw
.addr
= cpu_to_be64(cpu
->env
.psw
.addr
);
256 sa
->psw
.mask
= cpu_to_be64(get_psw_mask(&cpu
->env
));
257 sa
->prefix
= cpu_to_be32(cpu
->env
.psa
);
258 sa
->fpc
= cpu_to_be32(cpu
->env
.fpc
);
259 sa
->todpr
= cpu_to_be32(cpu
->env
.todpr
);
260 sa
->cputm
= cpu_to_be64(cpu
->env
.cputm
);
261 sa
->ckc
= cpu_to_be64(cpu
->env
.ckc
>> 8);
262 for (i
= 0; i
< 16; ++i
) {
263 sa
->ars
[i
] = cpu_to_be32(cpu
->env
.aregs
[i
]);
265 for (i
= 0; i
< 16; ++i
) {
266 sa
->crs
[i
] = cpu_to_be64(cpu
->env
.cregs
[i
]);
269 cpu_physical_memory_unmap(sa
, len
, 1, len
);
274 #define ADTL_GS_OFFSET 1024 /* offset of GS data in adtl save area */
275 #define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */
276 int s390_store_adtl_status(S390CPU
*cpu
, hwaddr addr
, hwaddr len
)
281 mem
= cpu_physical_memory_map(addr
, &save
, 1);
286 cpu_physical_memory_unmap(mem
, len
, 1, 0);
290 /* FIXME: as soon as TCG supports these features, convert cpu->be */
291 if (s390_has_feat(S390_FEAT_VECTOR
)) {
292 memcpy(mem
, &cpu
->env
.vregs
, 512);
294 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE
) && len
>= ADTL_GS_MIN_SIZE
) {
295 memcpy(mem
+ ADTL_GS_OFFSET
, &cpu
->env
.gscb
, 32);
298 cpu_physical_memory_unmap(mem
, len
, 1, len
);
302 #endif /* CONFIG_USER_ONLY */
304 void s390_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
307 S390CPU
*cpu
= S390_CPU(cs
);
308 CPUS390XState
*env
= &cpu
->env
;
311 if (env
->cc_op
> 3) {
312 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %15s\n",
313 env
->psw
.mask
, env
->psw
.addr
, cc_name(env
->cc_op
));
315 cpu_fprintf(f
, "PSW=mask %016" PRIx64
" addr %016" PRIx64
" cc %02x\n",
316 env
->psw
.mask
, env
->psw
.addr
, env
->cc_op
);
319 for (i
= 0; i
< 16; i
++) {
320 cpu_fprintf(f
, "R%02d=%016" PRIx64
, i
, env
->regs
[i
]);
322 cpu_fprintf(f
, "\n");
328 for (i
= 0; i
< 16; i
++) {
329 cpu_fprintf(f
, "F%02d=%016" PRIx64
, i
, get_freg(env
, i
)->ll
);
331 cpu_fprintf(f
, "\n");
337 for (i
= 0; i
< 32; i
++) {
338 cpu_fprintf(f
, "V%02d=%016" PRIx64
"%016" PRIx64
, i
,
339 env
->vregs
[i
][0].ll
, env
->vregs
[i
][1].ll
);
340 cpu_fprintf(f
, (i
% 2) ? "\n" : " ");
343 #ifndef CONFIG_USER_ONLY
344 for (i
= 0; i
< 16; i
++) {
345 cpu_fprintf(f
, "C%02d=%016" PRIx64
, i
, env
->cregs
[i
]);
347 cpu_fprintf(f
, "\n");
354 #ifdef DEBUG_INLINE_BRANCHES
355 for (i
= 0; i
< CC_OP_MAX
; i
++) {
356 cpu_fprintf(f
, " %15s = %10ld\t%10ld\n", cc_name(i
),
357 inline_branch_miss
[i
], inline_branch_hit
[i
]);
361 cpu_fprintf(f
, "\n");
364 const char *cc_name(enum cc_op cc_op
)
366 static const char * const cc_names
[] = {
367 [CC_OP_CONST0
] = "CC_OP_CONST0",
368 [CC_OP_CONST1
] = "CC_OP_CONST1",
369 [CC_OP_CONST2
] = "CC_OP_CONST2",
370 [CC_OP_CONST3
] = "CC_OP_CONST3",
371 [CC_OP_DYNAMIC
] = "CC_OP_DYNAMIC",
372 [CC_OP_STATIC
] = "CC_OP_STATIC",
373 [CC_OP_NZ
] = "CC_OP_NZ",
374 [CC_OP_LTGT_32
] = "CC_OP_LTGT_32",
375 [CC_OP_LTGT_64
] = "CC_OP_LTGT_64",
376 [CC_OP_LTUGTU_32
] = "CC_OP_LTUGTU_32",
377 [CC_OP_LTUGTU_64
] = "CC_OP_LTUGTU_64",
378 [CC_OP_LTGT0_32
] = "CC_OP_LTGT0_32",
379 [CC_OP_LTGT0_64
] = "CC_OP_LTGT0_64",
380 [CC_OP_ADD_64
] = "CC_OP_ADD_64",
381 [CC_OP_ADDU_64
] = "CC_OP_ADDU_64",
382 [CC_OP_ADDC_64
] = "CC_OP_ADDC_64",
383 [CC_OP_SUB_64
] = "CC_OP_SUB_64",
384 [CC_OP_SUBU_64
] = "CC_OP_SUBU_64",
385 [CC_OP_SUBB_64
] = "CC_OP_SUBB_64",
386 [CC_OP_ABS_64
] = "CC_OP_ABS_64",
387 [CC_OP_NABS_64
] = "CC_OP_NABS_64",
388 [CC_OP_ADD_32
] = "CC_OP_ADD_32",
389 [CC_OP_ADDU_32
] = "CC_OP_ADDU_32",
390 [CC_OP_ADDC_32
] = "CC_OP_ADDC_32",
391 [CC_OP_SUB_32
] = "CC_OP_SUB_32",
392 [CC_OP_SUBU_32
] = "CC_OP_SUBU_32",
393 [CC_OP_SUBB_32
] = "CC_OP_SUBB_32",
394 [CC_OP_ABS_32
] = "CC_OP_ABS_32",
395 [CC_OP_NABS_32
] = "CC_OP_NABS_32",
396 [CC_OP_COMP_32
] = "CC_OP_COMP_32",
397 [CC_OP_COMP_64
] = "CC_OP_COMP_64",
398 [CC_OP_TM_32
] = "CC_OP_TM_32",
399 [CC_OP_TM_64
] = "CC_OP_TM_64",
400 [CC_OP_NZ_F32
] = "CC_OP_NZ_F32",
401 [CC_OP_NZ_F64
] = "CC_OP_NZ_F64",
402 [CC_OP_NZ_F128
] = "CC_OP_NZ_F128",
403 [CC_OP_ICM
] = "CC_OP_ICM",
404 [CC_OP_SLA_32
] = "CC_OP_SLA_32",
405 [CC_OP_SLA_64
] = "CC_OP_SLA_64",
406 [CC_OP_FLOGR
] = "CC_OP_FLOGR",
409 return cc_names
[cc_op
];