2 * QEMU sPAPR PCI host originated from Uninorth PCI host
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
30 #include "hw/sysbus.h"
31 #include "migration/vmstate.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/msi.h"
34 #include "hw/pci/msix.h"
35 #include "hw/pci/pci_host.h"
36 #include "hw/ppc/spapr.h"
37 #include "hw/pci-host/spapr.h"
38 #include "exec/address-spaces.h"
39 #include "exec/ram_addr.h"
42 #include "qemu/error-report.h"
43 #include "qemu/module.h"
44 #include "qapi/qmp/qerror.h"
45 #include "hw/ppc/fdt.h"
46 #include "hw/pci/pci_bridge.h"
47 #include "hw/pci/pci_bus.h"
48 #include "hw/pci/pci_ids.h"
49 #include "hw/ppc/spapr_drc.h"
50 #include "hw/qdev-properties.h"
51 #include "sysemu/device_tree.h"
52 #include "sysemu/kvm.h"
53 #include "sysemu/hostmem.h"
54 #include "sysemu/numa.h"
56 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
57 #define RTAS_QUERY_FN 0
58 #define RTAS_CHANGE_FN 1
59 #define RTAS_RESET_FN 2
60 #define RTAS_CHANGE_MSI_FN 3
61 #define RTAS_CHANGE_MSIX_FN 4
63 /* Interrupt types to return on RTAS_CHANGE_* */
64 #define RTAS_TYPE_MSI 1
65 #define RTAS_TYPE_MSIX 2
67 SpaprPhbState
*spapr_pci_find_phb(SpaprMachineState
*spapr
, uint64_t buid
)
71 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
72 if (sphb
->buid
!= buid
) {
81 PCIDevice
*spapr_pci_find_dev(SpaprMachineState
*spapr
, uint64_t buid
,
84 SpaprPhbState
*sphb
= spapr_pci_find_phb(spapr
, buid
);
85 PCIHostState
*phb
= PCI_HOST_BRIDGE(sphb
);
86 int bus_num
= (config_addr
>> 16) & 0xFF;
87 int devfn
= (config_addr
>> 8) & 0xFF;
93 return pci_find_device(phb
->bus
, bus_num
, devfn
);
96 static uint32_t rtas_pci_cfgaddr(uint32_t arg
)
98 /* This handles the encoding of extended config space addresses */
99 return ((arg
>> 20) & 0xf00) | (arg
& 0xff);
102 static void finish_read_pci_config(SpaprMachineState
*spapr
, uint64_t buid
,
103 uint32_t addr
, uint32_t size
,
109 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
110 /* access must be 1, 2 or 4 bytes */
111 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
115 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
116 addr
= rtas_pci_cfgaddr(addr
);
118 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
119 /* Access must be to a valid device, within bounds and
120 * naturally aligned */
121 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
125 val
= pci_host_config_read_common(pci_dev
, addr
,
126 pci_config_size(pci_dev
), size
);
128 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
129 rtas_st(rets
, 1, val
);
132 static void rtas_ibm_read_pci_config(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
133 uint32_t token
, uint32_t nargs
,
135 uint32_t nret
, target_ulong rets
)
140 if ((nargs
!= 4) || (nret
!= 2)) {
141 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
145 buid
= rtas_ldq(args
, 1);
146 size
= rtas_ld(args
, 3);
147 addr
= rtas_ld(args
, 0);
149 finish_read_pci_config(spapr
, buid
, addr
, size
, rets
);
152 static void rtas_read_pci_config(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
153 uint32_t token
, uint32_t nargs
,
155 uint32_t nret
, target_ulong rets
)
159 if ((nargs
!= 2) || (nret
!= 2)) {
160 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
164 size
= rtas_ld(args
, 1);
165 addr
= rtas_ld(args
, 0);
167 finish_read_pci_config(spapr
, 0, addr
, size
, rets
);
170 static void finish_write_pci_config(SpaprMachineState
*spapr
, uint64_t buid
,
171 uint32_t addr
, uint32_t size
,
172 uint32_t val
, target_ulong rets
)
176 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
177 /* access must be 1, 2 or 4 bytes */
178 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
182 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
183 addr
= rtas_pci_cfgaddr(addr
);
185 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
186 /* Access must be to a valid device, within bounds and
187 * naturally aligned */
188 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
192 pci_host_config_write_common(pci_dev
, addr
, pci_config_size(pci_dev
),
195 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
198 static void rtas_ibm_write_pci_config(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
199 uint32_t token
, uint32_t nargs
,
201 uint32_t nret
, target_ulong rets
)
204 uint32_t val
, size
, addr
;
206 if ((nargs
!= 5) || (nret
!= 1)) {
207 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
211 buid
= rtas_ldq(args
, 1);
212 val
= rtas_ld(args
, 4);
213 size
= rtas_ld(args
, 3);
214 addr
= rtas_ld(args
, 0);
216 finish_write_pci_config(spapr
, buid
, addr
, size
, val
, rets
);
219 static void rtas_write_pci_config(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
220 uint32_t token
, uint32_t nargs
,
222 uint32_t nret
, target_ulong rets
)
224 uint32_t val
, size
, addr
;
226 if ((nargs
!= 3) || (nret
!= 1)) {
227 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
232 val
= rtas_ld(args
, 2);
233 size
= rtas_ld(args
, 1);
234 addr
= rtas_ld(args
, 0);
236 finish_write_pci_config(spapr
, 0, addr
, size
, val
, rets
);
240 * Set MSI/MSIX message data.
241 * This is required for msi_notify()/msix_notify() which
242 * will write at the addresses via spapr_msi_write().
244 * If hwaddr == 0, all entries will have .data == first_irq i.e.
245 * table will be reset.
247 static void spapr_msi_setmsg(PCIDevice
*pdev
, hwaddr addr
, bool msix
,
248 unsigned first_irq
, unsigned req_num
)
251 MSIMessage msg
= { .address
= addr
, .data
= first_irq
};
254 msi_set_message(pdev
, msg
);
255 trace_spapr_pci_msi_setup(pdev
->name
, 0, msg
.address
);
259 for (i
= 0; i
< req_num
; ++i
) {
260 msix_set_message(pdev
, i
, msg
);
261 trace_spapr_pci_msi_setup(pdev
->name
, i
, msg
.address
);
268 static void rtas_ibm_change_msi(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
269 uint32_t token
, uint32_t nargs
,
270 target_ulong args
, uint32_t nret
,
273 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
274 uint32_t config_addr
= rtas_ld(args
, 0);
275 uint64_t buid
= rtas_ldq(args
, 1);
276 unsigned int func
= rtas_ld(args
, 3);
277 unsigned int req_num
= rtas_ld(args
, 4); /* 0 == remove all */
278 unsigned int seq_num
= rtas_ld(args
, 5);
279 unsigned int ret_intr_type
;
280 unsigned int irq
, max_irqs
= 0;
281 SpaprPhbState
*phb
= NULL
;
282 PCIDevice
*pdev
= NULL
;
284 int *config_addr_key
;
288 /* Fins SpaprPhbState */
289 phb
= spapr_pci_find_phb(spapr
, buid
);
291 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
294 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
300 if (msi_present(pdev
)) {
301 ret_intr_type
= RTAS_TYPE_MSI
;
302 } else if (msix_present(pdev
)) {
303 ret_intr_type
= RTAS_TYPE_MSIX
;
305 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
309 case RTAS_CHANGE_MSI_FN
:
310 if (msi_present(pdev
)) {
311 ret_intr_type
= RTAS_TYPE_MSI
;
313 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
317 case RTAS_CHANGE_MSIX_FN
:
318 if (msix_present(pdev
)) {
319 ret_intr_type
= RTAS_TYPE_MSIX
;
321 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
326 error_report("rtas_ibm_change_msi(%u) is not implemented", func
);
327 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
331 msi
= (SpaprPciMsi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
336 trace_spapr_pci_msi("Releasing wrong config", config_addr
);
337 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
341 if (msi_present(pdev
)) {
342 spapr_msi_setmsg(pdev
, 0, false, 0, 0);
344 if (msix_present(pdev
)) {
345 spapr_msi_setmsg(pdev
, 0, true, 0, 0);
347 g_hash_table_remove(phb
->msi
, &config_addr
);
349 trace_spapr_pci_msi("Released MSIs", config_addr
);
350 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
357 /* Check if the device supports as many IRQs as requested */
358 if (ret_intr_type
== RTAS_TYPE_MSI
) {
359 max_irqs
= msi_nr_vectors_allocated(pdev
);
360 } else if (ret_intr_type
== RTAS_TYPE_MSIX
) {
361 max_irqs
= pdev
->msix_entries_nr
;
364 error_report("Requested interrupt type %d is not enabled for device %x",
365 ret_intr_type
, config_addr
);
366 rtas_st(rets
, 0, -1); /* Hardware error */
369 /* Correct the number if the guest asked for too many */
370 if (req_num
> max_irqs
) {
371 trace_spapr_pci_msi_retry(config_addr
, req_num
, max_irqs
);
373 irq
= 0; /* to avoid misleading trace */
378 if (smc
->legacy_irq_allocation
) {
379 irq
= spapr_irq_find(spapr
, req_num
, ret_intr_type
== RTAS_TYPE_MSI
,
382 irq
= spapr_irq_msi_alloc(spapr
, req_num
,
383 ret_intr_type
== RTAS_TYPE_MSI
, &err
);
386 error_reportf_err(err
, "Can't allocate MSIs for device %x: ",
388 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
392 for (i
= 0; i
< req_num
; i
++) {
393 spapr_irq_claim(spapr
, irq
+ i
, false, &err
);
396 spapr_irq_free(spapr
, irq
, i
);
398 if (!smc
->legacy_irq_allocation
) {
399 spapr_irq_msi_free(spapr
, irq
, req_num
);
401 error_reportf_err(err
, "Can't allocate MSIs for device %x: ",
403 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
408 /* Release previous MSIs */
410 g_hash_table_remove(phb
->msi
, &config_addr
);
413 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
414 spapr_msi_setmsg(pdev
, SPAPR_PCI_MSI_WINDOW
, ret_intr_type
== RTAS_TYPE_MSIX
,
417 /* Add MSI device to cache */
418 msi
= g_new(SpaprPciMsi
, 1);
419 msi
->first_irq
= irq
;
421 config_addr_key
= g_new(int, 1);
422 *config_addr_key
= config_addr
;
423 g_hash_table_insert(phb
->msi
, config_addr_key
, msi
);
426 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
427 rtas_st(rets
, 1, req_num
);
428 rtas_st(rets
, 2, ++seq_num
);
430 rtas_st(rets
, 3, ret_intr_type
);
433 trace_spapr_pci_rtas_ibm_change_msi(config_addr
, func
, req_num
, irq
);
436 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU
*cpu
,
437 SpaprMachineState
*spapr
,
444 uint32_t config_addr
= rtas_ld(args
, 0);
445 uint64_t buid
= rtas_ldq(args
, 1);
446 unsigned int intr_src_num
= -1, ioa_intr_num
= rtas_ld(args
, 3);
447 SpaprPhbState
*phb
= NULL
;
448 PCIDevice
*pdev
= NULL
;
451 /* Find SpaprPhbState */
452 phb
= spapr_pci_find_phb(spapr
, buid
);
454 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
457 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
461 /* Find device descriptor and start IRQ */
462 msi
= (SpaprPciMsi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
463 if (!msi
|| !msi
->first_irq
|| !msi
->num
|| (ioa_intr_num
>= msi
->num
)) {
464 trace_spapr_pci_msi("Failed to return vector", config_addr
);
465 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
468 intr_src_num
= msi
->first_irq
+ ioa_intr_num
;
469 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num
,
472 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
473 rtas_st(rets
, 1, intr_src_num
);
474 rtas_st(rets
, 2, 1);/* 0 == level; 1 == edge */
477 static void rtas_ibm_set_eeh_option(PowerPCCPU
*cpu
,
478 SpaprMachineState
*spapr
,
479 uint32_t token
, uint32_t nargs
,
480 target_ulong args
, uint32_t nret
,
484 uint32_t addr
, option
;
488 if ((nargs
!= 4) || (nret
!= 1)) {
489 goto param_error_exit
;
492 buid
= rtas_ldq(args
, 1);
493 addr
= rtas_ld(args
, 0);
494 option
= rtas_ld(args
, 3);
496 sphb
= spapr_pci_find_phb(spapr
, buid
);
498 goto param_error_exit
;
501 if (!spapr_phb_eeh_available(sphb
)) {
502 goto param_error_exit
;
505 ret
= spapr_phb_vfio_eeh_set_option(sphb
, addr
, option
);
506 rtas_st(rets
, 0, ret
);
510 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
513 static void rtas_ibm_get_config_addr_info2(PowerPCCPU
*cpu
,
514 SpaprMachineState
*spapr
,
515 uint32_t token
, uint32_t nargs
,
516 target_ulong args
, uint32_t nret
,
521 uint32_t addr
, option
;
524 if ((nargs
!= 4) || (nret
!= 2)) {
525 goto param_error_exit
;
528 buid
= rtas_ldq(args
, 1);
529 sphb
= spapr_pci_find_phb(spapr
, buid
);
531 goto param_error_exit
;
534 if (!spapr_phb_eeh_available(sphb
)) {
535 goto param_error_exit
;
539 * We always have PE address of form "00BB0001". "BB"
540 * represents the bus number of PE's primary bus.
542 option
= rtas_ld(args
, 3);
544 case RTAS_GET_PE_ADDR
:
545 addr
= rtas_ld(args
, 0);
546 pdev
= spapr_pci_find_dev(spapr
, buid
, addr
);
548 goto param_error_exit
;
551 rtas_st(rets
, 1, (pci_bus_num(pci_get_bus(pdev
)) << 16) + 1);
553 case RTAS_GET_PE_MODE
:
554 rtas_st(rets
, 1, RTAS_PE_MODE_SHARED
);
557 goto param_error_exit
;
560 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
564 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
567 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU
*cpu
,
568 SpaprMachineState
*spapr
,
569 uint32_t token
, uint32_t nargs
,
570 target_ulong args
, uint32_t nret
,
577 if ((nargs
!= 3) || (nret
!= 4 && nret
!= 5)) {
578 goto param_error_exit
;
581 buid
= rtas_ldq(args
, 1);
582 sphb
= spapr_pci_find_phb(spapr
, buid
);
584 goto param_error_exit
;
587 if (!spapr_phb_eeh_available(sphb
)) {
588 goto param_error_exit
;
591 ret
= spapr_phb_vfio_eeh_get_state(sphb
, &state
);
592 rtas_st(rets
, 0, ret
);
593 if (ret
!= RTAS_OUT_SUCCESS
) {
597 rtas_st(rets
, 1, state
);
598 rtas_st(rets
, 2, RTAS_EEH_SUPPORT
);
599 rtas_st(rets
, 3, RTAS_EEH_PE_UNAVAIL_INFO
);
601 rtas_st(rets
, 4, RTAS_EEH_PE_RECOVER_INFO
);
606 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
609 static void rtas_ibm_set_slot_reset(PowerPCCPU
*cpu
,
610 SpaprMachineState
*spapr
,
611 uint32_t token
, uint32_t nargs
,
612 target_ulong args
, uint32_t nret
,
620 if ((nargs
!= 4) || (nret
!= 1)) {
621 goto param_error_exit
;
624 buid
= rtas_ldq(args
, 1);
625 option
= rtas_ld(args
, 3);
626 sphb
= spapr_pci_find_phb(spapr
, buid
);
628 goto param_error_exit
;
631 if (!spapr_phb_eeh_available(sphb
)) {
632 goto param_error_exit
;
635 ret
= spapr_phb_vfio_eeh_reset(sphb
, option
);
636 rtas_st(rets
, 0, ret
);
640 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
643 static void rtas_ibm_configure_pe(PowerPCCPU
*cpu
,
644 SpaprMachineState
*spapr
,
645 uint32_t token
, uint32_t nargs
,
646 target_ulong args
, uint32_t nret
,
653 if ((nargs
!= 3) || (nret
!= 1)) {
654 goto param_error_exit
;
657 buid
= rtas_ldq(args
, 1);
658 sphb
= spapr_pci_find_phb(spapr
, buid
);
660 goto param_error_exit
;
663 if (!spapr_phb_eeh_available(sphb
)) {
664 goto param_error_exit
;
667 ret
= spapr_phb_vfio_eeh_configure(sphb
);
668 rtas_st(rets
, 0, ret
);
672 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
675 /* To support it later */
676 static void rtas_ibm_slot_error_detail(PowerPCCPU
*cpu
,
677 SpaprMachineState
*spapr
,
678 uint32_t token
, uint32_t nargs
,
679 target_ulong args
, uint32_t nret
,
686 if ((nargs
!= 8) || (nret
!= 1)) {
687 goto param_error_exit
;
690 buid
= rtas_ldq(args
, 1);
691 sphb
= spapr_pci_find_phb(spapr
, buid
);
693 goto param_error_exit
;
696 if (!spapr_phb_eeh_available(sphb
)) {
697 goto param_error_exit
;
700 option
= rtas_ld(args
, 7);
702 case RTAS_SLOT_TEMP_ERR_LOG
:
703 case RTAS_SLOT_PERM_ERR_LOG
:
706 goto param_error_exit
;
709 /* We don't have error log yet */
710 rtas_st(rets
, 0, RTAS_OUT_NO_ERRORS_FOUND
);
714 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
717 static void pci_spapr_set_irq(void *opaque
, int irq_num
, int level
)
720 * Here we use the number returned by pci_swizzle_map_irq_fn to find a
721 * corresponding qemu_irq.
723 SpaprPhbState
*phb
= opaque
;
724 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
726 trace_spapr_pci_lsi_set(phb
->dtbusname
, irq_num
, phb
->lsi_table
[irq_num
].irq
);
727 qemu_set_irq(spapr_qirq(spapr
, phb
->lsi_table
[irq_num
].irq
), level
);
730 static PCIINTxRoute
spapr_route_intx_pin_to_irq(void *opaque
, int pin
)
732 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(opaque
);
735 route
.mode
= PCI_INTX_ENABLED
;
736 route
.irq
= sphb
->lsi_table
[pin
].irq
;
742 * MSI/MSIX memory region implementation.
743 * The handler handles both MSI and MSIX.
744 * The vector number is encoded in least bits in data.
746 static void spapr_msi_write(void *opaque
, hwaddr addr
,
747 uint64_t data
, unsigned size
)
749 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
752 trace_spapr_pci_msi_write(addr
, data
, irq
);
754 qemu_irq_pulse(spapr_qirq(spapr
, irq
));
757 static const MemoryRegionOps spapr_msi_ops
= {
758 /* There is no .read as the read result is undefined by PCI spec */
760 .write
= spapr_msi_write
,
761 .endianness
= DEVICE_LITTLE_ENDIAN
767 static AddressSpace
*spapr_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
769 SpaprPhbState
*phb
= opaque
;
771 return &phb
->iommu_as
;
774 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState
*sphb
, PCIDevice
*pdev
)
776 char *path
= NULL
, *buf
= NULL
, *host
= NULL
;
778 /* Get the PCI VFIO host id */
779 host
= object_property_get_str(OBJECT(pdev
), "host", NULL
);
784 /* Construct the path of the file that will give us the DT location */
785 path
= g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host
);
787 if (!g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
792 /* Construct and read from host device tree the loc-code */
793 path
= g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf
);
795 if (!g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
805 static char *spapr_phb_get_loc_code(SpaprPhbState
*sphb
, PCIDevice
*pdev
)
808 const char *devtype
= "qemu";
809 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
811 if (object_dynamic_cast(OBJECT(pdev
), "vfio-pci")) {
812 buf
= spapr_phb_vfio_get_loc_code(sphb
, pdev
);
819 * For emulated devices and VFIO-failure case, make up
822 buf
= g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
823 devtype
, pdev
->name
, sphb
->index
, busnr
,
824 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
));
828 /* Macros to operate with address in OF binding to PCI */
829 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
830 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
831 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
832 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
833 #define b_ss(x) b_x((x), 24, 2) /* the space code */
834 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
835 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
836 #define b_fff(x) b_x((x), 8, 3) /* function number */
837 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
839 /* for 'reg' OF properties */
840 #define RESOURCE_CELLS_SIZE 2
841 #define RESOURCE_CELLS_ADDRESS 3
843 typedef struct ResourceFields
{
849 } QEMU_PACKED ResourceFields
;
851 typedef struct ResourceProps
{
852 ResourceFields reg
[8];
856 /* fill in the 'reg' OF properties for
857 * a PCI device. 'reg' describes resource requirements for a
858 * device's IO/MEM regions.
860 * the property is an array of ('phys-addr', 'size') pairs describing
861 * the addressable regions of the PCI device, where 'phys-addr' is a
862 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
863 * (phys.hi, phys.mid, phys.lo), and 'size' is a
864 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
866 * phys.hi = 0xYYXXXXZZ, where:
871 * ||| + 00 if configuration space
872 * ||| + 01 if IO region,
873 * ||| + 10 if 32-bit MEM region
874 * ||| + 11 if 64-bit MEM region
876 * ||+------ for non-relocatable IO: 1 if aliased
877 * || for relocatable IO: 1 if below 64KB
878 * || for MEM: 1 if below 1MB
879 * |+------- 1 if region is prefetchable
880 * +-------- 1 if region is non-relocatable
881 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
883 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
886 * phys.mid and phys.lo correspond respectively to the hi/lo portions
887 * of the actual address of the region.
889 * note also that addresses defined in this property are, at least
890 * for PAPR guests, relative to the PHBs IO/MEM windows, and
891 * correspond directly to the addresses in the BARs.
893 * in accordance with PCI Bus Binding to Open Firmware,
894 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
897 static void populate_resource_props(PCIDevice
*d
, ResourceProps
*rp
)
899 int bus_num
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d
))));
900 uint32_t dev_id
= (b_bbbbbbbb(bus_num
) |
901 b_ddddd(PCI_SLOT(d
->devfn
)) |
902 b_fff(PCI_FUNC(d
->devfn
)));
906 /* config space region */
907 reg
= &rp
->reg
[reg_idx
++];
908 reg
->phys_hi
= cpu_to_be32(dev_id
);
914 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
915 if (!d
->io_regions
[i
].size
) {
919 reg
= &rp
->reg
[reg_idx
++];
921 reg
->phys_hi
= cpu_to_be32(dev_id
| b_rrrrrrrr(pci_bar(d
, i
)));
922 if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_SPACE_IO
) {
923 reg
->phys_hi
|= cpu_to_be32(b_ss(1));
924 } else if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
925 reg
->phys_hi
|= cpu_to_be32(b_ss(3));
927 reg
->phys_hi
|= cpu_to_be32(b_ss(2));
931 reg
->size_hi
= cpu_to_be32(d
->io_regions
[i
].size
>> 32);
932 reg
->size_lo
= cpu_to_be32(d
->io_regions
[i
].size
);
935 rp
->reg_len
= reg_idx
* sizeof(ResourceFields
);
938 typedef struct PCIClass PCIClass
;
939 typedef struct PCISubClass PCISubClass
;
940 typedef struct PCIIFace PCIIFace
;
950 const PCIIFace
*iface
;
955 const PCISubClass
*subc
;
958 static const PCISubClass undef_subclass
[] = {
959 { PCI_CLASS_NOT_DEFINED_VGA
, "display", NULL
},
960 { 0xFF, NULL
, NULL
},
963 static const PCISubClass mass_subclass
[] = {
964 { PCI_CLASS_STORAGE_SCSI
, "scsi", NULL
},
965 { PCI_CLASS_STORAGE_IDE
, "ide", NULL
},
966 { PCI_CLASS_STORAGE_FLOPPY
, "fdc", NULL
},
967 { PCI_CLASS_STORAGE_IPI
, "ipi", NULL
},
968 { PCI_CLASS_STORAGE_RAID
, "raid", NULL
},
969 { PCI_CLASS_STORAGE_ATA
, "ata", NULL
},
970 { PCI_CLASS_STORAGE_SATA
, "sata", NULL
},
971 { PCI_CLASS_STORAGE_SAS
, "sas", NULL
},
972 { 0xFF, NULL
, NULL
},
975 static const PCISubClass net_subclass
[] = {
976 { PCI_CLASS_NETWORK_ETHERNET
, "ethernet", NULL
},
977 { PCI_CLASS_NETWORK_TOKEN_RING
, "token-ring", NULL
},
978 { PCI_CLASS_NETWORK_FDDI
, "fddi", NULL
},
979 { PCI_CLASS_NETWORK_ATM
, "atm", NULL
},
980 { PCI_CLASS_NETWORK_ISDN
, "isdn", NULL
},
981 { PCI_CLASS_NETWORK_WORLDFIP
, "worldfip", NULL
},
982 { PCI_CLASS_NETWORK_PICMG214
, "picmg", NULL
},
983 { 0xFF, NULL
, NULL
},
986 static const PCISubClass displ_subclass
[] = {
987 { PCI_CLASS_DISPLAY_VGA
, "vga", NULL
},
988 { PCI_CLASS_DISPLAY_XGA
, "xga", NULL
},
989 { PCI_CLASS_DISPLAY_3D
, "3d-controller", NULL
},
990 { 0xFF, NULL
, NULL
},
993 static const PCISubClass media_subclass
[] = {
994 { PCI_CLASS_MULTIMEDIA_VIDEO
, "video", NULL
},
995 { PCI_CLASS_MULTIMEDIA_AUDIO
, "sound", NULL
},
996 { PCI_CLASS_MULTIMEDIA_PHONE
, "telephony", NULL
},
997 { 0xFF, NULL
, NULL
},
1000 static const PCISubClass mem_subclass
[] = {
1001 { PCI_CLASS_MEMORY_RAM
, "memory", NULL
},
1002 { PCI_CLASS_MEMORY_FLASH
, "flash", NULL
},
1003 { 0xFF, NULL
, NULL
},
1006 static const PCISubClass bridg_subclass
[] = {
1007 { PCI_CLASS_BRIDGE_HOST
, "host", NULL
},
1008 { PCI_CLASS_BRIDGE_ISA
, "isa", NULL
},
1009 { PCI_CLASS_BRIDGE_EISA
, "eisa", NULL
},
1010 { PCI_CLASS_BRIDGE_MC
, "mca", NULL
},
1011 { PCI_CLASS_BRIDGE_PCI
, "pci", NULL
},
1012 { PCI_CLASS_BRIDGE_PCMCIA
, "pcmcia", NULL
},
1013 { PCI_CLASS_BRIDGE_NUBUS
, "nubus", NULL
},
1014 { PCI_CLASS_BRIDGE_CARDBUS
, "cardbus", NULL
},
1015 { PCI_CLASS_BRIDGE_RACEWAY
, "raceway", NULL
},
1016 { PCI_CLASS_BRIDGE_PCI_SEMITP
, "semi-transparent-pci", NULL
},
1017 { PCI_CLASS_BRIDGE_IB_PCI
, "infiniband", NULL
},
1018 { 0xFF, NULL
, NULL
},
1021 static const PCISubClass comm_subclass
[] = {
1022 { PCI_CLASS_COMMUNICATION_SERIAL
, "serial", NULL
},
1023 { PCI_CLASS_COMMUNICATION_PARALLEL
, "parallel", NULL
},
1024 { PCI_CLASS_COMMUNICATION_MULTISERIAL
, "multiport-serial", NULL
},
1025 { PCI_CLASS_COMMUNICATION_MODEM
, "modem", NULL
},
1026 { PCI_CLASS_COMMUNICATION_GPIB
, "gpib", NULL
},
1027 { PCI_CLASS_COMMUNICATION_SC
, "smart-card", NULL
},
1028 { 0xFF, NULL
, NULL
, },
1031 static const PCIIFace pic_iface
[] = {
1032 { PCI_CLASS_SYSTEM_PIC_IOAPIC
, "io-apic" },
1033 { PCI_CLASS_SYSTEM_PIC_IOXAPIC
, "io-xapic" },
1037 static const PCISubClass sys_subclass
[] = {
1038 { PCI_CLASS_SYSTEM_PIC
, "interrupt-controller", pic_iface
},
1039 { PCI_CLASS_SYSTEM_DMA
, "dma-controller", NULL
},
1040 { PCI_CLASS_SYSTEM_TIMER
, "timer", NULL
},
1041 { PCI_CLASS_SYSTEM_RTC
, "rtc", NULL
},
1042 { PCI_CLASS_SYSTEM_PCI_HOTPLUG
, "hot-plug-controller", NULL
},
1043 { PCI_CLASS_SYSTEM_SDHCI
, "sd-host-controller", NULL
},
1044 { 0xFF, NULL
, NULL
},
1047 static const PCISubClass inp_subclass
[] = {
1048 { PCI_CLASS_INPUT_KEYBOARD
, "keyboard", NULL
},
1049 { PCI_CLASS_INPUT_PEN
, "pen", NULL
},
1050 { PCI_CLASS_INPUT_MOUSE
, "mouse", NULL
},
1051 { PCI_CLASS_INPUT_SCANNER
, "scanner", NULL
},
1052 { PCI_CLASS_INPUT_GAMEPORT
, "gameport", NULL
},
1053 { 0xFF, NULL
, NULL
},
1056 static const PCISubClass dock_subclass
[] = {
1057 { PCI_CLASS_DOCKING_GENERIC
, "dock", NULL
},
1058 { 0xFF, NULL
, NULL
},
1061 static const PCISubClass cpu_subclass
[] = {
1062 { PCI_CLASS_PROCESSOR_PENTIUM
, "pentium", NULL
},
1063 { PCI_CLASS_PROCESSOR_POWERPC
, "powerpc", NULL
},
1064 { PCI_CLASS_PROCESSOR_MIPS
, "mips", NULL
},
1065 { PCI_CLASS_PROCESSOR_CO
, "co-processor", NULL
},
1066 { 0xFF, NULL
, NULL
},
1069 static const PCIIFace usb_iface
[] = {
1070 { PCI_CLASS_SERIAL_USB_UHCI
, "usb-uhci" },
1071 { PCI_CLASS_SERIAL_USB_OHCI
, "usb-ohci", },
1072 { PCI_CLASS_SERIAL_USB_EHCI
, "usb-ehci" },
1073 { PCI_CLASS_SERIAL_USB_XHCI
, "usb-xhci" },
1074 { PCI_CLASS_SERIAL_USB_UNKNOWN
, "usb-unknown" },
1075 { PCI_CLASS_SERIAL_USB_DEVICE
, "usb-device" },
1079 static const PCISubClass ser_subclass
[] = {
1080 { PCI_CLASS_SERIAL_FIREWIRE
, "firewire", NULL
},
1081 { PCI_CLASS_SERIAL_ACCESS
, "access-bus", NULL
},
1082 { PCI_CLASS_SERIAL_SSA
, "ssa", NULL
},
1083 { PCI_CLASS_SERIAL_USB
, "usb", usb_iface
},
1084 { PCI_CLASS_SERIAL_FIBER
, "fibre-channel", NULL
},
1085 { PCI_CLASS_SERIAL_SMBUS
, "smb", NULL
},
1086 { PCI_CLASS_SERIAL_IB
, "infiniband", NULL
},
1087 { PCI_CLASS_SERIAL_IPMI
, "ipmi", NULL
},
1088 { PCI_CLASS_SERIAL_SERCOS
, "sercos", NULL
},
1089 { PCI_CLASS_SERIAL_CANBUS
, "canbus", NULL
},
1090 { 0xFF, NULL
, NULL
},
1093 static const PCISubClass wrl_subclass
[] = {
1094 { PCI_CLASS_WIRELESS_IRDA
, "irda", NULL
},
1095 { PCI_CLASS_WIRELESS_CIR
, "consumer-ir", NULL
},
1096 { PCI_CLASS_WIRELESS_RF_CONTROLLER
, "rf-controller", NULL
},
1097 { PCI_CLASS_WIRELESS_BLUETOOTH
, "bluetooth", NULL
},
1098 { PCI_CLASS_WIRELESS_BROADBAND
, "broadband", NULL
},
1099 { 0xFF, NULL
, NULL
},
1102 static const PCISubClass sat_subclass
[] = {
1103 { PCI_CLASS_SATELLITE_TV
, "satellite-tv", NULL
},
1104 { PCI_CLASS_SATELLITE_AUDIO
, "satellite-audio", NULL
},
1105 { PCI_CLASS_SATELLITE_VOICE
, "satellite-voice", NULL
},
1106 { PCI_CLASS_SATELLITE_DATA
, "satellite-data", NULL
},
1107 { 0xFF, NULL
, NULL
},
1110 static const PCISubClass crypt_subclass
[] = {
1111 { PCI_CLASS_CRYPT_NETWORK
, "network-encryption", NULL
},
1112 { PCI_CLASS_CRYPT_ENTERTAINMENT
,
1113 "entertainment-encryption", NULL
},
1114 { 0xFF, NULL
, NULL
},
1117 static const PCISubClass spc_subclass
[] = {
1118 { PCI_CLASS_SP_DPIO
, "dpio", NULL
},
1119 { PCI_CLASS_SP_PERF
, "counter", NULL
},
1120 { PCI_CLASS_SP_SYNCH
, "measurement", NULL
},
1121 { PCI_CLASS_SP_MANAGEMENT
, "management-card", NULL
},
1122 { 0xFF, NULL
, NULL
},
1125 static const PCIClass pci_classes
[] = {
1126 { "legacy-device", undef_subclass
},
1127 { "mass-storage", mass_subclass
},
1128 { "network", net_subclass
},
1129 { "display", displ_subclass
, },
1130 { "multimedia-device", media_subclass
},
1131 { "memory-controller", mem_subclass
},
1132 { "unknown-bridge", bridg_subclass
},
1133 { "communication-controller", comm_subclass
},
1134 { "system-peripheral", sys_subclass
},
1135 { "input-controller", inp_subclass
},
1136 { "docking-station", dock_subclass
},
1137 { "cpu", cpu_subclass
},
1138 { "serial-bus", ser_subclass
},
1139 { "wireless-controller", wrl_subclass
},
1140 { "intelligent-io", NULL
},
1141 { "satellite-device", sat_subclass
},
1142 { "encryption", crypt_subclass
},
1143 { "data-processing-controller", spc_subclass
},
1146 static const char *dt_name_from_class(uint8_t class, uint8_t subclass
,
1149 const PCIClass
*pclass
;
1150 const PCISubClass
*psubclass
;
1151 const PCIIFace
*piface
;
1154 if (class >= ARRAY_SIZE(pci_classes
)) {
1158 pclass
= pci_classes
+ class;
1159 name
= pclass
->name
;
1161 if (pclass
->subc
== NULL
) {
1165 psubclass
= pclass
->subc
;
1166 while ((psubclass
->subclass
& 0xff) != 0xff) {
1167 if ((psubclass
->subclass
& 0xff) == subclass
) {
1168 name
= psubclass
->name
;
1174 piface
= psubclass
->iface
;
1175 if (piface
== NULL
) {
1178 while ((piface
->iface
& 0xff) != 0xff) {
1179 if ((piface
->iface
& 0xff) == iface
) {
1180 name
= piface
->name
;
1190 * DRC helper functions
1193 static uint32_t drc_id_from_devfn(SpaprPhbState
*phb
,
1194 uint8_t chassis
, int32_t devfn
)
1196 return (phb
->index
<< 16) | (chassis
<< 8) | devfn
;
1199 static SpaprDrc
*drc_from_devfn(SpaprPhbState
*phb
,
1200 uint8_t chassis
, int32_t devfn
)
1202 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI
,
1203 drc_id_from_devfn(phb
, chassis
, devfn
));
1206 static uint8_t chassis_from_bus(PCIBus
*bus
, Error
**errp
)
1208 if (pci_bus_is_root(bus
)) {
1211 PCIDevice
*bridge
= pci_bridge_get_device(bus
);
1213 return object_property_get_uint(OBJECT(bridge
), "chassis_nr", errp
);
1217 static SpaprDrc
*drc_from_dev(SpaprPhbState
*phb
, PCIDevice
*dev
)
1219 Error
*local_err
= NULL
;
1220 uint8_t chassis
= chassis_from_bus(pci_get_bus(dev
), &local_err
);
1223 error_report_err(local_err
);
1227 return drc_from_devfn(phb
, chassis
, dev
->devfn
);
1230 static void add_drcs(SpaprPhbState
*phb
, PCIBus
*bus
, Error
**errp
)
1235 Error
*local_err
= NULL
;
1237 if (!phb
->dr_enabled
) {
1241 chassis
= chassis_from_bus(bus
, &local_err
);
1243 error_propagate(errp
, local_err
);
1247 if (pci_bus_is_root(bus
)) {
1248 owner
= OBJECT(phb
);
1250 owner
= OBJECT(pci_bridge_get_device(bus
));
1253 for (i
= 0; i
< PCI_SLOT_MAX
* PCI_FUNC_MAX
; i
++) {
1254 spapr_dr_connector_new(owner
, TYPE_SPAPR_DRC_PCI
,
1255 drc_id_from_devfn(phb
, chassis
, i
));
1259 static void remove_drcs(SpaprPhbState
*phb
, PCIBus
*bus
, Error
**errp
)
1263 Error
*local_err
= NULL
;
1265 if (!phb
->dr_enabled
) {
1269 chassis
= chassis_from_bus(bus
, &local_err
);
1271 error_propagate(errp
, local_err
);
1275 for (i
= PCI_SLOT_MAX
* PCI_FUNC_MAX
- 1; i
>= 0; i
--) {
1276 SpaprDrc
*drc
= drc_from_devfn(phb
, chassis
, i
);
1279 object_unparent(OBJECT(drc
));
1284 typedef struct PciWalkFdt
{
1287 SpaprPhbState
*sphb
;
1291 static int spapr_dt_pci_device(SpaprPhbState
*sphb
, PCIDevice
*dev
,
1292 void *fdt
, int parent_offset
);
1294 static void spapr_dt_pci_device_cb(PCIBus
*bus
, PCIDevice
*pdev
,
1297 PciWalkFdt
*p
= opaque
;
1301 /* Something's already broken, don't keep going */
1305 err
= spapr_dt_pci_device(p
->sphb
, pdev
, p
->fdt
, p
->offset
);
1311 /* Augment PCI device node with bridge specific information */
1312 static int spapr_dt_pci_bus(SpaprPhbState
*sphb
, PCIBus
*bus
,
1313 void *fdt
, int offset
)
1316 PciWalkFdt cbinfo
= {
1324 _FDT(fdt_setprop_cell(fdt
, offset
, "#address-cells",
1325 RESOURCE_CELLS_ADDRESS
));
1326 _FDT(fdt_setprop_cell(fdt
, offset
, "#size-cells",
1327 RESOURCE_CELLS_SIZE
));
1330 pci_for_each_device_reverse(bus
, pci_bus_num(bus
),
1331 spapr_dt_pci_device_cb
, &cbinfo
);
1336 if (pci_bus_is_root(bus
)) {
1337 owner
= OBJECT(sphb
);
1339 owner
= OBJECT(pci_bridge_get_device(bus
));
1342 ret
= spapr_dt_drc(fdt
, offset
, owner
,
1343 SPAPR_DR_CONNECTOR_TYPE_PCI
);
1351 /* create OF node for pci device and required OF DT properties */
1352 static int spapr_dt_pci_device(SpaprPhbState
*sphb
, PCIDevice
*dev
,
1353 void *fdt
, int parent_offset
)
1356 const gchar
*basename
;
1358 int slot
= PCI_SLOT(dev
->devfn
);
1359 int func
= PCI_FUNC(dev
->devfn
);
1360 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1362 SpaprDrc
*drc
= drc_from_dev(sphb
, dev
);
1363 uint32_t vendor_id
= pci_default_read_config(dev
, PCI_VENDOR_ID
, 2);
1364 uint32_t device_id
= pci_default_read_config(dev
, PCI_DEVICE_ID
, 2);
1365 uint32_t revision_id
= pci_default_read_config(dev
, PCI_REVISION_ID
, 1);
1366 uint32_t ccode
= pci_default_read_config(dev
, PCI_CLASS_PROG
, 3);
1367 uint32_t irq_pin
= pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1);
1368 uint32_t subsystem_id
= pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2);
1369 uint32_t subsystem_vendor_id
=
1370 pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2);
1371 uint32_t cache_line_size
=
1372 pci_default_read_config(dev
, PCI_CACHE_LINE_SIZE
, 1);
1373 uint32_t pci_status
= pci_default_read_config(dev
, PCI_STATUS
, 2);
1376 basename
= dt_name_from_class((ccode
>> 16) & 0xff, (ccode
>> 8) & 0xff,
1380 nodename
= g_strdup_printf("%s@%x,%x", basename
, slot
, func
);
1382 nodename
= g_strdup_printf("%s@%x", basename
, slot
);
1385 _FDT(offset
= fdt_add_subnode(fdt
, parent_offset
, nodename
));
1389 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1390 _FDT(fdt_setprop_cell(fdt
, offset
, "vendor-id", vendor_id
));
1391 _FDT(fdt_setprop_cell(fdt
, offset
, "device-id", device_id
));
1392 _FDT(fdt_setprop_cell(fdt
, offset
, "revision-id", revision_id
));
1394 _FDT(fdt_setprop_cell(fdt
, offset
, "class-code", ccode
));
1396 _FDT(fdt_setprop_cell(fdt
, offset
, "interrupts", irq_pin
));
1400 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-id", subsystem_id
));
1403 if (subsystem_vendor_id
) {
1404 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-vendor-id",
1405 subsystem_vendor_id
));
1408 _FDT(fdt_setprop_cell(fdt
, offset
, "cache-line-size", cache_line_size
));
1411 /* the following fdt cells are masked off the pci status register */
1412 _FDT(fdt_setprop_cell(fdt
, offset
, "devsel-speed",
1413 PCI_STATUS_DEVSEL_MASK
& pci_status
));
1415 if (pci_status
& PCI_STATUS_FAST_BACK
) {
1416 _FDT(fdt_setprop(fdt
, offset
, "fast-back-to-back", NULL
, 0));
1418 if (pci_status
& PCI_STATUS_66MHZ
) {
1419 _FDT(fdt_setprop(fdt
, offset
, "66mhz-capable", NULL
, 0));
1421 if (pci_status
& PCI_STATUS_UDF
) {
1422 _FDT(fdt_setprop(fdt
, offset
, "udf-supported", NULL
, 0));
1425 loc_code
= spapr_phb_get_loc_code(sphb
, dev
);
1426 _FDT(fdt_setprop_string(fdt
, offset
, "ibm,loc-code", loc_code
));
1430 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index",
1431 spapr_drc_index(drc
)));
1434 if (msi_present(dev
)) {
1435 uint32_t max_msi
= msi_nr_vectors_allocated(dev
);
1437 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi", max_msi
));
1440 if (msix_present(dev
)) {
1441 uint32_t max_msix
= dev
->msix_entries_nr
;
1443 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi-x", max_msix
));
1447 populate_resource_props(dev
, &rp
);
1448 _FDT(fdt_setprop(fdt
, offset
, "reg", (uint8_t *)rp
.reg
, rp
.reg_len
));
1450 if (sphb
->pcie_ecs
&& pci_is_express(dev
)) {
1451 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,pci-config-space-type", 0x1));
1454 spapr_phb_nvgpu_populate_pcidev_dt(dev
, fdt
, offset
, sphb
);
1456 if (!pc
->is_bridge
) {
1457 /* Properties only for non-bridges */
1458 uint32_t min_grant
= pci_default_read_config(dev
, PCI_MIN_GNT
, 1);
1459 uint32_t max_latency
= pci_default_read_config(dev
, PCI_MAX_LAT
, 1);
1460 _FDT(fdt_setprop_cell(fdt
, offset
, "min-grant", min_grant
));
1461 _FDT(fdt_setprop_cell(fdt
, offset
, "max-latency", max_latency
));
1464 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
1466 return spapr_dt_pci_bus(sphb
, sec_bus
, fdt
, offset
);
1470 /* Callback to be called during DRC release. */
1471 void spapr_phb_remove_pci_device_cb(DeviceState
*dev
)
1473 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
1475 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
1476 object_unparent(OBJECT(dev
));
1479 int spapr_pci_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
1480 void *fdt
, int *fdt_start_offset
, Error
**errp
)
1482 HotplugHandler
*plug_handler
= qdev_get_hotplug_handler(drc
->dev
);
1483 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(plug_handler
);
1484 PCIDevice
*pdev
= PCI_DEVICE(drc
->dev
);
1486 *fdt_start_offset
= spapr_dt_pci_device(sphb
, pdev
, fdt
, 0);
1490 static void spapr_pci_bridge_plug(SpaprPhbState
*phb
,
1494 Error
*local_err
= NULL
;
1495 PCIBus
*bus
= pci_bridge_get_sec_bus(bridge
);
1497 add_drcs(phb
, bus
, &local_err
);
1499 error_propagate(errp
, local_err
);
1504 static void spapr_pci_plug(HotplugHandler
*plug_handler
,
1505 DeviceState
*plugged_dev
, Error
**errp
)
1507 SpaprPhbState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1508 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1509 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(plugged_dev
);
1510 SpaprDrc
*drc
= drc_from_dev(phb
, pdev
);
1511 Error
*local_err
= NULL
;
1512 PCIBus
*bus
= PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
)));
1513 uint32_t slotnr
= PCI_SLOT(pdev
->devfn
);
1515 /* if DR is disabled we don't need to do anything in the case of
1516 * hotplug or coldplug callbacks
1518 if (!phb
->dr_enabled
) {
1519 /* if this is a hotplug operation initiated by the user
1520 * we need to let them know it's not enabled
1522 if (plugged_dev
->hotplugged
) {
1523 error_setg(&local_err
, QERR_BUS_NO_HOTPLUG
,
1524 object_get_typename(OBJECT(phb
)));
1531 if (pc
->is_bridge
) {
1532 spapr_pci_bridge_plug(phb
, PCI_BRIDGE(plugged_dev
), &local_err
);
1534 error_propagate(errp
, local_err
);
1539 /* Following the QEMU convention used for PCIe multifunction
1540 * hotplug, we do not allow functions to be hotplugged to a
1541 * slot that already has function 0 present
1543 if (plugged_dev
->hotplugged
&& bus
->devices
[PCI_DEVFN(slotnr
, 0)] &&
1544 PCI_FUNC(pdev
->devfn
) != 0) {
1545 error_setg(&local_err
, "PCI: slot %d function 0 already ocuppied by %s,"
1546 " additional functions can no longer be exposed to guest.",
1547 slotnr
, bus
->devices
[PCI_DEVFN(slotnr
, 0)]->name
);
1551 spapr_drc_attach(drc
, DEVICE(pdev
), &local_err
);
1556 /* If this is function 0, signal hotplug for all the device functions.
1557 * Otherwise defer sending the hotplug event.
1559 if (!spapr_drc_hotplugged(plugged_dev
)) {
1560 spapr_drc_reset(drc
);
1561 } else if (PCI_FUNC(pdev
->devfn
) == 0) {
1563 uint8_t chassis
= chassis_from_bus(pci_get_bus(pdev
), &local_err
);
1566 error_propagate(errp
, local_err
);
1570 for (i
= 0; i
< 8; i
++) {
1572 SpaprDrcClass
*func_drck
;
1573 SpaprDREntitySense state
;
1575 func_drc
= drc_from_devfn(phb
, chassis
, PCI_DEVFN(slotnr
, i
));
1576 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1577 state
= func_drck
->dr_entity_sense(func_drc
);
1579 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
) {
1580 spapr_hotplug_req_add_by_index(func_drc
);
1586 error_propagate(errp
, local_err
);
1589 static void spapr_pci_bridge_unplug(SpaprPhbState
*phb
,
1593 Error
*local_err
= NULL
;
1594 PCIBus
*bus
= pci_bridge_get_sec_bus(bridge
);
1596 remove_drcs(phb
, bus
, &local_err
);
1598 error_propagate(errp
, local_err
);
1603 static void spapr_pci_unplug(HotplugHandler
*plug_handler
,
1604 DeviceState
*plugged_dev
, Error
**errp
)
1606 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(plugged_dev
);
1607 SpaprPhbState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1609 /* some version guests do not wait for completion of a device
1610 * cleanup (generally done asynchronously by the kernel) before
1611 * signaling to QEMU that the device is safe, but instead sleep
1612 * for some 'safe' period of time. unfortunately on a busy host
1613 * this sleep isn't guaranteed to be long enough, resulting in
1614 * bad things like IRQ lines being left asserted during final
1615 * device removal. to deal with this we call reset just prior
1616 * to finalizing the device, which will put the device back into
1617 * an 'idle' state, as the device cleanup code expects.
1619 pci_device_reset(PCI_DEVICE(plugged_dev
));
1621 if (pc
->is_bridge
) {
1622 Error
*local_err
= NULL
;
1623 spapr_pci_bridge_unplug(phb
, PCI_BRIDGE(plugged_dev
), &local_err
);
1625 error_propagate(errp
, local_err
);
1630 object_property_set_bool(OBJECT(plugged_dev
), false, "realized", NULL
);
1633 static void spapr_pci_unplug_request(HotplugHandler
*plug_handler
,
1634 DeviceState
*plugged_dev
, Error
**errp
)
1636 SpaprPhbState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1637 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1638 SpaprDrc
*drc
= drc_from_dev(phb
, pdev
);
1640 if (!phb
->dr_enabled
) {
1641 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1642 object_get_typename(OBJECT(phb
)));
1647 g_assert(drc
->dev
== plugged_dev
);
1649 if (!spapr_drc_unplug_requested(drc
)) {
1650 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(plugged_dev
);
1651 uint32_t slotnr
= PCI_SLOT(pdev
->devfn
);
1653 SpaprDrcClass
*func_drck
;
1654 SpaprDREntitySense state
;
1656 Error
*local_err
= NULL
;
1657 uint8_t chassis
= chassis_from_bus(pci_get_bus(pdev
), &local_err
);
1660 error_propagate(errp
, local_err
);
1664 if (pc
->is_bridge
) {
1665 error_setg(errp
, "PCI: Hot unplug of PCI bridges not supported");
1668 /* ensure any other present functions are pending unplug */
1669 if (PCI_FUNC(pdev
->devfn
) == 0) {
1670 for (i
= 1; i
< 8; i
++) {
1671 func_drc
= drc_from_devfn(phb
, chassis
, PCI_DEVFN(slotnr
, i
));
1672 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1673 state
= func_drck
->dr_entity_sense(func_drc
);
1674 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
1675 && !spapr_drc_unplug_requested(func_drc
)) {
1677 * Attempting to remove function 0 of a multifunction
1678 * device will will cascade into removing all child
1679 * functions, even if their unplug weren't requested
1682 spapr_drc_detach(func_drc
);
1687 spapr_drc_detach(drc
);
1689 /* if this isn't func 0, defer unplug event. otherwise signal removal
1690 * for all present functions
1692 if (PCI_FUNC(pdev
->devfn
) == 0) {
1693 for (i
= 7; i
>= 0; i
--) {
1694 func_drc
= drc_from_devfn(phb
, chassis
, PCI_DEVFN(slotnr
, i
));
1695 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1696 state
= func_drck
->dr_entity_sense(func_drc
);
1697 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
) {
1698 spapr_hotplug_req_remove_by_index(func_drc
);
1705 static void spapr_phb_finalizefn(Object
*obj
)
1707 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(obj
);
1709 g_free(sphb
->dtbusname
);
1710 sphb
->dtbusname
= NULL
;
1713 static void spapr_phb_unrealize(DeviceState
*dev
, Error
**errp
)
1715 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
1716 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1717 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1718 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(phb
);
1719 SpaprTceTable
*tcet
;
1721 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
1722 Error
*local_err
= NULL
;
1724 spapr_phb_nvgpu_free(sphb
);
1727 g_hash_table_unref(sphb
->msi
);
1732 * Remove IO/MMIO subregions and aliases, rest should get cleaned
1733 * via PHB's unrealize->object_finalize
1735 for (i
= windows_supported
- 1; i
>= 0; i
--) {
1736 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[i
]);
1738 memory_region_del_subregion(&sphb
->iommu_root
,
1739 spapr_tce_get_iommu(tcet
));
1743 remove_drcs(sphb
, phb
->bus
, &local_err
);
1745 error_propagate(errp
, local_err
);
1749 for (i
= PCI_NUM_PINS
- 1; i
>= 0; i
--) {
1750 if (sphb
->lsi_table
[i
].irq
) {
1751 spapr_irq_free(spapr
, sphb
->lsi_table
[i
].irq
, 1);
1752 sphb
->lsi_table
[i
].irq
= 0;
1756 QLIST_REMOVE(sphb
, list
);
1758 memory_region_del_subregion(&sphb
->iommu_root
, &sphb
->msiwindow
);
1761 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have
1762 * unmapped all sections. Remove the listeners now, before destroying the
1765 address_space_remove_listeners(&sphb
->iommu_as
);
1766 address_space_destroy(&sphb
->iommu_as
);
1768 qbus_set_hotplug_handler(BUS(phb
->bus
), NULL
, &error_abort
);
1769 pci_unregister_root_bus(phb
->bus
);
1771 memory_region_del_subregion(get_system_memory(), &sphb
->iowindow
);
1772 if (sphb
->mem64_win_pciaddr
!= (hwaddr
)-1) {
1773 memory_region_del_subregion(get_system_memory(), &sphb
->mem64window
);
1775 memory_region_del_subregion(get_system_memory(), &sphb
->mem32window
);
1778 static void spapr_phb_destroy_msi(gpointer opaque
)
1780 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
1781 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
1782 SpaprPciMsi
*msi
= opaque
;
1784 if (!smc
->legacy_irq_allocation
) {
1785 spapr_irq_msi_free(spapr
, msi
->first_irq
, msi
->num
);
1787 spapr_irq_free(spapr
, msi
->first_irq
, msi
->num
);
1791 static void spapr_phb_realize(DeviceState
*dev
, Error
**errp
)
1793 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
1794 * tries to add a sPAPR PHB to a non-pseries machine.
1796 SpaprMachineState
*spapr
=
1797 (SpaprMachineState
*) object_dynamic_cast(qdev_get_machine(),
1798 TYPE_SPAPR_MACHINE
);
1799 SpaprMachineClass
*smc
= spapr
? SPAPR_MACHINE_GET_CLASS(spapr
) : NULL
;
1800 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1801 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(s
);
1802 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1803 MachineState
*ms
= MACHINE(spapr
);
1807 uint64_t msi_window_size
= 4096;
1808 SpaprTceTable
*tcet
;
1809 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
1810 Error
*local_err
= NULL
;
1813 error_setg(errp
, TYPE_SPAPR_PCI_HOST_BRIDGE
" needs a pseries machine");
1817 assert(sphb
->index
!= (uint32_t)-1); /* checked in spapr_phb_pre_plug() */
1819 if (sphb
->mem64_win_size
!= 0) {
1820 if (sphb
->mem_win_size
> SPAPR_PCI_MEM32_WIN_SIZE
) {
1821 error_setg(errp
, "32-bit memory window of size 0x%"HWADDR_PRIx
1822 " (max 2 GiB)", sphb
->mem_win_size
);
1826 /* 64-bit window defaults to identity mapping */
1827 sphb
->mem64_win_pciaddr
= sphb
->mem64_win_addr
;
1828 } else if (sphb
->mem_win_size
> SPAPR_PCI_MEM32_WIN_SIZE
) {
1830 * For compatibility with old configuration, if no 64-bit MMIO
1831 * window is specified, but the ordinary (32-bit) memory
1832 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1833 * window, with a 64-bit MMIO window following on immediately
1836 sphb
->mem64_win_size
= sphb
->mem_win_size
- SPAPR_PCI_MEM32_WIN_SIZE
;
1837 sphb
->mem64_win_addr
= sphb
->mem_win_addr
+ SPAPR_PCI_MEM32_WIN_SIZE
;
1838 sphb
->mem64_win_pciaddr
=
1839 SPAPR_PCI_MEM_WIN_BUS_OFFSET
+ SPAPR_PCI_MEM32_WIN_SIZE
;
1840 sphb
->mem_win_size
= SPAPR_PCI_MEM32_WIN_SIZE
;
1843 if (spapr_pci_find_phb(spapr
, sphb
->buid
)) {
1846 error_setg(errp
, "PCI host bridges must have unique indexes");
1847 error_append_hint(errp
, "The following indexes are already in use:");
1848 QLIST_FOREACH(s
, &spapr
->phbs
, list
) {
1849 error_append_hint(errp
, " %d", s
->index
);
1851 error_append_hint(errp
, "\nTry another value for the index property\n");
1855 if (sphb
->numa_node
!= -1 &&
1856 (sphb
->numa_node
>= MAX_NODES
||
1857 !ms
->numa_state
->nodes
[sphb
->numa_node
].present
)) {
1858 error_setg(errp
, "Invalid NUMA node ID for PCI host bridge");
1862 sphb
->dtbusname
= g_strdup_printf("pci@%" PRIx64
, sphb
->buid
);
1864 /* Initialize memory regions */
1865 namebuf
= g_strdup_printf("%s.mmio", sphb
->dtbusname
);
1866 memory_region_init(&sphb
->memspace
, OBJECT(sphb
), namebuf
, UINT64_MAX
);
1869 namebuf
= g_strdup_printf("%s.mmio32-alias", sphb
->dtbusname
);
1870 memory_region_init_alias(&sphb
->mem32window
, OBJECT(sphb
),
1871 namebuf
, &sphb
->memspace
,
1872 SPAPR_PCI_MEM_WIN_BUS_OFFSET
, sphb
->mem_win_size
);
1874 memory_region_add_subregion(get_system_memory(), sphb
->mem_win_addr
,
1875 &sphb
->mem32window
);
1877 if (sphb
->mem64_win_size
!= 0) {
1878 namebuf
= g_strdup_printf("%s.mmio64-alias", sphb
->dtbusname
);
1879 memory_region_init_alias(&sphb
->mem64window
, OBJECT(sphb
),
1880 namebuf
, &sphb
->memspace
,
1881 sphb
->mem64_win_pciaddr
, sphb
->mem64_win_size
);
1884 memory_region_add_subregion(get_system_memory(),
1885 sphb
->mem64_win_addr
,
1886 &sphb
->mem64window
);
1889 /* Initialize IO regions */
1890 namebuf
= g_strdup_printf("%s.io", sphb
->dtbusname
);
1891 memory_region_init(&sphb
->iospace
, OBJECT(sphb
),
1892 namebuf
, SPAPR_PCI_IO_WIN_SIZE
);
1895 namebuf
= g_strdup_printf("%s.io-alias", sphb
->dtbusname
);
1896 memory_region_init_alias(&sphb
->iowindow
, OBJECT(sphb
), namebuf
,
1897 &sphb
->iospace
, 0, SPAPR_PCI_IO_WIN_SIZE
);
1899 memory_region_add_subregion(get_system_memory(), sphb
->io_win_addr
,
1902 bus
= pci_register_root_bus(dev
, NULL
,
1903 pci_spapr_set_irq
, pci_swizzle_map_irq_fn
, sphb
,
1904 &sphb
->memspace
, &sphb
->iospace
,
1905 PCI_DEVFN(0, 0), PCI_NUM_PINS
,
1909 * Despite resembling a vanilla PCI bus in most ways, the PAPR
1910 * para-virtualized PCI bus *does* permit PCI-E extended config
1913 if (sphb
->pcie_ecs
) {
1914 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
1917 qbus_set_hotplug_handler(BUS(phb
->bus
), OBJECT(sphb
), NULL
);
1920 * Initialize PHB address space.
1921 * By default there will be at least one subregion for default
1923 * Later the guest might want to create another DMA window
1924 * which will become another memory subregion.
1926 namebuf
= g_strdup_printf("%s.iommu-root", sphb
->dtbusname
);
1927 memory_region_init(&sphb
->iommu_root
, OBJECT(sphb
),
1928 namebuf
, UINT64_MAX
);
1930 address_space_init(&sphb
->iommu_as
, &sphb
->iommu_root
,
1934 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1935 * we need to allocate some memory to catch those writes coming
1936 * from msi_notify()/msix_notify().
1937 * As MSIMessage:addr is going to be the same and MSIMessage:data
1938 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1941 * For KVM we want to ensure that this memory is a full page so that
1942 * our memory slot is of page size granularity.
1944 if (kvm_enabled()) {
1945 msi_window_size
= qemu_real_host_page_size
;
1948 memory_region_init_io(&sphb
->msiwindow
, OBJECT(sphb
), &spapr_msi_ops
, spapr
,
1949 "msi", msi_window_size
);
1950 memory_region_add_subregion(&sphb
->iommu_root
, SPAPR_PCI_MSI_WINDOW
,
1953 pci_setup_iommu(bus
, spapr_pci_dma_iommu
, sphb
);
1955 pci_bus_set_route_irq_fn(bus
, spapr_route_intx_pin_to_irq
);
1957 QLIST_INSERT_HEAD(&spapr
->phbs
, sphb
, list
);
1959 /* Initialize the LSI table */
1960 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
1961 uint32_t irq
= SPAPR_IRQ_PCI_LSI
+ sphb
->index
* PCI_NUM_PINS
+ i
;
1963 if (smc
->legacy_irq_allocation
) {
1964 irq
= spapr_irq_findone(spapr
, &local_err
);
1966 error_propagate_prepend(errp
, local_err
,
1967 "can't allocate LSIs: ");
1969 * Older machines will never support PHB hotplug, ie, this is an
1970 * init only path and QEMU will terminate. No need to rollback.
1976 spapr_irq_claim(spapr
, irq
, true, &local_err
);
1978 error_propagate_prepend(errp
, local_err
, "can't allocate LSIs: ");
1982 sphb
->lsi_table
[i
].irq
= irq
;
1985 /* allocate connectors for child PCI devices */
1986 add_drcs(sphb
, phb
->bus
, &local_err
);
1988 error_propagate(errp
, local_err
);
1993 for (i
= 0; i
< windows_supported
; ++i
) {
1994 tcet
= spapr_tce_new_table(DEVICE(sphb
), sphb
->dma_liobn
[i
]);
1996 error_setg(errp
, "Creating window#%d failed for %s",
1997 i
, sphb
->dtbusname
);
2000 memory_region_add_subregion(&sphb
->iommu_root
, 0,
2001 spapr_tce_get_iommu(tcet
));
2004 sphb
->msi
= g_hash_table_new_full(g_int_hash
, g_int_equal
, g_free
,
2005 spapr_phb_destroy_msi
);
2009 spapr_phb_unrealize(dev
, NULL
);
2012 static int spapr_phb_children_reset(Object
*child
, void *opaque
)
2014 DeviceState
*dev
= (DeviceState
*) object_dynamic_cast(child
, TYPE_DEVICE
);
2023 void spapr_phb_dma_reset(SpaprPhbState
*sphb
)
2026 SpaprTceTable
*tcet
;
2028 for (i
= 0; i
< SPAPR_PCI_DMA_MAX_WINDOWS
; ++i
) {
2029 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[i
]);
2031 if (tcet
&& tcet
->nb_table
) {
2032 spapr_tce_table_disable(tcet
);
2036 /* Register default 32bit DMA window */
2037 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[0]);
2038 spapr_tce_table_enable(tcet
, SPAPR_TCE_PAGE_SHIFT
, sphb
->dma_win_addr
,
2039 sphb
->dma_win_size
>> SPAPR_TCE_PAGE_SHIFT
);
2042 static void spapr_phb_reset(DeviceState
*qdev
)
2044 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(qdev
);
2047 spapr_phb_dma_reset(sphb
);
2048 spapr_phb_nvgpu_free(sphb
);
2049 spapr_phb_nvgpu_setup(sphb
, &err
);
2051 error_report_err(err
);
2054 /* Reset the IOMMU state */
2055 object_child_foreach(OBJECT(qdev
), spapr_phb_children_reset
, NULL
);
2057 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev
))) {
2058 spapr_phb_vfio_reset(qdev
);
2061 g_hash_table_remove_all(sphb
->msi
);
2064 static Property spapr_phb_properties
[] = {
2065 DEFINE_PROP_UINT32("index", SpaprPhbState
, index
, -1),
2066 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState
, mem_win_size
,
2067 SPAPR_PCI_MEM32_WIN_SIZE
),
2068 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState
, mem64_win_size
,
2069 SPAPR_PCI_MEM64_WIN_SIZE
),
2070 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState
, io_win_size
,
2071 SPAPR_PCI_IO_WIN_SIZE
),
2072 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState
, dr_enabled
,
2074 /* Default DMA window is 0..1GB */
2075 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState
, dma_win_addr
, 0),
2076 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState
, dma_win_size
, 0x40000000),
2077 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState
, dma64_win_addr
,
2078 0x800000000000000ULL
),
2079 DEFINE_PROP_BOOL("ddw", SpaprPhbState
, ddw_enabled
, true),
2080 DEFINE_PROP_UINT64("pgsz", SpaprPhbState
, page_size_mask
,
2081 (1ULL << 12) | (1ULL << 16)
2082 | (1ULL << 21) | (1ULL << 24)),
2083 DEFINE_PROP_UINT32("numa_node", SpaprPhbState
, numa_node
, -1),
2084 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState
,
2085 pre_2_8_migration
, false),
2086 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState
,
2088 DEFINE_PROP_UINT64("gpa", SpaprPhbState
, nv2_gpa_win_addr
, 0),
2089 DEFINE_PROP_UINT64("atsd", SpaprPhbState
, nv2_atsd_win_addr
, 0),
2090 DEFINE_PROP_END_OF_LIST(),
2093 static const VMStateDescription vmstate_spapr_pci_lsi
= {
2094 .name
= "spapr_pci/lsi",
2096 .minimum_version_id
= 1,
2097 .fields
= (VMStateField
[]) {
2098 VMSTATE_UINT32_EQUAL(irq
, SpaprPciLsi
, NULL
),
2100 VMSTATE_END_OF_LIST()
2104 static const VMStateDescription vmstate_spapr_pci_msi
= {
2105 .name
= "spapr_pci/msi",
2107 .minimum_version_id
= 1,
2108 .fields
= (VMStateField
[]) {
2109 VMSTATE_UINT32(key
, SpaprPciMsiMig
),
2110 VMSTATE_UINT32(value
.first_irq
, SpaprPciMsiMig
),
2111 VMSTATE_UINT32(value
.num
, SpaprPciMsiMig
),
2112 VMSTATE_END_OF_LIST()
2116 static int spapr_pci_pre_save(void *opaque
)
2118 SpaprPhbState
*sphb
= opaque
;
2119 GHashTableIter iter
;
2120 gpointer key
, value
;
2123 if (sphb
->pre_2_8_migration
) {
2124 sphb
->mig_liobn
= sphb
->dma_liobn
[0];
2125 sphb
->mig_mem_win_addr
= sphb
->mem_win_addr
;
2126 sphb
->mig_mem_win_size
= sphb
->mem_win_size
;
2127 sphb
->mig_io_win_addr
= sphb
->io_win_addr
;
2128 sphb
->mig_io_win_size
= sphb
->io_win_size
;
2130 if ((sphb
->mem64_win_size
!= 0)
2131 && (sphb
->mem64_win_addr
2132 == (sphb
->mem_win_addr
+ sphb
->mem_win_size
))) {
2133 sphb
->mig_mem_win_size
+= sphb
->mem64_win_size
;
2137 g_free(sphb
->msi_devs
);
2138 sphb
->msi_devs
= NULL
;
2139 sphb
->msi_devs_num
= g_hash_table_size(sphb
->msi
);
2140 if (!sphb
->msi_devs_num
) {
2143 sphb
->msi_devs
= g_new(SpaprPciMsiMig
, sphb
->msi_devs_num
);
2145 g_hash_table_iter_init(&iter
, sphb
->msi
);
2146 for (i
= 0; g_hash_table_iter_next(&iter
, &key
, &value
); ++i
) {
2147 sphb
->msi_devs
[i
].key
= *(uint32_t *) key
;
2148 sphb
->msi_devs
[i
].value
= *(SpaprPciMsi
*) value
;
2154 static int spapr_pci_post_load(void *opaque
, int version_id
)
2156 SpaprPhbState
*sphb
= opaque
;
2157 gpointer key
, value
;
2160 for (i
= 0; i
< sphb
->msi_devs_num
; ++i
) {
2161 key
= g_memdup(&sphb
->msi_devs
[i
].key
,
2162 sizeof(sphb
->msi_devs
[i
].key
));
2163 value
= g_memdup(&sphb
->msi_devs
[i
].value
,
2164 sizeof(sphb
->msi_devs
[i
].value
));
2165 g_hash_table_insert(sphb
->msi
, key
, value
);
2167 g_free(sphb
->msi_devs
);
2168 sphb
->msi_devs
= NULL
;
2169 sphb
->msi_devs_num
= 0;
2174 static bool pre_2_8_migration(void *opaque
, int version_id
)
2176 SpaprPhbState
*sphb
= opaque
;
2178 return sphb
->pre_2_8_migration
;
2181 static const VMStateDescription vmstate_spapr_pci
= {
2182 .name
= "spapr_pci",
2184 .minimum_version_id
= 2,
2185 .pre_save
= spapr_pci_pre_save
,
2186 .post_load
= spapr_pci_post_load
,
2187 .fields
= (VMStateField
[]) {
2188 VMSTATE_UINT64_EQUAL(buid
, SpaprPhbState
, NULL
),
2189 VMSTATE_UINT32_TEST(mig_liobn
, SpaprPhbState
, pre_2_8_migration
),
2190 VMSTATE_UINT64_TEST(mig_mem_win_addr
, SpaprPhbState
, pre_2_8_migration
),
2191 VMSTATE_UINT64_TEST(mig_mem_win_size
, SpaprPhbState
, pre_2_8_migration
),
2192 VMSTATE_UINT64_TEST(mig_io_win_addr
, SpaprPhbState
, pre_2_8_migration
),
2193 VMSTATE_UINT64_TEST(mig_io_win_size
, SpaprPhbState
, pre_2_8_migration
),
2194 VMSTATE_STRUCT_ARRAY(lsi_table
, SpaprPhbState
, PCI_NUM_PINS
, 0,
2195 vmstate_spapr_pci_lsi
, SpaprPciLsi
),
2196 VMSTATE_INT32(msi_devs_num
, SpaprPhbState
),
2197 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs
, SpaprPhbState
, msi_devs_num
, 0,
2198 vmstate_spapr_pci_msi
, SpaprPciMsiMig
),
2199 VMSTATE_END_OF_LIST()
2203 static const char *spapr_phb_root_bus_path(PCIHostState
*host_bridge
,
2206 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(host_bridge
);
2208 return sphb
->dtbusname
;
2211 static void spapr_phb_class_init(ObjectClass
*klass
, void *data
)
2213 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
2214 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2215 HotplugHandlerClass
*hp
= HOTPLUG_HANDLER_CLASS(klass
);
2217 hc
->root_bus_path
= spapr_phb_root_bus_path
;
2218 dc
->realize
= spapr_phb_realize
;
2219 dc
->unrealize
= spapr_phb_unrealize
;
2220 dc
->props
= spapr_phb_properties
;
2221 dc
->reset
= spapr_phb_reset
;
2222 dc
->vmsd
= &vmstate_spapr_pci
;
2223 /* Supported by TYPE_SPAPR_MACHINE */
2224 dc
->user_creatable
= true;
2225 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
2226 hp
->plug
= spapr_pci_plug
;
2227 hp
->unplug
= spapr_pci_unplug
;
2228 hp
->unplug_request
= spapr_pci_unplug_request
;
2231 static const TypeInfo spapr_phb_info
= {
2232 .name
= TYPE_SPAPR_PCI_HOST_BRIDGE
,
2233 .parent
= TYPE_PCI_HOST_BRIDGE
,
2234 .instance_size
= sizeof(SpaprPhbState
),
2235 .instance_finalize
= spapr_phb_finalizefn
,
2236 .class_init
= spapr_phb_class_init
,
2237 .interfaces
= (InterfaceInfo
[]) {
2238 { TYPE_HOTPLUG_HANDLER
},
2243 static void spapr_phb_pci_enumerate_bridge(PCIBus
*bus
, PCIDevice
*pdev
,
2246 unsigned int *bus_no
= opaque
;
2247 PCIBus
*sec_bus
= NULL
;
2249 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
2250 PCI_HEADER_TYPE_BRIDGE
)) {
2255 pci_default_write_config(pdev
, PCI_PRIMARY_BUS
, pci_dev_bus_num(pdev
), 1);
2256 pci_default_write_config(pdev
, PCI_SECONDARY_BUS
, *bus_no
, 1);
2257 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
2259 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
2264 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
2265 spapr_phb_pci_enumerate_bridge
, bus_no
);
2266 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
2269 static void spapr_phb_pci_enumerate(SpaprPhbState
*phb
)
2271 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
2272 unsigned int bus_no
= 0;
2274 pci_for_each_device(bus
, pci_bus_num(bus
),
2275 spapr_phb_pci_enumerate_bridge
,
2280 int spapr_dt_phb(SpaprMachineState
*spapr
, SpaprPhbState
*phb
,
2281 uint32_t intc_phandle
, void *fdt
, int *node_offset
)
2283 int bus_off
, i
, j
, ret
;
2284 uint32_t bus_range
[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2290 } QEMU_PACKED ranges
[] = {
2292 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2293 cpu_to_be64(phb
->io_win_addr
),
2294 cpu_to_be64(memory_region_size(&phb
->iospace
)),
2297 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET
),
2298 cpu_to_be64(phb
->mem_win_addr
),
2299 cpu_to_be64(phb
->mem_win_size
),
2302 cpu_to_be32(b_ss(3)), cpu_to_be64(phb
->mem64_win_pciaddr
),
2303 cpu_to_be64(phb
->mem64_win_addr
),
2304 cpu_to_be64(phb
->mem64_win_size
),
2307 const unsigned sizeof_ranges
=
2308 (phb
->mem64_win_size
? 3 : 2) * sizeof(ranges
[0]);
2309 uint64_t bus_reg
[] = { cpu_to_be64(phb
->buid
), 0 };
2310 uint32_t interrupt_map_mask
[] = {
2311 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2312 uint32_t interrupt_map
[PCI_SLOT_MAX
* PCI_NUM_PINS
][7];
2313 uint32_t ddw_applicable
[] = {
2314 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW
),
2315 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW
),
2316 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW
)
2318 uint32_t ddw_extensions
[] = {
2320 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW
)
2322 uint32_t associativity
[] = {cpu_to_be32(0x4),
2326 cpu_to_be32(phb
->numa_node
)};
2327 SpaprTceTable
*tcet
;
2331 /* Start populating the FDT */
2332 _FDT(bus_off
= fdt_add_subnode(fdt
, 0, phb
->dtbusname
));
2334 *node_offset
= bus_off
;
2337 /* Write PHB properties */
2338 _FDT(fdt_setprop_string(fdt
, bus_off
, "device_type", "pci"));
2339 _FDT(fdt_setprop_string(fdt
, bus_off
, "compatible", "IBM,Logical_PHB"));
2340 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#interrupt-cells", 0x1));
2341 _FDT(fdt_setprop(fdt
, bus_off
, "used-by-rtas", NULL
, 0));
2342 _FDT(fdt_setprop(fdt
, bus_off
, "bus-range", &bus_range
, sizeof(bus_range
)));
2343 _FDT(fdt_setprop(fdt
, bus_off
, "ranges", &ranges
, sizeof_ranges
));
2344 _FDT(fdt_setprop(fdt
, bus_off
, "reg", &bus_reg
, sizeof(bus_reg
)));
2345 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pci-config-space-type", 0x1));
2346 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pe-total-#msi",
2347 spapr_irq_nr_msis(spapr
)));
2349 /* Dynamic DMA window */
2350 if (phb
->ddw_enabled
) {
2351 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,ddw-applicable", &ddw_applicable
,
2352 sizeof(ddw_applicable
)));
2353 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,ddw-extensions",
2354 &ddw_extensions
, sizeof(ddw_extensions
)));
2357 /* Advertise NUMA via ibm,associativity */
2358 if (phb
->numa_node
!= -1) {
2359 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,associativity", associativity
,
2360 sizeof(associativity
)));
2363 /* Build the interrupt-map, this must matches what is done
2364 * in pci_swizzle_map_irq_fn
2366 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map-mask",
2367 &interrupt_map_mask
, sizeof(interrupt_map_mask
)));
2368 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
2369 for (j
= 0; j
< PCI_NUM_PINS
; j
++) {
2370 uint32_t *irqmap
= interrupt_map
[i
*PCI_NUM_PINS
+ j
];
2371 int lsi_num
= pci_swizzle(i
, j
);
2373 irqmap
[0] = cpu_to_be32(b_ddddd(i
)|b_fff(0));
2376 irqmap
[3] = cpu_to_be32(j
+1);
2377 irqmap
[4] = cpu_to_be32(intc_phandle
);
2378 spapr_dt_irq(&irqmap
[5], phb
->lsi_table
[lsi_num
].irq
, true);
2381 /* Write interrupt map */
2382 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map", &interrupt_map
,
2383 sizeof(interrupt_map
)));
2385 tcet
= spapr_tce_find_by_liobn(phb
->dma_liobn
[0]);
2389 spapr_dma_dt(fdt
, bus_off
, "ibm,dma-window",
2390 tcet
->liobn
, tcet
->bus_offset
,
2391 tcet
->nb_table
<< tcet
->page_shift
);
2393 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, phb
->index
);
2395 uint32_t drc_index
= cpu_to_be32(spapr_drc_index(drc
));
2397 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,my-drc-index", &drc_index
,
2398 sizeof(drc_index
)));
2401 /* Walk the bridges and program the bus numbers*/
2402 spapr_phb_pci_enumerate(phb
);
2403 _FDT(fdt_setprop_cell(fdt
, bus_off
, "qemu,phb-enumerated", 0x1));
2405 /* Walk the bridge and subordinate buses */
2406 ret
= spapr_dt_pci_bus(phb
, PCI_HOST_BRIDGE(phb
)->bus
, fdt
, bus_off
);
2411 spapr_phb_nvgpu_populate_dt(phb
, fdt
, bus_off
, &err
);
2413 error_report_err(err
);
2415 spapr_phb_nvgpu_ram_populate_dt(phb
, fdt
);
2420 void spapr_pci_rtas_init(void)
2422 spapr_rtas_register(RTAS_READ_PCI_CONFIG
, "read-pci-config",
2423 rtas_read_pci_config
);
2424 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG
, "write-pci-config",
2425 rtas_write_pci_config
);
2426 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG
, "ibm,read-pci-config",
2427 rtas_ibm_read_pci_config
);
2428 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG
, "ibm,write-pci-config",
2429 rtas_ibm_write_pci_config
);
2430 if (msi_nonbroken
) {
2431 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER
,
2432 "ibm,query-interrupt-source-number",
2433 rtas_ibm_query_interrupt_source_number
);
2434 spapr_rtas_register(RTAS_IBM_CHANGE_MSI
, "ibm,change-msi",
2435 rtas_ibm_change_msi
);
2438 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION
,
2439 "ibm,set-eeh-option",
2440 rtas_ibm_set_eeh_option
);
2441 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2
,
2442 "ibm,get-config-addr-info2",
2443 rtas_ibm_get_config_addr_info2
);
2444 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2
,
2445 "ibm,read-slot-reset-state2",
2446 rtas_ibm_read_slot_reset_state2
);
2447 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET
,
2448 "ibm,set-slot-reset",
2449 rtas_ibm_set_slot_reset
);
2450 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE
,
2452 rtas_ibm_configure_pe
);
2453 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL
,
2454 "ibm,slot-error-detail",
2455 rtas_ibm_slot_error_detail
);
2458 static void spapr_pci_register_types(void)
2460 type_register_static(&spapr_phb_info
);
2463 type_init(spapr_pci_register_types
)
2465 static int spapr_switch_one_vga(DeviceState
*dev
, void *opaque
)
2467 bool be
= *(bool *)opaque
;
2469 if (object_dynamic_cast(OBJECT(dev
), "VGA")
2470 || object_dynamic_cast(OBJECT(dev
), "secondary-vga")) {
2471 object_property_set_bool(OBJECT(dev
), be
, "big-endian-framebuffer",
2477 void spapr_pci_switch_vga(bool big_endian
)
2479 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
2480 SpaprPhbState
*sphb
;
2483 * For backward compatibility with existing guests, we switch
2484 * the endianness of the VGA controller when changing the guest
2487 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
2488 BusState
*bus
= &PCI_HOST_BRIDGE(sphb
)->bus
->qbus
;
2489 qbus_walk_children(bus
, spapr_switch_one_vga
, NULL
, NULL
, NULL
,