1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
4 #include "exec/translator.h"
9 typedef struct DisasContext
{
10 DisasContextBase base
;
11 const ARMISARegisters
*isar
;
13 /* The address of the current instruction being translated. */
15 target_ulong page_start
;
17 /* Nonzero if this instruction has been conditionally skipped. */
19 /* The label that will be jumped to when the instruction is skipped. */
21 /* Thumb-2 conditional execution bits. */
27 #if !defined(CONFIG_USER_ONLY)
30 ARMMMUIdx mmu_idx
; /* MMU index to use for normal loads/stores */
31 uint8_t tbii
; /* TBI1|TBI0 for insns */
32 uint8_t tbid
; /* TBI1|TBI0 for data */
33 bool ns
; /* Use non-secure CPREG bank on access */
34 int fp_excp_el
; /* FP exception EL or 0 if enabled */
35 int sve_excp_el
; /* SVE exception EL or 0 if enabled */
36 int sve_len
; /* SVE vector length in bytes */
37 /* Flag indicating that exceptions from secure mode are routed to EL3. */
38 bool secure_routed_to_el3
;
39 bool vfp_enabled
; /* FP enabled via FPSCR.EN */
42 bool v7m_handler_mode
;
43 bool v8m_secure
; /* true if v8M and we're in Secure mode */
44 bool v8m_stackcheck
; /* true if we need to perform v8M stack limit checks */
45 bool v8m_fpccr_s_wrong
; /* true if v8M FPCCR.S != v8m_secure */
46 bool v7m_new_fp_ctxt_needed
; /* ASPEN set but no active FP context */
47 bool v7m_lspact
; /* FPCCR.LSPACT set */
48 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
49 * so that top level loop can generate correct syndrome information.
54 /* Debug target exception level for single-step exceptions */
57 uint64_t features
; /* CPU features bits */
58 /* Because unallocated encodings generate different exception syndrome
59 * information from traps due to FP being disabled, we can't do a single
60 * "is fp access disabled" check at a high level in the decode tree.
61 * To help in catching bugs where the access check was forgotten in some
62 * code path, we set this flag when the access check is done, and assert
63 * that it is set at the point where we actually touch the FP regs.
65 bool fp_access_checked
;
66 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
67 * single-step support).
71 /* True if the insn just emitted was a load-exclusive instruction
72 * (necessary for syndrome information for single step exceptions),
73 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
76 /* True if AccType_UNPRIV should be used for LDTR et al */
78 /* True if v8.3-PAuth is active. */
80 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */
82 /* True if any CP15 access is trapped by HSTR_EL2 */
85 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
86 * < 0, set by the current instruction.
89 /* True if this page is guarded. */
91 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
93 /* TCG op of the current insn_start. */
95 #define TMP_A64_MAX 16
97 TCGv_i64 tmp_a64
[TMP_A64_MAX
];
100 typedef struct DisasCompare
{
106 /* Share the TCG temporaries common between 32 and 64 bit modes. */
107 extern TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
108 extern TCGv_i64 cpu_exclusive_addr
;
109 extern TCGv_i64 cpu_exclusive_val
;
111 static inline int arm_dc_feature(DisasContext
*dc
, int feature
)
113 return (dc
->features
& (1ULL << feature
)) != 0;
116 static inline int get_mem_index(DisasContext
*s
)
118 return arm_to_core_mmu_idx(s
->mmu_idx
);
121 /* Function used to determine the target exception EL when otherwise not known
124 static inline int default_exception_el(DisasContext
*s
)
126 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
127 * there is no secure EL1, so we route exceptions to EL3. Otherwise,
128 * exceptions can only be routed to ELs above 1, so we target the higher of
129 * 1 or the current EL.
131 return (s
->mmu_idx
== ARMMMUIdx_SE10_0
&& s
->secure_routed_to_el3
)
132 ? 3 : MAX(1, s
->current_el
);
135 static inline void disas_set_insn_syndrome(DisasContext
*s
, uint32_t syn
)
137 /* We don't need to save all of the syndrome so we mask and shift
138 * out unneeded bits to help the sleb128 encoder do a better job.
140 syn
&= ARM_INSN_START_WORD2_MASK
;
141 syn
>>= ARM_INSN_START_WORD2_SHIFT
;
143 /* We check and clear insn_start_idx to catch multiple updates. */
144 assert(s
->insn_start
!= NULL
);
145 tcg_set_insn_start_param(s
->insn_start
, 2, syn
);
146 s
->insn_start
= NULL
;
149 /* is_jmp field values */
150 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
151 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
152 /* These instructions trap after executing, so the A32/T32 decoder must
153 * defer them until after the conditional execution state has been updated.
154 * WFI also needs special handling when single-stepping.
156 #define DISAS_WFI DISAS_TARGET_2
157 #define DISAS_SWI DISAS_TARGET_3
159 #define DISAS_WFE DISAS_TARGET_4
160 #define DISAS_HVC DISAS_TARGET_5
161 #define DISAS_SMC DISAS_TARGET_6
162 #define DISAS_YIELD DISAS_TARGET_7
163 /* M profile branch which might be an exception return (and so needs
164 * custom end-of-TB code)
166 #define DISAS_BX_EXCRET DISAS_TARGET_8
167 /* For instructions which want an immediate exit to the main loop,
168 * as opposed to attempting to use lookup_and_goto_ptr. Unlike
169 * DISAS_UPDATE this doesn't write the PC on exiting the translation
170 * loop so you need to ensure something (gen_a64_set_pc_im or runtime
171 * helper) has done so before we reach return from cpu_tb_exec.
173 #define DISAS_EXIT DISAS_TARGET_9
175 #ifdef TARGET_AARCH64
176 void a64_translate_init(void);
177 void gen_a64_set_pc_im(uint64_t val
);
178 extern const TranslatorOps aarch64_translator_ops
;
180 static inline void a64_translate_init(void)
184 static inline void gen_a64_set_pc_im(uint64_t val
)
189 void arm_test_cc(DisasCompare
*cmp
, int cc
);
190 void arm_free_cc(DisasCompare
*cmp
);
191 void arm_jump_cc(DisasCompare
*cmp
, TCGLabel
*label
);
192 void arm_gen_test_cc(int cc
, TCGLabel
*label
);
194 /* Return state of Alternate Half-precision flag, caller frees result */
195 static inline TCGv_i32
get_ahp_flag(void)
197 TCGv_i32 ret
= tcg_temp_new_i32();
199 tcg_gen_ld_i32(ret
, cpu_env
,
200 offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPSCR
]));
201 tcg_gen_extract_i32(ret
, ret
, 26, 1);
206 /* Set bits within PSTATE. */
207 static inline void set_pstate_bits(uint32_t bits
)
209 TCGv_i32 p
= tcg_temp_new_i32();
211 tcg_debug_assert(!(bits
& CACHED_PSTATE_BITS
));
213 tcg_gen_ld_i32(p
, cpu_env
, offsetof(CPUARMState
, pstate
));
214 tcg_gen_ori_i32(p
, p
, bits
);
215 tcg_gen_st_i32(p
, cpu_env
, offsetof(CPUARMState
, pstate
));
216 tcg_temp_free_i32(p
);
219 /* Clear bits within PSTATE. */
220 static inline void clear_pstate_bits(uint32_t bits
)
222 TCGv_i32 p
= tcg_temp_new_i32();
224 tcg_debug_assert(!(bits
& CACHED_PSTATE_BITS
));
226 tcg_gen_ld_i32(p
, cpu_env
, offsetof(CPUARMState
, pstate
));
227 tcg_gen_andi_i32(p
, p
, ~bits
);
228 tcg_gen_st_i32(p
, cpu_env
, offsetof(CPUARMState
, pstate
));
229 tcg_temp_free_i32(p
);
232 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
233 static inline void gen_ss_advance(DisasContext
*s
)
237 clear_pstate_bits(PSTATE_SS
);
241 static inline void gen_exception(int excp
, uint32_t syndrome
,
244 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
245 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
246 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
248 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
251 tcg_temp_free_i32(tcg_el
);
252 tcg_temp_free_i32(tcg_syn
);
253 tcg_temp_free_i32(tcg_excp
);
256 /* Generate an architectural singlestep exception */
257 static inline void gen_swstep_exception(DisasContext
*s
, int isv
, int ex
)
259 bool same_el
= (s
->debug_target_el
== s
->current_el
);
262 * If singlestep is targeting a lower EL than the current one,
263 * then s->ss_active must be false and we can never get here.
265 assert(s
->debug_target_el
>= s
->current_el
);
267 gen_exception(EXCP_UDEF
, syn_swstep(same_el
, isv
, ex
), s
->debug_target_el
);
271 * Given a VFP floating point constant encoded into an 8 bit immediate in an
272 * instruction, expand it to the actual constant value of the specified
273 * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
275 uint64_t vfp_expand_imm(int size
, uint8_t imm8
);
277 /* Vector operations shared between ARM and AArch64. */
278 void gen_gvec_ceq0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
279 uint32_t opr_sz
, uint32_t max_sz
);
280 void gen_gvec_clt0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
281 uint32_t opr_sz
, uint32_t max_sz
);
282 void gen_gvec_cgt0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
283 uint32_t opr_sz
, uint32_t max_sz
);
284 void gen_gvec_cle0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
285 uint32_t opr_sz
, uint32_t max_sz
);
286 void gen_gvec_cge0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
287 uint32_t opr_sz
, uint32_t max_sz
);
289 void gen_gvec_mla(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
290 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
291 void gen_gvec_mls(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
292 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
294 void gen_gvec_cmtst(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
295 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
296 void gen_gvec_sshl(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
297 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
298 void gen_gvec_ushl(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
299 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
301 void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
302 void gen_ushl_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
);
303 void gen_sshl_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
);
304 void gen_ushl_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
305 void gen_sshl_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
307 void gen_gvec_uqadd_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
308 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
309 void gen_gvec_sqadd_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
310 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
311 void gen_gvec_uqsub_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
312 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
313 void gen_gvec_sqsub_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
314 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
316 void gen_gvec_ssra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
317 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
318 void gen_gvec_usra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
319 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
321 void gen_gvec_srshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
322 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
323 void gen_gvec_urshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
324 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
325 void gen_gvec_srsra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
326 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
327 void gen_gvec_ursra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
328 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
330 void gen_gvec_sri(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
331 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
332 void gen_gvec_sli(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
333 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
335 void gen_gvec_sqrdmlah_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
336 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
337 void gen_gvec_sqrdmlsh_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
338 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
340 void gen_gvec_sabd(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
341 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
342 void gen_gvec_uabd(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
343 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
345 void gen_gvec_saba(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
346 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
347 void gen_gvec_uaba(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
348 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
351 * Forward to the isar_feature_* tests given a DisasContext pointer.
353 #define dc_isar_feature(name, ctx) \
354 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
356 /* Note that the gvec expanders operate on offsets + sizes. */
357 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
358 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
360 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
361 uint32_t, uint32_t, uint32_t);
362 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
363 uint32_t, uint32_t, uint32_t);
365 /* Function prototype for gen_ functions for calling Neon helpers */
366 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
367 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
368 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
369 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
370 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
371 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
372 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
373 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
374 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
375 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
376 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
377 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
378 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
379 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
380 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, MemOp
);
382 #endif /* TARGET_ARM_TRANSLATE_H */