2 * Copyright (C) 2014-2016 Broadcom Corporation
3 * Copyright (c) 2017 Red Hat, Inc.
4 * Written by Prem Mallappa, Eric Auger
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "hw/sysbus.h"
22 #include "migration/vmstate.h"
23 #include "hw/qdev-core.h"
24 #include "hw/pci/pci.h"
25 #include "exec/address-spaces.h"
29 #include "qemu/error-report.h"
30 #include "qapi/error.h"
32 #include "hw/arm/smmuv3.h"
33 #include "smmuv3-internal.h"
36 * smmuv3_trigger_irq - pulse @irq if enabled and update
37 * GERROR register in case of GERROR interrupt
40 * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
42 static void smmuv3_trigger_irq(SMMUv3State
*s
, SMMUIrq irq
,
50 pulse
= smmuv3_eventq_irq_enabled(s
);
53 qemu_log_mask(LOG_UNIMP
, "PRI not yet supported\n");
55 case SMMU_IRQ_CMD_SYNC
:
60 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
61 uint32_t new_gerrors
= ~pending
& gerror_mask
;
64 /* only toggle non pending errors */
67 s
->gerror
^= new_gerrors
;
68 trace_smmuv3_write_gerror(new_gerrors
, s
->gerror
);
70 pulse
= smmuv3_gerror_irq_enabled(s
);
75 trace_smmuv3_trigger_irq(irq
);
76 qemu_irq_pulse(s
->irq
[irq
]);
80 static void smmuv3_write_gerrorn(SMMUv3State
*s
, uint32_t new_gerrorn
)
82 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
83 uint32_t toggled
= s
->gerrorn
^ new_gerrorn
;
85 if (toggled
& ~pending
) {
86 qemu_log_mask(LOG_GUEST_ERROR
,
87 "guest toggles non pending errors = 0x%x\n",
92 * We do not raise any error in case guest toggles bits corresponding
93 * to not active IRQs (CONSTRAINED UNPREDICTABLE)
95 s
->gerrorn
= new_gerrorn
;
97 trace_smmuv3_write_gerrorn(toggled
& pending
, s
->gerrorn
);
100 static inline MemTxResult
queue_read(SMMUQueue
*q
, void *data
)
102 dma_addr_t addr
= Q_CONS_ENTRY(q
);
104 return dma_memory_read(&address_space_memory
, addr
, data
, q
->entry_size
);
107 static MemTxResult
queue_write(SMMUQueue
*q
, void *data
)
109 dma_addr_t addr
= Q_PROD_ENTRY(q
);
112 ret
= dma_memory_write(&address_space_memory
, addr
, data
, q
->entry_size
);
113 if (ret
!= MEMTX_OK
) {
121 static MemTxResult
smmuv3_write_eventq(SMMUv3State
*s
, Evt
*evt
)
123 SMMUQueue
*q
= &s
->eventq
;
126 if (!smmuv3_eventq_enabled(s
)) {
130 if (smmuv3_q_full(q
)) {
134 r
= queue_write(q
, evt
);
139 if (!smmuv3_q_empty(q
)) {
140 smmuv3_trigger_irq(s
, SMMU_IRQ_EVTQ
, 0);
145 void smmuv3_record_event(SMMUv3State
*s
, SMMUEventInfo
*info
)
150 if (!smmuv3_eventq_enabled(s
)) {
154 EVT_SET_TYPE(&evt
, info
->type
);
155 EVT_SET_SID(&evt
, info
->sid
);
157 switch (info
->type
) {
161 EVT_SET_SSID(&evt
, info
->u
.f_uut
.ssid
);
162 EVT_SET_SSV(&evt
, info
->u
.f_uut
.ssv
);
163 EVT_SET_ADDR(&evt
, info
->u
.f_uut
.addr
);
164 EVT_SET_RNW(&evt
, info
->u
.f_uut
.rnw
);
165 EVT_SET_PNU(&evt
, info
->u
.f_uut
.pnu
);
166 EVT_SET_IND(&evt
, info
->u
.f_uut
.ind
);
168 case SMMU_EVT_C_BAD_STREAMID
:
169 EVT_SET_SSID(&evt
, info
->u
.c_bad_streamid
.ssid
);
170 EVT_SET_SSV(&evt
, info
->u
.c_bad_streamid
.ssv
);
172 case SMMU_EVT_F_STE_FETCH
:
173 EVT_SET_SSID(&evt
, info
->u
.f_ste_fetch
.ssid
);
174 EVT_SET_SSV(&evt
, info
->u
.f_ste_fetch
.ssv
);
175 EVT_SET_ADDR2(&evt
, info
->u
.f_ste_fetch
.addr
);
177 case SMMU_EVT_C_BAD_STE
:
178 EVT_SET_SSID(&evt
, info
->u
.c_bad_ste
.ssid
);
179 EVT_SET_SSV(&evt
, info
->u
.c_bad_ste
.ssv
);
181 case SMMU_EVT_F_STREAM_DISABLED
:
183 case SMMU_EVT_F_TRANS_FORBIDDEN
:
184 EVT_SET_ADDR(&evt
, info
->u
.f_transl_forbidden
.addr
);
185 EVT_SET_RNW(&evt
, info
->u
.f_transl_forbidden
.rnw
);
187 case SMMU_EVT_C_BAD_SUBSTREAMID
:
188 EVT_SET_SSID(&evt
, info
->u
.c_bad_substream
.ssid
);
190 case SMMU_EVT_F_CD_FETCH
:
191 EVT_SET_SSID(&evt
, info
->u
.f_cd_fetch
.ssid
);
192 EVT_SET_SSV(&evt
, info
->u
.f_cd_fetch
.ssv
);
193 EVT_SET_ADDR(&evt
, info
->u
.f_cd_fetch
.addr
);
195 case SMMU_EVT_C_BAD_CD
:
196 EVT_SET_SSID(&evt
, info
->u
.c_bad_cd
.ssid
);
197 EVT_SET_SSV(&evt
, info
->u
.c_bad_cd
.ssv
);
199 case SMMU_EVT_F_WALK_EABT
:
200 case SMMU_EVT_F_TRANSLATION
:
201 case SMMU_EVT_F_ADDR_SIZE
:
202 case SMMU_EVT_F_ACCESS
:
203 case SMMU_EVT_F_PERMISSION
:
204 EVT_SET_STALL(&evt
, info
->u
.f_walk_eabt
.stall
);
205 EVT_SET_STAG(&evt
, info
->u
.f_walk_eabt
.stag
);
206 EVT_SET_SSID(&evt
, info
->u
.f_walk_eabt
.ssid
);
207 EVT_SET_SSV(&evt
, info
->u
.f_walk_eabt
.ssv
);
208 EVT_SET_S2(&evt
, info
->u
.f_walk_eabt
.s2
);
209 EVT_SET_ADDR(&evt
, info
->u
.f_walk_eabt
.addr
);
210 EVT_SET_RNW(&evt
, info
->u
.f_walk_eabt
.rnw
);
211 EVT_SET_PNU(&evt
, info
->u
.f_walk_eabt
.pnu
);
212 EVT_SET_IND(&evt
, info
->u
.f_walk_eabt
.ind
);
213 EVT_SET_CLASS(&evt
, info
->u
.f_walk_eabt
.class);
214 EVT_SET_ADDR2(&evt
, info
->u
.f_walk_eabt
.addr2
);
216 case SMMU_EVT_F_CFG_CONFLICT
:
217 EVT_SET_SSID(&evt
, info
->u
.f_cfg_conflict
.ssid
);
218 EVT_SET_SSV(&evt
, info
->u
.f_cfg_conflict
.ssv
);
220 /* rest is not implemented */
221 case SMMU_EVT_F_BAD_ATS_TREQ
:
222 case SMMU_EVT_F_TLB_CONFLICT
:
223 case SMMU_EVT_E_PAGE_REQ
:
225 g_assert_not_reached();
228 trace_smmuv3_record_event(smmu_event_string(info
->type
), info
->sid
);
229 r
= smmuv3_write_eventq(s
, &evt
);
231 smmuv3_trigger_irq(s
, SMMU_IRQ_GERROR
, R_GERROR_EVENTQ_ABT_ERR_MASK
);
233 info
->recorded
= true;
236 static void smmuv3_init_regs(SMMUv3State
*s
)
239 * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
240 * multi-level stream table
242 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, S1P
, 1); /* stage 1 supported */
243 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TTF
, 2); /* AArch64 PTW only */
244 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, COHACC
, 1); /* IO coherent */
245 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, ASID16
, 1); /* 16-bit ASID */
246 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TTENDIAN
, 2); /* little endian */
247 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, STALL_MODEL
, 1); /* No stall */
248 /* terminated transaction will always be aborted/error returned */
249 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TERM_MODEL
, 1);
250 /* 2-level stream table supported */
251 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, STLEVEL
, 1);
253 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, SIDSIZE
, SMMU_IDR1_SIDSIZE
);
254 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, EVENTQS
, SMMU_EVENTQS
);
255 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, CMDQS
, SMMU_CMDQS
);
257 /* 4K and 64K granule support */
258 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, GRAN4K
, 1);
259 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, GRAN64K
, 1);
260 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, OAS
, SMMU_IDR5_OAS
); /* 44 bits */
262 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 0, 5, SMMU_CMDQS
);
265 s
->cmdq
.entry_size
= sizeof(struct Cmd
);
266 s
->eventq
.base
= deposit64(s
->eventq
.base
, 0, 5, SMMU_EVENTQS
);
269 s
->eventq
.entry_size
= sizeof(struct Evt
);
275 static int smmu_get_ste(SMMUv3State
*s
, dma_addr_t addr
, STE
*buf
,
276 SMMUEventInfo
*event
)
280 trace_smmuv3_get_ste(addr
);
281 /* TODO: guarantee 64-bit single-copy atomicity */
282 ret
= dma_memory_read(&address_space_memory
, addr
, buf
, sizeof(*buf
));
283 if (ret
!= MEMTX_OK
) {
284 qemu_log_mask(LOG_GUEST_ERROR
,
285 "Cannot fetch pte at address=0x%"PRIx64
"\n", addr
);
286 event
->type
= SMMU_EVT_F_STE_FETCH
;
287 event
->u
.f_ste_fetch
.addr
= addr
;
294 /* @ssid > 0 not supported yet */
295 static int smmu_get_cd(SMMUv3State
*s
, STE
*ste
, uint32_t ssid
,
296 CD
*buf
, SMMUEventInfo
*event
)
298 dma_addr_t addr
= STE_CTXPTR(ste
);
301 trace_smmuv3_get_cd(addr
);
302 /* TODO: guarantee 64-bit single-copy atomicity */
303 ret
= dma_memory_read(&address_space_memory
, addr
, buf
, sizeof(*buf
));
304 if (ret
!= MEMTX_OK
) {
305 qemu_log_mask(LOG_GUEST_ERROR
,
306 "Cannot fetch pte at address=0x%"PRIx64
"\n", addr
);
307 event
->type
= SMMU_EVT_F_CD_FETCH
;
308 event
->u
.f_ste_fetch
.addr
= addr
;
314 /* Returns < 0 in case of invalid STE, 0 otherwise */
315 static int decode_ste(SMMUv3State
*s
, SMMUTransCfg
*cfg
,
316 STE
*ste
, SMMUEventInfo
*event
)
320 if (!STE_VALID(ste
)) {
321 if (!event
->inval_ste_allowed
) {
322 qemu_log_mask(LOG_GUEST_ERROR
, "invalid STE\n");
327 config
= STE_CONFIG(ste
);
329 if (STE_CFG_ABORT(config
)) {
334 if (STE_CFG_BYPASS(config
)) {
335 cfg
->bypassed
= true;
339 if (STE_CFG_S2_ENABLED(config
)) {
340 qemu_log_mask(LOG_UNIMP
, "SMMUv3 does not support stage 2 yet\n");
344 if (STE_S1CDMAX(ste
) != 0) {
345 qemu_log_mask(LOG_UNIMP
,
346 "SMMUv3 does not support multiple context descriptors yet\n");
350 if (STE_S1STALLD(ste
)) {
351 qemu_log_mask(LOG_UNIMP
,
352 "SMMUv3 S1 stalling fault model not allowed yet\n");
358 event
->type
= SMMU_EVT_C_BAD_STE
;
363 * smmu_find_ste - Return the stream table entry associated
368 * @ste: returned stream table entry
369 * @event: handle to an event info
371 * Supports linear and 2-level stream table
372 * Return 0 on success, -EINVAL otherwise
374 static int smmu_find_ste(SMMUv3State
*s
, uint32_t sid
, STE
*ste
,
375 SMMUEventInfo
*event
)
377 dma_addr_t addr
, strtab_base
;
379 int strtab_size_shift
;
382 trace_smmuv3_find_ste(sid
, s
->features
, s
->sid_split
);
383 log2size
= FIELD_EX32(s
->strtab_base_cfg
, STRTAB_BASE_CFG
, LOG2SIZE
);
385 * Check SID range against both guest-configured and implementation limits
387 if (sid
>= (1 << MIN(log2size
, SMMU_IDR1_SIDSIZE
))) {
388 event
->type
= SMMU_EVT_C_BAD_STREAMID
;
391 if (s
->features
& SMMU_FEATURE_2LVL_STE
) {
392 int l1_ste_offset
, l2_ste_offset
, max_l2_ste
, span
;
393 dma_addr_t l1ptr
, l2ptr
;
397 * Align strtab base address to table size. For this purpose, assume it
398 * is not bounded by SMMU_IDR1_SIDSIZE.
400 strtab_size_shift
= MAX(5, (int)log2size
- s
->sid_split
- 1 + 3);
401 strtab_base
= s
->strtab_base
& SMMU_BASE_ADDR_MASK
&
402 ~MAKE_64BIT_MASK(0, strtab_size_shift
);
403 l1_ste_offset
= sid
>> s
->sid_split
;
404 l2_ste_offset
= sid
& ((1 << s
->sid_split
) - 1);
405 l1ptr
= (dma_addr_t
)(strtab_base
+ l1_ste_offset
* sizeof(l1std
));
406 /* TODO: guarantee 64-bit single-copy atomicity */
407 ret
= dma_memory_read(&address_space_memory
, l1ptr
, &l1std
,
409 if (ret
!= MEMTX_OK
) {
410 qemu_log_mask(LOG_GUEST_ERROR
,
411 "Could not read L1PTR at 0X%"PRIx64
"\n", l1ptr
);
412 event
->type
= SMMU_EVT_F_STE_FETCH
;
413 event
->u
.f_ste_fetch
.addr
= l1ptr
;
417 span
= L1STD_SPAN(&l1std
);
420 /* l2ptr is not valid */
421 if (!event
->inval_ste_allowed
) {
422 qemu_log_mask(LOG_GUEST_ERROR
,
423 "invalid sid=%d (L1STD span=0)\n", sid
);
425 event
->type
= SMMU_EVT_C_BAD_STREAMID
;
428 max_l2_ste
= (1 << span
) - 1;
429 l2ptr
= l1std_l2ptr(&l1std
);
430 trace_smmuv3_find_ste_2lvl(s
->strtab_base
, l1ptr
, l1_ste_offset
,
431 l2ptr
, l2_ste_offset
, max_l2_ste
);
432 if (l2_ste_offset
> max_l2_ste
) {
433 qemu_log_mask(LOG_GUEST_ERROR
,
434 "l2_ste_offset=%d > max_l2_ste=%d\n",
435 l2_ste_offset
, max_l2_ste
);
436 event
->type
= SMMU_EVT_C_BAD_STE
;
439 addr
= l2ptr
+ l2_ste_offset
* sizeof(*ste
);
441 strtab_size_shift
= log2size
+ 5;
442 strtab_base
= s
->strtab_base
& SMMU_BASE_ADDR_MASK
&
443 ~MAKE_64BIT_MASK(0, strtab_size_shift
);
444 addr
= strtab_base
+ sid
* sizeof(*ste
);
447 if (smmu_get_ste(s
, addr
, ste
, event
)) {
454 static int decode_cd(SMMUTransCfg
*cfg
, CD
*cd
, SMMUEventInfo
*event
)
459 if (!CD_VALID(cd
) || !CD_AARCH64(cd
)) {
463 goto bad_cd
; /* SMMU_IDR0.TERM_MODEL == 1 */
466 goto bad_cd
; /* !STE_SECURE && SMMU_IDR0.STALL_MODEL == 1 */
468 if (CD_HA(cd
) || CD_HD(cd
)) {
469 goto bad_cd
; /* HTTU = 0 */
472 /* we support only those at the moment */
476 cfg
->oas
= oas2bits(CD_IPS(cd
));
477 cfg
->oas
= MIN(oas2bits(SMMU_IDR5_OAS
), cfg
->oas
);
478 cfg
->tbi
= CD_TBI(cd
);
479 cfg
->asid
= CD_ASID(cd
);
481 trace_smmuv3_decode_cd(cfg
->oas
);
483 /* decode data dependent on TT */
484 for (i
= 0; i
<= 1; i
++) {
486 SMMUTransTableInfo
*tt
= &cfg
->tt
[i
];
488 cfg
->tt
[i
].disabled
= CD_EPD(cd
, i
);
489 if (cfg
->tt
[i
].disabled
) {
494 if (tsz
< 16 || tsz
> 39) {
499 tt
->granule_sz
= tg2granule(tg
, i
);
500 if ((tt
->granule_sz
!= 12 && tt
->granule_sz
!= 16) || CD_ENDI(cd
)) {
505 tt
->ttb
= CD_TTB(cd
, i
);
506 if (tt
->ttb
& ~(MAKE_64BIT_MASK(0, cfg
->oas
))) {
509 trace_smmuv3_decode_cd_tt(i
, tt
->tsz
, tt
->ttb
, tt
->granule_sz
);
512 event
->record_trans_faults
= CD_R(cd
);
517 event
->type
= SMMU_EVT_C_BAD_CD
;
522 * smmuv3_decode_config - Prepare the translation configuration
523 * for the @mr iommu region
524 * @mr: iommu memory region the translation config must be prepared for
525 * @cfg: output translation configuration which is populated through
526 * the different configuration decoding steps
527 * @event: must be zero'ed by the caller
529 * return < 0 in case of config decoding error (@event is filled
530 * accordingly). Return 0 otherwise.
532 static int smmuv3_decode_config(IOMMUMemoryRegion
*mr
, SMMUTransCfg
*cfg
,
533 SMMUEventInfo
*event
)
535 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
536 uint32_t sid
= smmu_get_sid(sdev
);
537 SMMUv3State
*s
= sdev
->smmu
;
542 ret
= smmu_find_ste(s
, sid
, &ste
, event
);
547 ret
= decode_ste(s
, cfg
, &ste
, event
);
552 if (cfg
->aborted
|| cfg
->bypassed
) {
556 ret
= smmu_get_cd(s
, &ste
, 0 /* ssid */, &cd
, event
);
561 return decode_cd(cfg
, &cd
, event
);
565 * smmuv3_get_config - Look up for a cached copy of configuration data for
566 * @sdev and on cache miss performs a configuration structure decoding from
569 * @sdev: SMMUDevice handle
570 * @event: output event info
572 * The configuration cache contains data resulting from both STE and CD
573 * decoding under the form of an SMMUTransCfg struct. The hash table is indexed
574 * by the SMMUDevice handle.
576 static SMMUTransCfg
*smmuv3_get_config(SMMUDevice
*sdev
, SMMUEventInfo
*event
)
578 SMMUv3State
*s
= sdev
->smmu
;
579 SMMUState
*bc
= &s
->smmu_state
;
582 cfg
= g_hash_table_lookup(bc
->configs
, sdev
);
584 sdev
->cfg_cache_hits
++;
585 trace_smmuv3_config_cache_hit(smmu_get_sid(sdev
),
586 sdev
->cfg_cache_hits
, sdev
->cfg_cache_misses
,
587 100 * sdev
->cfg_cache_hits
/
588 (sdev
->cfg_cache_hits
+ sdev
->cfg_cache_misses
));
590 sdev
->cfg_cache_misses
++;
591 trace_smmuv3_config_cache_miss(smmu_get_sid(sdev
),
592 sdev
->cfg_cache_hits
, sdev
->cfg_cache_misses
,
593 100 * sdev
->cfg_cache_hits
/
594 (sdev
->cfg_cache_hits
+ sdev
->cfg_cache_misses
));
595 cfg
= g_new0(SMMUTransCfg
, 1);
597 if (!smmuv3_decode_config(&sdev
->iommu
, cfg
, event
)) {
598 g_hash_table_insert(bc
->configs
, sdev
, cfg
);
607 static void smmuv3_flush_config(SMMUDevice
*sdev
)
609 SMMUv3State
*s
= sdev
->smmu
;
610 SMMUState
*bc
= &s
->smmu_state
;
612 trace_smmuv3_config_cache_inv(smmu_get_sid(sdev
));
613 g_hash_table_remove(bc
->configs
, sdev
);
616 static IOMMUTLBEntry
smmuv3_translate(IOMMUMemoryRegion
*mr
, hwaddr addr
,
617 IOMMUAccessFlags flag
, int iommu_idx
)
619 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
620 SMMUv3State
*s
= sdev
->smmu
;
621 uint32_t sid
= smmu_get_sid(sdev
);
622 SMMUEventInfo event
= {.type
= SMMU_EVT_NONE
,
624 .inval_ste_allowed
= false};
625 SMMUPTWEventInfo ptw_info
= {};
626 SMMUTranslationStatus status
;
627 SMMUState
*bs
= ARM_SMMU(s
);
628 uint64_t page_mask
, aligned_addr
;
629 IOMMUTLBEntry
*cached_entry
= NULL
;
630 SMMUTransTableInfo
*tt
;
631 SMMUTransCfg
*cfg
= NULL
;
632 IOMMUTLBEntry entry
= {
633 .target_as
= &address_space_memory
,
635 .translated_addr
= addr
,
636 .addr_mask
= ~(hwaddr
)0,
639 SMMUIOTLBKey key
, *new_key
;
641 qemu_mutex_lock(&s
->mutex
);
643 if (!smmu_enabled(s
)) {
644 status
= SMMU_TRANS_DISABLE
;
648 cfg
= smmuv3_get_config(sdev
, &event
);
650 status
= SMMU_TRANS_ERROR
;
655 status
= SMMU_TRANS_ABORT
;
660 status
= SMMU_TRANS_BYPASS
;
664 tt
= select_tt(cfg
, addr
);
666 if (event
.record_trans_faults
) {
667 event
.type
= SMMU_EVT_F_TRANSLATION
;
668 event
.u
.f_translation
.addr
= addr
;
669 event
.u
.f_translation
.rnw
= flag
& 0x1;
671 status
= SMMU_TRANS_ERROR
;
675 page_mask
= (1ULL << (tt
->granule_sz
)) - 1;
676 aligned_addr
= addr
& ~page_mask
;
678 key
.asid
= cfg
->asid
;
679 key
.iova
= aligned_addr
;
681 cached_entry
= g_hash_table_lookup(bs
->iotlb
, &key
);
684 trace_smmu_iotlb_cache_hit(cfg
->asid
, aligned_addr
,
685 cfg
->iotlb_hits
, cfg
->iotlb_misses
,
686 100 * cfg
->iotlb_hits
/
687 (cfg
->iotlb_hits
+ cfg
->iotlb_misses
));
688 if ((flag
& IOMMU_WO
) && !(cached_entry
->perm
& IOMMU_WO
)) {
689 status
= SMMU_TRANS_ERROR
;
690 if (event
.record_trans_faults
) {
691 event
.type
= SMMU_EVT_F_PERMISSION
;
692 event
.u
.f_permission
.addr
= addr
;
693 event
.u
.f_permission
.rnw
= flag
& 0x1;
696 status
= SMMU_TRANS_SUCCESS
;
702 trace_smmu_iotlb_cache_miss(cfg
->asid
, addr
& ~page_mask
,
703 cfg
->iotlb_hits
, cfg
->iotlb_misses
,
704 100 * cfg
->iotlb_hits
/
705 (cfg
->iotlb_hits
+ cfg
->iotlb_misses
));
707 if (g_hash_table_size(bs
->iotlb
) >= SMMU_IOTLB_MAX_SIZE
) {
708 smmu_iotlb_inv_all(bs
);
711 cached_entry
= g_new0(IOMMUTLBEntry
, 1);
713 if (smmu_ptw(cfg
, aligned_addr
, flag
, cached_entry
, &ptw_info
)) {
714 g_free(cached_entry
);
715 switch (ptw_info
.type
) {
716 case SMMU_PTW_ERR_WALK_EABT
:
717 event
.type
= SMMU_EVT_F_WALK_EABT
;
718 event
.u
.f_walk_eabt
.addr
= addr
;
719 event
.u
.f_walk_eabt
.rnw
= flag
& 0x1;
720 event
.u
.f_walk_eabt
.class = 0x1;
721 event
.u
.f_walk_eabt
.addr2
= ptw_info
.addr
;
723 case SMMU_PTW_ERR_TRANSLATION
:
724 if (event
.record_trans_faults
) {
725 event
.type
= SMMU_EVT_F_TRANSLATION
;
726 event
.u
.f_translation
.addr
= addr
;
727 event
.u
.f_translation
.rnw
= flag
& 0x1;
730 case SMMU_PTW_ERR_ADDR_SIZE
:
731 if (event
.record_trans_faults
) {
732 event
.type
= SMMU_EVT_F_ADDR_SIZE
;
733 event
.u
.f_addr_size
.addr
= addr
;
734 event
.u
.f_addr_size
.rnw
= flag
& 0x1;
737 case SMMU_PTW_ERR_ACCESS
:
738 if (event
.record_trans_faults
) {
739 event
.type
= SMMU_EVT_F_ACCESS
;
740 event
.u
.f_access
.addr
= addr
;
741 event
.u
.f_access
.rnw
= flag
& 0x1;
744 case SMMU_PTW_ERR_PERMISSION
:
745 if (event
.record_trans_faults
) {
746 event
.type
= SMMU_EVT_F_PERMISSION
;
747 event
.u
.f_permission
.addr
= addr
;
748 event
.u
.f_permission
.rnw
= flag
& 0x1;
752 g_assert_not_reached();
754 status
= SMMU_TRANS_ERROR
;
756 new_key
= g_new0(SMMUIOTLBKey
, 1);
757 new_key
->asid
= cfg
->asid
;
758 new_key
->iova
= aligned_addr
;
759 g_hash_table_insert(bs
->iotlb
, new_key
, cached_entry
);
760 status
= SMMU_TRANS_SUCCESS
;
764 qemu_mutex_unlock(&s
->mutex
);
766 case SMMU_TRANS_SUCCESS
:
768 entry
.translated_addr
= cached_entry
->translated_addr
+
770 entry
.addr_mask
= cached_entry
->addr_mask
;
771 trace_smmuv3_translate_success(mr
->parent_obj
.name
, sid
, addr
,
772 entry
.translated_addr
, entry
.perm
);
774 case SMMU_TRANS_DISABLE
:
776 entry
.addr_mask
= ~TARGET_PAGE_MASK
;
777 trace_smmuv3_translate_disable(mr
->parent_obj
.name
, sid
, addr
,
780 case SMMU_TRANS_BYPASS
:
782 entry
.addr_mask
= ~TARGET_PAGE_MASK
;
783 trace_smmuv3_translate_bypass(mr
->parent_obj
.name
, sid
, addr
,
786 case SMMU_TRANS_ABORT
:
787 /* no event is recorded on abort */
788 trace_smmuv3_translate_abort(mr
->parent_obj
.name
, sid
, addr
,
791 case SMMU_TRANS_ERROR
:
792 qemu_log_mask(LOG_GUEST_ERROR
,
793 "%s translation failed for iova=0x%"PRIx64
"(%s)\n",
794 mr
->parent_obj
.name
, addr
, smmu_event_string(event
.type
));
795 smmuv3_record_event(s
, &event
);
803 * smmuv3_notify_iova - call the notifier @n for a given
804 * @asid and @iova tuple.
806 * @mr: IOMMU mr region handle
807 * @n: notifier to be called
808 * @asid: address space ID or negative value if we don't care
811 static void smmuv3_notify_iova(IOMMUMemoryRegion
*mr
,
816 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
817 SMMUEventInfo event
= {.inval_ste_allowed
= true};
818 SMMUTransTableInfo
*tt
;
822 cfg
= smmuv3_get_config(sdev
, &event
);
827 if (asid
>= 0 && cfg
->asid
!= asid
) {
831 tt
= select_tt(cfg
, iova
);
836 entry
.target_as
= &address_space_memory
;
838 entry
.addr_mask
= (1 << tt
->granule_sz
) - 1;
839 entry
.perm
= IOMMU_NONE
;
841 memory_region_notify_one(n
, &entry
);
844 /* invalidate an asid/iova tuple in all mr's */
845 static void smmuv3_inv_notifiers_iova(SMMUState
*s
, int asid
, dma_addr_t iova
)
849 QLIST_FOREACH(sdev
, &s
->devices_with_notifiers
, next
) {
850 IOMMUMemoryRegion
*mr
= &sdev
->iommu
;
853 trace_smmuv3_inv_notifiers_iova(mr
->parent_obj
.name
, asid
, iova
);
855 IOMMU_NOTIFIER_FOREACH(n
, mr
) {
856 smmuv3_notify_iova(mr
, n
, asid
, iova
);
861 static int smmuv3_cmdq_consume(SMMUv3State
*s
)
863 SMMUState
*bs
= ARM_SMMU(s
);
864 SMMUCmdError cmd_error
= SMMU_CERROR_NONE
;
865 SMMUQueue
*q
= &s
->cmdq
;
866 SMMUCommandType type
= 0;
868 if (!smmuv3_cmdq_enabled(s
)) {
872 * some commands depend on register values, typically CR0. In case those
873 * register values change while handling the command, spec says it
874 * is UNPREDICTABLE whether the command is interpreted under the new
878 while (!smmuv3_q_empty(q
)) {
879 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
882 trace_smmuv3_cmdq_consume(Q_PROD(q
), Q_CONS(q
),
883 Q_PROD_WRAP(q
), Q_CONS_WRAP(q
));
885 if (FIELD_EX32(pending
, GERROR
, CMDQ_ERR
)) {
889 if (queue_read(q
, &cmd
) != MEMTX_OK
) {
890 cmd_error
= SMMU_CERROR_ABT
;
894 type
= CMD_TYPE(&cmd
);
896 trace_smmuv3_cmdq_opcode(smmu_cmd_string(type
));
898 qemu_mutex_lock(&s
->mutex
);
901 if (CMD_SYNC_CS(&cmd
) & CMD_SYNC_SIG_IRQ
) {
902 smmuv3_trigger_irq(s
, SMMU_IRQ_CMD_SYNC
, 0);
905 case SMMU_CMD_PREFETCH_CONFIG
:
906 case SMMU_CMD_PREFETCH_ADDR
:
908 case SMMU_CMD_CFGI_STE
:
910 uint32_t sid
= CMD_SID(&cmd
);
911 IOMMUMemoryRegion
*mr
= smmu_iommu_mr(bs
, sid
);
914 if (CMD_SSEC(&cmd
)) {
915 cmd_error
= SMMU_CERROR_ILL
;
923 trace_smmuv3_cmdq_cfgi_ste(sid
);
924 sdev
= container_of(mr
, SMMUDevice
, iommu
);
925 smmuv3_flush_config(sdev
);
929 case SMMU_CMD_CFGI_STE_RANGE
: /* same as SMMU_CMD_CFGI_ALL */
931 uint32_t start
= CMD_SID(&cmd
), end
, i
;
932 uint8_t range
= CMD_STE_RANGE(&cmd
);
934 if (CMD_SSEC(&cmd
)) {
935 cmd_error
= SMMU_CERROR_ILL
;
939 end
= start
+ (1 << (range
+ 1)) - 1;
940 trace_smmuv3_cmdq_cfgi_ste_range(start
, end
);
942 for (i
= start
; i
<= end
; i
++) {
943 IOMMUMemoryRegion
*mr
= smmu_iommu_mr(bs
, i
);
949 sdev
= container_of(mr
, SMMUDevice
, iommu
);
950 smmuv3_flush_config(sdev
);
954 case SMMU_CMD_CFGI_CD
:
955 case SMMU_CMD_CFGI_CD_ALL
:
957 uint32_t sid
= CMD_SID(&cmd
);
958 IOMMUMemoryRegion
*mr
= smmu_iommu_mr(bs
, sid
);
961 if (CMD_SSEC(&cmd
)) {
962 cmd_error
= SMMU_CERROR_ILL
;
970 trace_smmuv3_cmdq_cfgi_cd(sid
);
971 sdev
= container_of(mr
, SMMUDevice
, iommu
);
972 smmuv3_flush_config(sdev
);
975 case SMMU_CMD_TLBI_NH_ASID
:
977 uint16_t asid
= CMD_ASID(&cmd
);
979 trace_smmuv3_cmdq_tlbi_nh_asid(asid
);
980 smmu_inv_notifiers_all(&s
->smmu_state
);
981 smmu_iotlb_inv_asid(bs
, asid
);
984 case SMMU_CMD_TLBI_NH_ALL
:
985 case SMMU_CMD_TLBI_NSNH_ALL
:
986 trace_smmuv3_cmdq_tlbi_nh();
987 smmu_inv_notifiers_all(&s
->smmu_state
);
988 smmu_iotlb_inv_all(bs
);
990 case SMMU_CMD_TLBI_NH_VAA
:
992 dma_addr_t addr
= CMD_ADDR(&cmd
);
993 uint16_t vmid
= CMD_VMID(&cmd
);
995 trace_smmuv3_cmdq_tlbi_nh_vaa(vmid
, addr
);
996 smmuv3_inv_notifiers_iova(bs
, -1, addr
);
997 smmu_iotlb_inv_all(bs
);
1000 case SMMU_CMD_TLBI_NH_VA
:
1002 uint16_t asid
= CMD_ASID(&cmd
);
1003 uint16_t vmid
= CMD_VMID(&cmd
);
1004 dma_addr_t addr
= CMD_ADDR(&cmd
);
1005 bool leaf
= CMD_LEAF(&cmd
);
1007 trace_smmuv3_cmdq_tlbi_nh_va(vmid
, asid
, addr
, leaf
);
1008 smmuv3_inv_notifiers_iova(bs
, asid
, addr
);
1009 smmu_iotlb_inv_iova(bs
, asid
, addr
);
1012 case SMMU_CMD_TLBI_EL3_ALL
:
1013 case SMMU_CMD_TLBI_EL3_VA
:
1014 case SMMU_CMD_TLBI_EL2_ALL
:
1015 case SMMU_CMD_TLBI_EL2_ASID
:
1016 case SMMU_CMD_TLBI_EL2_VA
:
1017 case SMMU_CMD_TLBI_EL2_VAA
:
1018 case SMMU_CMD_TLBI_S12_VMALL
:
1019 case SMMU_CMD_TLBI_S2_IPA
:
1020 case SMMU_CMD_ATC_INV
:
1021 case SMMU_CMD_PRI_RESP
:
1022 case SMMU_CMD_RESUME
:
1023 case SMMU_CMD_STALL_TERM
:
1024 trace_smmuv3_unhandled_cmd(type
);
1027 cmd_error
= SMMU_CERROR_ILL
;
1028 qemu_log_mask(LOG_GUEST_ERROR
,
1029 "Illegal command type: %d\n", CMD_TYPE(&cmd
));
1032 qemu_mutex_unlock(&s
->mutex
);
1037 * We only increment the cons index after the completion of
1038 * the command. We do that because the SYNC returns immediately
1039 * and does not check the completion of previous commands
1045 trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type
), cmd_error
);
1046 smmu_write_cmdq_err(s
, cmd_error
);
1047 smmuv3_trigger_irq(s
, SMMU_IRQ_GERROR
, R_GERROR_CMDQ_ERR_MASK
);
1050 trace_smmuv3_cmdq_consume_out(Q_PROD(q
), Q_CONS(q
),
1051 Q_PROD_WRAP(q
), Q_CONS_WRAP(q
));
1056 static MemTxResult
smmu_writell(SMMUv3State
*s
, hwaddr offset
,
1057 uint64_t data
, MemTxAttrs attrs
)
1060 case A_GERROR_IRQ_CFG0
:
1061 s
->gerror_irq_cfg0
= data
;
1064 s
->strtab_base
= data
;
1067 s
->cmdq
.base
= data
;
1068 s
->cmdq
.log2size
= extract64(s
->cmdq
.base
, 0, 5);
1069 if (s
->cmdq
.log2size
> SMMU_CMDQS
) {
1070 s
->cmdq
.log2size
= SMMU_CMDQS
;
1074 s
->eventq
.base
= data
;
1075 s
->eventq
.log2size
= extract64(s
->eventq
.base
, 0, 5);
1076 if (s
->eventq
.log2size
> SMMU_EVENTQS
) {
1077 s
->eventq
.log2size
= SMMU_EVENTQS
;
1080 case A_EVENTQ_IRQ_CFG0
:
1081 s
->eventq_irq_cfg0
= data
;
1084 qemu_log_mask(LOG_UNIMP
,
1085 "%s Unexpected 64-bit access to 0x%"PRIx64
" (WI)\n",
1091 static MemTxResult
smmu_writel(SMMUv3State
*s
, hwaddr offset
,
1092 uint64_t data
, MemTxAttrs attrs
)
1097 s
->cr0ack
= data
& ~SMMU_CR0_RESERVED
;
1098 /* in case the command queue has been enabled */
1099 smmuv3_cmdq_consume(s
);
1111 smmuv3_write_gerrorn(s
, data
);
1113 * By acknowledging the CMDQ_ERR, SW may notify cmds can
1114 * be processed again
1116 smmuv3_cmdq_consume(s
);
1118 case A_GERROR_IRQ_CFG0
: /* 64b */
1119 s
->gerror_irq_cfg0
= deposit64(s
->gerror_irq_cfg0
, 0, 32, data
);
1121 case A_GERROR_IRQ_CFG0
+ 4:
1122 s
->gerror_irq_cfg0
= deposit64(s
->gerror_irq_cfg0
, 32, 32, data
);
1124 case A_GERROR_IRQ_CFG1
:
1125 s
->gerror_irq_cfg1
= data
;
1127 case A_GERROR_IRQ_CFG2
:
1128 s
->gerror_irq_cfg2
= data
;
1130 case A_STRTAB_BASE
: /* 64b */
1131 s
->strtab_base
= deposit64(s
->strtab_base
, 0, 32, data
);
1133 case A_STRTAB_BASE
+ 4:
1134 s
->strtab_base
= deposit64(s
->strtab_base
, 32, 32, data
);
1136 case A_STRTAB_BASE_CFG
:
1137 s
->strtab_base_cfg
= data
;
1138 if (FIELD_EX32(data
, STRTAB_BASE_CFG
, FMT
) == 1) {
1139 s
->sid_split
= FIELD_EX32(data
, STRTAB_BASE_CFG
, SPLIT
);
1140 s
->features
|= SMMU_FEATURE_2LVL_STE
;
1143 case A_CMDQ_BASE
: /* 64b */
1144 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 0, 32, data
);
1145 s
->cmdq
.log2size
= extract64(s
->cmdq
.base
, 0, 5);
1146 if (s
->cmdq
.log2size
> SMMU_CMDQS
) {
1147 s
->cmdq
.log2size
= SMMU_CMDQS
;
1150 case A_CMDQ_BASE
+ 4: /* 64b */
1151 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 32, 32, data
);
1154 s
->cmdq
.prod
= data
;
1155 smmuv3_cmdq_consume(s
);
1158 s
->cmdq
.cons
= data
;
1160 case A_EVENTQ_BASE
: /* 64b */
1161 s
->eventq
.base
= deposit64(s
->eventq
.base
, 0, 32, data
);
1162 s
->eventq
.log2size
= extract64(s
->eventq
.base
, 0, 5);
1163 if (s
->eventq
.log2size
> SMMU_EVENTQS
) {
1164 s
->eventq
.log2size
= SMMU_EVENTQS
;
1167 case A_EVENTQ_BASE
+ 4:
1168 s
->eventq
.base
= deposit64(s
->eventq
.base
, 32, 32, data
);
1171 s
->eventq
.prod
= data
;
1174 s
->eventq
.cons
= data
;
1176 case A_EVENTQ_IRQ_CFG0
: /* 64b */
1177 s
->eventq_irq_cfg0
= deposit64(s
->eventq_irq_cfg0
, 0, 32, data
);
1179 case A_EVENTQ_IRQ_CFG0
+ 4:
1180 s
->eventq_irq_cfg0
= deposit64(s
->eventq_irq_cfg0
, 32, 32, data
);
1182 case A_EVENTQ_IRQ_CFG1
:
1183 s
->eventq_irq_cfg1
= data
;
1185 case A_EVENTQ_IRQ_CFG2
:
1186 s
->eventq_irq_cfg2
= data
;
1189 qemu_log_mask(LOG_UNIMP
,
1190 "%s Unexpected 32-bit access to 0x%"PRIx64
" (WI)\n",
1196 static MemTxResult
smmu_write_mmio(void *opaque
, hwaddr offset
, uint64_t data
,
1197 unsigned size
, MemTxAttrs attrs
)
1199 SMMUState
*sys
= opaque
;
1200 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1203 /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
1208 r
= smmu_writell(s
, offset
, data
, attrs
);
1211 r
= smmu_writel(s
, offset
, data
, attrs
);
1218 trace_smmuv3_write_mmio(offset
, data
, size
, r
);
1222 static MemTxResult
smmu_readll(SMMUv3State
*s
, hwaddr offset
,
1223 uint64_t *data
, MemTxAttrs attrs
)
1226 case A_GERROR_IRQ_CFG0
:
1227 *data
= s
->gerror_irq_cfg0
;
1230 *data
= s
->strtab_base
;
1233 *data
= s
->cmdq
.base
;
1236 *data
= s
->eventq
.base
;
1240 qemu_log_mask(LOG_UNIMP
,
1241 "%s Unexpected 64-bit access to 0x%"PRIx64
" (RAZ)\n",
1247 static MemTxResult
smmu_readl(SMMUv3State
*s
, hwaddr offset
,
1248 uint64_t *data
, MemTxAttrs attrs
)
1251 case A_IDREGS
... A_IDREGS
+ 0x2f:
1252 *data
= smmuv3_idreg(offset
- A_IDREGS
);
1254 case A_IDR0
... A_IDR5
:
1255 *data
= s
->idr
[(offset
- A_IDR0
) / 4];
1276 case A_IRQ_CTRL_ACK
:
1277 *data
= s
->irq_ctrl
;
1285 case A_GERROR_IRQ_CFG0
: /* 64b */
1286 *data
= extract64(s
->gerror_irq_cfg0
, 0, 32);
1288 case A_GERROR_IRQ_CFG0
+ 4:
1289 *data
= extract64(s
->gerror_irq_cfg0
, 32, 32);
1291 case A_GERROR_IRQ_CFG1
:
1292 *data
= s
->gerror_irq_cfg1
;
1294 case A_GERROR_IRQ_CFG2
:
1295 *data
= s
->gerror_irq_cfg2
;
1297 case A_STRTAB_BASE
: /* 64b */
1298 *data
= extract64(s
->strtab_base
, 0, 32);
1300 case A_STRTAB_BASE
+ 4: /* 64b */
1301 *data
= extract64(s
->strtab_base
, 32, 32);
1303 case A_STRTAB_BASE_CFG
:
1304 *data
= s
->strtab_base_cfg
;
1306 case A_CMDQ_BASE
: /* 64b */
1307 *data
= extract64(s
->cmdq
.base
, 0, 32);
1309 case A_CMDQ_BASE
+ 4:
1310 *data
= extract64(s
->cmdq
.base
, 32, 32);
1313 *data
= s
->cmdq
.prod
;
1316 *data
= s
->cmdq
.cons
;
1318 case A_EVENTQ_BASE
: /* 64b */
1319 *data
= extract64(s
->eventq
.base
, 0, 32);
1321 case A_EVENTQ_BASE
+ 4: /* 64b */
1322 *data
= extract64(s
->eventq
.base
, 32, 32);
1325 *data
= s
->eventq
.prod
;
1328 *data
= s
->eventq
.cons
;
1332 qemu_log_mask(LOG_UNIMP
,
1333 "%s unhandled 32-bit access at 0x%"PRIx64
" (RAZ)\n",
1339 static MemTxResult
smmu_read_mmio(void *opaque
, hwaddr offset
, uint64_t *data
,
1340 unsigned size
, MemTxAttrs attrs
)
1342 SMMUState
*sys
= opaque
;
1343 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1346 /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
1351 r
= smmu_readll(s
, offset
, data
, attrs
);
1354 r
= smmu_readl(s
, offset
, data
, attrs
);
1361 trace_smmuv3_read_mmio(offset
, *data
, size
, r
);
1365 static const MemoryRegionOps smmu_mem_ops
= {
1366 .read_with_attrs
= smmu_read_mmio
,
1367 .write_with_attrs
= smmu_write_mmio
,
1368 .endianness
= DEVICE_LITTLE_ENDIAN
,
1370 .min_access_size
= 4,
1371 .max_access_size
= 8,
1374 .min_access_size
= 4,
1375 .max_access_size
= 8,
1379 static void smmu_init_irq(SMMUv3State
*s
, SysBusDevice
*dev
)
1383 for (i
= 0; i
< ARRAY_SIZE(s
->irq
); i
++) {
1384 sysbus_init_irq(dev
, &s
->irq
[i
]);
1388 static void smmu_reset(DeviceState
*dev
)
1390 SMMUv3State
*s
= ARM_SMMUV3(dev
);
1391 SMMUv3Class
*c
= ARM_SMMUV3_GET_CLASS(s
);
1393 c
->parent_reset(dev
);
1395 smmuv3_init_regs(s
);
1398 static void smmu_realize(DeviceState
*d
, Error
**errp
)
1400 SMMUState
*sys
= ARM_SMMU(d
);
1401 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1402 SMMUv3Class
*c
= ARM_SMMUV3_GET_CLASS(s
);
1403 SysBusDevice
*dev
= SYS_BUS_DEVICE(d
);
1404 Error
*local_err
= NULL
;
1406 c
->parent_realize(d
, &local_err
);
1408 error_propagate(errp
, local_err
);
1412 qemu_mutex_init(&s
->mutex
);
1414 memory_region_init_io(&sys
->iomem
, OBJECT(s
),
1415 &smmu_mem_ops
, sys
, TYPE_ARM_SMMUV3
, 0x20000);
1417 sys
->mrtypename
= TYPE_SMMUV3_IOMMU_MEMORY_REGION
;
1419 sysbus_init_mmio(dev
, &sys
->iomem
);
1421 smmu_init_irq(s
, dev
);
1424 static const VMStateDescription vmstate_smmuv3_queue
= {
1425 .name
= "smmuv3_queue",
1427 .minimum_version_id
= 1,
1428 .fields
= (VMStateField
[]) {
1429 VMSTATE_UINT64(base
, SMMUQueue
),
1430 VMSTATE_UINT32(prod
, SMMUQueue
),
1431 VMSTATE_UINT32(cons
, SMMUQueue
),
1432 VMSTATE_UINT8(log2size
, SMMUQueue
),
1433 VMSTATE_END_OF_LIST(),
1437 static const VMStateDescription vmstate_smmuv3
= {
1440 .minimum_version_id
= 1,
1441 .fields
= (VMStateField
[]) {
1442 VMSTATE_UINT32(features
, SMMUv3State
),
1443 VMSTATE_UINT8(sid_size
, SMMUv3State
),
1444 VMSTATE_UINT8(sid_split
, SMMUv3State
),
1446 VMSTATE_UINT32_ARRAY(cr
, SMMUv3State
, 3),
1447 VMSTATE_UINT32(cr0ack
, SMMUv3State
),
1448 VMSTATE_UINT32(statusr
, SMMUv3State
),
1449 VMSTATE_UINT32(irq_ctrl
, SMMUv3State
),
1450 VMSTATE_UINT32(gerror
, SMMUv3State
),
1451 VMSTATE_UINT32(gerrorn
, SMMUv3State
),
1452 VMSTATE_UINT64(gerror_irq_cfg0
, SMMUv3State
),
1453 VMSTATE_UINT32(gerror_irq_cfg1
, SMMUv3State
),
1454 VMSTATE_UINT32(gerror_irq_cfg2
, SMMUv3State
),
1455 VMSTATE_UINT64(strtab_base
, SMMUv3State
),
1456 VMSTATE_UINT32(strtab_base_cfg
, SMMUv3State
),
1457 VMSTATE_UINT64(eventq_irq_cfg0
, SMMUv3State
),
1458 VMSTATE_UINT32(eventq_irq_cfg1
, SMMUv3State
),
1459 VMSTATE_UINT32(eventq_irq_cfg2
, SMMUv3State
),
1461 VMSTATE_STRUCT(cmdq
, SMMUv3State
, 0, vmstate_smmuv3_queue
, SMMUQueue
),
1462 VMSTATE_STRUCT(eventq
, SMMUv3State
, 0, vmstate_smmuv3_queue
, SMMUQueue
),
1464 VMSTATE_END_OF_LIST(),
1468 static void smmuv3_instance_init(Object
*obj
)
1470 /* Nothing much to do here as of now */
1473 static void smmuv3_class_init(ObjectClass
*klass
, void *data
)
1475 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1476 SMMUv3Class
*c
= ARM_SMMUV3_CLASS(klass
);
1478 dc
->vmsd
= &vmstate_smmuv3
;
1479 device_class_set_parent_reset(dc
, smmu_reset
, &c
->parent_reset
);
1480 c
->parent_realize
= dc
->realize
;
1481 dc
->realize
= smmu_realize
;
1484 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion
*iommu
,
1485 IOMMUNotifierFlag old
,
1486 IOMMUNotifierFlag
new,
1489 SMMUDevice
*sdev
= container_of(iommu
, SMMUDevice
, iommu
);
1490 SMMUv3State
*s3
= sdev
->smmu
;
1491 SMMUState
*s
= &(s3
->smmu_state
);
1493 if (new & IOMMU_NOTIFIER_MAP
) {
1495 "device %02x.%02x.%x requires iommu MAP notifier which is "
1496 "not currently supported", pci_bus_num(sdev
->bus
),
1497 PCI_SLOT(sdev
->devfn
), PCI_FUNC(sdev
->devfn
));
1501 if (old
== IOMMU_NOTIFIER_NONE
) {
1502 trace_smmuv3_notify_flag_add(iommu
->parent_obj
.name
);
1503 QLIST_INSERT_HEAD(&s
->devices_with_notifiers
, sdev
, next
);
1504 } else if (new == IOMMU_NOTIFIER_NONE
) {
1505 trace_smmuv3_notify_flag_del(iommu
->parent_obj
.name
);
1506 QLIST_REMOVE(sdev
, next
);
1511 static void smmuv3_iommu_memory_region_class_init(ObjectClass
*klass
,
1514 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
1516 imrc
->translate
= smmuv3_translate
;
1517 imrc
->notify_flag_changed
= smmuv3_notify_flag_changed
;
1520 static const TypeInfo smmuv3_type_info
= {
1521 .name
= TYPE_ARM_SMMUV3
,
1522 .parent
= TYPE_ARM_SMMU
,
1523 .instance_size
= sizeof(SMMUv3State
),
1524 .instance_init
= smmuv3_instance_init
,
1525 .class_size
= sizeof(SMMUv3Class
),
1526 .class_init
= smmuv3_class_init
,
1529 static const TypeInfo smmuv3_iommu_memory_region_info
= {
1530 .parent
= TYPE_IOMMU_MEMORY_REGION
,
1531 .name
= TYPE_SMMUV3_IOMMU_MEMORY_REGION
,
1532 .class_init
= smmuv3_iommu_memory_region_class_init
,
1535 static void smmuv3_register_types(void)
1537 type_register(&smmuv3_type_info
);
1538 type_register(&smmuv3_iommu_memory_region_info
);
1541 type_init(smmuv3_register_types
)