2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu-timer.h"
31 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
33 #define DPRINTF(...) do {} while (0)
35 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
36 __func__, __LINE__); abort(); } while (0)
44 #define MAXPORTS (USB2_PORTS+USB3_PORTS)
50 /* Very pessimistic, let's hope it's enough for all cases */
51 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
52 /* Do not deliver ER Full events. NEC's driver does some things not bound
53 * to the specs when it gets them */
57 #define OFF_OPER LEN_CAP
58 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
59 #define OFF_RUNTIME ((OFF_OPER + LEN_OPER + 0x20) & ~0x1f)
60 #define LEN_RUNTIME (0x20 + MAXINTRS * 0x20)
61 #define OFF_DOORBELL (OFF_RUNTIME + LEN_RUNTIME)
62 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
64 /* must be power of 2 */
65 #define LEN_REGS 0x2000
67 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
68 # error Increase LEN_REGS
72 # error TODO: only one interrupter supported
76 #define USBCMD_RS (1<<0)
77 #define USBCMD_HCRST (1<<1)
78 #define USBCMD_INTE (1<<2)
79 #define USBCMD_HSEE (1<<3)
80 #define USBCMD_LHCRST (1<<7)
81 #define USBCMD_CSS (1<<8)
82 #define USBCMD_CRS (1<<9)
83 #define USBCMD_EWE (1<<10)
84 #define USBCMD_EU3S (1<<11)
86 #define USBSTS_HCH (1<<0)
87 #define USBSTS_HSE (1<<2)
88 #define USBSTS_EINT (1<<3)
89 #define USBSTS_PCD (1<<4)
90 #define USBSTS_SSS (1<<8)
91 #define USBSTS_RSS (1<<9)
92 #define USBSTS_SRE (1<<10)
93 #define USBSTS_CNR (1<<11)
94 #define USBSTS_HCE (1<<12)
97 #define PORTSC_CCS (1<<0)
98 #define PORTSC_PED (1<<1)
99 #define PORTSC_OCA (1<<3)
100 #define PORTSC_PR (1<<4)
101 #define PORTSC_PLS_SHIFT 5
102 #define PORTSC_PLS_MASK 0xf
103 #define PORTSC_PP (1<<9)
104 #define PORTSC_SPEED_SHIFT 10
105 #define PORTSC_SPEED_MASK 0xf
106 #define PORTSC_SPEED_FULL (1<<10)
107 #define PORTSC_SPEED_LOW (2<<10)
108 #define PORTSC_SPEED_HIGH (3<<10)
109 #define PORTSC_SPEED_SUPER (4<<10)
110 #define PORTSC_PIC_SHIFT 14
111 #define PORTSC_PIC_MASK 0x3
112 #define PORTSC_LWS (1<<16)
113 #define PORTSC_CSC (1<<17)
114 #define PORTSC_PEC (1<<18)
115 #define PORTSC_WRC (1<<19)
116 #define PORTSC_OCC (1<<20)
117 #define PORTSC_PRC (1<<21)
118 #define PORTSC_PLC (1<<22)
119 #define PORTSC_CEC (1<<23)
120 #define PORTSC_CAS (1<<24)
121 #define PORTSC_WCE (1<<25)
122 #define PORTSC_WDE (1<<26)
123 #define PORTSC_WOE (1<<27)
124 #define PORTSC_DR (1<<30)
125 #define PORTSC_WPR (1<<31)
127 #define CRCR_RCS (1<<0)
128 #define CRCR_CS (1<<1)
129 #define CRCR_CA (1<<2)
130 #define CRCR_CRR (1<<3)
132 #define IMAN_IP (1<<0)
133 #define IMAN_IE (1<<1)
135 #define ERDP_EHB (1<<3)
138 typedef struct XHCITRB
{
147 typedef enum TRBType
{
160 CR_CONFIGURE_ENDPOINT
,
168 CR_SET_LATENCY_TOLERANCE
,
169 CR_GET_PORT_BANDWIDTH
,
174 ER_PORT_STATUS_CHANGE
,
175 ER_BANDWIDTH_REQUEST
,
178 ER_DEVICE_NOTIFICATION
,
180 /* vendor specific bits */
181 CR_VENDOR_VIA_CHALLENGE_RESPONSE
= 48,
182 CR_VENDOR_NEC_FIRMWARE_REVISION
= 49,
183 CR_VENDOR_NEC_CHALLENGE_RESPONSE
= 50,
186 #define CR_LINK TR_LINK
188 typedef enum TRBCCode
{
191 CC_DATA_BUFFER_ERROR
,
193 CC_USB_TRANSACTION_ERROR
,
199 CC_INVALID_STREAM_TYPE_ERROR
,
200 CC_SLOT_NOT_ENABLED_ERROR
,
201 CC_EP_NOT_ENABLED_ERROR
,
207 CC_BANDWIDTH_OVERRUN
,
208 CC_CONTEXT_STATE_ERROR
,
209 CC_NO_PING_RESPONSE_ERROR
,
210 CC_EVENT_RING_FULL_ERROR
,
211 CC_INCOMPATIBLE_DEVICE_ERROR
,
212 CC_MISSED_SERVICE_ERROR
,
213 CC_COMMAND_RING_STOPPED
,
216 CC_STOPPED_LENGTH_INVALID
,
217 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
= 29,
218 CC_ISOCH_BUFFER_OVERRUN
= 31,
221 CC_INVALID_STREAM_ID_ERROR
,
222 CC_SECONDARY_BANDWIDTH_ERROR
,
223 CC_SPLIT_TRANSACTION_ERROR
227 #define TRB_TYPE_SHIFT 10
228 #define TRB_TYPE_MASK 0x3f
229 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
231 #define TRB_EV_ED (1<<2)
233 #define TRB_TR_ENT (1<<1)
234 #define TRB_TR_ISP (1<<2)
235 #define TRB_TR_NS (1<<3)
236 #define TRB_TR_CH (1<<4)
237 #define TRB_TR_IOC (1<<5)
238 #define TRB_TR_IDT (1<<6)
239 #define TRB_TR_TBC_SHIFT 7
240 #define TRB_TR_TBC_MASK 0x3
241 #define TRB_TR_BEI (1<<9)
242 #define TRB_TR_TLBPC_SHIFT 16
243 #define TRB_TR_TLBPC_MASK 0xf
244 #define TRB_TR_FRAMEID_SHIFT 20
245 #define TRB_TR_FRAMEID_MASK 0x7ff
246 #define TRB_TR_SIA (1<<31)
248 #define TRB_TR_DIR (1<<16)
250 #define TRB_CR_SLOTID_SHIFT 24
251 #define TRB_CR_SLOTID_MASK 0xff
252 #define TRB_CR_EPID_SHIFT 16
253 #define TRB_CR_EPID_MASK 0x1f
255 #define TRB_CR_BSR (1<<9)
256 #define TRB_CR_DC (1<<9)
258 #define TRB_LK_TC (1<<1)
260 #define EP_TYPE_MASK 0x7
261 #define EP_TYPE_SHIFT 3
263 #define EP_STATE_MASK 0x7
264 #define EP_DISABLED (0<<0)
265 #define EP_RUNNING (1<<0)
266 #define EP_HALTED (2<<0)
267 #define EP_STOPPED (3<<0)
268 #define EP_ERROR (4<<0)
270 #define SLOT_STATE_MASK 0x1f
271 #define SLOT_STATE_SHIFT 27
272 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
273 #define SLOT_ENABLED 0
274 #define SLOT_DEFAULT 1
275 #define SLOT_ADDRESSED 2
276 #define SLOT_CONFIGURED 3
278 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
279 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
281 typedef enum EPType
{
292 typedef struct XHCIRing
{
298 typedef struct XHCIPort
{
304 typedef struct XHCIState XHCIState
;
306 typedef struct XHCITransfer
{
314 unsigned int iso_pkts
;
321 unsigned int trb_count
;
322 unsigned int trb_alloced
;
325 unsigned int data_length
;
326 unsigned int data_alloced
;
332 unsigned int pktsize
;
333 unsigned int cur_pkt
;
336 typedef struct XHCIEPContext
{
338 unsigned int next_xfer
;
339 unsigned int comp_xfer
;
340 XHCITransfer transfers
[TD_QUEUE
];
344 unsigned int next_bg
;
345 XHCITransfer bg_transfers
[BG_XFERS
];
348 unsigned int max_psize
;
353 typedef struct XHCISlot
{
357 unsigned int devaddr
;
358 XHCIEPContext
* eps
[31];
361 typedef struct XHCIEvent
{
378 unsigned int devaddr
;
380 /* Operational Registers */
387 uint32_t dcbaap_high
;
390 XHCIPort ports
[MAXPORTS
];
391 XHCISlot slots
[MAXSLOTS
];
393 /* Runtime Registers */
395 /* note: we only support one interrupter */
400 uint32_t erstba_high
;
407 unsigned int er_ep_idx
;
410 XHCIEvent ev_buffer
[EV_QUEUE
];
411 unsigned int ev_buffer_put
;
412 unsigned int ev_buffer_get
;
417 typedef struct XHCIEvRingSeg
{
425 static const char *TRBType_names
[] = {
426 [TRB_RESERVED
] = "TRB_RESERVED",
427 [TR_NORMAL
] = "TR_NORMAL",
428 [TR_SETUP
] = "TR_SETUP",
429 [TR_DATA
] = "TR_DATA",
430 [TR_STATUS
] = "TR_STATUS",
431 [TR_ISOCH
] = "TR_ISOCH",
432 [TR_LINK
] = "TR_LINK",
433 [TR_EVDATA
] = "TR_EVDATA",
434 [TR_NOOP
] = "TR_NOOP",
435 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
436 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
437 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
438 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
439 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
440 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
441 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
442 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
443 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
444 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
445 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
446 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
447 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
448 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
449 [CR_NOOP
] = "CR_NOOP",
450 [ER_TRANSFER
] = "ER_TRANSFER",
451 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
452 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
453 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
454 [ER_DOORBELL
] = "ER_DOORBELL",
455 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
456 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
457 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
458 [CR_VENDOR_VIA_CHALLENGE_RESPONSE
] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
459 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
460 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
463 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
465 if (index
>= llen
|| list
[index
] == NULL
) {
471 static const char *trb_name(XHCITRB
*trb
)
473 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
474 ARRAY_SIZE(TRBType_names
));
478 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
481 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
483 if (sizeof(dma_addr_t
) == 4) {
486 return low
| (((dma_addr_t
)high
<< 16) << 16);
490 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
492 if (sizeof(dma_addr_t
) == 4) {
493 return addr
& 0xffffffff;
499 static void xhci_irq_update(XHCIState
*xhci
)
503 if (xhci
->iman
& IMAN_IP
&& xhci
->iman
& IMAN_IE
&&
504 xhci
->usbcmd
& USBCMD_INTE
) {
508 DPRINTF("xhci_irq_update(): %d\n", level
);
510 if (xhci
->msi
&& msi_enabled(&xhci
->pci_dev
)) {
512 DPRINTF("xhci_irq_update(): MSI signal\n");
513 msi_notify(&xhci
->pci_dev
, 0);
516 qemu_set_irq(xhci
->irq
, level
);
520 static inline int xhci_running(XHCIState
*xhci
)
522 return !(xhci
->usbsts
& USBSTS_HCH
) && !xhci
->er_full
;
525 static void xhci_die(XHCIState
*xhci
)
527 xhci
->usbsts
|= USBSTS_HCE
;
528 fprintf(stderr
, "xhci: asserted controller error\n");
531 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
)
536 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
537 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
538 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
539 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
541 ev_trb
.control
|= TRB_C
;
543 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
545 DPRINTF("xhci_write_event(): [%d] %016"PRIx64
" %08x %08x %s\n",
546 xhci
->er_ep_idx
, ev_trb
.parameter
, ev_trb
.status
, ev_trb
.control
,
549 addr
= xhci
->er_start
+ TRB_SIZE
*xhci
->er_ep_idx
;
550 pci_dma_write(&xhci
->pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
553 if (xhci
->er_ep_idx
>= xhci
->er_size
) {
555 xhci
->er_pcs
= !xhci
->er_pcs
;
559 static void xhci_events_update(XHCIState
*xhci
)
565 if (xhci
->usbsts
& USBSTS_HCH
) {
569 erdp
= xhci_addr64(xhci
->erdp_low
, xhci
->erdp_high
);
570 if (erdp
< xhci
->er_start
||
571 erdp
>= (xhci
->er_start
+ TRB_SIZE
*xhci
->er_size
)) {
572 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
573 fprintf(stderr
, "xhci: ER at "DMA_ADDR_FMT
" len %d\n",
574 xhci
->er_start
, xhci
->er_size
);
578 dp_idx
= (erdp
- xhci
->er_start
) / TRB_SIZE
;
579 assert(dp_idx
< xhci
->er_size
);
581 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
582 * deadlocks when the ER is full. Hack it by holding off events until
583 * the driver decides to free at least half of the ring */
585 int er_free
= dp_idx
- xhci
->er_ep_idx
;
587 er_free
+= xhci
->er_size
;
589 if (er_free
< (xhci
->er_size
/2)) {
590 DPRINTF("xhci_events_update(): event ring still "
591 "more than half full (hack)\n");
596 while (xhci
->ev_buffer_put
!= xhci
->ev_buffer_get
) {
597 assert(xhci
->er_full
);
598 if (((xhci
->er_ep_idx
+1) % xhci
->er_size
) == dp_idx
) {
599 DPRINTF("xhci_events_update(): event ring full again\n");
601 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
602 xhci_write_event(xhci
, &full
);
607 XHCIEvent
*event
= &xhci
->ev_buffer
[xhci
->ev_buffer_get
];
608 xhci_write_event(xhci
, event
);
609 xhci
->ev_buffer_get
++;
611 if (xhci
->ev_buffer_get
== EV_QUEUE
) {
612 xhci
->ev_buffer_get
= 0;
617 xhci
->erdp_low
|= ERDP_EHB
;
618 xhci
->iman
|= IMAN_IP
;
619 xhci
->usbsts
|= USBSTS_EINT
;
620 xhci_irq_update(xhci
);
623 if (xhci
->er_full
&& xhci
->ev_buffer_put
== xhci
->ev_buffer_get
) {
624 DPRINTF("xhci_events_update(): event ring no longer full\n");
630 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
)
636 DPRINTF("xhci_event(): ER full, queueing\n");
637 if (((xhci
->ev_buffer_put
+1) % EV_QUEUE
) == xhci
->ev_buffer_get
) {
638 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
641 xhci
->ev_buffer
[xhci
->ev_buffer_put
++] = *event
;
642 if (xhci
->ev_buffer_put
== EV_QUEUE
) {
643 xhci
->ev_buffer_put
= 0;
648 erdp
= xhci_addr64(xhci
->erdp_low
, xhci
->erdp_high
);
649 if (erdp
< xhci
->er_start
||
650 erdp
>= (xhci
->er_start
+ TRB_SIZE
*xhci
->er_size
)) {
651 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
652 fprintf(stderr
, "xhci: ER at "DMA_ADDR_FMT
" len %d\n",
653 xhci
->er_start
, xhci
->er_size
);
658 dp_idx
= (erdp
- xhci
->er_start
) / TRB_SIZE
;
659 assert(dp_idx
< xhci
->er_size
);
661 if ((xhci
->er_ep_idx
+1) % xhci
->er_size
== dp_idx
) {
662 DPRINTF("xhci_event(): ER full, queueing\n");
664 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
665 xhci_write_event(xhci
, &full
);
668 if (((xhci
->ev_buffer_put
+1) % EV_QUEUE
) == xhci
->ev_buffer_get
) {
669 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
672 xhci
->ev_buffer
[xhci
->ev_buffer_put
++] = *event
;
673 if (xhci
->ev_buffer_put
== EV_QUEUE
) {
674 xhci
->ev_buffer_put
= 0;
677 xhci_write_event(xhci
, event
);
680 xhci
->erdp_low
|= ERDP_EHB
;
681 xhci
->iman
|= IMAN_IP
;
682 xhci
->usbsts
|= USBSTS_EINT
;
684 xhci_irq_update(xhci
);
687 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
691 ring
->dequeue
= base
;
695 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
700 pci_dma_read(&xhci
->pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
701 trb
->addr
= ring
->dequeue
;
702 trb
->ccs
= ring
->ccs
;
703 le64_to_cpus(&trb
->parameter
);
704 le32_to_cpus(&trb
->status
);
705 le32_to_cpus(&trb
->control
);
707 DPRINTF("xhci: TRB fetched [" DMA_ADDR_FMT
"]: "
708 "%016" PRIx64
" %08x %08x %s\n",
709 ring
->dequeue
, trb
->parameter
, trb
->status
, trb
->control
,
712 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
716 type
= TRB_TYPE(*trb
);
718 if (type
!= TR_LINK
) {
720 *addr
= ring
->dequeue
;
722 ring
->dequeue
+= TRB_SIZE
;
725 ring
->dequeue
= xhci_mask64(trb
->parameter
);
726 if (trb
->control
& TRB_LK_TC
) {
727 ring
->ccs
= !ring
->ccs
;
733 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
737 dma_addr_t dequeue
= ring
->dequeue
;
738 bool ccs
= ring
->ccs
;
739 /* hack to bundle together the two/three TDs that make a setup transfer */
740 bool control_td_set
= 0;
744 pci_dma_read(&xhci
->pci_dev
, dequeue
, &trb
, TRB_SIZE
);
745 le64_to_cpus(&trb
.parameter
);
746 le32_to_cpus(&trb
.status
);
747 le32_to_cpus(&trb
.control
);
749 DPRINTF("xhci: TRB peeked [" DMA_ADDR_FMT
"]: "
750 "%016" PRIx64
" %08x %08x\n",
751 dequeue
, trb
.parameter
, trb
.status
, trb
.control
);
753 if ((trb
.control
& TRB_C
) != ccs
) {
757 type
= TRB_TYPE(trb
);
759 if (type
== TR_LINK
) {
760 dequeue
= xhci_mask64(trb
.parameter
);
761 if (trb
.control
& TRB_LK_TC
) {
770 if (type
== TR_SETUP
) {
772 } else if (type
== TR_STATUS
) {
776 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
782 static void xhci_er_reset(XHCIState
*xhci
)
786 /* cache the (sole) event ring segment location */
787 if (xhci
->erstsz
!= 1) {
788 fprintf(stderr
, "xhci: invalid value for ERSTSZ: %d\n", xhci
->erstsz
);
792 dma_addr_t erstba
= xhci_addr64(xhci
->erstba_low
, xhci
->erstba_high
);
793 pci_dma_read(&xhci
->pci_dev
, erstba
, &seg
, sizeof(seg
));
794 le32_to_cpus(&seg
.addr_low
);
795 le32_to_cpus(&seg
.addr_high
);
796 le32_to_cpus(&seg
.size
);
797 if (seg
.size
< 16 || seg
.size
> 4096) {
798 fprintf(stderr
, "xhci: invalid value for segment size: %d\n", seg
.size
);
802 xhci
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
803 xhci
->er_size
= seg
.size
;
809 DPRINTF("xhci: event ring:" DMA_ADDR_FMT
" [%d]\n",
810 xhci
->er_start
, xhci
->er_size
);
813 static void xhci_run(XHCIState
*xhci
)
815 DPRINTF("xhci_run()\n");
817 xhci
->usbsts
&= ~USBSTS_HCH
;
820 static void xhci_stop(XHCIState
*xhci
)
822 DPRINTF("xhci_stop()\n");
823 xhci
->usbsts
|= USBSTS_HCH
;
824 xhci
->crcr_low
&= ~CRCR_CRR
;
827 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
831 if (epctx
->state
== state
) {
835 pci_dma_read(&xhci
->pci_dev
, epctx
->pctx
, ctx
, sizeof(ctx
));
836 ctx
[0] &= ~EP_STATE_MASK
;
838 ctx
[2] = epctx
->ring
.dequeue
| epctx
->ring
.ccs
;
839 ctx
[3] = (epctx
->ring
.dequeue
>> 16) >> 16;
840 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
841 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
842 pci_dma_write(&xhci
->pci_dev
, epctx
->pctx
, ctx
, sizeof(ctx
));
843 epctx
->state
= state
;
846 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
847 unsigned int epid
, dma_addr_t pctx
,
851 XHCIEPContext
*epctx
;
855 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
856 assert(epid
>= 1 && epid
<= 31);
858 DPRINTF("xhci_enable_ep(%d, %d)\n", slotid
, epid
);
860 slot
= &xhci
->slots
[slotid
-1];
861 if (slot
->eps
[epid
-1]) {
862 fprintf(stderr
, "xhci: slot %d ep %d already enabled!\n", slotid
, epid
);
866 epctx
= g_malloc(sizeof(XHCIEPContext
));
867 memset(epctx
, 0, sizeof(XHCIEPContext
));
869 slot
->eps
[epid
-1] = epctx
;
871 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
872 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
);
873 epctx
->ring
.ccs
= ctx
[2] & 1;
875 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
876 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid
/2, epid
%2, epctx
->type
);
878 epctx
->max_psize
= ctx
[1]>>16;
879 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
880 epctx
->has_bg
= false;
881 if (epctx
->type
== ET_ISO_IN
) {
882 epctx
->has_bg
= true;
884 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
885 epid
/2, epid
%2, epctx
->max_psize
);
886 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
887 usb_packet_init(&epctx
->transfers
[i
].packet
);
890 epctx
->state
= EP_RUNNING
;
891 ctx
[0] &= ~EP_STATE_MASK
;
892 ctx
[0] |= EP_RUNNING
;
897 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
901 XHCIEPContext
*epctx
;
902 int i
, xferi
, killed
= 0;
903 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
904 assert(epid
>= 1 && epid
<= 31);
906 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
908 slot
= &xhci
->slots
[slotid
-1];
910 if (!slot
->eps
[epid
-1]) {
914 epctx
= slot
->eps
[epid
-1];
916 xferi
= epctx
->next_xfer
;
917 for (i
= 0; i
< TD_QUEUE
; i
++) {
918 XHCITransfer
*t
= &epctx
->transfers
[xferi
];
919 if (t
->running_async
) {
920 usb_cancel_packet(&t
->packet
);
921 t
->running_async
= 0;
923 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i
);
926 if (t
->running_retry
) {
927 t
->running_retry
= 0;
930 if (t
->backgrounded
) {
942 t
->trb_count
= t
->trb_alloced
= 0;
943 t
->data_length
= t
->data_alloced
= 0;
944 xferi
= (xferi
+ 1) % TD_QUEUE
;
947 xferi
= epctx
->next_bg
;
948 for (i
= 0; i
< BG_XFERS
; i
++) {
949 XHCITransfer
*t
= &epctx
->bg_transfers
[xferi
];
950 if (t
->running_async
) {
951 usb_cancel_packet(&t
->packet
);
952 t
->running_async
= 0;
954 DPRINTF("xhci: cancelling bg transfer %d, waiting for it to complete...\n", i
);
962 xferi
= (xferi
+ 1) % BG_XFERS
;
968 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
972 XHCIEPContext
*epctx
;
974 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
975 assert(epid
>= 1 && epid
<= 31);
977 DPRINTF("xhci_disable_ep(%d, %d)\n", slotid
, epid
);
979 slot
= &xhci
->slots
[slotid
-1];
981 if (!slot
->eps
[epid
-1]) {
982 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
986 xhci_ep_nuke_xfers(xhci
, slotid
, epid
);
988 epctx
= slot
->eps
[epid
-1];
990 xhci_set_ep_state(xhci
, epctx
, EP_DISABLED
);
993 slot
->eps
[epid
-1] = NULL
;
998 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1002 XHCIEPContext
*epctx
;
1004 DPRINTF("xhci_stop_ep(%d, %d)\n", slotid
, epid
);
1006 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1008 if (epid
< 1 || epid
> 31) {
1009 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1010 return CC_TRB_ERROR
;
1013 slot
= &xhci
->slots
[slotid
-1];
1015 if (!slot
->eps
[epid
-1]) {
1016 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1017 return CC_EP_NOT_ENABLED_ERROR
;
1020 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1021 fprintf(stderr
, "xhci: FIXME: endpoint stopped w/ xfers running, "
1022 "data might be lost\n");
1025 epctx
= slot
->eps
[epid
-1];
1027 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1032 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1036 XHCIEPContext
*epctx
;
1039 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1041 DPRINTF("xhci_reset_ep(%d, %d)\n", slotid
, epid
);
1043 if (epid
< 1 || epid
> 31) {
1044 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1045 return CC_TRB_ERROR
;
1048 slot
= &xhci
->slots
[slotid
-1];
1050 if (!slot
->eps
[epid
-1]) {
1051 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1052 return CC_EP_NOT_ENABLED_ERROR
;
1055 epctx
= slot
->eps
[epid
-1];
1057 if (epctx
->state
!= EP_HALTED
) {
1058 fprintf(stderr
, "xhci: reset EP while EP %d not halted (%d)\n",
1059 epid
, epctx
->state
);
1060 return CC_CONTEXT_STATE_ERROR
;
1063 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1064 fprintf(stderr
, "xhci: FIXME: endpoint reset w/ xfers running, "
1065 "data might be lost\n");
1068 uint8_t ep
= epid
>>1;
1074 dev
= xhci
->ports
[xhci
->slots
[slotid
-1].port
-1].port
.dev
;
1076 return CC_USB_TRANSACTION_ERROR
;
1079 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1084 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1085 unsigned int epid
, uint64_t pdequeue
)
1088 XHCIEPContext
*epctx
;
1091 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1093 if (epid
< 1 || epid
> 31) {
1094 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1095 return CC_TRB_ERROR
;
1098 DPRINTF("xhci_set_ep_dequeue(%d, %d, %016"PRIx64
")\n", slotid
, epid
, pdequeue
);
1099 dequeue
= xhci_mask64(pdequeue
);
1101 slot
= &xhci
->slots
[slotid
-1];
1103 if (!slot
->eps
[epid
-1]) {
1104 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1105 return CC_EP_NOT_ENABLED_ERROR
;
1108 epctx
= slot
->eps
[epid
-1];
1111 if (epctx
->state
!= EP_STOPPED
) {
1112 fprintf(stderr
, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1113 return CC_CONTEXT_STATE_ERROR
;
1116 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1117 epctx
->ring
.ccs
= dequeue
& 1;
1119 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1124 static int xhci_xfer_data(XHCITransfer
*xfer
, uint8_t *data
,
1125 unsigned int length
, bool in_xfer
, bool out_xfer
,
1130 unsigned int transferred
= 0;
1131 unsigned int left
= length
;
1134 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1135 XHCIState
*xhci
= xfer
->xhci
;
1137 DPRINTF("xhci_xfer_data(len=%d, in_xfer=%d, out_xfer=%d, report=%d)\n",
1138 length
, in_xfer
, out_xfer
, report
);
1140 assert(!(in_xfer
&& out_xfer
));
1142 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1143 XHCITRB
*trb
= &xfer
->trbs
[i
];
1145 unsigned int chunk
= 0;
1147 switch (TRB_TYPE(*trb
)) {
1149 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1150 fprintf(stderr
, "xhci: data direction mismatch for TR_DATA\n");
1157 addr
= xhci_mask64(trb
->parameter
);
1158 chunk
= trb
->status
& 0x1ffff;
1163 if (in_xfer
|| out_xfer
) {
1164 if (trb
->control
& TRB_TR_IDT
) {
1166 if (chunk
> 8 || in_xfer
) {
1167 fprintf(stderr
, "xhci: invalid immediate data TRB\n");
1171 idata
= le64_to_cpu(trb
->parameter
);
1172 memcpy(data
, &idata
, chunk
);
1174 DPRINTF("xhci_xfer_data: r/w(%d) %d bytes at "
1175 DMA_ADDR_FMT
"\n", in_xfer
, chunk
, addr
);
1177 pci_dma_write(&xhci
->pci_dev
, addr
, data
, chunk
);
1179 pci_dma_read(&xhci
->pci_dev
, addr
, data
, chunk
);
1182 unsigned int count
= chunk
;
1188 for (i
= 0; i
< count
; i
++) {
1189 DPRINTF(" %02x", data
[i
]);
1198 transferred
+= chunk
;
1206 if (report
&& !reported
&& (trb
->control
& TRB_TR_IOC
||
1207 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)))) {
1208 event
.slotid
= xfer
->slotid
;
1209 event
.epid
= xfer
->epid
;
1210 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1212 event
.ptr
= trb
->addr
;
1213 if (xfer
->status
== CC_SUCCESS
) {
1214 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1216 event
.ccode
= xfer
->status
;
1218 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1219 event
.ptr
= trb
->parameter
;
1220 event
.flags
|= TRB_EV_ED
;
1221 event
.length
= edtla
& 0xffffff;
1222 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1225 xhci_event(xhci
, &event
);
1232 static void xhci_stall_ep(XHCITransfer
*xfer
)
1234 XHCIState
*xhci
= xfer
->xhci
;
1235 XHCISlot
*slot
= &xhci
->slots
[xfer
->slotid
-1];
1236 XHCIEPContext
*epctx
= slot
->eps
[xfer
->epid
-1];
1238 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1239 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1240 xhci_set_ep_state(xhci
, epctx
, EP_HALTED
);
1241 DPRINTF("xhci: stalled slot %d ep %d\n", xfer
->slotid
, xfer
->epid
);
1242 DPRINTF("xhci: will continue at "DMA_ADDR_FMT
"\n", epctx
->ring
.dequeue
);
1245 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
,
1246 XHCIEPContext
*epctx
);
1248 static void xhci_bg_update(XHCIState
*xhci
, XHCIEPContext
*epctx
)
1250 if (epctx
->bg_updating
) {
1253 DPRINTF("xhci_bg_update(%p, %p)\n", xhci
, epctx
);
1254 assert(epctx
->has_bg
);
1255 DPRINTF("xhci: fg=%d bg=%d\n", epctx
->comp_xfer
, epctx
->next_bg
);
1256 epctx
->bg_updating
= 1;
1257 while (epctx
->transfers
[epctx
->comp_xfer
].backgrounded
&&
1258 epctx
->bg_transfers
[epctx
->next_bg
].complete
) {
1259 XHCITransfer
*fg
= &epctx
->transfers
[epctx
->comp_xfer
];
1260 XHCITransfer
*bg
= &epctx
->bg_transfers
[epctx
->next_bg
];
1262 DPRINTF("xhci: completing fg %d from bg %d.%d (stat: %d)\n",
1263 epctx
->comp_xfer
, epctx
->next_bg
, bg
->cur_pkt
,
1264 bg
->usbxfer
->iso_packet_desc
[bg
->cur_pkt
].status
1267 assert(epctx
->type
== ET_ISO_IN
);
1268 assert(bg
->iso_xfer
);
1269 assert(bg
->in_xfer
);
1270 uint8_t *p
= bg
->data
+ bg
->cur_pkt
* bg
->pktsize
;
1272 int len
= bg
->usbxfer
->iso_packet_desc
[bg
->cur_pkt
].actual_length
;
1273 fg
->status
= libusb_to_ccode(bg
->usbxfer
->iso_packet_desc
[bg
->cur_pkt
].status
);
1279 fg
->backgrounded
= 0;
1281 if (fg
->status
== CC_STALL_ERROR
) {
1285 xhci_xfer_data(fg
, p
, len
, 1, 0, 1);
1288 if (epctx
->comp_xfer
== TD_QUEUE
) {
1289 epctx
->comp_xfer
= 0;
1291 DPRINTF("next fg xfer: %d\n", epctx
->comp_xfer
);
1293 if (bg
->cur_pkt
== bg
->pkts
) {
1295 if (xhci_submit(xhci
, bg
, epctx
) < 0) {
1296 fprintf(stderr
, "xhci: bg resubmit failed\n");
1299 if (epctx
->next_bg
== BG_XFERS
) {
1302 DPRINTF("next bg xfer: %d\n", epctx
->next_bg
);
1304 xhci_kick_ep(xhci
, fg
->slotid
, fg
->epid
);
1307 epctx
->bg_updating
= 0;
1311 static void xhci_xfer_cb(struct libusb_transfer
*transfer
)
1316 xfer
= (XHCITransfer
*)transfer
->user_data
;
1319 DPRINTF("xhci_xfer_cb(slot=%d, ep=%d, status=%d)\n", xfer
->slotid
,
1320 xfer
->epid
, transfer
->status
);
1322 assert(xfer
->slotid
>= 1 && xfer
->slotid
<= MAXSLOTS
);
1323 assert(xfer
->epid
>= 1 && xfer
->epid
<= 31);
1325 if (xfer
->cancelled
) {
1326 DPRINTF("xhci: transfer cancelled, not reporting anything\n");
1331 XHCIEPContext
*epctx
;
1333 slot
= &xhci
->slots
[xfer
->slotid
-1];
1334 assert(slot
->eps
[xfer
->epid
-1]);
1335 epctx
= slot
->eps
[xfer
->epid
-1];
1337 if (xfer
->bg_xfer
) {
1338 DPRINTF("xhci: background transfer, updating\n");
1341 xhci_bg_update(xhci
, epctx
);
1345 if (xfer
->iso_xfer
) {
1346 transfer
->status
= transfer
->iso_packet_desc
[0].status
;
1347 transfer
->actual_length
= transfer
->iso_packet_desc
[0].actual_length
;
1350 xfer
->status
= libusb_to_ccode(transfer
->status
);
1355 if (transfer
->status
== LIBUSB_TRANSFER_STALL
)
1356 xhci_stall_ep(xhci
, epctx
, xfer
);
1358 DPRINTF("xhci: transfer actual length = %d\n", transfer
->actual_length
);
1360 if (xfer
->in_xfer
) {
1361 if (xfer
->epid
== 1) {
1362 xhci_xfer_data(xhci
, xfer
, xfer
->data
+ 8,
1363 transfer
->actual_length
, 1, 0, 1);
1365 xhci_xfer_data(xhci
, xfer
, xfer
->data
,
1366 transfer
->actual_length
, 1, 0, 1);
1369 xhci_xfer_data(xhci
, xfer
, NULL
, transfer
->actual_length
, 0, 0, 1);
1372 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1375 static int xhci_hle_control(XHCIState
*xhci
, XHCITransfer
*xfer
,
1376 uint8_t bmRequestType
, uint8_t bRequest
,
1377 uint16_t wValue
, uint16_t wIndex
, uint16_t wLength
)
1379 uint16_t type_req
= (bmRequestType
<< 8) | bRequest
;
1382 case 0x0000 | USB_REQ_SET_CONFIGURATION
:
1383 DPRINTF("xhci: HLE switch configuration\n");
1384 return xhci_switch_config(xhci
, xfer
->slotid
, wValue
) == 0;
1385 case 0x0100 | USB_REQ_SET_INTERFACE
:
1386 DPRINTF("xhci: HLE set interface altsetting\n");
1387 return xhci_set_iface_alt(xhci
, xfer
->slotid
, wIndex
, wValue
) == 0;
1388 case 0x0200 | USB_REQ_CLEAR_FEATURE
:
1389 if (wValue
== 0) { // endpoint halt
1390 DPRINTF("xhci: HLE clear halt\n");
1391 return xhci_clear_halt(xhci
, xfer
->slotid
, wIndex
);
1393 case 0x0000 | USB_REQ_SET_ADDRESS
:
1394 fprintf(stderr
, "xhci: warn: illegal SET_ADDRESS request\n");
1402 static int xhci_setup_packet(XHCITransfer
*xfer
, USBDevice
*dev
)
1407 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1408 ep
= usb_ep_get(dev
, dir
, xfer
->epid
>> 1);
1409 usb_packet_setup(&xfer
->packet
, dir
, ep
);
1410 usb_packet_addbuf(&xfer
->packet
, xfer
->data
, xfer
->data_length
);
1411 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1412 xfer
->packet
.pid
, dev
->addr
, ep
->nr
);
1416 static int xhci_complete_packet(XHCITransfer
*xfer
, int ret
)
1418 if (ret
== USB_RET_ASYNC
) {
1419 xfer
->running_async
= 1;
1420 xfer
->running_retry
= 0;
1422 xfer
->cancelled
= 0;
1424 } else if (ret
== USB_RET_NAK
) {
1425 xfer
->running_async
= 0;
1426 xfer
->running_retry
= 1;
1428 xfer
->cancelled
= 0;
1431 xfer
->running_async
= 0;
1432 xfer
->running_retry
= 0;
1437 xfer
->status
= CC_SUCCESS
;
1438 xhci_xfer_data(xfer
, xfer
->data
, ret
, xfer
->in_xfer
, 0, 1);
1445 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1446 xhci_xfer_data(xfer
, xfer
->data
, 0, xfer
->in_xfer
, 0, 1);
1447 xhci_stall_ep(xfer
);
1450 xfer
->status
= CC_STALL_ERROR
;
1451 xhci_xfer_data(xfer
, xfer
->data
, 0, xfer
->in_xfer
, 0, 1);
1452 xhci_stall_ep(xfer
);
1455 fprintf(stderr
, "%s: FIXME: ret = %d\n", __FUNCTION__
, ret
);
1461 static USBDevice
*xhci_find_device(XHCIPort
*port
, uint8_t addr
)
1463 if (!(port
->portsc
& PORTSC_PED
)) {
1466 return usb_find_device(&port
->port
, addr
);
1469 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1471 XHCITRB
*trb_setup
, *trb_status
;
1472 uint8_t bmRequestType
;
1478 DPRINTF("xhci_fire_ctl_transfer(slot=%d)\n", xfer
->slotid
);
1480 trb_setup
= &xfer
->trbs
[0];
1481 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1483 /* at most one Event Data TRB allowed after STATUS */
1484 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1488 /* do some sanity checks */
1489 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1490 fprintf(stderr
, "xhci: ep0 first TD not SETUP: %d\n",
1491 TRB_TYPE(*trb_setup
));
1494 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1495 fprintf(stderr
, "xhci: ep0 last TD not STATUS: %d\n",
1496 TRB_TYPE(*trb_status
));
1499 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1500 fprintf(stderr
, "xhci: Setup TRB doesn't have IDT set\n");
1503 if ((trb_setup
->status
& 0x1ffff) != 8) {
1504 fprintf(stderr
, "xhci: Setup TRB has bad length (%d)\n",
1505 (trb_setup
->status
& 0x1ffff));
1509 bmRequestType
= trb_setup
->parameter
;
1510 wLength
= trb_setup
->parameter
>> 48;
1512 if (xfer
->data
&& xfer
->data_alloced
< wLength
) {
1513 xfer
->data_alloced
= 0;
1518 DPRINTF("xhci: alloc %d bytes data\n", wLength
);
1519 xfer
->data
= g_malloc(wLength
+1);
1520 xfer
->data_alloced
= wLength
;
1522 xfer
->data_length
= wLength
;
1524 port
= &xhci
->ports
[xhci
->slots
[xfer
->slotid
-1].port
-1];
1525 dev
= xhci_find_device(port
, xhci
->slots
[xfer
->slotid
-1].devaddr
);
1527 fprintf(stderr
, "xhci: slot %d port %d has no device\n", xfer
->slotid
,
1528 xhci
->slots
[xfer
->slotid
-1].port
);
1532 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1533 xfer
->iso_xfer
= false;
1535 xhci_setup_packet(xfer
, dev
);
1536 xfer
->packet
.parameter
= trb_setup
->parameter
;
1537 if (!xfer
->in_xfer
) {
1538 xhci_xfer_data(xfer
, xfer
->data
, wLength
, 0, 1, 0);
1541 ret
= usb_handle_packet(dev
, &xfer
->packet
);
1543 xhci_complete_packet(xfer
, ret
);
1544 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1545 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1550 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1556 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1558 xfer
->in_xfer
= epctx
->type
>>2;
1560 if (xfer
->data
&& xfer
->data_alloced
< xfer
->data_length
) {
1561 xfer
->data_alloced
= 0;
1565 if (!xfer
->data
&& xfer
->data_length
) {
1566 DPRINTF("xhci: alloc %d bytes data\n", xfer
->data_length
);
1567 xfer
->data
= g_malloc(xfer
->data_length
);
1568 xfer
->data_alloced
= xfer
->data_length
;
1570 if (epctx
->type
== ET_ISO_IN
|| epctx
->type
== ET_ISO_OUT
) {
1571 if (!xfer
->bg_xfer
) {
1578 port
= &xhci
->ports
[xhci
->slots
[xfer
->slotid
-1].port
-1];
1579 dev
= xhci_find_device(port
, xhci
->slots
[xfer
->slotid
-1].devaddr
);
1581 fprintf(stderr
, "xhci: slot %d port %d has no device\n", xfer
->slotid
,
1582 xhci
->slots
[xfer
->slotid
-1].port
);
1586 xhci_setup_packet(xfer
, dev
);
1588 switch(epctx
->type
) {
1599 fprintf(stderr
, "xhci: unknown or unhandled EP "
1600 "(type %d, in %d, ep %02x)\n",
1601 epctx
->type
, xfer
->in_xfer
, xfer
->epid
);
1605 if (!xfer
->in_xfer
) {
1606 xhci_xfer_data(xfer
, xfer
->data
, xfer
->data_length
, 0, 1, 0);
1608 ret
= usb_handle_packet(dev
, &xfer
->packet
);
1610 xhci_complete_packet(xfer
, ret
);
1611 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1612 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1617 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1620 unsigned int length
= 0;
1623 DPRINTF("xhci_fire_transfer(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1625 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1626 trb
= &xfer
->trbs
[i
];
1627 if (TRB_TYPE(*trb
) == TR_NORMAL
|| TRB_TYPE(*trb
) == TR_ISOCH
) {
1628 length
+= trb
->status
& 0x1ffff;
1631 DPRINTF("xhci: total TD length=%d\n", length
);
1633 if (!epctx
->has_bg
) {
1634 xfer
->data_length
= length
;
1635 xfer
->backgrounded
= 0;
1636 return xhci_submit(xhci
, xfer
, epctx
);
1638 if (!epctx
->bg_running
) {
1639 for (i
= 0; i
< BG_XFERS
; i
++) {
1640 XHCITransfer
*t
= &epctx
->bg_transfers
[i
];
1642 t
->epid
= xfer
->epid
;
1643 t
->slotid
= xfer
->slotid
;
1645 t
->pktsize
= epctx
->max_psize
;
1646 t
->data_length
= t
->pkts
* t
->pktsize
;
1648 if (xhci_submit(xhci
, t
, epctx
) < 0) {
1649 fprintf(stderr
, "xhci: bg submit failed\n");
1653 epctx
->bg_running
= 1;
1655 xfer
->backgrounded
= 1;
1656 xhci_bg_update(xhci
, epctx
);
1661 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
, unsigned int epid
)
1663 XHCIEPContext
*epctx
;
1667 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1668 assert(epid
>= 1 && epid
<= 31);
1669 DPRINTF("xhci_kick_ep(%d, %d)\n", slotid
, epid
);
1671 if (!xhci
->slots
[slotid
-1].enabled
) {
1672 fprintf(stderr
, "xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1675 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1677 fprintf(stderr
, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1683 /* retry nak'ed transfer */
1684 XHCITransfer
*xfer
= epctx
->retry
;
1687 DPRINTF("xhci: retry nack'ed transfer ...\n");
1688 assert(xfer
->running_retry
);
1689 xhci_setup_packet(xfer
, xfer
->packet
.ep
->dev
);
1690 result
= usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1691 if (result
== USB_RET_NAK
) {
1692 DPRINTF("xhci: ... xfer still nacked\n");
1695 DPRINTF("xhci: ... result %d\n", result
);
1696 xhci_complete_packet(xfer
, result
);
1697 assert(!xfer
->running_retry
);
1698 epctx
->retry
= NULL
;
1701 if (epctx
->state
== EP_HALTED
) {
1702 DPRINTF("xhci: ep halted, not running schedule\n");
1706 xhci_set_ep_state(xhci
, epctx
, EP_RUNNING
);
1709 XHCITransfer
*xfer
= &epctx
->transfers
[epctx
->next_xfer
];
1710 if (xfer
->running_async
|| xfer
->running_retry
|| xfer
->backgrounded
) {
1711 DPRINTF("xhci: ep is busy (#%d,%d,%d,%d)\n",
1712 epctx
->next_xfer
, xfer
->running_async
,
1713 xfer
->running_retry
, xfer
->backgrounded
);
1716 DPRINTF("xhci: ep: using #%d\n", epctx
->next_xfer
);
1718 length
= xhci_ring_chain_length(xhci
, &epctx
->ring
);
1720 DPRINTF("xhci: incomplete TD (%d TRBs)\n", -length
);
1722 } else if (length
== 0) {
1725 DPRINTF("xhci: fetching %d-TRB TD\n", length
);
1726 if (xfer
->trbs
&& xfer
->trb_alloced
< length
) {
1727 xfer
->trb_count
= 0;
1728 xfer
->trb_alloced
= 0;
1733 xfer
->trbs
= g_malloc(sizeof(XHCITRB
) * length
);
1734 xfer
->trb_alloced
= length
;
1736 xfer
->trb_count
= length
;
1738 for (i
= 0; i
< length
; i
++) {
1739 assert(xhci_ring_fetch(xhci
, &epctx
->ring
, &xfer
->trbs
[i
], NULL
));
1743 xfer
->slotid
= slotid
;
1746 if (xhci_fire_ctl_transfer(xhci
, xfer
) >= 0) {
1747 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1749 fprintf(stderr
, "xhci: error firing CTL transfer\n");
1752 if (xhci_fire_transfer(xhci
, xfer
, epctx
) >= 0) {
1753 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1755 fprintf(stderr
, "xhci: error firing data transfer\n");
1759 if (epctx
->state
== EP_HALTED
) {
1760 DPRINTF("xhci: ep halted, stopping schedule\n");
1763 if (xfer
->running_retry
) {
1764 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1765 epctx
->retry
= xfer
;
1771 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
1773 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1774 DPRINTF("xhci_enable_slot(%d)\n", slotid
);
1775 xhci
->slots
[slotid
-1].enabled
= 1;
1776 xhci
->slots
[slotid
-1].port
= 0;
1777 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
1782 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
1786 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1787 DPRINTF("xhci_disable_slot(%d)\n", slotid
);
1789 for (i
= 1; i
<= 31; i
++) {
1790 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1791 xhci_disable_ep(xhci
, slotid
, i
);
1795 xhci
->slots
[slotid
-1].enabled
= 0;
1799 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
1800 uint64_t pictx
, bool bsr
)
1804 dma_addr_t ictx
, octx
, dcbaap
;
1806 uint32_t ictl_ctx
[2];
1807 uint32_t slot_ctx
[4];
1808 uint32_t ep0_ctx
[5];
1813 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1814 DPRINTF("xhci_address_slot(%d)\n", slotid
);
1816 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
1817 pci_dma_read(&xhci
->pci_dev
, dcbaap
+ 8*slotid
, &poctx
, sizeof(poctx
));
1818 ictx
= xhci_mask64(pictx
);
1819 octx
= xhci_mask64(le64_to_cpu(poctx
));
1821 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1822 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1824 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1826 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
1827 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1828 ictl_ctx
[0], ictl_ctx
[1]);
1829 return CC_TRB_ERROR
;
1832 pci_dma_read(&xhci
->pci_dev
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
1833 pci_dma_read(&xhci
->pci_dev
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
1835 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1836 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1838 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1839 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1841 port
= (slot_ctx
[1]>>16) & 0xFF;
1842 dev
= xhci
->ports
[port
-1].port
.dev
;
1844 if (port
< 1 || port
> MAXPORTS
) {
1845 fprintf(stderr
, "xhci: bad port %d\n", port
);
1846 return CC_TRB_ERROR
;
1848 fprintf(stderr
, "xhci: port %d not connected\n", port
);
1849 return CC_USB_TRANSACTION_ERROR
;
1852 for (i
= 0; i
< MAXSLOTS
; i
++) {
1853 if (xhci
->slots
[i
].port
== port
) {
1854 fprintf(stderr
, "xhci: port %d already assigned to slot %d\n",
1856 return CC_TRB_ERROR
;
1860 slot
= &xhci
->slots
[slotid
-1];
1865 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
1867 slot
->devaddr
= xhci
->devaddr
++;
1868 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slot
->devaddr
;
1869 DPRINTF("xhci: device address is %d\n", slot
->devaddr
);
1870 usb_device_handle_control(dev
, NULL
,
1871 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
1872 slot
->devaddr
, 0, 0, NULL
);
1875 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
1877 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1878 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1879 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1880 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1882 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1883 pci_dma_write(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
1889 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
1890 uint64_t pictx
, bool dc
)
1892 dma_addr_t ictx
, octx
;
1893 uint32_t ictl_ctx
[2];
1894 uint32_t slot_ctx
[4];
1895 uint32_t islot_ctx
[4];
1900 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1901 DPRINTF("xhci_configure_slot(%d)\n", slotid
);
1903 ictx
= xhci_mask64(pictx
);
1904 octx
= xhci
->slots
[slotid
-1].ctx
;
1906 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1907 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1910 for (i
= 2; i
<= 31; i
++) {
1911 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1912 xhci_disable_ep(xhci
, slotid
, i
);
1916 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1917 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
1918 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
1919 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1920 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1921 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1926 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1928 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
1929 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1930 ictl_ctx
[0], ictl_ctx
[1]);
1931 return CC_TRB_ERROR
;
1934 pci_dma_read(&xhci
->pci_dev
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
1935 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1937 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
1938 fprintf(stderr
, "xhci: invalid slot state %08x\n", slot_ctx
[3]);
1939 return CC_CONTEXT_STATE_ERROR
;
1942 for (i
= 2; i
<= 31; i
++) {
1943 if (ictl_ctx
[0] & (1<<i
)) {
1944 xhci_disable_ep(xhci
, slotid
, i
);
1946 if (ictl_ctx
[1] & (1<<i
)) {
1947 pci_dma_read(&xhci
->pci_dev
, ictx
+32+(32*i
), ep_ctx
,
1949 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1950 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
1951 ep_ctx
[3], ep_ctx
[4]);
1952 xhci_disable_ep(xhci
, slotid
, i
);
1953 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
1954 if (res
!= CC_SUCCESS
) {
1957 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1958 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
1959 ep_ctx
[3], ep_ctx
[4]);
1960 pci_dma_write(&xhci
->pci_dev
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
1964 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
1965 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
1966 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
1967 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
1968 SLOT_CONTEXT_ENTRIES_SHIFT
);
1969 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1970 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1972 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1978 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
1981 dma_addr_t ictx
, octx
;
1982 uint32_t ictl_ctx
[2];
1983 uint32_t iep0_ctx
[5];
1984 uint32_t ep0_ctx
[5];
1985 uint32_t islot_ctx
[4];
1986 uint32_t slot_ctx
[4];
1988 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1989 DPRINTF("xhci_evaluate_slot(%d)\n", slotid
);
1991 ictx
= xhci_mask64(pictx
);
1992 octx
= xhci
->slots
[slotid
-1].ctx
;
1994 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1995 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1997 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1999 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2000 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2001 ictl_ctx
[0], ictl_ctx
[1]);
2002 return CC_TRB_ERROR
;
2005 if (ictl_ctx
[1] & 0x1) {
2006 pci_dma_read(&xhci
->pci_dev
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2008 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2009 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2011 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2013 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2014 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2015 slot_ctx
[2] &= ~0xFF00000; /* interrupter target */
2016 slot_ctx
[2] |= islot_ctx
[2] & 0xFF000000;
2018 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2019 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2021 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2024 if (ictl_ctx
[1] & 0x2) {
2025 pci_dma_read(&xhci
->pci_dev
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2027 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2028 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2029 iep0_ctx
[3], iep0_ctx
[4]);
2031 pci_dma_read(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2033 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2034 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2036 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2037 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2039 pci_dma_write(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2045 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2047 uint32_t slot_ctx
[4];
2051 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
2052 DPRINTF("xhci_reset_slot(%d)\n", slotid
);
2054 octx
= xhci
->slots
[slotid
-1].ctx
;
2056 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2058 for (i
= 2; i
<= 31; i
++) {
2059 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2060 xhci_disable_ep(xhci
, slotid
, i
);
2064 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2065 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2066 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2067 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2068 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2069 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2074 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2076 unsigned int slotid
;
2077 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2078 if (slotid
< 1 || slotid
> MAXSLOTS
) {
2079 fprintf(stderr
, "xhci: bad slot id %d\n", slotid
);
2080 event
->ccode
= CC_TRB_ERROR
;
2082 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2083 fprintf(stderr
, "xhci: slot id %d not enabled\n", slotid
);
2084 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2090 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2093 uint8_t bw_ctx
[MAXPORTS
+1];
2095 DPRINTF("xhci_get_port_bandwidth()\n");
2097 ctx
= xhci_mask64(pctx
);
2099 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2101 /* TODO: actually implement real values here */
2103 memset(&bw_ctx
[1], 80, MAXPORTS
); /* 80% */
2104 pci_dma_write(&xhci
->pci_dev
, ctx
, bw_ctx
, sizeof(bw_ctx
));
2109 static uint32_t rotl(uint32_t v
, unsigned count
)
2112 return (v
<< count
) | (v
>> (32 - count
));
2116 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2119 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2120 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2121 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2125 static void xhci_via_challenge(XHCIState
*xhci
, uint64_t addr
)
2129 dma_addr_t paddr
= xhci_mask64(addr
);
2131 pci_dma_read(&xhci
->pci_dev
, paddr
, &buf
, 32);
2133 memcpy(obuf
, buf
, sizeof(obuf
));
2135 if ((buf
[0] & 0xff) == 2) {
2136 obuf
[0] = 0x49932000 + 0x54dc200 * buf
[2] + 0x7429b578 * buf
[3];
2137 obuf
[0] |= (buf
[2] * buf
[3]) & 0xff;
2138 obuf
[1] = 0x0132bb37 + 0xe89 * buf
[2] + 0xf09 * buf
[3];
2139 obuf
[2] = 0x0066c2e9 + 0x2091 * buf
[2] + 0x19bd * buf
[3];
2140 obuf
[3] = 0xd5281342 + 0x2cc9691 * buf
[2] + 0x2367662 * buf
[3];
2141 obuf
[4] = 0x0123c75c + 0x1595 * buf
[2] + 0x19ec * buf
[3];
2142 obuf
[5] = 0x00f695de + 0x26fd * buf
[2] + 0x3e9 * buf
[3];
2143 obuf
[6] = obuf
[2] ^ obuf
[3] ^ 0x29472956;
2144 obuf
[7] = obuf
[2] ^ obuf
[3] ^ 0x65866593;
2147 pci_dma_write(&xhci
->pci_dev
, paddr
, &obuf
, 32);
2150 static void xhci_process_commands(XHCIState
*xhci
)
2154 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2156 unsigned int i
, slotid
= 0;
2158 DPRINTF("xhci_process_commands()\n");
2159 if (!xhci_running(xhci
)) {
2160 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2164 xhci
->crcr_low
|= CRCR_CRR
;
2166 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2169 case CR_ENABLE_SLOT
:
2170 for (i
= 0; i
< MAXSLOTS
; i
++) {
2171 if (!xhci
->slots
[i
].enabled
) {
2175 if (i
>= MAXSLOTS
) {
2176 fprintf(stderr
, "xhci: no device slots available\n");
2177 event
.ccode
= CC_NO_SLOTS_ERROR
;
2180 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2183 case CR_DISABLE_SLOT
:
2184 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2186 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2189 case CR_ADDRESS_DEVICE
:
2190 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2192 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2193 trb
.control
& TRB_CR_BSR
);
2196 case CR_CONFIGURE_ENDPOINT
:
2197 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2199 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2200 trb
.control
& TRB_CR_DC
);
2203 case CR_EVALUATE_CONTEXT
:
2204 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2206 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2209 case CR_STOP_ENDPOINT
:
2210 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2212 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2214 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2217 case CR_RESET_ENDPOINT
:
2218 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2220 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2222 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2225 case CR_SET_TR_DEQUEUE
:
2226 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2228 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2230 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
, epid
,
2234 case CR_RESET_DEVICE
:
2235 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2237 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2240 case CR_GET_PORT_BANDWIDTH
:
2241 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2243 case CR_VENDOR_VIA_CHALLENGE_RESPONSE
:
2244 xhci_via_challenge(xhci
, trb
.parameter
);
2246 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2247 event
.type
= 48; /* NEC reply */
2248 event
.length
= 0x3025;
2250 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2252 uint32_t chi
= trb
.parameter
>> 32;
2253 uint32_t clo
= trb
.parameter
;
2254 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2255 event
.length
= val
& 0xFFFF;
2256 event
.epid
= val
>> 16;
2258 event
.type
= 48; /* NEC reply */
2262 fprintf(stderr
, "xhci: unimplemented command %d\n", type
);
2263 event
.ccode
= CC_TRB_ERROR
;
2266 event
.slotid
= slotid
;
2267 xhci_event(xhci
, &event
);
2271 static void xhci_update_port(XHCIState
*xhci
, XHCIPort
*port
, int is_detach
)
2273 int nr
= port
->port
.index
+ 1;
2275 port
->portsc
= PORTSC_PP
;
2276 if (port
->port
.dev
&& port
->port
.dev
->attached
&& !is_detach
) {
2277 port
->portsc
|= PORTSC_CCS
;
2278 switch (port
->port
.dev
->speed
) {
2280 port
->portsc
|= PORTSC_SPEED_LOW
;
2282 case USB_SPEED_FULL
:
2283 port
->portsc
|= PORTSC_SPEED_FULL
;
2285 case USB_SPEED_HIGH
:
2286 port
->portsc
|= PORTSC_SPEED_HIGH
;
2291 if (xhci_running(xhci
)) {
2292 port
->portsc
|= PORTSC_CSC
;
2293 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
, nr
<< 24};
2294 xhci_event(xhci
, &ev
);
2295 DPRINTF("xhci: port change event for port %d\n", nr
);
2299 static void xhci_reset(void *opaque
)
2301 XHCIState
*xhci
= opaque
;
2304 DPRINTF("xhci: full reset\n");
2305 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2306 fprintf(stderr
, "xhci: reset while running!\n");
2310 xhci
->usbsts
= USBSTS_HCH
;
2313 xhci
->crcr_high
= 0;
2314 xhci
->dcbaap_low
= 0;
2315 xhci
->dcbaap_high
= 0;
2319 for (i
= 0; i
< MAXSLOTS
; i
++) {
2320 xhci_disable_slot(xhci
, i
+1);
2323 for (i
= 0; i
< MAXPORTS
; i
++) {
2324 xhci_update_port(xhci
, xhci
->ports
+ i
, 0);
2331 xhci
->erstba_low
= 0;
2332 xhci
->erstba_high
= 0;
2334 xhci
->erdp_high
= 0;
2336 xhci
->er_ep_idx
= 0;
2339 xhci
->ev_buffer_put
= 0;
2340 xhci
->ev_buffer_get
= 0;
2343 static uint32_t xhci_cap_read(XHCIState
*xhci
, uint32_t reg
)
2345 DPRINTF("xhci_cap_read(0x%x)\n", reg
);
2348 case 0x00: /* HCIVERSION, CAPLENGTH */
2349 return 0x01000000 | LEN_CAP
;
2350 case 0x04: /* HCSPARAMS 1 */
2351 return (MAXPORTS
<<24) | (MAXINTRS
<<8) | MAXSLOTS
;
2352 case 0x08: /* HCSPARAMS 2 */
2354 case 0x0c: /* HCSPARAMS 3 */
2356 case 0x10: /* HCCPARAMS */
2357 #if TARGET_PHYS_ADDR_BITS > 32
2362 case 0x14: /* DBOFF */
2363 return OFF_DOORBELL
;
2364 case 0x18: /* RTSOFF */
2367 /* extended capabilities */
2368 case 0x20: /* Supported Protocol:00 */
2370 return 0x02000402; /* USB 2.0 */
2372 return 0x02000002; /* USB 2.0 */
2374 case 0x24: /* Supported Protocol:04 */
2375 return 0x20425455; /* "USB " */
2376 case 0x28: /* Supported Protocol:08 */
2377 return 0x00000001 | (USB2_PORTS
<<8);
2378 case 0x2c: /* Supported Protocol:0c */
2379 return 0x00000000; /* reserved */
2381 case 0x30: /* Supported Protocol:00 */
2382 return 0x03000002; /* USB 3.0 */
2383 case 0x34: /* Supported Protocol:04 */
2384 return 0x20425455; /* "USB " */
2385 case 0x38: /* Supported Protocol:08 */
2386 return 0x00000000 | (USB2_PORTS
+1) | (USB3_PORTS
<<8);
2387 case 0x3c: /* Supported Protocol:0c */
2388 return 0x00000000; /* reserved */
2391 fprintf(stderr
, "xhci_cap_read: reg %d unimplemented\n", reg
);
2396 static uint32_t xhci_port_read(XHCIState
*xhci
, uint32_t reg
)
2398 uint32_t port
= reg
>> 4;
2399 if (port
>= MAXPORTS
) {
2400 fprintf(stderr
, "xhci_port_read: port %d out of bounds\n", port
);
2404 switch (reg
& 0xf) {
2405 case 0x00: /* PORTSC */
2406 return xhci
->ports
[port
].portsc
;
2407 case 0x04: /* PORTPMSC */
2408 case 0x08: /* PORTLI */
2410 case 0x0c: /* reserved */
2412 fprintf(stderr
, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2418 static void xhci_port_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2420 uint32_t port
= reg
>> 4;
2423 if (port
>= MAXPORTS
) {
2424 fprintf(stderr
, "xhci_port_read: port %d out of bounds\n", port
);
2428 switch (reg
& 0xf) {
2429 case 0x00: /* PORTSC */
2430 portsc
= xhci
->ports
[port
].portsc
;
2431 /* write-1-to-clear bits*/
2432 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2433 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2434 if (val
& PORTSC_LWS
) {
2435 /* overwrite PLS only when LWS=1 */
2436 portsc
&= ~(PORTSC_PLS_MASK
<< PORTSC_PLS_SHIFT
);
2437 portsc
|= val
& (PORTSC_PLS_MASK
<< PORTSC_PLS_SHIFT
);
2439 /* read/write bits */
2440 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2441 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2442 /* write-1-to-start bits */
2443 if (val
& PORTSC_PR
) {
2444 DPRINTF("xhci: port %d reset\n", port
);
2445 usb_device_reset(xhci
->ports
[port
].port
.dev
);
2446 portsc
|= PORTSC_PRC
| PORTSC_PED
;
2448 xhci
->ports
[port
].portsc
= portsc
;
2450 case 0x04: /* PORTPMSC */
2451 case 0x08: /* PORTLI */
2453 fprintf(stderr
, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2458 static uint32_t xhci_oper_read(XHCIState
*xhci
, uint32_t reg
)
2460 DPRINTF("xhci_oper_read(0x%x)\n", reg
);
2463 return xhci_port_read(xhci
, reg
- 0x400);
2467 case 0x00: /* USBCMD */
2468 return xhci
->usbcmd
;
2469 case 0x04: /* USBSTS */
2470 return xhci
->usbsts
;
2471 case 0x08: /* PAGESIZE */
2472 return 1; /* 4KiB */
2473 case 0x14: /* DNCTRL */
2474 return xhci
->dnctrl
;
2475 case 0x18: /* CRCR low */
2476 return xhci
->crcr_low
& ~0xe;
2477 case 0x1c: /* CRCR high */
2478 return xhci
->crcr_high
;
2479 case 0x30: /* DCBAAP low */
2480 return xhci
->dcbaap_low
;
2481 case 0x34: /* DCBAAP high */
2482 return xhci
->dcbaap_high
;
2483 case 0x38: /* CONFIG */
2484 return xhci
->config
;
2486 fprintf(stderr
, "xhci_oper_read: reg 0x%x unimplemented\n", reg
);
2491 static void xhci_oper_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2493 DPRINTF("xhci_oper_write(0x%x, 0x%08x)\n", reg
, val
);
2496 xhci_port_write(xhci
, reg
- 0x400, val
);
2501 case 0x00: /* USBCMD */
2502 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2504 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2507 xhci
->usbcmd
= val
& 0xc0f;
2508 if (val
& USBCMD_HCRST
) {
2511 xhci_irq_update(xhci
);
2514 case 0x04: /* USBSTS */
2515 /* these bits are write-1-to-clear */
2516 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2517 xhci_irq_update(xhci
);
2520 case 0x14: /* DNCTRL */
2521 xhci
->dnctrl
= val
& 0xffff;
2523 case 0x18: /* CRCR low */
2524 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2526 case 0x1c: /* CRCR high */
2527 xhci
->crcr_high
= val
;
2528 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2529 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2530 xhci
->crcr_low
&= ~CRCR_CRR
;
2531 xhci_event(xhci
, &event
);
2532 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2534 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2535 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2537 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2539 case 0x30: /* DCBAAP low */
2540 xhci
->dcbaap_low
= val
& 0xffffffc0;
2542 case 0x34: /* DCBAAP high */
2543 xhci
->dcbaap_high
= val
;
2545 case 0x38: /* CONFIG */
2546 xhci
->config
= val
& 0xff;
2549 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n", reg
);
2553 static uint32_t xhci_runtime_read(XHCIState
*xhci
, uint32_t reg
)
2555 DPRINTF("xhci_runtime_read(0x%x)\n", reg
);
2558 case 0x00: /* MFINDEX */
2559 fprintf(stderr
, "xhci_runtime_read: MFINDEX not yet implemented\n");
2560 return xhci
->mfindex
;
2561 case 0x20: /* IMAN */
2563 case 0x24: /* IMOD */
2565 case 0x28: /* ERSTSZ */
2566 return xhci
->erstsz
;
2567 case 0x30: /* ERSTBA low */
2568 return xhci
->erstba_low
;
2569 case 0x34: /* ERSTBA high */
2570 return xhci
->erstba_high
;
2571 case 0x38: /* ERDP low */
2572 return xhci
->erdp_low
;
2573 case 0x3c: /* ERDP high */
2574 return xhci
->erdp_high
;
2576 fprintf(stderr
, "xhci_runtime_read: reg 0x%x unimplemented\n", reg
);
2581 static void xhci_runtime_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2583 DPRINTF("xhci_runtime_write(0x%x, 0x%08x)\n", reg
, val
);
2586 case 0x20: /* IMAN */
2587 if (val
& IMAN_IP
) {
2588 xhci
->iman
&= ~IMAN_IP
;
2590 xhci
->iman
&= ~IMAN_IE
;
2591 xhci
->iman
|= val
& IMAN_IE
;
2592 xhci_irq_update(xhci
);
2594 case 0x24: /* IMOD */
2597 case 0x28: /* ERSTSZ */
2598 xhci
->erstsz
= val
& 0xffff;
2600 case 0x30: /* ERSTBA low */
2601 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2602 xhci->erstba_low = val & 0xffffffc0; */
2603 xhci
->erstba_low
= val
& 0xfffffff0;
2605 case 0x34: /* ERSTBA high */
2606 xhci
->erstba_high
= val
;
2607 xhci_er_reset(xhci
);
2609 case 0x38: /* ERDP low */
2610 if (val
& ERDP_EHB
) {
2611 xhci
->erdp_low
&= ~ERDP_EHB
;
2613 xhci
->erdp_low
= (val
& ~ERDP_EHB
) | (xhci
->erdp_low
& ERDP_EHB
);
2615 case 0x3c: /* ERDP high */
2616 xhci
->erdp_high
= val
;
2617 xhci_events_update(xhci
);
2620 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n", reg
);
2624 static uint32_t xhci_doorbell_read(XHCIState
*xhci
, uint32_t reg
)
2626 DPRINTF("xhci_doorbell_read(0x%x)\n", reg
);
2627 /* doorbells always read as 0 */
2631 static void xhci_doorbell_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2633 DPRINTF("xhci_doorbell_write(0x%x, 0x%08x)\n", reg
, val
);
2635 if (!xhci_running(xhci
)) {
2636 fprintf(stderr
, "xhci: wrote doorbell while xHC stopped or paused\n");
2644 xhci_process_commands(xhci
);
2646 fprintf(stderr
, "xhci: bad doorbell 0 write: 0x%x\n", val
);
2649 if (reg
> MAXSLOTS
) {
2650 fprintf(stderr
, "xhci: bad doorbell %d\n", reg
);
2651 } else if (val
> 31) {
2652 fprintf(stderr
, "xhci: bad doorbell %d write: 0x%x\n", reg
, val
);
2654 xhci_kick_ep(xhci
, reg
, val
);
2659 static uint64_t xhci_mem_read(void *ptr
, target_phys_addr_t addr
,
2662 XHCIState
*xhci
= ptr
;
2664 /* Only aligned reads are allowed on xHCI */
2666 fprintf(stderr
, "xhci_mem_read: Mis-aligned read\n");
2670 if (addr
< LEN_CAP
) {
2671 return xhci_cap_read(xhci
, addr
);
2672 } else if (addr
>= OFF_OPER
&& addr
< (OFF_OPER
+ LEN_OPER
)) {
2673 return xhci_oper_read(xhci
, addr
- OFF_OPER
);
2674 } else if (addr
>= OFF_RUNTIME
&& addr
< (OFF_RUNTIME
+ LEN_RUNTIME
)) {
2675 return xhci_runtime_read(xhci
, addr
- OFF_RUNTIME
);
2676 } else if (addr
>= OFF_DOORBELL
&& addr
< (OFF_DOORBELL
+ LEN_DOORBELL
)) {
2677 return xhci_doorbell_read(xhci
, addr
- OFF_DOORBELL
);
2679 fprintf(stderr
, "xhci_mem_read: Bad offset %x\n", (int)addr
);
2684 static void xhci_mem_write(void *ptr
, target_phys_addr_t addr
,
2685 uint64_t val
, unsigned size
)
2687 XHCIState
*xhci
= ptr
;
2689 /* Only aligned writes are allowed on xHCI */
2691 fprintf(stderr
, "xhci_mem_write: Mis-aligned write\n");
2695 if (addr
>= OFF_OPER
&& addr
< (OFF_OPER
+ LEN_OPER
)) {
2696 xhci_oper_write(xhci
, addr
- OFF_OPER
, val
);
2697 } else if (addr
>= OFF_RUNTIME
&& addr
< (OFF_RUNTIME
+ LEN_RUNTIME
)) {
2698 xhci_runtime_write(xhci
, addr
- OFF_RUNTIME
, val
);
2699 } else if (addr
>= OFF_DOORBELL
&& addr
< (OFF_DOORBELL
+ LEN_DOORBELL
)) {
2700 xhci_doorbell_write(xhci
, addr
- OFF_DOORBELL
, val
);
2702 fprintf(stderr
, "xhci_mem_write: Bad offset %x\n", (int)addr
);
2706 static const MemoryRegionOps xhci_mem_ops
= {
2707 .read
= xhci_mem_read
,
2708 .write
= xhci_mem_write
,
2709 .valid
.min_access_size
= 4,
2710 .valid
.max_access_size
= 4,
2711 .endianness
= DEVICE_LITTLE_ENDIAN
,
2714 static void xhci_attach(USBPort
*usbport
)
2716 XHCIState
*xhci
= usbport
->opaque
;
2717 XHCIPort
*port
= &xhci
->ports
[usbport
->index
];
2719 xhci_update_port(xhci
, port
, 0);
2722 static void xhci_detach(USBPort
*usbport
)
2724 XHCIState
*xhci
= usbport
->opaque
;
2725 XHCIPort
*port
= &xhci
->ports
[usbport
->index
];
2727 xhci_update_port(xhci
, port
, 1);
2730 static void xhci_wakeup(USBPort
*usbport
)
2732 XHCIState
*xhci
= usbport
->opaque
;
2733 XHCIPort
*port
= &xhci
->ports
[usbport
->index
];
2734 int nr
= port
->port
.index
+ 1;
2735 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
, nr
<< 24};
2738 pls
= (port
->portsc
>> PORTSC_PLS_SHIFT
) & PORTSC_PLS_MASK
;
2742 port
->portsc
|= 0xf << PORTSC_PLS_SHIFT
;
2743 if (port
->portsc
& PORTSC_PLC
) {
2746 port
->portsc
|= PORTSC_PLC
;
2747 xhci_event(xhci
, &ev
);
2750 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
2752 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
2754 xhci_complete_packet(xfer
, packet
->result
);
2755 xhci_kick_ep(xfer
->xhci
, xfer
->slotid
, xfer
->epid
);
2758 static void xhci_child_detach(USBPort
*port
, USBDevice
*child
)
2763 static USBPortOps xhci_port_ops
= {
2764 .attach
= xhci_attach
,
2765 .detach
= xhci_detach
,
2766 .wakeup
= xhci_wakeup
,
2767 .complete
= xhci_complete
,
2768 .child_detach
= xhci_child_detach
,
2771 static int xhci_find_slotid(XHCIState
*xhci
, USBDevice
*dev
)
2776 for (slotid
= 1; slotid
<= MAXSLOTS
; slotid
++) {
2777 slot
= &xhci
->slots
[slotid
-1];
2778 if (slot
->devaddr
== dev
->addr
) {
2785 static int xhci_find_epid(USBEndpoint
*ep
)
2790 if (ep
->pid
== USB_TOKEN_IN
) {
2791 return ep
->nr
* 2 + 1;
2797 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
)
2799 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
2802 DPRINTF("%s\n", __func__
);
2803 slotid
= xhci_find_slotid(xhci
, ep
->dev
);
2804 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
2805 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
2808 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
));
2811 static USBBusOps xhci_bus_ops
= {
2812 .wakeup_endpoint
= xhci_wakeup_endpoint
,
2815 static void usb_xhci_init(XHCIState
*xhci
, DeviceState
*dev
)
2819 xhci
->usbsts
= USBSTS_HCH
;
2821 usb_bus_new(&xhci
->bus
, &xhci_bus_ops
, &xhci
->pci_dev
.qdev
);
2823 for (i
= 0; i
< MAXPORTS
; i
++) {
2824 memset(&xhci
->ports
[i
], 0, sizeof(xhci
->ports
[i
]));
2825 usb_register_port(&xhci
->bus
, &xhci
->ports
[i
].port
, xhci
, i
,
2827 USB_SPEED_MASK_LOW
|
2828 USB_SPEED_MASK_FULL
|
2829 USB_SPEED_MASK_HIGH
);
2831 for (i
= 0; i
< MAXSLOTS
; i
++) {
2832 xhci
->slots
[i
].enabled
= 0;
2835 qemu_register_reset(xhci_reset
, xhci
);
2838 static int usb_xhci_initfn(struct PCIDevice
*dev
)
2842 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
, dev
);
2844 xhci
->pci_dev
.config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
2845 xhci
->pci_dev
.config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
2846 xhci
->pci_dev
.config
[PCI_CACHE_LINE_SIZE
] = 0x10;
2847 xhci
->pci_dev
.config
[0x60] = 0x30; /* release number */
2849 usb_xhci_init(xhci
, &dev
->qdev
);
2851 xhci
->irq
= xhci
->pci_dev
.irq
[0];
2853 memory_region_init_io(&xhci
->mem
, &xhci_mem_ops
, xhci
,
2855 pci_register_bar(&xhci
->pci_dev
, 0,
2856 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
2859 ret
= pcie_cap_init(&xhci
->pci_dev
, 0xa0, PCI_EXP_TYPE_ENDPOINT
, 0);
2863 ret
= msi_init(&xhci
->pci_dev
, 0x70, 1, true, false);
2870 static void xhci_write_config(PCIDevice
*dev
, uint32_t addr
, uint32_t val
,
2873 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
, dev
);
2875 pci_default_write_config(dev
, addr
, val
, len
);
2877 msi_write_config(dev
, addr
, val
, len
);
2881 static const VMStateDescription vmstate_xhci
= {
2886 static Property xhci_properties
[] = {
2887 DEFINE_PROP_UINT32("msi", XHCIState
, msi
, 0),
2888 DEFINE_PROP_END_OF_LIST(),
2891 static void xhci_class_init(ObjectClass
*klass
, void *data
)
2893 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2894 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2896 dc
->vmsd
= &vmstate_xhci
;
2897 dc
->props
= xhci_properties
;
2898 k
->init
= usb_xhci_initfn
;
2899 k
->vendor_id
= PCI_VENDOR_ID_NEC
;
2900 k
->device_id
= PCI_DEVICE_ID_NEC_UPD720200
;
2901 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2904 k
->config_write
= xhci_write_config
;
2907 static TypeInfo xhci_info
= {
2908 .name
= "nec-usb-xhci",
2909 .parent
= TYPE_PCI_DEVICE
,
2910 .instance_size
= sizeof(XHCIState
),
2911 .class_init
= xhci_class_init
,
2914 static void xhci_register_types(void)
2916 type_register_static(&xhci_info
);
2919 type_init(xhci_register_types
)