hw/pxa2xx_gpio.c

   1 /*
   2  * Intel XScale PXA255/270 GPIO controller emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw.h"
  11 #include "sysbus.h"
  12 #include "pxa.h"
  13
  14 #define PXA2XX_GPIO_BANKS       4
  15
  16 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
  17 struct PXA2xxGPIOInfo {
  18     SysBusDevice busdev;
  19     MemoryRegion iomem;
  20     qemu_irq irq0, irq1, irqX;
  21     int lines;
  22     int ncpu;
  23     CPUARMState *cpu_env;
  24
  25     /* XXX: GNU C vectors are more suitable */
  26     uint32_t ilevel[PXA2XX_GPIO_BANKS];
  27     uint32_t olevel[PXA2XX_GPIO_BANKS];
  28     uint32_t dir[PXA2XX_GPIO_BANKS];
  29     uint32_t rising[PXA2XX_GPIO_BANKS];
  30     uint32_t falling[PXA2XX_GPIO_BANKS];
  31     uint32_t status[PXA2XX_GPIO_BANKS];
  32     uint32_t gpsr[PXA2XX_GPIO_BANKS];
  33     uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
  34
  35     uint32_t prev_level[PXA2XX_GPIO_BANKS];
  36     qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
  37     qemu_irq read_notify;
  38 };
  39
  40 static struct {
  41     enum {
  42         GPIO_NONE,
  43         GPLR,
  44         GPSR,
  45         GPCR,
  46         GPDR,
  47         GRER,
  48         GFER,
  49         GEDR,
  50         GAFR_L,
  51         GAFR_U,
  52     } reg;
  53     int bank;
  54 } pxa2xx_gpio_regs[0x200] = {
  55     [0 ... 0x1ff] = { GPIO_NONE, 0 },
  56 #define PXA2XX_REG(reg, a0, a1, a2, a3) \
  57     [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
  58
  59     PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
  60     PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
  61     PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
  62     PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
  63     PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
  64     PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
  65     PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
  66     PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
  67     PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
  68 };
  69
  70 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
  71 {
  72     if (s->status[0] & (1 << 0))
  73         qemu_irq_raise(s->irq0);
  74     else
  75         qemu_irq_lower(s->irq0);
  76
  77     if (s->status[0] & (1 << 1))
  78         qemu_irq_raise(s->irq1);
  79     else
  80         qemu_irq_lower(s->irq1);
  81
  82     if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
  83         qemu_irq_raise(s->irqX);
  84     else
  85         qemu_irq_lower(s->irqX);
  86 }
  87
  88 /* Bitmap of pins used as standby and sleep wake-up sources.  */
  89 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
  90     0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
  91 };
  92
  93 static void pxa2xx_gpio_set(void *opaque, int line, int level)
  94 {
  95     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
  96     int bank;
  97     uint32_t mask;
  98
  99     if (line >= s->lines) {
 100         printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
 101         return;
 102     }
 103
 104     bank = line >> 5;
 105     mask = 1 << (line & 31);
 106
 107     if (level) {
 108         s->status[bank] |= s->rising[bank] & mask &
 109                 ~s->ilevel[bank] & ~s->dir[bank];
 110         s->ilevel[bank] |= mask;
 111     } else {
 112         s->status[bank] |= s->falling[bank] & mask &
 113                 s->ilevel[bank] & ~s->dir[bank];
 114         s->ilevel[bank] &= ~mask;
 115     }
 116
 117     if (s->status[bank] & mask)
 118         pxa2xx_gpio_irq_update(s);
 119
 120     /* Wake-up GPIOs */
 121     if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
 122         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
 123 }
 124
 125 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
 126     uint32_t level, diff;
 127     int i, bit, line;
 128     for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
 129         level = s->olevel[i] & s->dir[i];
 130
 131         for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
 132             bit = ffs(diff) - 1;
 133             line = bit + 32 * i;
 134             qemu_set_irq(s->handler[line], (level >> bit) & 1);
 135         }
 136
 137         s->prev_level[i] = level;
 138     }
 139 }
 140
 141 static uint64_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset,
 142                                  unsigned size)
 143 {
 144     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
 145     uint32_t ret;
 146     int bank;
 147     if (offset >= 0x200)
 148         return 0;
 149
 150     bank = pxa2xx_gpio_regs[offset].bank;
 151     switch (pxa2xx_gpio_regs[offset].reg) {
 152     case GPDR:          /* GPIO Pin-Direction registers */
 153         return s->dir[bank];
 154
 155     case GPSR:          /* GPIO Pin-Output Set registers */
 156         printf("%s: Read from a write-only register " REG_FMT "\n",
 157                         __FUNCTION__, offset);
 158         return s->gpsr[bank];   /* Return last written value.  */
 159
 160     case GPCR:          /* GPIO Pin-Output Clear registers */
 161         printf("%s: Read from a write-only register " REG_FMT "\n",
 162                         __FUNCTION__, offset);
 163         return 31337;           /* Specified as unpredictable in the docs.  */
 164
 165     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 166         return s->rising[bank];
 167
 168     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 169         return s->falling[bank];
 170
 171     case GAFR_L:        /* GPIO Alternate Function registers */
 172         return s->gafr[bank * 2];
 173
 174     case GAFR_U:        /* GPIO Alternate Function registers */
 175         return s->gafr[bank * 2 + 1];
 176
 177     case GPLR:          /* GPIO Pin-Level registers */
 178         ret = (s->olevel[bank] & s->dir[bank]) |
 179                 (s->ilevel[bank] & ~s->dir[bank]);
 180         qemu_irq_raise(s->read_notify);
 181         return ret;
 182
 183     case GEDR:          /* GPIO Edge Detect Status registers */
 184         return s->status[bank];
 185
 186     default:
 187         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 188     }
 189
 190     return 0;
 191 }
 192
 193 static void pxa2xx_gpio_write(void *opaque, target_phys_addr_t offset,
 194                               uint64_t value, unsigned size)
 195 {
 196     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
 197     int bank;
 198     if (offset >= 0x200)
 199         return;
 200
 201     bank = pxa2xx_gpio_regs[offset].bank;
 202     switch (pxa2xx_gpio_regs[offset].reg) {
 203     case GPDR:          /* GPIO Pin-Direction registers */
 204         s->dir[bank] = value;
 205         pxa2xx_gpio_handler_update(s);
 206         break;
 207
 208     case GPSR:          /* GPIO Pin-Output Set registers */
 209         s->olevel[bank] |= value;
 210         pxa2xx_gpio_handler_update(s);
 211         s->gpsr[bank] = value;
 212         break;
 213
 214     case GPCR:          /* GPIO Pin-Output Clear registers */
 215         s->olevel[bank] &= ~value;
 216         pxa2xx_gpio_handler_update(s);
 217         break;
 218
 219     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 220         s->rising[bank] = value;
 221         break;
 222
 223     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 224         s->falling[bank] = value;
 225         break;
 226
 227     case GAFR_L:        /* GPIO Alternate Function registers */
 228         s->gafr[bank * 2] = value;
 229         break;
 230
 231     case GAFR_U:        /* GPIO Alternate Function registers */
 232         s->gafr[bank * 2 + 1] = value;
 233         break;
 234
 235     case GEDR:          /* GPIO Edge Detect Status registers */
 236         s->status[bank] &= ~value;
 237         pxa2xx_gpio_irq_update(s);
 238         break;
 239
 240     default:
 241         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 242     }
 243 }
 244
 245 static const MemoryRegionOps pxa_gpio_ops = {
 246     .read = pxa2xx_gpio_read,
 247     .write = pxa2xx_gpio_write,
 248     .endianness = DEVICE_NATIVE_ENDIAN,
 249 };
 250
 251 DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
 252                 CPUARMState *env, DeviceState *pic, int lines)
 253 {
 254     DeviceState *dev;
 255
 256     dev = qdev_create(NULL, "pxa2xx-gpio");
 257     qdev_prop_set_int32(dev, "lines", lines);
 258     qdev_prop_set_int32(dev, "ncpu", env->cpu_index);
 259     qdev_init_nofail(dev);
 260
 261     sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
 262     sysbus_connect_irq(sysbus_from_qdev(dev), 0,
 263                     qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
 264     sysbus_connect_irq(sysbus_from_qdev(dev), 1,
 265                     qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
 266     sysbus_connect_irq(sysbus_from_qdev(dev), 2,
 267                     qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
 268
 269     return dev;
 270 }
 271
 272 static int pxa2xx_gpio_initfn(SysBusDevice *dev)
 273 {
 274     PXA2xxGPIOInfo *s;
 275
 276     s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
 277
 278     s->cpu_env = qemu_get_cpu(s->ncpu);
 279
 280     qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
 281     qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
 282
 283     memory_region_init_io(&s->iomem, &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
 284     sysbus_init_mmio(dev, &s->iomem);
 285     sysbus_init_irq(dev, &s->irq0);
 286     sysbus_init_irq(dev, &s->irq1);
 287     sysbus_init_irq(dev, &s->irqX);
 288
 289     return 0;
 290 }
 291
 292 /*
 293  * Registers a callback to notify on GPLR reads.  This normally
 294  * shouldn't be needed but it is used for the hack on Spitz machines.
 295  */
 296 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
 297 {
 298     PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, sysbus_from_qdev(dev));
 299     s->read_notify = handler;
 300 }
 301
 302 static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
 303     .name = "pxa2xx-gpio",
 304     .version_id = 1,
 305     .minimum_version_id = 1,
 306     .minimum_version_id_old = 1,
 307     .fields = (VMStateField []) {
 308         VMSTATE_INT32(lines, PXA2xxGPIOInfo),
 309         VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 310         VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 311         VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 312         VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 313         VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 314         VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 315         VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
 316         VMSTATE_END_OF_LIST(),
 317     },
 318 };
 319
 320 static Property pxa2xx_gpio_properties[] = {
 321     DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
 322     DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
 323     DEFINE_PROP_END_OF_LIST(),
 324 };
 325
 326 static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
 327 {
 328     DeviceClass *dc = DEVICE_CLASS(klass);
 329     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 330
 331     k->init = pxa2xx_gpio_initfn;
 332     dc->desc = "PXA2xx GPIO controller";
 333     dc->props = pxa2xx_gpio_properties;
 334 }
 335
 336 static TypeInfo pxa2xx_gpio_info = {
 337     .name          = "pxa2xx-gpio",
 338     .parent        = TYPE_SYS_BUS_DEVICE,
 339     .instance_size = sizeof(PXA2xxGPIOInfo),
 340     .class_init    = pxa2xx_gpio_class_init,
 341 };
 342
 343 static void pxa2xx_gpio_register_types(void)
 344 {
 345     type_register_static(&pxa2xx_gpio_info);
 346 }
 347
 348 type_init(pxa2xx_gpio_register_types)