2 * Model of Petalogix linux reference design targeting Xilinx Spartan ml605
5 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
6 * Copyright (c) 2011 PetaLogix
7 * Copyright (c) 2009 Edgar E. Iglesias.
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
38 #include "exec-memory.h"
40 #include "microblaze_boot.h"
41 #include "microblaze_pic_cpu.h"
42 #include "xilinx_axidma.h"
44 #define LMB_BRAM_SIZE (128 * 1024)
45 #define FLASH_SIZE (32 * 1024 * 1024)
47 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
49 #define MEMORY_BASEADDR 0x50000000
50 #define FLASH_BASEADDR 0x86000000
51 #define INTC_BASEADDR 0x81800000
52 #define TIMER_BASEADDR 0x83c00000
53 #define UART16550_BASEADDR 0x83e00000
54 #define AXIENET_BASEADDR 0x82780000
55 #define AXIDMA_BASEADDR 0x84600000
57 static void machine_cpu_reset(CPUMBState
*env
)
59 env
->pvr
.regs
[10] = 0x0e000000; /* virtex 6 */
60 /* setup pvr to match kernel setting */
61 env
->pvr
.regs
[5] |= PVR5_DCACHE_WRITEBACK_MASK
;
62 env
->pvr
.regs
[0] |= PVR0_USE_FPU_MASK
| PVR0_ENDI
;
63 env
->pvr
.regs
[0] = (env
->pvr
.regs
[0] & ~PVR0_VERSION_MASK
) | (0x14 << 8);
64 env
->pvr
.regs
[2] ^= PVR2_USE_FPU2_MASK
;
65 env
->pvr
.regs
[4] = 0xc56b8000;
66 env
->pvr
.regs
[5] = 0xc56be000;
70 petalogix_ml605_init(ram_addr_t ram_size
,
71 const char *boot_device
,
72 const char *kernel_filename
,
73 const char *kernel_cmdline
,
74 const char *initrd_filename
, const char *cpu_model
)
76 MemoryRegion
*address_space_mem
= get_system_memory();
81 target_phys_addr_t ddr_base
= MEMORY_BASEADDR
;
82 MemoryRegion
*phys_lmb_bram
= g_new(MemoryRegion
, 1);
83 MemoryRegion
*phys_ram
= g_new(MemoryRegion
, 1);
84 qemu_irq irq
[32], *cpu_irq
;
87 if (cpu_model
== NULL
) {
88 cpu_model
= "microblaze";
90 env
= cpu_init(cpu_model
);
92 /* Attach emulated BRAM through the LMB. */
93 memory_region_init_ram(phys_lmb_bram
, "petalogix_ml605.lmb_bram",
95 vmstate_register_ram_global(phys_lmb_bram
);
96 memory_region_add_subregion(address_space_mem
, 0x00000000, phys_lmb_bram
);
98 memory_region_init_ram(phys_ram
, "petalogix_ml605.ram", ram_size
);
99 vmstate_register_ram_global(phys_ram
);
100 memory_region_add_subregion(address_space_mem
, ddr_base
, phys_ram
);
102 dinfo
= drive_get(IF_PFLASH
, 0, 0);
103 /* 5th parameter 2 means bank-width
104 * 10th paremeter 0 means little-endian */
105 pflash_cfi01_register(FLASH_BASEADDR
,
106 NULL
, "petalogix_ml605.flash", FLASH_SIZE
,
107 dinfo
? dinfo
->bdrv
: NULL
, (64 * 1024),
109 2, 0x89, 0x18, 0x0000, 0x0, 0);
112 cpu_irq
= microblaze_pic_init_cpu(env
);
113 dev
= xilinx_intc_create(INTC_BASEADDR
, cpu_irq
[0], 4);
114 for (i
= 0; i
< 32; i
++) {
115 irq
[i
] = qdev_get_gpio_in(dev
, i
);
118 serial_mm_init(address_space_mem
, UART16550_BASEADDR
+ 0x1000, 2,
119 irq
[5], 115200, serial_hds
[0], DEVICE_LITTLE_ENDIAN
);
121 /* 2 timers at irq 2 @ 100 Mhz. */
122 xilinx_timer_create(TIMER_BASEADDR
, irq
[2], 2, 100 * 1000000);
124 /* axi ethernet and dma initialization. TODO: Dynamically connect them. */
126 static struct XilinxDMAConnection dmach
;
128 xilinx_axiethernet_create(&dmach
, &nd_table
[0], 0x82780000,
129 irq
[3], 0x1000, 0x1000);
130 xilinx_axiethernetdma_create(&dmach
, 0x84600000,
131 irq
[1], irq
[0], 100 * 1000000);
134 microblaze_load_kernel(env
, ddr_base
, ram_size
, BINARY_DEVICE_TREE_FILE
,
139 static QEMUMachine petalogix_ml605_machine
= {
140 .name
= "petalogix-ml605",
141 .desc
= "PetaLogix linux refdesign for xilinx ml605 little endian",
142 .init
= petalogix_ml605_init
,
146 static void petalogix_ml605_machine_init(void)
148 qemu_register_machine(&petalogix_ml605_machine
);
151 machine_init(petalogix_ml605_machine_init
);