2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "vmware_vga.h"
33 #include "hpet_emul.h"
37 #include "multiboot.h"
38 #include "mc146818rtc.h"
47 #include "ui/qemu-spice.h"
49 #include "exec-memory.h"
50 #include "arch_init.h"
52 /* output Bochs bios info messages */
55 /* debug PC/ISA interrupts */
59 #define DPRINTF(fmt, ...) \
60 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
62 #define DPRINTF(fmt, ...)
65 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
66 #define ACPI_DATA_SIZE 0x10000
67 #define BIOS_CFG_IOPORT 0x510
68 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
69 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
70 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
71 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
72 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
74 #define MSI_ADDR_BASE 0xfee00000
76 #define E820_NR_ENTRIES 16
82 } QEMU_PACKED
__attribute((__aligned__(4)));
86 struct e820_entry entry
[E820_NR_ENTRIES
];
87 } QEMU_PACKED
__attribute((__aligned__(4)));
89 static struct e820_table e820_table
;
90 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
92 void gsi_handler(void *opaque
, int n
, int level
)
96 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
97 if (n
< ISA_NUM_IRQS
) {
98 qemu_set_irq(s
->i8259_irq
[n
], level
);
100 qemu_set_irq(s
->ioapic_irq
[n
], level
);
103 static void ioport80_write(void *opaque
, uint32_t addr
, uint32_t data
)
107 /* MSDOS compatibility mode FPU exception support */
108 static qemu_irq ferr_irq
;
110 void pc_register_ferr_irq(qemu_irq irq
)
115 /* XXX: add IGNNE support */
116 void cpu_set_ferr(CPUX86State
*s
)
118 qemu_irq_raise(ferr_irq
);
121 static void ioportF0_write(void *opaque
, uint32_t addr
, uint32_t data
)
123 qemu_irq_lower(ferr_irq
);
127 uint64_t cpu_get_tsc(CPUX86State
*env
)
129 return cpu_get_ticks();
134 static cpu_set_smm_t smm_set
;
135 static void *smm_arg
;
137 void cpu_smm_register(cpu_set_smm_t callback
, void *arg
)
139 assert(smm_set
== NULL
);
140 assert(smm_arg
== NULL
);
145 void cpu_smm_update(CPUX86State
*env
)
147 if (smm_set
&& smm_arg
&& env
== first_cpu
)
148 smm_set(!!(env
->hflags
& HF_SMM_MASK
), smm_arg
);
153 int cpu_get_pic_interrupt(CPUX86State
*env
)
157 intno
= apic_get_interrupt(env
->apic_state
);
161 /* read the irq from the PIC */
162 if (!apic_accept_pic_intr(env
->apic_state
)) {
166 intno
= pic_read_irq(isa_pic
);
170 static void pic_irq_request(void *opaque
, int irq
, int level
)
172 CPUX86State
*env
= first_cpu
;
174 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
175 if (env
->apic_state
) {
177 if (apic_accept_pic_intr(env
->apic_state
)) {
178 apic_deliver_pic_intr(env
->apic_state
, level
);
184 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
186 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
190 /* PC cmos mappings */
192 #define REG_EQUIPMENT_BYTE 0x14
194 static int cmos_get_fd_drive_type(FDriveType fd0
)
200 /* 1.44 Mb 3"5 drive */
204 /* 2.88 Mb 3"5 drive */
208 /* 1.2 Mb 5"5 drive */
211 case FDRIVE_DRV_NONE
:
219 static void cmos_init_hd(int type_ofs
, int info_ofs
, BlockDriverState
*hd
,
222 int cylinders
, heads
, sectors
;
223 bdrv_get_geometry_hint(hd
, &cylinders
, &heads
, §ors
);
224 rtc_set_memory(s
, type_ofs
, 47);
225 rtc_set_memory(s
, info_ofs
, cylinders
);
226 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
227 rtc_set_memory(s
, info_ofs
+ 2, heads
);
228 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
229 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
230 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
231 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
232 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
233 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
236 /* convert boot_device letter to something recognizable by the bios */
237 static int boot_device2nibble(char boot_device
)
239 switch(boot_device
) {
242 return 0x01; /* floppy boot */
244 return 0x02; /* hard drive boot */
246 return 0x03; /* CD-ROM boot */
248 return 0x04; /* Network boot */
253 static int set_boot_dev(ISADevice
*s
, const char *boot_device
, int fd_bootchk
)
255 #define PC_MAX_BOOT_DEVICES 3
256 int nbds
, bds
[3] = { 0, };
259 nbds
= strlen(boot_device
);
260 if (nbds
> PC_MAX_BOOT_DEVICES
) {
261 error_report("Too many boot devices for PC");
264 for (i
= 0; i
< nbds
; i
++) {
265 bds
[i
] = boot_device2nibble(boot_device
[i
]);
267 error_report("Invalid boot device for PC: '%c'",
272 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
273 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
277 static int pc_boot_set(void *opaque
, const char *boot_device
)
279 return set_boot_dev(opaque
, boot_device
, 0);
282 typedef struct pc_cmos_init_late_arg
{
283 ISADevice
*rtc_state
;
284 BusState
*idebus0
, *idebus1
;
285 } pc_cmos_init_late_arg
;
287 static void pc_cmos_init_late(void *opaque
)
289 pc_cmos_init_late_arg
*arg
= opaque
;
290 ISADevice
*s
= arg
->rtc_state
;
292 BlockDriverState
*hd_table
[4];
295 ide_get_bs(hd_table
, arg
->idebus0
);
296 ide_get_bs(hd_table
+ 2, arg
->idebus1
);
298 rtc_set_memory(s
, 0x12, (hd_table
[0] ? 0xf0 : 0) | (hd_table
[1] ? 0x0f : 0));
300 cmos_init_hd(0x19, 0x1b, hd_table
[0], s
);
302 cmos_init_hd(0x1a, 0x24, hd_table
[1], s
);
305 for (i
= 0; i
< 4; i
++) {
307 int cylinders
, heads
, sectors
, translation
;
308 /* NOTE: bdrv_get_geometry_hint() returns the physical
309 geometry. It is always such that: 1 <= sects <= 63, 1
310 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
311 geometry can be different if a translation is done. */
312 translation
= bdrv_get_translation_hint(hd_table
[i
]);
313 if (translation
== BIOS_ATA_TRANSLATION_AUTO
) {
314 bdrv_get_geometry_hint(hd_table
[i
], &cylinders
, &heads
, §ors
);
315 if (cylinders
<= 1024 && heads
<= 16 && sectors
<= 63) {
316 /* No translation. */
319 /* LBA translation. */
325 val
|= translation
<< (i
* 2);
328 rtc_set_memory(s
, 0x39, val
);
330 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
333 void pc_cmos_init(ram_addr_t ram_size
, ram_addr_t above_4g_mem_size
,
334 const char *boot_device
,
335 ISADevice
*floppy
, BusState
*idebus0
, BusState
*idebus1
,
338 int val
, nb
, nb_heads
, max_track
, last_sect
, i
;
339 FDriveType fd_type
[2] = { FDRIVE_DRV_NONE
, FDRIVE_DRV_NONE
};
341 BlockDriverState
*fd
[MAX_FD
];
342 static pc_cmos_init_late_arg arg
;
344 /* various important CMOS locations needed by PC/Bochs bios */
347 val
= 640; /* base memory in K */
348 rtc_set_memory(s
, 0x15, val
);
349 rtc_set_memory(s
, 0x16, val
>> 8);
351 val
= (ram_size
/ 1024) - 1024;
354 rtc_set_memory(s
, 0x17, val
);
355 rtc_set_memory(s
, 0x18, val
>> 8);
356 rtc_set_memory(s
, 0x30, val
);
357 rtc_set_memory(s
, 0x31, val
>> 8);
359 if (above_4g_mem_size
) {
360 rtc_set_memory(s
, 0x5b, (unsigned int)above_4g_mem_size
>> 16);
361 rtc_set_memory(s
, 0x5c, (unsigned int)above_4g_mem_size
>> 24);
362 rtc_set_memory(s
, 0x5d, (uint64_t)above_4g_mem_size
>> 32);
365 if (ram_size
> (16 * 1024 * 1024))
366 val
= (ram_size
/ 65536) - ((16 * 1024 * 1024) / 65536);
371 rtc_set_memory(s
, 0x34, val
);
372 rtc_set_memory(s
, 0x35, val
>> 8);
374 /* set the number of CPU */
375 rtc_set_memory(s
, 0x5f, smp_cpus
- 1);
377 /* set boot devices, and disable floppy signature check if requested */
378 if (set_boot_dev(s
, boot_device
, fd_bootchk
)) {
384 fdc_get_bs(fd
, floppy
);
385 for (i
= 0; i
< 2; i
++) {
387 bdrv_get_floppy_geometry_hint(fd
[i
], &nb_heads
, &max_track
,
388 &last_sect
, FDRIVE_DRV_NONE
,
393 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
394 cmos_get_fd_drive_type(fd_type
[1]);
395 rtc_set_memory(s
, 0x10, val
);
399 if (fd_type
[0] < FDRIVE_DRV_NONE
) {
402 if (fd_type
[1] < FDRIVE_DRV_NONE
) {
409 val
|= 0x01; /* 1 drive, ready for boot */
412 val
|= 0x41; /* 2 drives, ready for boot */
415 val
|= 0x02; /* FPU is there */
416 val
|= 0x04; /* PS/2 mouse installed */
417 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
421 arg
.idebus0
= idebus0
;
422 arg
.idebus1
= idebus1
;
423 qemu_register_reset(pc_cmos_init_late
, &arg
);
426 /* port 92 stuff: could be split off */
427 typedef struct Port92State
{
434 static void port92_write(void *opaque
, uint32_t addr
, uint32_t val
)
436 Port92State
*s
= opaque
;
438 DPRINTF("port92: write 0x%02x\n", val
);
440 qemu_set_irq(*s
->a20_out
, (val
>> 1) & 1);
442 qemu_system_reset_request();
446 static uint32_t port92_read(void *opaque
, uint32_t addr
)
448 Port92State
*s
= opaque
;
452 DPRINTF("port92: read 0x%02x\n", ret
);
456 static void port92_init(ISADevice
*dev
, qemu_irq
*a20_out
)
458 Port92State
*s
= DO_UPCAST(Port92State
, dev
, dev
);
460 s
->a20_out
= a20_out
;
463 static const VMStateDescription vmstate_port92_isa
= {
466 .minimum_version_id
= 1,
467 .minimum_version_id_old
= 1,
468 .fields
= (VMStateField
[]) {
469 VMSTATE_UINT8(outport
, Port92State
),
470 VMSTATE_END_OF_LIST()
474 static void port92_reset(DeviceState
*d
)
476 Port92State
*s
= container_of(d
, Port92State
, dev
.qdev
);
481 static const MemoryRegionPortio port92_portio
[] = {
482 { 0, 1, 1, .read
= port92_read
, .write
= port92_write
},
483 PORTIO_END_OF_LIST(),
486 static const MemoryRegionOps port92_ops
= {
487 .old_portio
= port92_portio
490 static int port92_initfn(ISADevice
*dev
)
492 Port92State
*s
= DO_UPCAST(Port92State
, dev
, dev
);
494 memory_region_init_io(&s
->io
, &port92_ops
, s
, "port92", 1);
495 isa_register_ioport(dev
, &s
->io
, 0x92);
501 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
503 DeviceClass
*dc
= DEVICE_CLASS(klass
);
504 ISADeviceClass
*ic
= ISA_DEVICE_CLASS(klass
);
505 ic
->init
= port92_initfn
;
507 dc
->reset
= port92_reset
;
508 dc
->vmsd
= &vmstate_port92_isa
;
511 static TypeInfo port92_info
= {
513 .parent
= TYPE_ISA_DEVICE
,
514 .instance_size
= sizeof(Port92State
),
515 .class_init
= port92_class_initfn
,
518 static void port92_register_types(void)
520 type_register_static(&port92_info
);
523 type_init(port92_register_types
)
525 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
527 CPUX86State
*cpu
= opaque
;
529 /* XXX: send to all CPUs ? */
530 /* XXX: add logic to handle multiple A20 line sources */
531 cpu_x86_set_a20(cpu
, level
);
534 /***********************************************************/
535 /* Bochs BIOS debug ports */
537 static void bochs_bios_write(void *opaque
, uint32_t addr
, uint32_t val
)
539 static const char shutdown_str
[8] = "Shutdown";
540 static int shutdown_index
= 0;
543 /* Bochs BIOS messages */
546 /* used to be panic, now unused */
551 fprintf(stderr
, "%c", val
);
555 /* same as Bochs power off */
556 if (val
== shutdown_str
[shutdown_index
]) {
558 if (shutdown_index
== 8) {
560 qemu_system_shutdown_request();
567 /* LGPL'ed VGA BIOS messages */
570 exit((val
<< 1) | 1);
574 fprintf(stderr
, "%c", val
);
580 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
582 int index
= le32_to_cpu(e820_table
.count
);
583 struct e820_entry
*entry
;
585 if (index
>= E820_NR_ENTRIES
)
587 entry
= &e820_table
.entry
[index
++];
589 entry
->address
= cpu_to_le64(address
);
590 entry
->length
= cpu_to_le64(length
);
591 entry
->type
= cpu_to_le32(type
);
593 e820_table
.count
= cpu_to_le32(index
);
597 static void *bochs_bios_init(void)
600 uint8_t *smbios_table
;
602 uint64_t *numa_fw_cfg
;
605 register_ioport_write(0x400, 1, 2, bochs_bios_write
, NULL
);
606 register_ioport_write(0x401, 1, 2, bochs_bios_write
, NULL
);
607 register_ioport_write(0x402, 1, 1, bochs_bios_write
, NULL
);
608 register_ioport_write(0x403, 1, 1, bochs_bios_write
, NULL
);
609 register_ioport_write(0x8900, 1, 1, bochs_bios_write
, NULL
);
611 register_ioport_write(0x501, 1, 1, bochs_bios_write
, NULL
);
612 register_ioport_write(0x501, 1, 2, bochs_bios_write
, NULL
);
613 register_ioport_write(0x502, 1, 2, bochs_bios_write
, NULL
);
614 register_ioport_write(0x500, 1, 1, bochs_bios_write
, NULL
);
615 register_ioport_write(0x503, 1, 1, bochs_bios_write
, NULL
);
617 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
619 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
620 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
621 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
, (uint8_t *)acpi_tables
,
623 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
625 smbios_table
= smbios_get_table(&smbios_len
);
627 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
628 smbios_table
, smbios_len
);
629 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
, (uint8_t *)&e820_table
,
630 sizeof(struct e820_table
));
632 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, (uint8_t *)&hpet_cfg
,
633 sizeof(struct hpet_fw_config
));
634 /* allocate memory for the NUMA channel: one (64bit) word for the number
635 * of nodes, one word for each VCPU->node and one word for each node to
636 * hold the amount of memory.
638 numa_fw_cfg
= g_malloc0((1 + max_cpus
+ nb_numa_nodes
) * 8);
639 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
640 for (i
= 0; i
< max_cpus
; i
++) {
641 for (j
= 0; j
< nb_numa_nodes
; j
++) {
642 if (node_cpumask
[j
] & (1 << i
)) {
643 numa_fw_cfg
[i
+ 1] = cpu_to_le64(j
);
648 for (i
= 0; i
< nb_numa_nodes
; i
++) {
649 numa_fw_cfg
[max_cpus
+ 1 + i
] = cpu_to_le64(node_mem
[i
]);
651 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, (uint8_t *)numa_fw_cfg
,
652 (1 + max_cpus
+ nb_numa_nodes
) * 8);
657 static long get_file_size(FILE *f
)
661 /* XXX: on Unix systems, using fstat() probably makes more sense */
664 fseek(f
, 0, SEEK_END
);
666 fseek(f
, where
, SEEK_SET
);
671 static void load_linux(void *fw_cfg
,
672 const char *kernel_filename
,
673 const char *initrd_filename
,
674 const char *kernel_cmdline
,
675 target_phys_addr_t max_ram_size
)
678 int setup_size
, kernel_size
, initrd_size
= 0, cmdline_size
;
680 uint8_t header
[8192], *setup
, *kernel
, *initrd_data
;
681 target_phys_addr_t real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
685 /* Align to 16 bytes as a paranoia measure */
686 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
688 /* load the kernel header */
689 f
= fopen(kernel_filename
, "rb");
690 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
691 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
692 MIN(ARRAY_SIZE(header
), kernel_size
)) {
693 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
694 kernel_filename
, strerror(errno
));
698 /* kernel protocol version */
700 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
702 if (ldl_p(header
+0x202) == 0x53726448)
703 protocol
= lduw_p(header
+0x206);
705 /* This looks like a multiboot kernel. If it is, let's stop
706 treating it like a Linux kernel. */
707 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
708 kernel_cmdline
, kernel_size
, header
))
713 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
716 cmdline_addr
= 0x9a000 - cmdline_size
;
718 } else if (protocol
< 0x202) {
719 /* High but ancient kernel */
721 cmdline_addr
= 0x9a000 - cmdline_size
;
722 prot_addr
= 0x100000;
724 /* High and recent kernel */
726 cmdline_addr
= 0x20000;
727 prot_addr
= 0x100000;
732 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
733 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
734 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
740 /* highest address for loading the initrd */
741 if (protocol
>= 0x203)
742 initrd_max
= ldl_p(header
+0x22c);
744 initrd_max
= 0x37ffffff;
746 if (initrd_max
>= max_ram_size
-ACPI_DATA_SIZE
)
747 initrd_max
= max_ram_size
-ACPI_DATA_SIZE
-1;
749 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
750 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
751 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
752 (uint8_t*)strdup(kernel_cmdline
),
753 strlen(kernel_cmdline
)+1);
755 if (protocol
>= 0x202) {
756 stl_p(header
+0x228, cmdline_addr
);
758 stw_p(header
+0x20, 0xA33F);
759 stw_p(header
+0x22, cmdline_addr
-real_addr
);
762 /* handle vga= parameter */
763 vmode
= strstr(kernel_cmdline
, "vga=");
765 unsigned int video_mode
;
768 if (!strncmp(vmode
, "normal", 6)) {
770 } else if (!strncmp(vmode
, "ext", 3)) {
772 } else if (!strncmp(vmode
, "ask", 3)) {
775 video_mode
= strtol(vmode
, NULL
, 0);
777 stw_p(header
+0x1fa, video_mode
);
781 /* High nybble = B reserved for QEMU; low nybble is revision number.
782 If this code is substantially changed, you may want to consider
783 incrementing the revision. */
784 if (protocol
>= 0x200)
785 header
[0x210] = 0xB0;
788 if (protocol
>= 0x201) {
789 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
790 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
794 if (initrd_filename
) {
795 if (protocol
< 0x200) {
796 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
800 initrd_size
= get_image_size(initrd_filename
);
801 if (initrd_size
< 0) {
802 fprintf(stderr
, "qemu: error reading initrd %s\n",
807 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
809 initrd_data
= g_malloc(initrd_size
);
810 load_image(initrd_filename
, initrd_data
);
812 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
813 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
814 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
816 stl_p(header
+0x218, initrd_addr
);
817 stl_p(header
+0x21c, initrd_size
);
820 /* load kernel and setup */
821 setup_size
= header
[0x1f1];
824 setup_size
= (setup_size
+1)*512;
825 kernel_size
-= setup_size
;
827 setup
= g_malloc(setup_size
);
828 kernel
= g_malloc(kernel_size
);
829 fseek(f
, 0, SEEK_SET
);
830 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
831 fprintf(stderr
, "fread() failed\n");
834 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
835 fprintf(stderr
, "fread() failed\n");
839 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
841 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
842 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
843 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
845 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
846 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
847 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
849 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
850 option_rom
[nb_option_roms
].bootindex
= 0;
854 #define NE2000_NB_MAX 6
856 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
858 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
860 static const int parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
861 static const int parallel_irq
[MAX_PARALLEL_PORTS
] = { 7, 7, 7 };
863 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
865 static int nb_ne2k
= 0;
867 if (nb_ne2k
== NE2000_NB_MAX
)
869 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
870 ne2000_irq
[nb_ne2k
], nd
);
874 int cpu_is_bsp(CPUX86State
*env
)
876 /* We hard-wire the BSP to the first CPU. */
877 return env
->cpu_index
== 0;
880 DeviceState
*cpu_get_current_apic(void)
882 if (cpu_single_env
) {
883 return cpu_single_env
->apic_state
;
889 static DeviceState
*apic_init(void *env
, uint8_t apic_id
)
892 static int apic_mapped
;
894 if (kvm_irqchip_in_kernel()) {
895 dev
= qdev_create(NULL
, "kvm-apic");
896 } else if (xen_enabled()) {
897 dev
= qdev_create(NULL
, "xen-apic");
899 dev
= qdev_create(NULL
, "apic");
902 qdev_prop_set_uint8(dev
, "id", apic_id
);
903 qdev_prop_set_ptr(dev
, "cpu_env", env
);
904 qdev_init_nofail(dev
);
906 /* XXX: mapping more APICs at the same memory location */
907 if (apic_mapped
== 0) {
908 /* NOTE: the APIC is directly connected to the CPU - it is not
909 on the global memory bus. */
910 /* XXX: what if the base changes? */
911 sysbus_mmio_map(sysbus_from_qdev(dev
), 0, MSI_ADDR_BASE
);
918 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
920 CPUX86State
*s
= opaque
;
923 cpu_interrupt(s
, CPU_INTERRUPT_SMI
);
927 static void pc_cpu_reset(void *opaque
)
929 CPUX86State
*env
= opaque
;
931 cpu_state_reset(env
);
932 env
->halted
= !cpu_is_bsp(env
);
935 static CPUX86State
*pc_new_cpu(const char *cpu_model
)
939 env
= cpu_init(cpu_model
);
941 fprintf(stderr
, "Unable to find x86 CPU definition\n");
944 if ((env
->cpuid_features
& CPUID_APIC
) || smp_cpus
> 1) {
945 env
->apic_state
= apic_init(env
, env
->cpuid_apic_id
);
947 qemu_register_reset(pc_cpu_reset
, env
);
952 void pc_cpus_init(const char *cpu_model
)
957 if (cpu_model
== NULL
) {
959 cpu_model
= "qemu64";
961 cpu_model
= "qemu32";
965 for(i
= 0; i
< smp_cpus
; i
++) {
966 pc_new_cpu(cpu_model
);
970 void pc_memory_init(MemoryRegion
*system_memory
,
971 const char *kernel_filename
,
972 const char *kernel_cmdline
,
973 const char *initrd_filename
,
974 ram_addr_t below_4g_mem_size
,
975 ram_addr_t above_4g_mem_size
,
976 MemoryRegion
*rom_memory
,
977 MemoryRegion
**ram_memory
)
980 MemoryRegion
*ram
, *option_rom_mr
;
981 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
984 linux_boot
= (kernel_filename
!= NULL
);
986 /* Allocate RAM. We allocate it as a single memory region and use
987 * aliases to address portions of it, mostly for backwards compatibility
988 * with older qemus that used qemu_ram_alloc().
990 ram
= g_malloc(sizeof(*ram
));
991 memory_region_init_ram(ram
, "pc.ram",
992 below_4g_mem_size
+ above_4g_mem_size
);
993 vmstate_register_ram_global(ram
);
995 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
996 memory_region_init_alias(ram_below_4g
, "ram-below-4g", ram
,
997 0, below_4g_mem_size
);
998 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
999 if (above_4g_mem_size
> 0) {
1000 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1001 memory_region_init_alias(ram_above_4g
, "ram-above-4g", ram
,
1002 below_4g_mem_size
, above_4g_mem_size
);
1003 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1008 /* Initialize PC system firmware */
1009 pc_system_firmware_init(rom_memory
);
1011 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1012 memory_region_init_ram(option_rom_mr
, "pc.rom", PC_ROM_SIZE
);
1013 vmstate_register_ram_global(option_rom_mr
);
1014 memory_region_add_subregion_overlap(rom_memory
,
1019 fw_cfg
= bochs_bios_init();
1023 load_linux(fw_cfg
, kernel_filename
, initrd_filename
, kernel_cmdline
, below_4g_mem_size
);
1026 for (i
= 0; i
< nb_option_roms
; i
++) {
1027 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1031 qemu_irq
*pc_allocate_cpu_irq(void)
1033 return qemu_allocate_irqs(pic_irq_request
, NULL
, 1);
1036 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1038 DeviceState
*dev
= NULL
;
1040 if (cirrus_vga_enabled
) {
1042 dev
= pci_cirrus_vga_init(pci_bus
);
1044 dev
= &isa_create_simple(isa_bus
, "isa-cirrus-vga")->qdev
;
1046 } else if (vmsvga_enabled
) {
1048 dev
= pci_vmsvga_init(pci_bus
);
1050 fprintf(stderr
, "%s: vmware_vga: no PCI bus\n", __FUNCTION__
);
1053 } else if (qxl_enabled
) {
1055 dev
= &pci_create_simple(pci_bus
, -1, "qxl-vga")->qdev
;
1057 fprintf(stderr
, "%s: qxl: no PCI bus\n", __FUNCTION__
);
1060 } else if (std_vga_enabled
) {
1062 dev
= pci_vga_init(pci_bus
);
1064 dev
= isa_vga_init(isa_bus
);
1071 static void cpu_request_exit(void *opaque
, int irq
, int level
)
1073 CPUX86State
*env
= cpu_single_env
;
1080 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1081 ISADevice
**rtc_state
,
1086 DriveInfo
*fd
[MAX_FD
];
1087 DeviceState
*hpet
= NULL
;
1088 int pit_isa_irq
= 0;
1089 qemu_irq pit_alt_irq
= NULL
;
1090 qemu_irq rtc_irq
= NULL
;
1092 ISADevice
*i8042
, *port92
, *vmmouse
, *pit
= NULL
;
1093 qemu_irq
*cpu_exit_irq
;
1095 register_ioport_write(0x80, 1, 1, ioport80_write
, NULL
);
1097 register_ioport_write(0xf0, 1, 1, ioportF0_write
, NULL
);
1100 * Check if an HPET shall be created.
1102 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1103 * when the HPET wants to take over. Thus we have to disable the latter.
1105 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1106 hpet
= sysbus_try_create_simple("hpet", HPET_BASE
, NULL
);
1109 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1110 sysbus_connect_irq(sysbus_from_qdev(hpet
), i
, gsi
[i
]);
1113 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1114 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1117 *rtc_state
= rtc_init(isa_bus
, 2000, rtc_irq
);
1119 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1121 if (!xen_enabled()) {
1122 if (kvm_irqchip_in_kernel()) {
1123 pit
= kvm_pit_init(isa_bus
, 0x40);
1125 pit
= pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1128 /* connect PIT to output control line of the HPET */
1129 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(&pit
->qdev
, 0));
1131 pcspk_init(isa_bus
, pit
);
1134 for(i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1135 if (serial_hds
[i
]) {
1136 serial_isa_init(isa_bus
, i
, serial_hds
[i
]);
1140 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
1141 if (parallel_hds
[i
]) {
1142 parallel_init(isa_bus
, i
, parallel_hds
[i
]);
1146 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1147 i8042
= isa_create_simple(isa_bus
, "i8042");
1148 i8042_setup_a20_line(i8042
, &a20_line
[0]);
1150 vmport_init(isa_bus
);
1151 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1156 qdev_prop_set_ptr(&vmmouse
->qdev
, "ps2_mouse", i8042
);
1157 qdev_init_nofail(&vmmouse
->qdev
);
1159 port92
= isa_create_simple(isa_bus
, "port92");
1160 port92_init(port92
, &a20_line
[1]);
1162 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
1163 DMA_init(0, cpu_exit_irq
);
1165 for(i
= 0; i
< MAX_FD
; i
++) {
1166 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1168 *floppy
= fdctrl_init_isa(isa_bus
, fd
);
1171 void pc_pci_device_init(PCIBus
*pci_bus
)
1176 max_bus
= drive_get_max_bus(IF_SCSI
);
1177 for (bus
= 0; bus
<= max_bus
; bus
++) {
1178 pci_create_simple(pci_bus
, -1, "lsi53c895a");