hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licensed under the GNU GPL v2.
   7  *
   8  * Contributions after 2012-01-13 are licensed under the terms of the
   9  * GNU GPL, version 2 or (at your option) any later version.
  10  */
  11
  12 #include "sysbus.h"
  13 #include "arm-misc.h"
  14 #include "devices.h"
  15 #include "net.h"
  16 #include "sysemu.h"
  17 #include "boards.h"
  18 #include "pc.h"
  19 #include "qemu-timer.h"
  20 #include "ptimer.h"
  21 #include "block.h"
  22 #include "flash.h"
  23 #include "console.h"
  24 #include "i2c.h"
  25 #include "blockdev.h"
  26 #include "exec-memory.h"
  27
  28 #define MP_MISC_BASE            0x80002000
  29 #define MP_MISC_SIZE            0x00001000
  30
  31 #define MP_ETH_BASE             0x80008000
  32 #define MP_ETH_SIZE             0x00001000
  33
  34 #define MP_WLAN_BASE            0x8000C000
  35 #define MP_WLAN_SIZE            0x00000800
  36
  37 #define MP_UART1_BASE           0x8000C840
  38 #define MP_UART2_BASE           0x8000C940
  39
  40 #define MP_GPIO_BASE            0x8000D000
  41 #define MP_GPIO_SIZE            0x00001000
  42
  43 #define MP_FLASHCFG_BASE        0x90006000
  44 #define MP_FLASHCFG_SIZE        0x00001000
  45
  46 #define MP_AUDIO_BASE           0x90007000
  47
  48 #define MP_PIC_BASE             0x90008000
  49 #define MP_PIC_SIZE             0x00001000
  50
  51 #define MP_PIT_BASE             0x90009000
  52 #define MP_PIT_SIZE             0x00001000
  53
  54 #define MP_LCD_BASE             0x9000c000
  55 #define MP_LCD_SIZE             0x00001000
  56
  57 #define MP_SRAM_BASE            0xC0000000
  58 #define MP_SRAM_SIZE            0x00020000
  59
  60 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  61 #define MP_FLASH_SIZE_MAX       32*1024*1024
  62
  63 #define MP_TIMER1_IRQ           4
  64 #define MP_TIMER2_IRQ           5
  65 #define MP_TIMER3_IRQ           6
  66 #define MP_TIMER4_IRQ           7
  67 #define MP_EHCI_IRQ             8
  68 #define MP_ETH_IRQ              9
  69 #define MP_UART1_IRQ            11
  70 #define MP_UART2_IRQ            11
  71 #define MP_GPIO_IRQ             12
  72 #define MP_RTC_IRQ              28
  73 #define MP_AUDIO_IRQ            30
  74
  75 /* Wolfson 8750 I2C address */
  76 #define MP_WM_ADDR              0x1A
  77
  78 /* Ethernet register offsets */
  79 #define MP_ETH_SMIR             0x010
  80 #define MP_ETH_PCXR             0x408
  81 #define MP_ETH_SDCMR            0x448
  82 #define MP_ETH_ICR              0x450
  83 #define MP_ETH_IMR              0x458
  84 #define MP_ETH_FRDP0            0x480
  85 #define MP_ETH_FRDP1            0x484
  86 #define MP_ETH_FRDP2            0x488
  87 #define MP_ETH_FRDP3            0x48C
  88 #define MP_ETH_CRDP0            0x4A0
  89 #define MP_ETH_CRDP1            0x4A4
  90 #define MP_ETH_CRDP2            0x4A8
  91 #define MP_ETH_CRDP3            0x4AC
  92 #define MP_ETH_CTDP0            0x4E0
  93 #define MP_ETH_CTDP1            0x4E4
  94 #define MP_ETH_CTDP2            0x4E8
  95 #define MP_ETH_CTDP3            0x4EC
  96
  97 /* MII PHY access */
  98 #define MP_ETH_SMIR_DATA        0x0000FFFF
  99 #define MP_ETH_SMIR_ADDR        0x03FF0000
 100 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 101 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 102
 103 /* PHY registers */
 104 #define MP_ETH_PHY1_BMSR        0x00210000
 105 #define MP_ETH_PHY1_PHYSID1     0x00410000
 106 #define MP_ETH_PHY1_PHYSID2     0x00610000
 107
 108 #define MP_PHY_BMSR_LINK        0x0004
 109 #define MP_PHY_BMSR_AUTONEG     0x0008
 110
 111 #define MP_PHY_88E3015          0x01410E20
 112
 113 /* TX descriptor status */
 114 #define MP_ETH_TX_OWN           (1 << 31)
 115
 116 /* RX descriptor status */
 117 #define MP_ETH_RX_OWN           (1 << 31)
 118
 119 /* Interrupt cause/mask bits */
 120 #define MP_ETH_IRQ_RX_BIT       0
 121 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 122 #define MP_ETH_IRQ_TXHI_BIT     2
 123 #define MP_ETH_IRQ_TXLO_BIT     3
 124
 125 /* Port config bits */
 126 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 127
 128 /* SDMA command bits */
 129 #define MP_ETH_CMD_TXHI         (1 << 23)
 130 #define MP_ETH_CMD_TXLO         (1 << 22)
 131
 132 typedef struct mv88w8618_tx_desc {
 133     uint32_t cmdstat;
 134     uint16_t res;
 135     uint16_t bytes;
 136     uint32_t buffer;
 137     uint32_t next;
 138 } mv88w8618_tx_desc;
 139
 140 typedef struct mv88w8618_rx_desc {
 141     uint32_t cmdstat;
 142     uint16_t bytes;
 143     uint16_t buffer_size;
 144     uint32_t buffer;
 145     uint32_t next;
 146 } mv88w8618_rx_desc;
 147
 148 typedef struct mv88w8618_eth_state {
 149     SysBusDevice busdev;
 150     MemoryRegion iomem;
 151     qemu_irq irq;
 152     uint32_t smir;
 153     uint32_t icr;
 154     uint32_t imr;
 155     int mmio_index;
 156     uint32_t vlan_header;
 157     uint32_t tx_queue[2];
 158     uint32_t rx_queue[4];
 159     uint32_t frx_queue[4];
 160     uint32_t cur_rx[4];
 161     NICState *nic;
 162     NICConf conf;
 163 } mv88w8618_eth_state;
 164
 165 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 166 {
 167     cpu_to_le32s(&desc->cmdstat);
 168     cpu_to_le16s(&desc->bytes);
 169     cpu_to_le16s(&desc->buffer_size);
 170     cpu_to_le32s(&desc->buffer);
 171     cpu_to_le32s(&desc->next);
 172     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 173 }
 174
 175 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 176 {
 177     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 178     le32_to_cpus(&desc->cmdstat);
 179     le16_to_cpus(&desc->bytes);
 180     le16_to_cpus(&desc->buffer_size);
 181     le32_to_cpus(&desc->buffer);
 182     le32_to_cpus(&desc->next);
 183 }
 184
 185 static int eth_can_receive(VLANClientState *nc)
 186 {
 187     return 1;
 188 }
 189
 190 static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
 191 {
 192     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 193     uint32_t desc_addr;
 194     mv88w8618_rx_desc desc;
 195     int i;
 196
 197     for (i = 0; i < 4; i++) {
 198         desc_addr = s->cur_rx[i];
 199         if (!desc_addr) {
 200             continue;
 201         }
 202         do {
 203             eth_rx_desc_get(desc_addr, &desc);
 204             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 205                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 206                                           buf, size);
 207                 desc.bytes = size + s->vlan_header;
 208                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 209                 s->cur_rx[i] = desc.next;
 210
 211                 s->icr |= MP_ETH_IRQ_RX;
 212                 if (s->icr & s->imr) {
 213                     qemu_irq_raise(s->irq);
 214                 }
 215                 eth_rx_desc_put(desc_addr, &desc);
 216                 return size;
 217             }
 218             desc_addr = desc.next;
 219         } while (desc_addr != s->rx_queue[i]);
 220     }
 221     return size;
 222 }
 223
 224 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 225 {
 226     cpu_to_le32s(&desc->cmdstat);
 227     cpu_to_le16s(&desc->res);
 228     cpu_to_le16s(&desc->bytes);
 229     cpu_to_le32s(&desc->buffer);
 230     cpu_to_le32s(&desc->next);
 231     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 232 }
 233
 234 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 235 {
 236     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 237     le32_to_cpus(&desc->cmdstat);
 238     le16_to_cpus(&desc->res);
 239     le16_to_cpus(&desc->bytes);
 240     le32_to_cpus(&desc->buffer);
 241     le32_to_cpus(&desc->next);
 242 }
 243
 244 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 245 {
 246     uint32_t desc_addr = s->tx_queue[queue_index];
 247     mv88w8618_tx_desc desc;
 248     uint32_t next_desc;
 249     uint8_t buf[2048];
 250     int len;
 251
 252     do {
 253         eth_tx_desc_get(desc_addr, &desc);
 254         next_desc = desc.next;
 255         if (desc.cmdstat & MP_ETH_TX_OWN) {
 256             len = desc.bytes;
 257             if (len < 2048) {
 258                 cpu_physical_memory_read(desc.buffer, buf, len);
 259                 qemu_send_packet(&s->nic->nc, buf, len);
 260             }
 261             desc.cmdstat &= ~MP_ETH_TX_OWN;
 262             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 263             eth_tx_desc_put(desc_addr, &desc);
 264         }
 265         desc_addr = next_desc;
 266     } while (desc_addr != s->tx_queue[queue_index]);
 267 }
 268
 269 static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
 270                                    unsigned size)
 271 {
 272     mv88w8618_eth_state *s = opaque;
 273
 274     switch (offset) {
 275     case MP_ETH_SMIR:
 276         if (s->smir & MP_ETH_SMIR_OPCODE) {
 277             switch (s->smir & MP_ETH_SMIR_ADDR) {
 278             case MP_ETH_PHY1_BMSR:
 279                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 280                        MP_ETH_SMIR_RDVALID;
 281             case MP_ETH_PHY1_PHYSID1:
 282                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 283             case MP_ETH_PHY1_PHYSID2:
 284                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 285             default:
 286                 return MP_ETH_SMIR_RDVALID;
 287             }
 288         }
 289         return 0;
 290
 291     case MP_ETH_ICR:
 292         return s->icr;
 293
 294     case MP_ETH_IMR:
 295         return s->imr;
 296
 297     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 298         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 299
 300     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 301         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 302
 303     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 304         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 305
 306     default:
 307         return 0;
 308     }
 309 }
 310
 311 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 312                                 uint64_t value, unsigned size)
 313 {
 314     mv88w8618_eth_state *s = opaque;
 315
 316     switch (offset) {
 317     case MP_ETH_SMIR:
 318         s->smir = value;
 319         break;
 320
 321     case MP_ETH_PCXR:
 322         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 323         break;
 324
 325     case MP_ETH_SDCMR:
 326         if (value & MP_ETH_CMD_TXHI) {
 327             eth_send(s, 1);
 328         }
 329         if (value & MP_ETH_CMD_TXLO) {
 330             eth_send(s, 0);
 331         }
 332         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 333             qemu_irq_raise(s->irq);
 334         }
 335         break;
 336
 337     case MP_ETH_ICR:
 338         s->icr &= value;
 339         break;
 340
 341     case MP_ETH_IMR:
 342         s->imr = value;
 343         if (s->icr & s->imr) {
 344             qemu_irq_raise(s->irq);
 345         }
 346         break;
 347
 348     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 349         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 350         break;
 351
 352     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 353         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 354             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 355         break;
 356
 357     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 358         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 359         break;
 360     }
 361 }
 362
 363 static const MemoryRegionOps mv88w8618_eth_ops = {
 364     .read = mv88w8618_eth_read,
 365     .write = mv88w8618_eth_write,
 366     .endianness = DEVICE_NATIVE_ENDIAN,
 367 };
 368
 369 static void eth_cleanup(VLANClientState *nc)
 370 {
 371     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 372
 373     s->nic = NULL;
 374 }
 375
 376 static NetClientInfo net_mv88w8618_info = {
 377     .type = NET_CLIENT_TYPE_NIC,
 378     .size = sizeof(NICState),
 379     .can_receive = eth_can_receive,
 380     .receive = eth_receive,
 381     .cleanup = eth_cleanup,
 382 };
 383
 384 static int mv88w8618_eth_init(SysBusDevice *dev)
 385 {
 386     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 387
 388     sysbus_init_irq(dev, &s->irq);
 389     s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
 390                           object_get_typename(OBJECT(dev)), dev->qdev.id, s);
 391     memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
 392                           MP_ETH_SIZE);
 393     sysbus_init_mmio(dev, &s->iomem);
 394     return 0;
 395 }
 396
 397 static const VMStateDescription mv88w8618_eth_vmsd = {
 398     .name = "mv88w8618_eth",
 399     .version_id = 1,
 400     .minimum_version_id = 1,
 401     .minimum_version_id_old = 1,
 402     .fields = (VMStateField[]) {
 403         VMSTATE_UINT32(smir, mv88w8618_eth_state),
 404         VMSTATE_UINT32(icr, mv88w8618_eth_state),
 405         VMSTATE_UINT32(imr, mv88w8618_eth_state),
 406         VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
 407         VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
 408         VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
 409         VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
 410         VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
 411         VMSTATE_END_OF_LIST()
 412     }
 413 };
 414
 415 static Property mv88w8618_eth_properties[] = {
 416     DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
 417     DEFINE_PROP_END_OF_LIST(),
 418 };
 419
 420 static void mv88w8618_eth_class_init(ObjectClass *klass, void *data)
 421 {
 422     DeviceClass *dc = DEVICE_CLASS(klass);
 423     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 424
 425     k->init = mv88w8618_eth_init;
 426     dc->vmsd = &mv88w8618_eth_vmsd;
 427     dc->props = mv88w8618_eth_properties;
 428 }
 429
 430 static TypeInfo mv88w8618_eth_info = {
 431     .name          = "mv88w8618_eth",
 432     .parent        = TYPE_SYS_BUS_DEVICE,
 433     .instance_size = sizeof(mv88w8618_eth_state),
 434     .class_init    = mv88w8618_eth_class_init,
 435 };
 436
 437 /* LCD register offsets */
 438 #define MP_LCD_IRQCTRL          0x180
 439 #define MP_LCD_IRQSTAT          0x184
 440 #define MP_LCD_SPICTRL          0x1ac
 441 #define MP_LCD_INST             0x1bc
 442 #define MP_LCD_DATA             0x1c0
 443
 444 /* Mode magics */
 445 #define MP_LCD_SPI_DATA         0x00100011
 446 #define MP_LCD_SPI_CMD          0x00104011
 447 #define MP_LCD_SPI_INVALID      0x00000000
 448
 449 /* Commmands */
 450 #define MP_LCD_INST_SETPAGE0    0xB0
 451 /* ... */
 452 #define MP_LCD_INST_SETPAGE7    0xB7
 453
 454 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 455
 456 typedef struct musicpal_lcd_state {
 457     SysBusDevice busdev;
 458     MemoryRegion iomem;
 459     uint32_t brightness;
 460     uint32_t mode;
 461     uint32_t irqctrl;
 462     uint32_t page;
 463     uint32_t page_off;
 464     DisplayState *ds;
 465     uint8_t video_ram[128*64/8];
 466 } musicpal_lcd_state;
 467
 468 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 469 {
 470     switch (s->brightness) {
 471     case 7:
 472         return col;
 473     case 0:
 474         return 0;
 475     default:
 476         return (col * s->brightness) / 7;
 477     }
 478 }
 479
 480 #define SET_LCD_PIXEL(depth, type) \
 481 static inline void glue(set_lcd_pixel, depth) \
 482         (musicpal_lcd_state *s, int x, int y, type col) \
 483 { \
 484     int dx, dy; \
 485     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 486 \
 487     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 488         for (dx = 0; dx < 3; dx++, pixel++) \
 489             *pixel = col; \
 490 }
 491 SET_LCD_PIXEL(8, uint8_t)
 492 SET_LCD_PIXEL(16, uint16_t)
 493 SET_LCD_PIXEL(32, uint32_t)
 494
 495 #include "pixel_ops.h"
 496
 497 static void lcd_refresh(void *opaque)
 498 {
 499     musicpal_lcd_state *s = opaque;
 500     int x, y, col;
 501
 502     switch (ds_get_bits_per_pixel(s->ds)) {
 503     case 0:
 504         return;
 505 #define LCD_REFRESH(depth, func) \
 506     case depth: \
 507         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 508                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 509                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 510         for (x = 0; x < 128; x++) { \
 511             for (y = 0; y < 64; y++) { \
 512                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 513                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 514                 } else { \
 515                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 516                 } \
 517             } \
 518         } \
 519         break;
 520     LCD_REFRESH(8, rgb_to_pixel8)
 521     LCD_REFRESH(16, rgb_to_pixel16)
 522     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 523                      rgb_to_pixel32bgr : rgb_to_pixel32))
 524     default:
 525         hw_error("unsupported colour depth %i\n",
 526                   ds_get_bits_per_pixel(s->ds));
 527     }
 528
 529     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 530 }
 531
 532 static void lcd_invalidate(void *opaque)
 533 {
 534 }
 535
 536 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 537 {
 538     musicpal_lcd_state *s = opaque;
 539     s->brightness &= ~(1 << irq);
 540     s->brightness |= level << irq;
 541 }
 542
 543 static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
 544                                   unsigned size)
 545 {
 546     musicpal_lcd_state *s = opaque;
 547
 548     switch (offset) {
 549     case MP_LCD_IRQCTRL:
 550         return s->irqctrl;
 551
 552     default:
 553         return 0;
 554     }
 555 }
 556
 557 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 558                                uint64_t value, unsigned size)
 559 {
 560     musicpal_lcd_state *s = opaque;
 561
 562     switch (offset) {
 563     case MP_LCD_IRQCTRL:
 564         s->irqctrl = value;
 565         break;
 566
 567     case MP_LCD_SPICTRL:
 568         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 569             s->mode = value;
 570         } else {
 571             s->mode = MP_LCD_SPI_INVALID;
 572         }
 573         break;
 574
 575     case MP_LCD_INST:
 576         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 577             s->page = value - MP_LCD_INST_SETPAGE0;
 578             s->page_off = 0;
 579         }
 580         break;
 581
 582     case MP_LCD_DATA:
 583         if (s->mode == MP_LCD_SPI_CMD) {
 584             if (value >= MP_LCD_INST_SETPAGE0 &&
 585                 value <= MP_LCD_INST_SETPAGE7) {
 586                 s->page = value - MP_LCD_INST_SETPAGE0;
 587                 s->page_off = 0;
 588             }
 589         } else if (s->mode == MP_LCD_SPI_DATA) {
 590             s->video_ram[s->page*128 + s->page_off] = value;
 591             s->page_off = (s->page_off + 1) & 127;
 592         }
 593         break;
 594     }
 595 }
 596
 597 static const MemoryRegionOps musicpal_lcd_ops = {
 598     .read = musicpal_lcd_read,
 599     .write = musicpal_lcd_write,
 600     .endianness = DEVICE_NATIVE_ENDIAN,
 601 };
 602
 603 static int musicpal_lcd_init(SysBusDevice *dev)
 604 {
 605     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 606
 607     s->brightness = 7;
 608
 609     memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
 610                           "musicpal-lcd", MP_LCD_SIZE);
 611     sysbus_init_mmio(dev, &s->iomem);
 612
 613     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 614                                  NULL, NULL, s);
 615     qemu_console_resize(s->ds, 128*3, 64*3);
 616
 617     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 618
 619     return 0;
 620 }
 621
 622 static const VMStateDescription musicpal_lcd_vmsd = {
 623     .name = "musicpal_lcd",
 624     .version_id = 1,
 625     .minimum_version_id = 1,
 626     .minimum_version_id_old = 1,
 627     .fields = (VMStateField[]) {
 628         VMSTATE_UINT32(brightness, musicpal_lcd_state),
 629         VMSTATE_UINT32(mode, musicpal_lcd_state),
 630         VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
 631         VMSTATE_UINT32(page, musicpal_lcd_state),
 632         VMSTATE_UINT32(page_off, musicpal_lcd_state),
 633         VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
 634         VMSTATE_END_OF_LIST()
 635     }
 636 };
 637
 638 static void musicpal_lcd_class_init(ObjectClass *klass, void *data)
 639 {
 640     DeviceClass *dc = DEVICE_CLASS(klass);
 641     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 642
 643     k->init = musicpal_lcd_init;
 644     dc->vmsd = &musicpal_lcd_vmsd;
 645 }
 646
 647 static TypeInfo musicpal_lcd_info = {
 648     .name          = "musicpal_lcd",
 649     .parent        = TYPE_SYS_BUS_DEVICE,
 650     .instance_size = sizeof(musicpal_lcd_state),
 651     .class_init    = musicpal_lcd_class_init,
 652 };
 653
 654 /* PIC register offsets */
 655 #define MP_PIC_STATUS           0x00
 656 #define MP_PIC_ENABLE_SET       0x08
 657 #define MP_PIC_ENABLE_CLR       0x0C
 658
 659 typedef struct mv88w8618_pic_state
 660 {
 661     SysBusDevice busdev;
 662     MemoryRegion iomem;
 663     uint32_t level;
 664     uint32_t enabled;
 665     qemu_irq parent_irq;
 666 } mv88w8618_pic_state;
 667
 668 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 669 {
 670     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 671 }
 672
 673 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 674 {
 675     mv88w8618_pic_state *s = opaque;
 676
 677     if (level) {
 678         s->level |= 1 << irq;
 679     } else {
 680         s->level &= ~(1 << irq);
 681     }
 682     mv88w8618_pic_update(s);
 683 }
 684
 685 static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
 686                                    unsigned size)
 687 {
 688     mv88w8618_pic_state *s = opaque;
 689
 690     switch (offset) {
 691     case MP_PIC_STATUS:
 692         return s->level & s->enabled;
 693
 694     default:
 695         return 0;
 696     }
 697 }
 698
 699 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 700                                 uint64_t value, unsigned size)
 701 {
 702     mv88w8618_pic_state *s = opaque;
 703
 704     switch (offset) {
 705     case MP_PIC_ENABLE_SET:
 706         s->enabled |= value;
 707         break;
 708
 709     case MP_PIC_ENABLE_CLR:
 710         s->enabled &= ~value;
 711         s->level &= ~value;
 712         break;
 713     }
 714     mv88w8618_pic_update(s);
 715 }
 716
 717 static void mv88w8618_pic_reset(DeviceState *d)
 718 {
 719     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
 720                                          sysbus_from_qdev(d));
 721
 722     s->level = 0;
 723     s->enabled = 0;
 724 }
 725
 726 static const MemoryRegionOps mv88w8618_pic_ops = {
 727     .read = mv88w8618_pic_read,
 728     .write = mv88w8618_pic_write,
 729     .endianness = DEVICE_NATIVE_ENDIAN,
 730 };
 731
 732 static int mv88w8618_pic_init(SysBusDevice *dev)
 733 {
 734     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 735
 736     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 737     sysbus_init_irq(dev, &s->parent_irq);
 738     memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
 739                           "musicpal-pic", MP_PIC_SIZE);
 740     sysbus_init_mmio(dev, &s->iomem);
 741     return 0;
 742 }
 743
 744 static const VMStateDescription mv88w8618_pic_vmsd = {
 745     .name = "mv88w8618_pic",
 746     .version_id = 1,
 747     .minimum_version_id = 1,
 748     .minimum_version_id_old = 1,
 749     .fields = (VMStateField[]) {
 750         VMSTATE_UINT32(level, mv88w8618_pic_state),
 751         VMSTATE_UINT32(enabled, mv88w8618_pic_state),
 752         VMSTATE_END_OF_LIST()
 753     }
 754 };
 755
 756 static void mv88w8618_pic_class_init(ObjectClass *klass, void *data)
 757 {
 758     DeviceClass *dc = DEVICE_CLASS(klass);
 759     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 760
 761     k->init = mv88w8618_pic_init;
 762     dc->reset = mv88w8618_pic_reset;
 763     dc->vmsd = &mv88w8618_pic_vmsd;
 764 }
 765
 766 static TypeInfo mv88w8618_pic_info = {
 767     .name          = "mv88w8618_pic",
 768     .parent        = TYPE_SYS_BUS_DEVICE,
 769     .instance_size = sizeof(mv88w8618_pic_state),
 770     .class_init    = mv88w8618_pic_class_init,
 771 };
 772
 773 /* PIT register offsets */
 774 #define MP_PIT_TIMER1_LENGTH    0x00
 775 /* ... */
 776 #define MP_PIT_TIMER4_LENGTH    0x0C
 777 #define MP_PIT_CONTROL          0x10
 778 #define MP_PIT_TIMER1_VALUE     0x14
 779 /* ... */
 780 #define MP_PIT_TIMER4_VALUE     0x20
 781 #define MP_BOARD_RESET          0x34
 782
 783 /* Magic board reset value (probably some watchdog behind it) */
 784 #define MP_BOARD_RESET_MAGIC    0x10000
 785
 786 typedef struct mv88w8618_timer_state {
 787     ptimer_state *ptimer;
 788     uint32_t limit;
 789     int freq;
 790     qemu_irq irq;
 791 } mv88w8618_timer_state;
 792
 793 typedef struct mv88w8618_pit_state {
 794     SysBusDevice busdev;
 795     MemoryRegion iomem;
 796     mv88w8618_timer_state timer[4];
 797 } mv88w8618_pit_state;
 798
 799 static void mv88w8618_timer_tick(void *opaque)
 800 {
 801     mv88w8618_timer_state *s = opaque;
 802
 803     qemu_irq_raise(s->irq);
 804 }
 805
 806 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 807                                  uint32_t freq)
 808 {
 809     QEMUBH *bh;
 810
 811     sysbus_init_irq(dev, &s->irq);
 812     s->freq = freq;
 813
 814     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 815     s->ptimer = ptimer_init(bh);
 816 }
 817
 818 static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
 819                                    unsigned size)
 820 {
 821     mv88w8618_pit_state *s = opaque;
 822     mv88w8618_timer_state *t;
 823
 824     switch (offset) {
 825     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 826         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 827         return ptimer_get_count(t->ptimer);
 828
 829     default:
 830         return 0;
 831     }
 832 }
 833
 834 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 835                                 uint64_t value, unsigned size)
 836 {
 837     mv88w8618_pit_state *s = opaque;
 838     mv88w8618_timer_state *t;
 839     int i;
 840
 841     switch (offset) {
 842     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 843         t = &s->timer[offset >> 2];
 844         t->limit = value;
 845         if (t->limit > 0) {
 846             ptimer_set_limit(t->ptimer, t->limit, 1);
 847         } else {
 848             ptimer_stop(t->ptimer);
 849         }
 850         break;
 851
 852     case MP_PIT_CONTROL:
 853         for (i = 0; i < 4; i++) {
 854             t = &s->timer[i];
 855             if (value & 0xf && t->limit > 0) {
 856                 ptimer_set_limit(t->ptimer, t->limit, 0);
 857                 ptimer_set_freq(t->ptimer, t->freq);
 858                 ptimer_run(t->ptimer, 0);
 859             } else {
 860                 ptimer_stop(t->ptimer);
 861             }
 862             value >>= 4;
 863         }
 864         break;
 865
 866     case MP_BOARD_RESET:
 867         if (value == MP_BOARD_RESET_MAGIC) {
 868             qemu_system_reset_request();
 869         }
 870         break;
 871     }
 872 }
 873
 874 static void mv88w8618_pit_reset(DeviceState *d)
 875 {
 876     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
 877                                          sysbus_from_qdev(d));
 878     int i;
 879
 880     for (i = 0; i < 4; i++) {
 881         ptimer_stop(s->timer[i].ptimer);
 882         s->timer[i].limit = 0;
 883     }
 884 }
 885
 886 static const MemoryRegionOps mv88w8618_pit_ops = {
 887     .read = mv88w8618_pit_read,
 888     .write = mv88w8618_pit_write,
 889     .endianness = DEVICE_NATIVE_ENDIAN,
 890 };
 891
 892 static int mv88w8618_pit_init(SysBusDevice *dev)
 893 {
 894     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 895     int i;
 896
 897     /* Letting them all run at 1 MHz is likely just a pragmatic
 898      * simplification. */
 899     for (i = 0; i < 4; i++) {
 900         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 901     }
 902
 903     memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
 904                           "musicpal-pit", MP_PIT_SIZE);
 905     sysbus_init_mmio(dev, &s->iomem);
 906     return 0;
 907 }
 908
 909 static const VMStateDescription mv88w8618_timer_vmsd = {
 910     .name = "timer",
 911     .version_id = 1,
 912     .minimum_version_id = 1,
 913     .minimum_version_id_old = 1,
 914     .fields = (VMStateField[]) {
 915         VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
 916         VMSTATE_UINT32(limit, mv88w8618_timer_state),
 917         VMSTATE_END_OF_LIST()
 918     }
 919 };
 920
 921 static const VMStateDescription mv88w8618_pit_vmsd = {
 922     .name = "mv88w8618_pit",
 923     .version_id = 1,
 924     .minimum_version_id = 1,
 925     .minimum_version_id_old = 1,
 926     .fields = (VMStateField[]) {
 927         VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
 928                              mv88w8618_timer_vmsd, mv88w8618_timer_state),
 929         VMSTATE_END_OF_LIST()
 930     }
 931 };
 932
 933 static void mv88w8618_pit_class_init(ObjectClass *klass, void *data)
 934 {
 935     DeviceClass *dc = DEVICE_CLASS(klass);
 936     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 937
 938     k->init = mv88w8618_pit_init;
 939     dc->reset = mv88w8618_pit_reset;
 940     dc->vmsd = &mv88w8618_pit_vmsd;
 941 }
 942
 943 static TypeInfo mv88w8618_pit_info = {
 944     .name          = "mv88w8618_pit",
 945     .parent        = TYPE_SYS_BUS_DEVICE,
 946     .instance_size = sizeof(mv88w8618_pit_state),
 947     .class_init    = mv88w8618_pit_class_init,
 948 };
 949
 950 /* Flash config register offsets */
 951 #define MP_FLASHCFG_CFGR0    0x04
 952
 953 typedef struct mv88w8618_flashcfg_state {
 954     SysBusDevice busdev;
 955     MemoryRegion iomem;
 956     uint32_t cfgr0;
 957 } mv88w8618_flashcfg_state;
 958
 959 static uint64_t mv88w8618_flashcfg_read(void *opaque,
 960                                         target_phys_addr_t offset,
 961                                         unsigned size)
 962 {
 963     mv88w8618_flashcfg_state *s = opaque;
 964
 965     switch (offset) {
 966     case MP_FLASHCFG_CFGR0:
 967         return s->cfgr0;
 968
 969     default:
 970         return 0;
 971     }
 972 }
 973
 974 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 975                                      uint64_t value, unsigned size)
 976 {
 977     mv88w8618_flashcfg_state *s = opaque;
 978
 979     switch (offset) {
 980     case MP_FLASHCFG_CFGR0:
 981         s->cfgr0 = value;
 982         break;
 983     }
 984 }
 985
 986 static const MemoryRegionOps mv88w8618_flashcfg_ops = {
 987     .read = mv88w8618_flashcfg_read,
 988     .write = mv88w8618_flashcfg_write,
 989     .endianness = DEVICE_NATIVE_ENDIAN,
 990 };
 991
 992 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 993 {
 994     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 995
 996     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 997     memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
 998                           "musicpal-flashcfg", MP_FLASHCFG_SIZE);
 999     sysbus_init_mmio(dev, &s->iomem);
1000     return 0;
1001 }
1002
1003 static const VMStateDescription mv88w8618_flashcfg_vmsd = {
1004     .name = "mv88w8618_flashcfg",
1005     .version_id = 1,
1006     .minimum_version_id = 1,
1007     .minimum_version_id_old = 1,
1008     .fields = (VMStateField[]) {
1009         VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
1010         VMSTATE_END_OF_LIST()
1011     }
1012 };
1013
1014 static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data)
1015 {
1016     DeviceClass *dc = DEVICE_CLASS(klass);
1017     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1018
1019     k->init = mv88w8618_flashcfg_init;
1020     dc->vmsd = &mv88w8618_flashcfg_vmsd;
1021 }
1022
1023 static TypeInfo mv88w8618_flashcfg_info = {
1024     .name          = "mv88w8618_flashcfg",
1025     .parent        = TYPE_SYS_BUS_DEVICE,
1026     .instance_size = sizeof(mv88w8618_flashcfg_state),
1027     .class_init    = mv88w8618_flashcfg_class_init,
1028 };
1029
1030 /* Misc register offsets */
1031 #define MP_MISC_BOARD_REVISION  0x18
1032
1033 #define MP_BOARD_REVISION       0x31
1034
1035 static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
1036                                    unsigned size)
1037 {
1038     switch (offset) {
1039     case MP_MISC_BOARD_REVISION:
1040         return MP_BOARD_REVISION;
1041
1042     default:
1043         return 0;
1044     }
1045 }
1046
1047 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1048                                 uint64_t value, unsigned size)
1049 {
1050 }
1051
1052 static const MemoryRegionOps musicpal_misc_ops = {
1053     .read = musicpal_misc_read,
1054     .write = musicpal_misc_write,
1055     .endianness = DEVICE_NATIVE_ENDIAN,
1056 };
1057
1058 static void musicpal_misc_init(SysBusDevice *dev)
1059 {
1060     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1061
1062     memory_region_init_io(iomem, &musicpal_misc_ops, NULL,
1063                           "musicpal-misc", MP_MISC_SIZE);
1064     sysbus_add_memory(dev, MP_MISC_BASE, iomem);
1065 }
1066
1067 /* WLAN register offsets */
1068 #define MP_WLAN_MAGIC1          0x11c
1069 #define MP_WLAN_MAGIC2          0x124
1070
1071 static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
1072                                     unsigned size)
1073 {
1074     switch (offset) {
1075     /* Workaround to allow loading the binary-only wlandrv.ko crap
1076      * from the original Freecom firmware. */
1077     case MP_WLAN_MAGIC1:
1078         return ~3;
1079     case MP_WLAN_MAGIC2:
1080         return -1;
1081
1082     default:
1083         return 0;
1084     }
1085 }
1086
1087 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1088                                  uint64_t value, unsigned size)
1089 {
1090 }
1091
1092 static const MemoryRegionOps mv88w8618_wlan_ops = {
1093     .read = mv88w8618_wlan_read,
1094     .write =mv88w8618_wlan_write,
1095     .endianness = DEVICE_NATIVE_ENDIAN,
1096 };
1097
1098 static int mv88w8618_wlan_init(SysBusDevice *dev)
1099 {
1100     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1101
1102     memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
1103                           "musicpal-wlan", MP_WLAN_SIZE);
1104     sysbus_init_mmio(dev, iomem);
1105     return 0;
1106 }
1107
1108 /* GPIO register offsets */
1109 #define MP_GPIO_OE_LO           0x008
1110 #define MP_GPIO_OUT_LO          0x00c
1111 #define MP_GPIO_IN_LO           0x010
1112 #define MP_GPIO_IER_LO          0x014
1113 #define MP_GPIO_IMR_LO          0x018
1114 #define MP_GPIO_ISR_LO          0x020
1115 #define MP_GPIO_OE_HI           0x508
1116 #define MP_GPIO_OUT_HI          0x50c
1117 #define MP_GPIO_IN_HI           0x510
1118 #define MP_GPIO_IER_HI          0x514
1119 #define MP_GPIO_IMR_HI          0x518
1120 #define MP_GPIO_ISR_HI          0x520
1121
1122 /* GPIO bits & masks */
1123 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1124 #define MP_GPIO_I2C_DATA_BIT    29
1125 #define MP_GPIO_I2C_CLOCK_BIT   30
1126
1127 /* LCD brightness bits in GPIO_OE_HI */
1128 #define MP_OE_LCD_BRIGHTNESS    0x0007
1129
1130 typedef struct musicpal_gpio_state {
1131     SysBusDevice busdev;
1132     MemoryRegion iomem;
1133     uint32_t lcd_brightness;
1134     uint32_t out_state;
1135     uint32_t in_state;
1136     uint32_t ier;
1137     uint32_t imr;
1138     uint32_t isr;
1139     qemu_irq irq;
1140     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1141 } musicpal_gpio_state;
1142
1143 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1144     int i;
1145     uint32_t brightness;
1146
1147     /* compute brightness ratio */
1148     switch (s->lcd_brightness) {
1149     case 0x00000007:
1150         brightness = 0;
1151         break;
1152
1153     case 0x00020000:
1154         brightness = 1;
1155         break;
1156
1157     case 0x00020001:
1158         brightness = 2;
1159         break;
1160
1161     case 0x00040000:
1162         brightness = 3;
1163         break;
1164
1165     case 0x00010006:
1166         brightness = 4;
1167         break;
1168
1169     case 0x00020005:
1170         brightness = 5;
1171         break;
1172
1173     case 0x00040003:
1174         brightness = 6;
1175         break;
1176
1177     case 0x00030004:
1178     default:
1179         brightness = 7;
1180     }
1181
1182     /* set lcd brightness GPIOs  */
1183     for (i = 0; i <= 2; i++) {
1184         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1185     }
1186 }
1187
1188 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1189 {
1190     musicpal_gpio_state *s = opaque;
1191     uint32_t mask = 1 << pin;
1192     uint32_t delta = level << pin;
1193     uint32_t old = s->in_state & mask;
1194
1195     s->in_state &= ~mask;
1196     s->in_state |= delta;
1197
1198     if ((old ^ delta) &&
1199         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1200         s->isr = mask;
1201         qemu_irq_raise(s->irq);
1202     }
1203 }
1204
1205 static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
1206                                    unsigned size)
1207 {
1208     musicpal_gpio_state *s = opaque;
1209
1210     switch (offset) {
1211     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1212         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1213
1214     case MP_GPIO_OUT_LO:
1215         return s->out_state & 0xFFFF;
1216     case MP_GPIO_OUT_HI:
1217         return s->out_state >> 16;
1218
1219     case MP_GPIO_IN_LO:
1220         return s->in_state & 0xFFFF;
1221     case MP_GPIO_IN_HI:
1222         return s->in_state >> 16;
1223
1224     case MP_GPIO_IER_LO:
1225         return s->ier & 0xFFFF;
1226     case MP_GPIO_IER_HI:
1227         return s->ier >> 16;
1228
1229     case MP_GPIO_IMR_LO:
1230         return s->imr & 0xFFFF;
1231     case MP_GPIO_IMR_HI:
1232         return s->imr >> 16;
1233
1234     case MP_GPIO_ISR_LO:
1235         return s->isr & 0xFFFF;
1236     case MP_GPIO_ISR_HI:
1237         return s->isr >> 16;
1238
1239     default:
1240         return 0;
1241     }
1242 }
1243
1244 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1245                                 uint64_t value, unsigned size)
1246 {
1247     musicpal_gpio_state *s = opaque;
1248     switch (offset) {
1249     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1250         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1251                          (value & MP_OE_LCD_BRIGHTNESS);
1252         musicpal_gpio_brightness_update(s);
1253         break;
1254
1255     case MP_GPIO_OUT_LO:
1256         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1257         break;
1258     case MP_GPIO_OUT_HI:
1259         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1260         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1261                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1262         musicpal_gpio_brightness_update(s);
1263         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1264         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1265         break;
1266
1267     case MP_GPIO_IER_LO:
1268         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1269         break;
1270     case MP_GPIO_IER_HI:
1271         s->ier = (s->ier & 0xFFFF) | (value << 16);
1272         break;
1273
1274     case MP_GPIO_IMR_LO:
1275         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1276         break;
1277     case MP_GPIO_IMR_HI:
1278         s->imr = (s->imr & 0xFFFF) | (value << 16);
1279         break;
1280     }
1281 }
1282
1283 static const MemoryRegionOps musicpal_gpio_ops = {
1284     .read = musicpal_gpio_read,
1285     .write = musicpal_gpio_write,
1286     .endianness = DEVICE_NATIVE_ENDIAN,
1287 };
1288
1289 static void musicpal_gpio_reset(DeviceState *d)
1290 {
1291     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
1292                                          sysbus_from_qdev(d));
1293
1294     s->lcd_brightness = 0;
1295     s->out_state = 0;
1296     s->in_state = 0xffffffff;
1297     s->ier = 0;
1298     s->imr = 0;
1299     s->isr = 0;
1300 }
1301
1302 static int musicpal_gpio_init(SysBusDevice *dev)
1303 {
1304     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1305
1306     sysbus_init_irq(dev, &s->irq);
1307
1308     memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
1309                           "musicpal-gpio", MP_GPIO_SIZE);
1310     sysbus_init_mmio(dev, &s->iomem);
1311
1312     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1313
1314     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1315
1316     return 0;
1317 }
1318
1319 static const VMStateDescription musicpal_gpio_vmsd = {
1320     .name = "musicpal_gpio",
1321     .version_id = 1,
1322     .minimum_version_id = 1,
1323     .minimum_version_id_old = 1,
1324     .fields = (VMStateField[]) {
1325         VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1326         VMSTATE_UINT32(out_state, musicpal_gpio_state),
1327         VMSTATE_UINT32(in_state, musicpal_gpio_state),
1328         VMSTATE_UINT32(ier, musicpal_gpio_state),
1329         VMSTATE_UINT32(imr, musicpal_gpio_state),
1330         VMSTATE_UINT32(isr, musicpal_gpio_state),
1331         VMSTATE_END_OF_LIST()
1332     }
1333 };
1334
1335 static void musicpal_gpio_class_init(ObjectClass *klass, void *data)
1336 {
1337     DeviceClass *dc = DEVICE_CLASS(klass);
1338     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1339
1340     k->init = musicpal_gpio_init;
1341     dc->reset = musicpal_gpio_reset;
1342     dc->vmsd = &musicpal_gpio_vmsd;
1343 }
1344
1345 static TypeInfo musicpal_gpio_info = {
1346     .name          = "musicpal_gpio",
1347     .parent        = TYPE_SYS_BUS_DEVICE,
1348     .instance_size = sizeof(musicpal_gpio_state),
1349     .class_init    = musicpal_gpio_class_init,
1350 };
1351
1352 /* Keyboard codes & masks */
1353 #define KEY_RELEASED            0x80
1354 #define KEY_CODE                0x7f
1355
1356 #define KEYCODE_TAB             0x0f
1357 #define KEYCODE_ENTER           0x1c
1358 #define KEYCODE_F               0x21
1359 #define KEYCODE_M               0x32
1360
1361 #define KEYCODE_EXTENDED        0xe0
1362 #define KEYCODE_UP              0x48
1363 #define KEYCODE_DOWN            0x50
1364 #define KEYCODE_LEFT            0x4b
1365 #define KEYCODE_RIGHT           0x4d
1366
1367 #define MP_KEY_WHEEL_VOL       (1 << 0)
1368 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1369 #define MP_KEY_WHEEL_NAV       (1 << 2)
1370 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1371 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1372 #define MP_KEY_BTN_MENU        (1 << 5)
1373 #define MP_KEY_BTN_VOLUME      (1 << 6)
1374 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1375
1376 typedef struct musicpal_key_state {
1377     SysBusDevice busdev;
1378     MemoryRegion iomem;
1379     uint32_t kbd_extended;
1380     uint32_t pressed_keys;
1381     qemu_irq out[8];
1382 } musicpal_key_state;
1383
1384 static void musicpal_key_event(void *opaque, int keycode)
1385 {
1386     musicpal_key_state *s = opaque;
1387     uint32_t event = 0;
1388     int i;
1389
1390     if (keycode == KEYCODE_EXTENDED) {
1391         s->kbd_extended = 1;
1392         return;
1393     }
1394
1395     if (s->kbd_extended) {
1396         switch (keycode & KEY_CODE) {
1397         case KEYCODE_UP:
1398             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1399             break;
1400
1401         case KEYCODE_DOWN:
1402             event = MP_KEY_WHEEL_NAV;
1403             break;
1404
1405         case KEYCODE_LEFT:
1406             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1407             break;
1408
1409         case KEYCODE_RIGHT:
1410             event = MP_KEY_WHEEL_VOL;
1411             break;
1412         }
1413     } else {
1414         switch (keycode & KEY_CODE) {
1415         case KEYCODE_F:
1416             event = MP_KEY_BTN_FAVORITS;
1417             break;
1418
1419         case KEYCODE_TAB:
1420             event = MP_KEY_BTN_VOLUME;
1421             break;
1422
1423         case KEYCODE_ENTER:
1424             event = MP_KEY_BTN_NAVIGATION;
1425             break;
1426
1427         case KEYCODE_M:
1428             event = MP_KEY_BTN_MENU;
1429             break;
1430         }
1431         /* Do not repeat already pressed buttons */
1432         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1433             event = 0;
1434         }
1435     }
1436
1437     if (event) {
1438         /* Raise GPIO pin first if repeating a key */
1439         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1440             for (i = 0; i <= 7; i++) {
1441                 if (event & (1 << i)) {
1442                     qemu_set_irq(s->out[i], 1);
1443                 }
1444             }
1445         }
1446         for (i = 0; i <= 7; i++) {
1447             if (event & (1 << i)) {
1448                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1449             }
1450         }
1451         if (keycode & KEY_RELEASED) {
1452             s->pressed_keys &= ~event;
1453         } else {
1454             s->pressed_keys |= event;
1455         }
1456     }
1457
1458     s->kbd_extended = 0;
1459 }
1460
1461 static int musicpal_key_init(SysBusDevice *dev)
1462 {
1463     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1464
1465     memory_region_init(&s->iomem, "dummy", 0);
1466     sysbus_init_mmio(dev, &s->iomem);
1467
1468     s->kbd_extended = 0;
1469     s->pressed_keys = 0;
1470
1471     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1472
1473     qemu_add_kbd_event_handler(musicpal_key_event, s);
1474
1475     return 0;
1476 }
1477
1478 static const VMStateDescription musicpal_key_vmsd = {
1479     .name = "musicpal_key",
1480     .version_id = 1,
1481     .minimum_version_id = 1,
1482     .minimum_version_id_old = 1,
1483     .fields = (VMStateField[]) {
1484         VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1485         VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1486         VMSTATE_END_OF_LIST()
1487     }
1488 };
1489
1490 static void musicpal_key_class_init(ObjectClass *klass, void *data)
1491 {
1492     DeviceClass *dc = DEVICE_CLASS(klass);
1493     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1494
1495     k->init = musicpal_key_init;
1496     dc->vmsd = &musicpal_key_vmsd;
1497 }
1498
1499 static TypeInfo musicpal_key_info = {
1500     .name          = "musicpal_key",
1501     .parent        = TYPE_SYS_BUS_DEVICE,
1502     .instance_size = sizeof(musicpal_key_state),
1503     .class_init    = musicpal_key_class_init,
1504 };
1505
1506 static struct arm_boot_info musicpal_binfo = {
1507     .loader_start = 0x0,
1508     .board_id = 0x20e,
1509 };
1510
1511 static void musicpal_init(ram_addr_t ram_size,
1512                const char *boot_device,
1513                const char *kernel_filename, const char *kernel_cmdline,
1514                const char *initrd_filename, const char *cpu_model)
1515 {
1516     CPUARMState *env;
1517     qemu_irq *cpu_pic;
1518     qemu_irq pic[32];
1519     DeviceState *dev;
1520     DeviceState *i2c_dev;
1521     DeviceState *lcd_dev;
1522     DeviceState *key_dev;
1523     DeviceState *wm8750_dev;
1524     SysBusDevice *s;
1525     i2c_bus *i2c;
1526     int i;
1527     unsigned long flash_size;
1528     DriveInfo *dinfo;
1529     MemoryRegion *address_space_mem = get_system_memory();
1530     MemoryRegion *ram = g_new(MemoryRegion, 1);
1531     MemoryRegion *sram = g_new(MemoryRegion, 1);
1532
1533     if (!cpu_model) {
1534         cpu_model = "arm926";
1535     }
1536     env = cpu_init(cpu_model);
1537     if (!env) {
1538         fprintf(stderr, "Unable to find CPU definition\n");
1539         exit(1);
1540     }
1541     cpu_pic = arm_pic_init_cpu(env);
1542
1543     /* For now we use a fixed - the original - RAM size */
1544     memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
1545     vmstate_register_ram_global(ram);
1546     memory_region_add_subregion(address_space_mem, 0, ram);
1547
1548     memory_region_init_ram(sram, "musicpal.sram", MP_SRAM_SIZE);
1549     vmstate_register_ram_global(sram);
1550     memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
1551
1552     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1553                                cpu_pic[ARM_PIC_CPU_IRQ]);
1554     for (i = 0; i < 32; i++) {
1555         pic[i] = qdev_get_gpio_in(dev, i);
1556     }
1557     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1558                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1559                           pic[MP_TIMER4_IRQ], NULL);
1560
1561     if (serial_hds[0]) {
1562         serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
1563                        1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN);
1564     }
1565     if (serial_hds[1]) {
1566         serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
1567                        1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN);
1568     }
1569
1570     /* Register flash */
1571     dinfo = drive_get(IF_PFLASH, 0, 0);
1572     if (dinfo) {
1573         flash_size = bdrv_getlength(dinfo->bdrv);
1574         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1575             flash_size != 32*1024*1024) {
1576             fprintf(stderr, "Invalid flash image size\n");
1577             exit(1);
1578         }
1579
1580         /*
1581          * The original U-Boot accesses the flash at 0xFE000000 instead of
1582          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1583          * image is smaller than 32 MB.
1584          */
1585 #ifdef TARGET_WORDS_BIGENDIAN
1586         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1587                               "musicpal.flash", flash_size,
1588                               dinfo->bdrv, 0x10000,
1589                               (flash_size + 0xffff) >> 16,
1590                               MP_FLASH_SIZE_MAX / flash_size,
1591                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1592                               0x5555, 0x2AAA, 1);
1593 #else
1594         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1595                               "musicpal.flash", flash_size,
1596                               dinfo->bdrv, 0x10000,
1597                               (flash_size + 0xffff) >> 16,
1598                               MP_FLASH_SIZE_MAX / flash_size,
1599                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1600                               0x5555, 0x2AAA, 0);
1601 #endif
1602
1603     }
1604     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1605
1606     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1607     dev = qdev_create(NULL, "mv88w8618_eth");
1608     qdev_set_nic_properties(dev, &nd_table[0]);
1609     qdev_init_nofail(dev);
1610     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1611     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1612
1613     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1614
1615     musicpal_misc_init(sysbus_from_qdev(dev));
1616
1617     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1618     i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
1619     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1620
1621     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1622     key_dev = sysbus_create_simple("musicpal_key", -1, NULL);
1623
1624     /* I2C read data */
1625     qdev_connect_gpio_out(i2c_dev, 0,
1626                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1627     /* I2C data */
1628     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1629     /* I2C clock */
1630     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1631
1632     for (i = 0; i < 3; i++) {
1633         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1634     }
1635     for (i = 0; i < 4; i++) {
1636         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1637     }
1638     for (i = 4; i < 8; i++) {
1639         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1640     }
1641
1642     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1643     dev = qdev_create(NULL, "mv88w8618_audio");
1644     s = sysbus_from_qdev(dev);
1645     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1646     qdev_init_nofail(dev);
1647     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1648     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1649
1650     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1651     musicpal_binfo.kernel_filename = kernel_filename;
1652     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1653     musicpal_binfo.initrd_filename = initrd_filename;
1654     arm_load_kernel(env, &musicpal_binfo);
1655 }
1656
1657 static QEMUMachine musicpal_machine = {
1658     .name = "musicpal",
1659     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1660     .init = musicpal_init,
1661 };
1662
1663 static void musicpal_machine_init(void)
1664 {
1665     qemu_register_machine(&musicpal_machine);
1666 }
1667
1668 machine_init(musicpal_machine_init);
1669
1670 static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data)
1671 {
1672     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1673
1674     sdc->init = mv88w8618_wlan_init;
1675 }
1676
1677 static TypeInfo mv88w8618_wlan_info = {
1678     .name          = "mv88w8618_wlan",
1679     .parent        = TYPE_SYS_BUS_DEVICE,
1680     .instance_size = sizeof(SysBusDevice),
1681     .class_init    = mv88w8618_wlan_class_init,
1682 };
1683
1684 static void musicpal_register_types(void)
1685 {
1686     type_register_static(&mv88w8618_pic_info);
1687     type_register_static(&mv88w8618_pit_info);
1688     type_register_static(&mv88w8618_flashcfg_info);
1689     type_register_static(&mv88w8618_eth_info);
1690     type_register_static(&mv88w8618_wlan_info);
1691     type_register_static(&musicpal_lcd_info);
1692     type_register_static(&musicpal_gpio_info);
1693     type_register_static(&musicpal_key_info);
1694 }
1695
1696 type_init(musicpal_register_types)