hw/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "sysbus.h"
  21 #include "arm-misc.h"
  22 #include "devices.h"
  23 #include "loader.h"
  24 #include "net.h"
  25 #include "sysemu.h"
  26 #include "boards.h"
  27 #include "sysbus.h"
  28 #include "blockdev.h"
  29 #include "exec-memory.h"
  30
  31 #define SMP_BOOT_ADDR 0x100
  32 #define SMP_BOOT_REG  0x40
  33 #define GIC_BASE_ADDR 0xfff10000
  34
  35 #define NIRQ_GIC      160
  36
  37 /* Board init.  */
  38
  39 static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
  40 {
  41     int n;
  42     uint32_t smpboot[] = {
  43         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  44         0xe210000f, /* ands r0, r0, #0x0f */
  45         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  46         0xe0830200, /* add r0, r3, r0, lsl #4 */
  47         0xe59f2018, /* ldr r2, privbase */
  48         0xe3a01001, /* mov r1, #1 */
  49         0xe5821100, /* str r1, [r2, #256] */
  50         0xe320f003, /* wfi */
  51         0xe5901000, /* ldr     r1, [r0] */
  52         0xe1110001, /* tst     r1, r1 */
  53         0x0afffffb, /* beq     <wfi> */
  54         0xe12fff11, /* bx      r1 */
  55         GIC_BASE_ADDR      /* privbase: gic address.  */
  56     };
  57     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  58         smpboot[n] = tswap32(smpboot[n]);
  59     }
  60     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  61 }
  62
  63 static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info)
  64 {
  65     switch (info->nb_cpus) {
  66     case 4:
  67         stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
  68     case 3:
  69         stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
  70     case 2:
  71         stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
  72         env->regs[15] = SMP_BOOT_ADDR;
  73         break;
  74     default:
  75         break;
  76     }
  77 }
  78
  79 #define NUM_REGS      0x200
  80 static void hb_regs_write(void *opaque, target_phys_addr_t offset,
  81                           uint64_t value, unsigned size)
  82 {
  83     uint32_t *regs = opaque;
  84
  85     if (offset == 0xf00) {
  86         if (value == 1 || value == 2) {
  87             qemu_system_reset_request();
  88         } else if (value == 3) {
  89             qemu_system_shutdown_request();
  90         }
  91     }
  92
  93     regs[offset/4] = value;
  94 }
  95
  96 static uint64_t hb_regs_read(void *opaque, target_phys_addr_t offset,
  97                              unsigned size)
  98 {
  99     uint32_t *regs = opaque;
 100     uint32_t value = regs[offset/4];
 101
 102     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 103         value |= 0x30000000;
 104     }
 105
 106     return value;
 107 }
 108
 109 static const MemoryRegionOps hb_mem_ops = {
 110     .read = hb_regs_read,
 111     .write = hb_regs_write,
 112     .endianness = DEVICE_NATIVE_ENDIAN,
 113 };
 114
 115 typedef struct {
 116     SysBusDevice busdev;
 117     MemoryRegion *iomem;
 118     uint32_t regs[NUM_REGS];
 119 } HighbankRegsState;
 120
 121 static VMStateDescription vmstate_highbank_regs = {
 122     .name = "highbank-regs",
 123     .version_id = 0,
 124     .minimum_version_id = 0,
 125     .minimum_version_id_old = 0,
 126     .fields = (VMStateField[]) {
 127         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 128         VMSTATE_END_OF_LIST(),
 129     },
 130 };
 131
 132 static void highbank_regs_reset(DeviceState *dev)
 133 {
 134     SysBusDevice *sys_dev = sysbus_from_qdev(dev);
 135     HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev);
 136
 137     s->regs[0x40] = 0x05F20121;
 138     s->regs[0x41] = 0x2;
 139     s->regs[0x42] = 0x05F30121;
 140     s->regs[0x43] = 0x05F40121;
 141 }
 142
 143 static int highbank_regs_init(SysBusDevice *dev)
 144 {
 145     HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);
 146
 147     s->iomem = g_new(MemoryRegion, 1);
 148     memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
 149                           0x1000);
 150     sysbus_init_mmio(dev, s->iomem);
 151
 152     return 0;
 153 }
 154
 155 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 156 {
 157     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 158     DeviceClass *dc = DEVICE_CLASS(klass);
 159
 160     sbc->init = highbank_regs_init;
 161     dc->desc = "Calxeda Highbank registers";
 162     dc->vmsd = &vmstate_highbank_regs;
 163     dc->reset = highbank_regs_reset;
 164 }
 165
 166 static TypeInfo highbank_regs_info = {
 167     .name          = "highbank-regs",
 168     .parent        = TYPE_SYS_BUS_DEVICE,
 169     .instance_size = sizeof(HighbankRegsState),
 170     .class_init    = highbank_regs_class_init,
 171 };
 172
 173 static void highbank_regs_register_types(void)
 174 {
 175     type_register_static(&highbank_regs_info);
 176 }
 177
 178 type_init(highbank_regs_register_types)
 179
 180 static struct arm_boot_info highbank_binfo;
 181
 182 /* ram_size must be set to match the upper bound of memory in the
 183  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 184  * normally 0xff900000 or -m 4089. When running this board on a
 185  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 186  * device tree and pass -m 2047 to QEMU.
 187  */
 188 static void highbank_init(ram_addr_t ram_size,
 189                      const char *boot_device,
 190                      const char *kernel_filename, const char *kernel_cmdline,
 191                      const char *initrd_filename, const char *cpu_model)
 192 {
 193     CPUARMState *env = NULL;
 194     DeviceState *dev;
 195     SysBusDevice *busdev;
 196     qemu_irq *irqp;
 197     qemu_irq pic[128];
 198     int n;
 199     qemu_irq cpu_irq[4];
 200     MemoryRegion *sysram;
 201     MemoryRegion *dram;
 202     MemoryRegion *sysmem;
 203     char *sysboot_filename;
 204
 205     if (!cpu_model) {
 206         cpu_model = "cortex-a9";
 207     }
 208
 209     for (n = 0; n < smp_cpus; n++) {
 210         ARMCPU *cpu;
 211         cpu = cpu_arm_init(cpu_model);
 212         if (cpu == NULL) {
 213             fprintf(stderr, "Unable to find CPU definition\n");
 214             exit(1);
 215         }
 216         env = &cpu->env;
 217         /* This will become a QOM property eventually */
 218         cpu->reset_cbar = GIC_BASE_ADDR;
 219         irqp = arm_pic_init_cpu(env);
 220         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 221     }
 222
 223     sysmem = get_system_memory();
 224     dram = g_new(MemoryRegion, 1);
 225     memory_region_init_ram(dram, "highbank.dram", ram_size);
 226     /* SDRAM at address zero.  */
 227     memory_region_add_subregion(sysmem, 0, dram);
 228
 229     sysram = g_new(MemoryRegion, 1);
 230     memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
 231     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 232     if (bios_name != NULL) {
 233         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 234         if (sysboot_filename != NULL) {
 235             uint32_t filesize = get_image_size(sysboot_filename);
 236             if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
 237                 hw_error("Unable to load %s\n", bios_name);
 238             }
 239         } else {
 240            hw_error("Unable to find %s\n", bios_name);
 241         }
 242     }
 243
 244     dev = qdev_create(NULL, "a9mpcore_priv");
 245     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 246     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 247     qdev_init_nofail(dev);
 248     busdev = sysbus_from_qdev(dev);
 249     sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
 250     for (n = 0; n < smp_cpus; n++) {
 251         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 252     }
 253
 254     for (n = 0; n < 128; n++) {
 255         pic[n] = qdev_get_gpio_in(dev, n);
 256     }
 257
 258     dev = qdev_create(NULL, "l2x0");
 259     qdev_init_nofail(dev);
 260     busdev = sysbus_from_qdev(dev);
 261     sysbus_mmio_map(busdev, 0, 0xfff12000);
 262
 263     dev = qdev_create(NULL, "sp804");
 264     qdev_prop_set_uint32(dev, "freq0", 150000000);
 265     qdev_prop_set_uint32(dev, "freq1", 150000000);
 266     qdev_init_nofail(dev);
 267     busdev = sysbus_from_qdev(dev);
 268     sysbus_mmio_map(busdev, 0, 0xfff34000);
 269     sysbus_connect_irq(busdev, 0, pic[18]);
 270     sysbus_create_simple("pl011", 0xfff36000, pic[20]);
 271
 272     dev = qdev_create(NULL, "highbank-regs");
 273     qdev_init_nofail(dev);
 274     busdev = sysbus_from_qdev(dev);
 275     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 276
 277     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 278     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 279     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 280     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 281     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 282     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 283
 284     sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
 285
 286     if (nd_table[0].vlan) {
 287         qemu_check_nic_model(&nd_table[0], "xgmac");
 288         dev = qdev_create(NULL, "xgmac");
 289         qdev_set_nic_properties(dev, &nd_table[0]);
 290         qdev_init_nofail(dev);
 291         sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff50000);
 292         sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[77]);
 293         sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[78]);
 294         sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[79]);
 295
 296         qemu_check_nic_model(&nd_table[1], "xgmac");
 297         dev = qdev_create(NULL, "xgmac");
 298         qdev_set_nic_properties(dev, &nd_table[1]);
 299         qdev_init_nofail(dev);
 300         sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff51000);
 301         sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[80]);
 302         sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[81]);
 303         sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[82]);
 304     }
 305
 306     highbank_binfo.ram_size = ram_size;
 307     highbank_binfo.kernel_filename = kernel_filename;
 308     highbank_binfo.kernel_cmdline = kernel_cmdline;
 309     highbank_binfo.initrd_filename = initrd_filename;
 310     /* highbank requires a dtb in order to boot, and the dtb will override
 311      * the board ID. The following value is ignored, so set it to -1 to be
 312      * clear that the value is meaningless.
 313      */
 314     highbank_binfo.board_id = -1;
 315     highbank_binfo.nb_cpus = smp_cpus;
 316     highbank_binfo.loader_start = 0;
 317     highbank_binfo.write_secondary_boot = hb_write_secondary;
 318     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 319     arm_load_kernel(first_cpu, &highbank_binfo);
 320 }
 321
 322 static QEMUMachine highbank_machine = {
 323     .name = "highbank",
 324     .desc = "Calxeda Highbank (ECX-1000)",
 325     .init = highbank_init,
 326     .use_scsi = 1,
 327     .max_cpus = 4,
 328 };
 329
 330 static void highbank_machine_init(void)
 331 {
 332     qemu_register_machine(&highbank_machine);
 333 }
 334
 335 machine_init(highbank_machine_init);