4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
18 * Contributions after 2012-01-13 are licensed under the terms of the
19 * GNU GPL, version 2 or (at your option) any later version.
34 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
36 # define PIIX4_DPRINTF(format, ...) do { } while (0)
39 #define ACPI_DBG_IO_ADDR 0xb044
41 #define GPE_BASE 0xafe0
43 #define PCI_UP_BASE 0xae00
44 #define PCI_DOWN_BASE 0xae04
45 #define PCI_EJ_BASE 0xae08
46 #define PCI_RMV_BASE 0xae0c
48 #define PIIX4_PCI_HOTPLUG_STATUS 2
51 uint32_t up
; /* deprecated, maintained for migration compatibility */
55 typedef struct PIIX4PMState
{
68 Notifier machine_ready
;
71 struct pci_status pci0_status
;
72 uint32_t pci0_hotplug_enable
;
73 uint32_t pci0_slot_device_present
;
76 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
);
78 #define ACPI_ENABLE 0xf1
79 #define ACPI_DISABLE 0xf0
81 static void pm_update_sci(PIIX4PMState
*s
)
85 pmsts
= acpi_pm1_evt_get_sts(&s
->ar
);
86 sci_level
= (((pmsts
& s
->ar
.pm1
.evt
.en
) &
87 (ACPI_BITMASK_RT_CLOCK_ENABLE
|
88 ACPI_BITMASK_POWER_BUTTON_ENABLE
|
89 ACPI_BITMASK_GLOBAL_LOCK_ENABLE
|
90 ACPI_BITMASK_TIMER_ENABLE
)) != 0) ||
91 (((s
->ar
.gpe
.sts
[0] & s
->ar
.gpe
.en
[0])
92 & PIIX4_PCI_HOTPLUG_STATUS
) != 0);
94 qemu_set_irq(s
->irq
, sci_level
);
95 /* schedule a timer interruption if needed */
96 acpi_pm_tmr_update(&s
->ar
, (s
->ar
.pm1
.evt
.en
& ACPI_BITMASK_TIMER_ENABLE
) &&
97 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
));
100 static void pm_tmr_timer(ACPIREGS
*ar
)
102 PIIX4PMState
*s
= container_of(ar
, PIIX4PMState
, ar
);
106 static void pm_ioport_write(IORange
*ioport
, uint64_t addr
, unsigned width
,
109 PIIX4PMState
*s
= container_of(ioport
, PIIX4PMState
, ioport
);
112 PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
113 (unsigned)addr
, width
, (unsigned)val
);
118 acpi_pm1_evt_write_sts(&s
->ar
, val
);
122 acpi_pm1_evt_write_en(&s
->ar
, val
);
126 acpi_pm1_cnt_write(&s
->ar
, val
);
131 PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr
,
135 static void pm_ioport_read(IORange
*ioport
, uint64_t addr
, unsigned width
,
138 PIIX4PMState
*s
= container_of(ioport
, PIIX4PMState
, ioport
);
143 val
= acpi_pm1_evt_get_sts(&s
->ar
);
146 val
= s
->ar
.pm1
.evt
.en
;
149 val
= s
->ar
.pm1
.cnt
.cnt
;
152 val
= acpi_pm_tmr_get(&s
->ar
);
158 PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr
, val
);
162 static const IORangeOps pm_iorange_ops
= {
163 .read
= pm_ioport_read
,
164 .write
= pm_ioport_write
,
167 static void apm_ctrl_changed(uint32_t val
, void *arg
)
169 PIIX4PMState
*s
= arg
;
171 /* ACPI specs 3.0, 4.7.2.5 */
172 acpi_pm1_cnt_update(&s
->ar
, val
== ACPI_ENABLE
, val
== ACPI_DISABLE
);
174 if (s
->dev
.config
[0x5b] & (1 << 1)) {
176 qemu_irq_raise(s
->smi_irq
);
181 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
183 PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val
);
186 static void pm_io_space_update(PIIX4PMState
*s
)
190 if (s
->dev
.config
[0x80] & 1) {
191 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
192 pm_io_base
&= 0xffc0;
194 /* XXX: need to improve memory and ioport allocation */
195 PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base
);
196 iorange_init(&s
->ioport
, &pm_iorange_ops
, pm_io_base
, 64);
197 ioport_register(&s
->ioport
);
201 static void pm_write_config(PCIDevice
*d
,
202 uint32_t address
, uint32_t val
, int len
)
204 pci_default_write_config(d
, address
, val
, len
);
205 if (range_covers_byte(address
, len
, 0x80))
206 pm_io_space_update((PIIX4PMState
*)d
);
209 static void vmstate_pci_status_pre_save(void *opaque
)
211 struct pci_status
*pci0_status
= opaque
;
212 PIIX4PMState
*s
= container_of(pci0_status
, PIIX4PMState
, pci0_status
);
214 /* We no longer track up, so build a safe value for migrating
215 * to a version that still does... of course these might get lost
216 * by an old buggy implementation, but we try. */
217 pci0_status
->up
= s
->pci0_slot_device_present
& s
->pci0_hotplug_enable
;
220 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
222 PIIX4PMState
*s
= opaque
;
224 pm_io_space_update(s
);
228 #define VMSTATE_GPE_ARRAY(_field, _state) \
230 .name = (stringify(_field)), \
233 .info = &vmstate_info_uint16, \
234 .size = sizeof(uint16_t), \
235 .flags = VMS_ARRAY | VMS_POINTER, \
236 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
239 static const VMStateDescription vmstate_gpe
= {
242 .minimum_version_id
= 1,
243 .minimum_version_id_old
= 1,
244 .fields
= (VMStateField
[]) {
245 VMSTATE_GPE_ARRAY(sts
, ACPIGPE
),
246 VMSTATE_GPE_ARRAY(en
, ACPIGPE
),
247 VMSTATE_END_OF_LIST()
251 static const VMStateDescription vmstate_pci_status
= {
252 .name
= "pci_status",
254 .minimum_version_id
= 1,
255 .minimum_version_id_old
= 1,
256 .pre_save
= vmstate_pci_status_pre_save
,
257 .fields
= (VMStateField
[]) {
258 VMSTATE_UINT32(up
, struct pci_status
),
259 VMSTATE_UINT32(down
, struct pci_status
),
260 VMSTATE_END_OF_LIST()
264 static const VMStateDescription vmstate_acpi
= {
267 .minimum_version_id
= 1,
268 .minimum_version_id_old
= 1,
269 .post_load
= vmstate_acpi_post_load
,
270 .fields
= (VMStateField
[]) {
271 VMSTATE_PCI_DEVICE(dev
, PIIX4PMState
),
272 VMSTATE_UINT16(ar
.pm1
.evt
.sts
, PIIX4PMState
),
273 VMSTATE_UINT16(ar
.pm1
.evt
.en
, PIIX4PMState
),
274 VMSTATE_UINT16(ar
.pm1
.cnt
.cnt
, PIIX4PMState
),
275 VMSTATE_STRUCT(apm
, PIIX4PMState
, 0, vmstate_apm
, APMState
),
276 VMSTATE_TIMER(ar
.tmr
.timer
, PIIX4PMState
),
277 VMSTATE_INT64(ar
.tmr
.overflow_time
, PIIX4PMState
),
278 VMSTATE_STRUCT(ar
.gpe
, PIIX4PMState
, 2, vmstate_gpe
, ACPIGPE
),
279 VMSTATE_STRUCT(pci0_status
, PIIX4PMState
, 2, vmstate_pci_status
,
281 VMSTATE_END_OF_LIST()
285 static void acpi_piix_eject_slot(PIIX4PMState
*s
, unsigned slots
)
287 DeviceState
*qdev
, *next
;
288 BusState
*bus
= qdev_get_parent_bus(&s
->dev
.qdev
);
289 int slot
= ffs(slots
) - 1;
290 bool slot_free
= true;
292 /* Mark request as complete */
293 s
->pci0_status
.down
&= ~(1U << slot
);
295 QTAILQ_FOREACH_SAFE(qdev
, &bus
->children
, sibling
, next
) {
296 PCIDevice
*dev
= PCI_DEVICE(qdev
);
297 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
298 if (PCI_SLOT(dev
->devfn
) == slot
) {
299 if (pc
->no_hotplug
) {
302 object_unparent(OBJECT(dev
));
308 s
->pci0_slot_device_present
&= ~(1U << slot
);
312 static void piix4_update_hotplug(PIIX4PMState
*s
)
314 PCIDevice
*dev
= &s
->dev
;
315 BusState
*bus
= qdev_get_parent_bus(&dev
->qdev
);
316 DeviceState
*qdev
, *next
;
318 /* Execute any pending removes during reset */
319 while (s
->pci0_status
.down
) {
320 acpi_piix_eject_slot(s
, s
->pci0_status
.down
);
323 s
->pci0_hotplug_enable
= ~0;
324 s
->pci0_slot_device_present
= 0;
326 QTAILQ_FOREACH_SAFE(qdev
, &bus
->children
, sibling
, next
) {
327 PCIDevice
*pdev
= PCI_DEVICE(qdev
);
328 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pdev
);
329 int slot
= PCI_SLOT(pdev
->devfn
);
331 if (pc
->no_hotplug
) {
332 s
->pci0_hotplug_enable
&= ~(1U << slot
);
335 s
->pci0_slot_device_present
|= (1U << slot
);
339 static void piix4_reset(void *opaque
)
341 PIIX4PMState
*s
= opaque
;
342 uint8_t *pci_conf
= s
->dev
.config
;
349 if (s
->kvm_enabled
) {
350 /* Mark SMM as already inited (until KVM supports SMM). */
351 pci_conf
[0x5B] = 0x02;
353 piix4_update_hotplug(s
);
356 static void piix4_powerdown(void *opaque
, int irq
, int power_failing
)
358 PIIX4PMState
*s
= opaque
;
361 acpi_pm1_evt_power_down(&s
->ar
);
364 static void piix4_pm_machine_ready(Notifier
*n
, void *opaque
)
366 PIIX4PMState
*s
= container_of(n
, PIIX4PMState
, machine_ready
);
369 pci_conf
= s
->dev
.config
;
370 pci_conf
[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
371 pci_conf
[0x63] = 0x60;
372 pci_conf
[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
373 (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
377 static int piix4_pm_initfn(PCIDevice
*dev
)
379 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
382 pci_conf
= s
->dev
.config
;
383 pci_conf
[0x06] = 0x80;
384 pci_conf
[0x07] = 0x02;
385 pci_conf
[0x09] = 0x00;
386 pci_conf
[0x3d] = 0x01; // interrupt pin 1
388 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
391 apm_init(&s
->apm
, apm_ctrl_changed
, s
);
393 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
395 if (s
->kvm_enabled
) {
396 /* Mark SMM as already inited to prevent SMM from running. KVM does not
397 * support SMM mode. */
398 pci_conf
[0x5B] = 0x02;
401 /* XXX: which specification is used ? The i82731AB has different
403 pci_conf
[0x90] = s
->smb_io_base
| 1;
404 pci_conf
[0x91] = s
->smb_io_base
>> 8;
405 pci_conf
[0xd2] = 0x09;
406 register_ioport_write(s
->smb_io_base
, 64, 1, smb_ioport_writeb
, &s
->smb
);
407 register_ioport_read(s
->smb_io_base
, 64, 1, smb_ioport_readb
, &s
->smb
);
409 acpi_pm_tmr_init(&s
->ar
, pm_tmr_timer
);
410 acpi_gpe_init(&s
->ar
, GPE_LEN
);
412 qemu_system_powerdown
= *qemu_allocate_irqs(piix4_powerdown
, s
, 1);
414 pm_smbus_init(&s
->dev
.qdev
, &s
->smb
);
415 s
->machine_ready
.notify
= piix4_pm_machine_ready
;
416 qemu_add_machine_init_done_notifier(&s
->machine_ready
);
417 qemu_register_reset(piix4_reset
, s
);
418 piix4_acpi_system_hot_add_init(dev
->bus
, s
);
423 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
424 qemu_irq sci_irq
, qemu_irq smi_irq
,
430 dev
= pci_create(bus
, devfn
, "PIIX4_PM");
431 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
433 s
= DO_UPCAST(PIIX4PMState
, dev
, dev
);
435 acpi_pm1_cnt_init(&s
->ar
);
436 s
->smi_irq
= smi_irq
;
437 s
->kvm_enabled
= kvm_enabled
;
439 qdev_init_nofail(&dev
->qdev
);
444 static Property piix4_pm_properties
[] = {
445 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState
, smb_io_base
, 0),
446 DEFINE_PROP_END_OF_LIST(),
449 static void piix4_pm_class_init(ObjectClass
*klass
, void *data
)
451 DeviceClass
*dc
= DEVICE_CLASS(klass
);
452 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
455 k
->init
= piix4_pm_initfn
;
456 k
->config_write
= pm_write_config
;
457 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
458 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB_3
;
460 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
463 dc
->vmsd
= &vmstate_acpi
;
464 dc
->props
= piix4_pm_properties
;
467 static TypeInfo piix4_pm_info
= {
469 .parent
= TYPE_PCI_DEVICE
,
470 .instance_size
= sizeof(PIIX4PMState
),
471 .class_init
= piix4_pm_class_init
,
474 static void piix4_pm_register_types(void)
476 type_register_static(&piix4_pm_info
);
479 type_init(piix4_pm_register_types
)
481 static uint32_t gpe_readb(void *opaque
, uint32_t addr
)
483 PIIX4PMState
*s
= opaque
;
484 uint32_t val
= acpi_gpe_ioport_readb(&s
->ar
, addr
);
486 PIIX4_DPRINTF("gpe read %x == %x\n", addr
, val
);
490 static void gpe_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
492 PIIX4PMState
*s
= opaque
;
494 acpi_gpe_ioport_writeb(&s
->ar
, addr
, val
);
497 PIIX4_DPRINTF("gpe write %x <== %d\n", addr
, val
);
500 static uint32_t pci_up_read(void *opaque
, uint32_t addr
)
502 PIIX4PMState
*s
= opaque
;
505 /* Manufacture an "up" value to cause a device check on any hotplug
506 * slot with a device. Extra device checks are harmless. */
507 val
= s
->pci0_slot_device_present
& s
->pci0_hotplug_enable
;
509 PIIX4_DPRINTF("pci_up_read %x\n", val
);
513 static uint32_t pci_down_read(void *opaque
, uint32_t addr
)
515 PIIX4PMState
*s
= opaque
;
516 uint32_t val
= s
->pci0_status
.down
;
518 PIIX4_DPRINTF("pci_down_read %x\n", val
);
522 static uint32_t pci_features_read(void *opaque
, uint32_t addr
)
524 /* No feature defined yet */
525 PIIX4_DPRINTF("pci_features_read %x\n", 0);
529 static void pciej_write(void *opaque
, uint32_t addr
, uint32_t val
)
531 acpi_piix_eject_slot(opaque
, val
);
533 PIIX4_DPRINTF("pciej write %x <== %d\n", addr
, val
);
536 static uint32_t pcirmv_read(void *opaque
, uint32_t addr
)
538 PIIX4PMState
*s
= opaque
;
540 return s
->pci0_hotplug_enable
;
543 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
,
544 PCIHotplugState state
);
546 static void piix4_acpi_system_hot_add_init(PCIBus
*bus
, PIIX4PMState
*s
)
549 register_ioport_write(GPE_BASE
, GPE_LEN
, 1, gpe_writeb
, s
);
550 register_ioport_read(GPE_BASE
, GPE_LEN
, 1, gpe_readb
, s
);
551 acpi_gpe_blk(&s
->ar
, GPE_BASE
);
553 register_ioport_read(PCI_UP_BASE
, 4, 4, pci_up_read
, s
);
554 register_ioport_read(PCI_DOWN_BASE
, 4, 4, pci_down_read
, s
);
556 register_ioport_write(PCI_EJ_BASE
, 4, 4, pciej_write
, s
);
557 register_ioport_read(PCI_EJ_BASE
, 4, 4, pci_features_read
, s
);
559 register_ioport_read(PCI_RMV_BASE
, 4, 4, pcirmv_read
, s
);
561 pci_bus_hotplug(bus
, piix4_device_hotplug
, &s
->dev
.qdev
);
564 static void enable_device(PIIX4PMState
*s
, int slot
)
566 s
->ar
.gpe
.sts
[0] |= PIIX4_PCI_HOTPLUG_STATUS
;
567 s
->pci0_slot_device_present
|= (1U << slot
);
570 static void disable_device(PIIX4PMState
*s
, int slot
)
572 s
->ar
.gpe
.sts
[0] |= PIIX4_PCI_HOTPLUG_STATUS
;
573 s
->pci0_status
.down
|= (1U << slot
);
576 static int piix4_device_hotplug(DeviceState
*qdev
, PCIDevice
*dev
,
577 PCIHotplugState state
)
579 int slot
= PCI_SLOT(dev
->devfn
);
580 PIIX4PMState
*s
= DO_UPCAST(PIIX4PMState
, dev
,
583 /* Don't send event when device is enabled during qemu machine creation:
584 * it is present on boot, no hotplug event is necessary. We do send an
585 * event when the device is disabled later. */
586 if (state
== PCI_COLDPLUG_ENABLED
) {
587 s
->pci0_slot_device_present
|= (1U << slot
);
591 if (state
== PCI_HOTPLUG_ENABLED
) {
592 enable_device(s
, slot
);
594 disable_device(s
, slot
);