2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "target/ppc/cpu.h"
14 #include "sysemu/cpus.h"
15 #include "sysemu/dma.h"
16 #include "hw/qdev-properties.h"
17 #include "monitor/monitor.h"
18 #include "hw/ppc/xive.h"
24 static uint8_t xive_esb_set(uint8_t *pq
, uint8_t value
)
26 uint8_t old_pq
= *pq
& 0x3;
34 static bool xive_esb_trigger(uint8_t *pq
)
36 uint8_t old_pq
= *pq
& 0x3;
40 xive_esb_set(pq
, XIVE_ESB_PENDING
);
42 case XIVE_ESB_PENDING
:
44 xive_esb_set(pq
, XIVE_ESB_QUEUED
);
47 xive_esb_set(pq
, XIVE_ESB_OFF
);
50 g_assert_not_reached();
54 static bool xive_esb_eoi(uint8_t *pq
)
56 uint8_t old_pq
= *pq
& 0x3;
60 case XIVE_ESB_PENDING
:
61 xive_esb_set(pq
, XIVE_ESB_RESET
);
64 xive_esb_set(pq
, XIVE_ESB_PENDING
);
67 xive_esb_set(pq
, XIVE_ESB_OFF
);
70 g_assert_not_reached();
75 * XIVE Interrupt Source (or IVSE)
78 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
)
80 assert(srcno
< xsrc
->nr_irqs
);
82 return xsrc
->status
[srcno
] & 0x3;
85 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
)
87 assert(srcno
< xsrc
->nr_irqs
);
89 return xive_esb_set(&xsrc
->status
[srcno
], pq
);
93 * Returns whether the event notification should be forwarded.
95 static bool xive_source_lsi_trigger(XiveSource
*xsrc
, uint32_t srcno
)
97 uint8_t old_pq
= xive_source_esb_get(xsrc
, srcno
);
99 xsrc
->status
[srcno
] |= XIVE_STATUS_ASSERTED
;
103 xive_source_esb_set(xsrc
, srcno
, XIVE_ESB_PENDING
);
111 * Returns whether the event notification should be forwarded.
113 static bool xive_source_esb_trigger(XiveSource
*xsrc
, uint32_t srcno
)
117 assert(srcno
< xsrc
->nr_irqs
);
119 ret
= xive_esb_trigger(&xsrc
->status
[srcno
]);
121 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
122 xive_source_esb_get(xsrc
, srcno
) == XIVE_ESB_QUEUED
) {
123 qemu_log_mask(LOG_GUEST_ERROR
,
124 "XIVE: queued an event on LSI IRQ %d\n", srcno
);
131 * Returns whether the event notification should be forwarded.
133 static bool xive_source_esb_eoi(XiveSource
*xsrc
, uint32_t srcno
)
137 assert(srcno
< xsrc
->nr_irqs
);
139 ret
= xive_esb_eoi(&xsrc
->status
[srcno
]);
142 * LSI sources do not set the Q bit but they can still be
143 * asserted, in which case we should forward a new event
146 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
147 xsrc
->status
[srcno
] & XIVE_STATUS_ASSERTED
) {
148 ret
= xive_source_lsi_trigger(xsrc
, srcno
);
155 * Forward the source event notification to the Router
157 static void xive_source_notify(XiveSource
*xsrc
, int srcno
)
159 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_GET_CLASS(xsrc
->xive
);
162 xnc
->notify(xsrc
->xive
, srcno
);
167 * In a two pages ESB MMIO setting, even page is the trigger page, odd
168 * page is for management
170 static inline bool addr_is_even(hwaddr addr
, uint32_t shift
)
172 return !((addr
>> shift
) & 1);
175 static inline bool xive_source_is_trigger_page(XiveSource
*xsrc
, hwaddr addr
)
177 return xive_source_esb_has_2page(xsrc
) &&
178 addr_is_even(addr
, xsrc
->esb_shift
- 1);
183 * Trigger page Management/EOI page
185 * ESB MMIO setting 2 pages 1 or 2 pages
187 * 0x000 .. 0x3FF -1 EOI and return 0|1
188 * 0x400 .. 0x7FF -1 EOI and return 0|1
189 * 0x800 .. 0xBFF -1 return PQ
190 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
191 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
192 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
193 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
195 static uint64_t xive_source_esb_read(void *opaque
, hwaddr addr
, unsigned size
)
197 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
198 uint32_t offset
= addr
& 0xFFF;
199 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
202 /* In a two pages ESB MMIO setting, trigger page should not be read */
203 if (xive_source_is_trigger_page(xsrc
, addr
)) {
204 qemu_log_mask(LOG_GUEST_ERROR
,
205 "XIVE: invalid load on IRQ %d trigger page at "
206 "0x%"HWADDR_PRIx
"\n", srcno
, addr
);
211 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
212 ret
= xive_source_esb_eoi(xsrc
, srcno
);
214 /* Forward the source event notification for routing */
216 xive_source_notify(xsrc
, srcno
);
220 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
221 ret
= xive_source_esb_get(xsrc
, srcno
);
224 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
225 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
226 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
227 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
228 ret
= xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
231 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB load addr %x\n",
240 * Trigger page Management/EOI page
242 * ESB MMIO setting 2 pages 1 or 2 pages
244 * 0x000 .. 0x3FF Trigger Trigger
245 * 0x400 .. 0x7FF Trigger EOI
246 * 0x800 .. 0xBFF Trigger undefined
247 * 0xC00 .. 0xCFF Trigger PQ=00
248 * 0xD00 .. 0xDFF Trigger PQ=01
249 * 0xE00 .. 0xDFF Trigger PQ=10
250 * 0xF00 .. 0xDFF Trigger PQ=11
252 static void xive_source_esb_write(void *opaque
, hwaddr addr
,
253 uint64_t value
, unsigned size
)
255 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
256 uint32_t offset
= addr
& 0xFFF;
257 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
260 /* In a two pages ESB MMIO setting, trigger page only triggers */
261 if (xive_source_is_trigger_page(xsrc
, addr
)) {
262 notify
= xive_source_esb_trigger(xsrc
, srcno
);
268 notify
= xive_source_esb_trigger(xsrc
, srcno
);
271 case XIVE_ESB_STORE_EOI
... XIVE_ESB_STORE_EOI
+ 0x3FF:
272 if (!(xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
)) {
273 qemu_log_mask(LOG_GUEST_ERROR
,
274 "XIVE: invalid Store EOI for IRQ %d\n", srcno
);
278 notify
= xive_source_esb_eoi(xsrc
, srcno
);
281 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
282 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
283 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
284 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
285 xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
289 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr %x\n",
295 /* Forward the source event notification for routing */
297 xive_source_notify(xsrc
, srcno
);
301 static const MemoryRegionOps xive_source_esb_ops
= {
302 .read
= xive_source_esb_read
,
303 .write
= xive_source_esb_write
,
304 .endianness
= DEVICE_BIG_ENDIAN
,
306 .min_access_size
= 8,
307 .max_access_size
= 8,
310 .min_access_size
= 8,
311 .max_access_size
= 8,
315 static void xive_source_set_irq(void *opaque
, int srcno
, int val
)
317 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
320 if (xive_source_irq_is_lsi(xsrc
, srcno
)) {
322 notify
= xive_source_lsi_trigger(xsrc
, srcno
);
324 xsrc
->status
[srcno
] &= ~XIVE_STATUS_ASSERTED
;
328 notify
= xive_source_esb_trigger(xsrc
, srcno
);
332 /* Forward the source event notification for routing */
334 xive_source_notify(xsrc
, srcno
);
338 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
, Monitor
*mon
)
342 for (i
= 0; i
< xsrc
->nr_irqs
; i
++) {
343 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
345 if (pq
== XIVE_ESB_OFF
) {
349 monitor_printf(mon
, " %08x %s %c%c%c\n", i
+ offset
,
350 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
351 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
352 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
353 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ');
357 static void xive_source_reset(void *dev
)
359 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
361 /* Do not clear the LSI bitmap */
363 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */
364 memset(xsrc
->status
, XIVE_ESB_OFF
, xsrc
->nr_irqs
);
367 static void xive_source_realize(DeviceState
*dev
, Error
**errp
)
369 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
371 Error
*local_err
= NULL
;
373 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
375 error_propagate(errp
, local_err
);
376 error_prepend(errp
, "required link 'xive' not found: ");
380 xsrc
->xive
= XIVE_NOTIFIER(obj
);
382 if (!xsrc
->nr_irqs
) {
383 error_setg(errp
, "Number of interrupt needs to be greater than 0");
387 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
388 xsrc
->esb_shift
!= XIVE_ESB_4K_2PAGE
&&
389 xsrc
->esb_shift
!= XIVE_ESB_64K
&&
390 xsrc
->esb_shift
!= XIVE_ESB_64K_2PAGE
) {
391 error_setg(errp
, "Invalid ESB shift setting");
395 xsrc
->status
= g_malloc0(xsrc
->nr_irqs
);
396 xsrc
->lsi_map
= bitmap_new(xsrc
->nr_irqs
);
398 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
399 &xive_source_esb_ops
, xsrc
, "xive.esb",
400 (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
);
402 xsrc
->qirqs
= qemu_allocate_irqs(xive_source_set_irq
, xsrc
,
405 qemu_register_reset(xive_source_reset
, dev
);
408 static const VMStateDescription vmstate_xive_source
= {
409 .name
= TYPE_XIVE_SOURCE
,
411 .minimum_version_id
= 1,
412 .fields
= (VMStateField
[]) {
413 VMSTATE_UINT32_EQUAL(nr_irqs
, XiveSource
, NULL
),
414 VMSTATE_VBUFFER_UINT32(status
, XiveSource
, 1, NULL
, nr_irqs
),
415 VMSTATE_END_OF_LIST()
420 * The default XIVE interrupt source setting for the ESB MMIOs is two
421 * 64k pages without Store EOI, to be in sync with KVM.
423 static Property xive_source_properties
[] = {
424 DEFINE_PROP_UINT64("flags", XiveSource
, esb_flags
, 0),
425 DEFINE_PROP_UINT32("nr-irqs", XiveSource
, nr_irqs
, 0),
426 DEFINE_PROP_UINT32("shift", XiveSource
, esb_shift
, XIVE_ESB_64K_2PAGE
),
427 DEFINE_PROP_END_OF_LIST(),
430 static void xive_source_class_init(ObjectClass
*klass
, void *data
)
432 DeviceClass
*dc
= DEVICE_CLASS(klass
);
434 dc
->desc
= "XIVE Interrupt Source";
435 dc
->props
= xive_source_properties
;
436 dc
->realize
= xive_source_realize
;
437 dc
->vmsd
= &vmstate_xive_source
;
440 static const TypeInfo xive_source_info
= {
441 .name
= TYPE_XIVE_SOURCE
,
442 .parent
= TYPE_DEVICE
,
443 .instance_size
= sizeof(XiveSource
),
444 .class_init
= xive_source_class_init
,
451 void xive_end_queue_pic_print_info(XiveEND
*end
, uint32_t width
, Monitor
*mon
)
453 uint64_t qaddr_base
= (uint64_t) be32_to_cpu(end
->w2
& 0x0fffffff) << 32
454 | be32_to_cpu(end
->w3
);
455 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
456 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
457 uint32_t qentries
= 1 << (qsize
+ 10);
461 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
463 monitor_printf(mon
, " [ ");
464 qindex
= (qindex
- (width
- 1)) & (qentries
- 1);
465 for (i
= 0; i
< width
; i
++) {
466 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
469 if (dma_memory_read(&address_space_memory
, qaddr
, &qdata
,
471 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to read EQ @0x%"
472 HWADDR_PRIx
"\n", qaddr
);
475 monitor_printf(mon
, "%s%08x ", i
== width
- 1 ? "^" : "",
477 qindex
= (qindex
+ 1) & (qentries
- 1);
481 void xive_end_pic_print_info(XiveEND
*end
, uint32_t end_idx
, Monitor
*mon
)
483 uint64_t qaddr_base
= (uint64_t) be32_to_cpu(end
->w2
& 0x0fffffff) << 32
484 | be32_to_cpu(end
->w3
);
485 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
486 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
487 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
488 uint32_t qentries
= 1 << (qsize
+ 10);
490 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
491 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
493 if (!xive_end_is_valid(end
)) {
497 monitor_printf(mon
, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64
498 "% 6d/%5d ^%d", end_idx
,
499 xive_end_is_valid(end
) ? 'v' : '-',
500 xive_end_is_enqueue(end
) ? 'q' : '-',
501 xive_end_is_notify(end
) ? 'n' : '-',
502 xive_end_is_backlog(end
) ? 'b' : '-',
503 xive_end_is_escalate(end
) ? 'e' : '-',
504 priority
, nvt
, qaddr_base
, qindex
, qentries
, qgen
);
506 xive_end_queue_pic_print_info(end
, 6, mon
);
507 monitor_printf(mon
, "]\n");
510 static void xive_end_enqueue(XiveEND
*end
, uint32_t data
)
512 uint64_t qaddr_base
= (uint64_t) be32_to_cpu(end
->w2
& 0x0fffffff) << 32
513 | be32_to_cpu(end
->w3
);
514 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
515 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
516 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
518 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
519 uint32_t qdata
= cpu_to_be32((qgen
<< 31) | (data
& 0x7fffffff));
520 uint32_t qentries
= 1 << (qsize
+ 10);
522 if (dma_memory_write(&address_space_memory
, qaddr
, &qdata
, sizeof(qdata
))) {
523 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to write END data @0x%"
524 HWADDR_PRIx
"\n", qaddr
);
528 qindex
= (qindex
+ 1) & (qentries
- 1);
531 end
->w1
= xive_set_field32(END_W1_GENERATION
, end
->w1
, qgen
);
533 end
->w1
= xive_set_field32(END_W1_PAGE_OFF
, end
->w1
, qindex
);
537 * XIVE Router (aka. Virtualization Controller or IVRE)
540 int xive_router_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
543 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
545 return xrc
->get_eas(xrtr
, eas_blk
, eas_idx
, eas
);
548 int xive_router_get_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
551 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
553 return xrc
->get_end(xrtr
, end_blk
, end_idx
, end
);
556 int xive_router_write_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
557 XiveEND
*end
, uint8_t word_number
)
559 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
561 return xrc
->write_end(xrtr
, end_blk
, end_idx
, end
, word_number
);
565 * An END trigger can come from an event trigger (IPI or HW) or from
566 * another chip. We don't model the PowerBus but the END trigger
567 * message has the same parameters than in the function below.
569 static void xive_router_end_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
570 uint32_t end_idx
, uint32_t end_data
)
576 /* END cache lookup */
577 if (xive_router_get_end(xrtr
, end_blk
, end_idx
, &end
)) {
578 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
583 if (!xive_end_is_valid(&end
)) {
584 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
589 if (xive_end_is_enqueue(&end
)) {
590 xive_end_enqueue(&end
, end_data
);
591 /* Enqueuing event data modifies the EQ toggle and index */
592 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
596 * The W7 format depends on the F bit in W6. It defines the type
597 * of the notification :
599 * F=0 : single or multiple NVT notification
600 * F=1 : User level Event-Based Branch (EBB) notification, no
603 format
= xive_get_field32(END_W6_FORMAT_BIT
, end
.w6
);
604 priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
.w7
);
606 /* The END is masked */
607 if (format
== 0 && priority
== 0xff) {
612 * Check the END ESn (Event State Buffer for notification) for
613 * even futher coalescing in the Router
615 if (!xive_end_is_notify(&end
)) {
616 uint8_t pq
= xive_get_field32(END_W1_ESn
, end
.w1
);
617 bool notify
= xive_esb_trigger(&pq
);
619 if (pq
!= xive_get_field32(END_W1_ESn
, end
.w1
)) {
620 end
.w1
= xive_set_field32(END_W1_ESn
, end
.w1
, pq
);
621 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
624 /* ESn[Q]=1 : end of notification */
631 * Follows IVPE notification
635 static void xive_router_notify(XiveNotifier
*xn
, uint32_t lisn
)
637 XiveRouter
*xrtr
= XIVE_ROUTER(xn
);
638 uint8_t eas_blk
= XIVE_SRCNO_BLOCK(lisn
);
639 uint32_t eas_idx
= XIVE_SRCNO_INDEX(lisn
);
642 /* EAS cache lookup */
643 if (xive_router_get_eas(xrtr
, eas_blk
, eas_idx
, &eas
)) {
644 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN %x\n", lisn
);
649 * The IVRE checks the State Bit Cache at this point. We skip the
650 * SBC lookup because the state bits of the sources are modeled
651 * internally in QEMU.
654 if (!xive_eas_is_valid(&eas
)) {
655 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid LISN %x\n", lisn
);
659 if (xive_eas_is_masked(&eas
)) {
660 /* Notification completed */
665 * The event trigger becomes an END trigger
667 xive_router_end_notify(xrtr
,
668 xive_get_field64(EAS_END_BLOCK
, eas
.w
),
669 xive_get_field64(EAS_END_INDEX
, eas
.w
),
670 xive_get_field64(EAS_END_DATA
, eas
.w
));
673 static void xive_router_class_init(ObjectClass
*klass
, void *data
)
675 DeviceClass
*dc
= DEVICE_CLASS(klass
);
676 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
678 dc
->desc
= "XIVE Router Engine";
679 xnc
->notify
= xive_router_notify
;
682 static const TypeInfo xive_router_info
= {
683 .name
= TYPE_XIVE_ROUTER
,
684 .parent
= TYPE_SYS_BUS_DEVICE
,
686 .class_size
= sizeof(XiveRouterClass
),
687 .class_init
= xive_router_class_init
,
688 .interfaces
= (InterfaceInfo
[]) {
689 { TYPE_XIVE_NOTIFIER
},
694 void xive_eas_pic_print_info(XiveEAS
*eas
, uint32_t lisn
, Monitor
*mon
)
696 if (!xive_eas_is_valid(eas
)) {
700 monitor_printf(mon
, " %08x %s end:%02x/%04x data:%08x\n",
701 lisn
, xive_eas_is_masked(eas
) ? "M" : " ",
702 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
703 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
704 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
710 static uint64_t xive_end_source_read(void *opaque
, hwaddr addr
, unsigned size
)
712 XiveENDSource
*xsrc
= XIVE_END_SOURCE(opaque
);
713 uint32_t offset
= addr
& 0xFFF;
721 end_blk
= xsrc
->block_id
;
722 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
724 if (xive_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
725 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
730 if (!xive_end_is_valid(&end
)) {
731 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
736 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END_W1_ESn
: END_W1_ESe
;
737 pq
= xive_get_field32(end_esmask
, end
.w1
);
740 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
741 ret
= xive_esb_eoi(&pq
);
743 /* Forward the source event notification for routing ?? */
746 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
750 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
751 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
752 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
753 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
754 ret
= xive_esb_set(&pq
, (offset
>> 8) & 0x3);
757 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB load addr %d\n",
762 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
763 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
764 xive_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
771 * END ESB MMIO stores are invalid
773 static void xive_end_source_write(void *opaque
, hwaddr addr
,
774 uint64_t value
, unsigned size
)
776 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr 0x%"
777 HWADDR_PRIx
"\n", addr
);
780 static const MemoryRegionOps xive_end_source_ops
= {
781 .read
= xive_end_source_read
,
782 .write
= xive_end_source_write
,
783 .endianness
= DEVICE_BIG_ENDIAN
,
785 .min_access_size
= 8,
786 .max_access_size
= 8,
789 .min_access_size
= 8,
790 .max_access_size
= 8,
794 static void xive_end_source_realize(DeviceState
*dev
, Error
**errp
)
796 XiveENDSource
*xsrc
= XIVE_END_SOURCE(dev
);
798 Error
*local_err
= NULL
;
800 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
802 error_propagate(errp
, local_err
);
803 error_prepend(errp
, "required link 'xive' not found: ");
807 xsrc
->xrtr
= XIVE_ROUTER(obj
);
809 if (!xsrc
->nr_ends
) {
810 error_setg(errp
, "Number of interrupt needs to be greater than 0");
814 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
815 xsrc
->esb_shift
!= XIVE_ESB_64K
) {
816 error_setg(errp
, "Invalid ESB shift setting");
821 * Each END is assigned an even/odd pair of MMIO pages, the even page
822 * manages the ESn field while the odd page manages the ESe field.
824 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
825 &xive_end_source_ops
, xsrc
, "xive.end",
826 (1ull << (xsrc
->esb_shift
+ 1)) * xsrc
->nr_ends
);
829 static Property xive_end_source_properties
[] = {
830 DEFINE_PROP_UINT8("block-id", XiveENDSource
, block_id
, 0),
831 DEFINE_PROP_UINT32("nr-ends", XiveENDSource
, nr_ends
, 0),
832 DEFINE_PROP_UINT32("shift", XiveENDSource
, esb_shift
, XIVE_ESB_64K
),
833 DEFINE_PROP_END_OF_LIST(),
836 static void xive_end_source_class_init(ObjectClass
*klass
, void *data
)
838 DeviceClass
*dc
= DEVICE_CLASS(klass
);
840 dc
->desc
= "XIVE END Source";
841 dc
->props
= xive_end_source_properties
;
842 dc
->realize
= xive_end_source_realize
;
845 static const TypeInfo xive_end_source_info
= {
846 .name
= TYPE_XIVE_END_SOURCE
,
847 .parent
= TYPE_DEVICE
,
848 .instance_size
= sizeof(XiveENDSource
),
849 .class_init
= xive_end_source_class_init
,
855 static const TypeInfo xive_fabric_info
= {
856 .name
= TYPE_XIVE_NOTIFIER
,
857 .parent
= TYPE_INTERFACE
,
858 .class_size
= sizeof(XiveNotifierClass
),
861 static void xive_register_types(void)
863 type_register_static(&xive_source_info
);
864 type_register_static(&xive_fabric_info
);
865 type_register_static(&xive_router_info
);
866 type_register_static(&xive_end_source_info
);
869 type_init(xive_register_types
)