target-sh4/cpu.h

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef _CPU_SH4_H
  20 #define _CPU_SH4_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #define TARGET_LONG_BITS 32
  26 #define TARGET_HAS_ICE 1
  27
  28 #define ELF_MACHINE     EM_SH
  29
  30 /* CPU Subtypes */
  31 #define SH_CPU_SH7750  (1 << 0)
  32 #define SH_CPU_SH7750S (1 << 1)
  33 #define SH_CPU_SH7750R (1 << 2)
  34 #define SH_CPU_SH7751  (1 << 3)
  35 #define SH_CPU_SH7751R (1 << 4)
  36 #define SH_CPU_SH7785  (1 << 5)
  37 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
  38 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
  39
  40 #define CPUArchState struct CPUSH4State
  41
  42 #include "exec/cpu-defs.h"
  43
  44 #include "fpu/softfloat.h"
  45
  46 #define TARGET_PAGE_BITS 12     /* 4k XXXXX */
  47
  48 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  49 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  50
  51 #define SR_MD (1 << 30)
  52 #define SR_RB (1 << 29)
  53 #define SR_BL (1 << 28)
  54 #define SR_FD (1 << 15)
  55 #define SR_M  (1 << 9)
  56 #define SR_Q  (1 << 8)
  57 #define SR_I3 (1 << 7)
  58 #define SR_I2 (1 << 6)
  59 #define SR_I1 (1 << 5)
  60 #define SR_I0 (1 << 4)
  61 #define SR_S  (1 << 1)
  62 #define SR_T  (1 << 0)
  63
  64 #define FPSCR_MASK             (0x003fffff)
  65 #define FPSCR_FR               (1 << 21)
  66 #define FPSCR_SZ               (1 << 20)
  67 #define FPSCR_PR               (1 << 19)
  68 #define FPSCR_DN               (1 << 18)
  69 #define FPSCR_CAUSE_MASK       (0x3f << 12)
  70 #define FPSCR_CAUSE_SHIFT      (12)
  71 #define FPSCR_CAUSE_E          (1 << 17)
  72 #define FPSCR_CAUSE_V          (1 << 16)
  73 #define FPSCR_CAUSE_Z          (1 << 15)
  74 #define FPSCR_CAUSE_O          (1 << 14)
  75 #define FPSCR_CAUSE_U          (1 << 13)
  76 #define FPSCR_CAUSE_I          (1 << 12)
  77 #define FPSCR_ENABLE_MASK      (0x1f << 7)
  78 #define FPSCR_ENABLE_SHIFT     (7)
  79 #define FPSCR_ENABLE_V         (1 << 11)
  80 #define FPSCR_ENABLE_Z         (1 << 10)
  81 #define FPSCR_ENABLE_O         (1 << 9)
  82 #define FPSCR_ENABLE_U         (1 << 8)
  83 #define FPSCR_ENABLE_I         (1 << 7)
  84 #define FPSCR_FLAG_MASK        (0x1f << 2)
  85 #define FPSCR_FLAG_SHIFT       (2)
  86 #define FPSCR_FLAG_V           (1 << 6)
  87 #define FPSCR_FLAG_Z           (1 << 5)
  88 #define FPSCR_FLAG_O           (1 << 4)
  89 #define FPSCR_FLAG_U           (1 << 3)
  90 #define FPSCR_FLAG_I           (1 << 2)
  91 #define FPSCR_RM_MASK          (0x03 << 0)
  92 #define FPSCR_RM_NEAREST       (0 << 0)
  93 #define FPSCR_RM_ZERO          (1 << 0)
  94
  95 #define DELAY_SLOT             (1 << 0)
  96 #define DELAY_SLOT_CONDITIONAL (1 << 1)
  97 #define DELAY_SLOT_TRUE        (1 << 2)
  98 #define DELAY_SLOT_CLEARME     (1 << 3)
  99 /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
 100  * after the delay slot should be taken or not. It is calculated from SR_T.
 101  *
 102  * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
 103  * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
 104  */
 105
 106 typedef struct tlb_t {
 107     uint32_t vpn;               /* virtual page number */
 108     uint32_t ppn;               /* physical page number */
 109     uint32_t size;              /* mapped page size in bytes */
 110     uint8_t asid;               /* address space identifier */
 111     uint8_t v:1;                /* validity */
 112     uint8_t sz:2;               /* page size */
 113     uint8_t sh:1;               /* share status */
 114     uint8_t c:1;                /* cacheability */
 115     uint8_t pr:2;               /* protection key */
 116     uint8_t d:1;                /* dirty */
 117     uint8_t wt:1;               /* write through */
 118     uint8_t sa:3;               /* space attribute (PCMCIA) */
 119     uint8_t tc:1;               /* timing control */
 120 } tlb_t;
 121
 122 #define UTLB_SIZE 64
 123 #define ITLB_SIZE 4
 124
 125 #define NB_MMU_MODES 2
 126
 127 enum sh_features {
 128     SH_FEATURE_SH4A = 1,
 129     SH_FEATURE_BCR3_AND_BCR4 = 2,
 130 };
 131
 132 typedef struct memory_content {
 133     uint32_t address;
 134     uint32_t value;
 135     struct memory_content *next;
 136 } memory_content;
 137
 138 typedef struct CPUSH4State {
 139     uint32_t flags;             /* general execution flags */
 140     uint32_t gregs[24];         /* general registers */
 141     float32 fregs[32];          /* floating point registers */
 142     uint32_t sr;                /* status register */
 143     uint32_t ssr;               /* saved status register */
 144     uint32_t spc;               /* saved program counter */
 145     uint32_t gbr;               /* global base register */
 146     uint32_t vbr;               /* vector base register */
 147     uint32_t sgr;               /* saved global register 15 */
 148     uint32_t dbr;               /* debug base register */
 149     uint32_t pc;                /* program counter */
 150     uint32_t delayed_pc;        /* target of delayed jump */
 151     uint32_t mach;              /* multiply and accumulate high */
 152     uint32_t macl;              /* multiply and accumulate low */
 153     uint32_t pr;                /* procedure register */
 154     uint32_t fpscr;             /* floating point status/control register */
 155     uint32_t fpul;              /* floating point communication register */
 156
 157     /* float point status register */
 158     float_status fp_status;
 159
 160     /* Those belong to the specific unit (SH7750) but are handled here */
 161     uint32_t mmucr;             /* MMU control register */
 162     uint32_t pteh;              /* page table entry high register */
 163     uint32_t ptel;              /* page table entry low register */
 164     uint32_t ptea;              /* page table entry assistance register */
 165     uint32_t ttb;               /* tranlation table base register */
 166     uint32_t tea;               /* TLB exception address register */
 167     uint32_t tra;               /* TRAPA exception register */
 168     uint32_t expevt;            /* exception event register */
 169     uint32_t intevt;            /* interrupt event register */
 170
 171     tlb_t itlb[ITLB_SIZE];      /* instruction translation table */
 172     tlb_t utlb[UTLB_SIZE];      /* unified translation table */
 173
 174     uint32_t ldst;
 175
 176     CPU_COMMON
 177
 178     /* Fields from here on are preserved over CPU reset. */
 179     int id;                     /* CPU model */
 180
 181     /* The features that we should emulate. See sh_features above.  */
 182     uint32_t features;
 183
 184     void *intc_handle;
 185     int in_sleep;               /* SR_BL ignored during sleep */
 186     memory_content *movcal_backup;
 187     memory_content **movcal_backup_tail;
 188 } CPUSH4State;
 189
 190 #include "cpu-qom.h"
 191
 192 void sh4_translate_init(void);
 193 SuperHCPU *cpu_sh4_init(const char *cpu_model);
 194 int cpu_sh4_exec(CPUSH4State * s);
 195 int cpu_sh4_signal_handler(int host_signum, void *pinfo,
 196                            void *puc);
 197 int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 198                                 int mmu_idx);
 199
 200 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 201 #if !defined(CONFIG_USER_ONLY)
 202 void cpu_sh4_invalidate_tlb(CPUSH4State *s);
 203 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
 204                                        hwaddr addr);
 205 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
 206                                     uint32_t mem_value);
 207 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
 208                                        hwaddr addr);
 209 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
 210                                     uint32_t mem_value);
 211 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
 212                                        hwaddr addr);
 213 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
 214                                     uint32_t mem_value);
 215 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
 216                                        hwaddr addr);
 217 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
 218                                     uint32_t mem_value);
 219 #endif
 220
 221 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
 222
 223 void cpu_load_tlb(CPUSH4State * env);
 224
 225 static inline CPUSH4State *cpu_init(const char *cpu_model)
 226 {
 227     SuperHCPU *cpu = cpu_sh4_init(cpu_model);
 228     if (cpu == NULL) {
 229         return NULL;
 230     }
 231     return &cpu->env;
 232 }
 233
 234 #define cpu_exec cpu_sh4_exec
 235 #define cpu_gen_code cpu_sh4_gen_code
 236 #define cpu_signal_handler cpu_sh4_signal_handler
 237 #define cpu_list sh4_cpu_list
 238
 239 /* MMU modes definitions */
 240 #define MMU_MODE0_SUFFIX _kernel
 241 #define MMU_MODE1_SUFFIX _user
 242 #define MMU_USER_IDX 1
 243 static inline int cpu_mmu_index (CPUSH4State *env)
 244 {
 245     return (env->sr & SR_MD) == 0 ? 1 : 0;
 246 }
 247
 248 #include "exec/cpu-all.h"
 249
 250 /* Memory access type */
 251 enum {
 252     /* Privilege */
 253     ACCESS_PRIV = 0x01,
 254     /* Direction */
 255     ACCESS_WRITE = 0x02,
 256     /* Type of instruction */
 257     ACCESS_CODE = 0x10,
 258     ACCESS_INT = 0x20
 259 };
 260
 261 /* MMU control register */
 262 #define MMUCR    0x1F000010
 263 #define MMUCR_AT (1<<0)
 264 #define MMUCR_TI (1<<2)
 265 #define MMUCR_SV (1<<8)
 266 #define MMUCR_URC_BITS (6)
 267 #define MMUCR_URC_OFFSET (10)
 268 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
 269 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
 270 static inline int cpu_mmucr_urc (uint32_t mmucr)
 271 {
 272     return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
 273 }
 274
 275 /* PTEH : Page Translation Entry High register */
 276 #define PTEH_ASID_BITS (8)
 277 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
 278 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
 279 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
 280 #define PTEH_VPN_BITS (22)
 281 #define PTEH_VPN_OFFSET (10)
 282 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
 283 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
 284 static inline int cpu_pteh_vpn (uint32_t pteh)
 285 {
 286     return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
 287 }
 288
 289 /* PTEL : Page Translation Entry Low register */
 290 #define PTEL_V        (1 << 8)
 291 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
 292 #define PTEL_C        (1 << 3)
 293 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
 294 #define PTEL_D        (1 << 2)
 295 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
 296 #define PTEL_SH       (1 << 1)
 297 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
 298 #define PTEL_WT       (1 << 0)
 299 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
 300
 301 #define PTEL_SZ_HIGH_OFFSET  (7)
 302 #define PTEL_SZ_HIGH  (1 << PTEL_SZ_HIGH_OFFSET)
 303 #define PTEL_SZ_LOW_OFFSET   (4)
 304 #define PTEL_SZ_LOW   (1 << PTEL_SZ_LOW_OFFSET)
 305 static inline int cpu_ptel_sz (uint32_t ptel)
 306 {
 307     int sz;
 308     sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
 309     sz <<= 1;
 310     sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
 311     return sz;
 312 }
 313
 314 #define PTEL_PPN_BITS (19)
 315 #define PTEL_PPN_OFFSET (10)
 316 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
 317 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
 318 static inline int cpu_ptel_ppn (uint32_t ptel)
 319 {
 320     return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
 321 }
 322
 323 #define PTEL_PR_BITS   (2)
 324 #define PTEL_PR_OFFSET (5)
 325 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
 326 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
 327 static inline int cpu_ptel_pr (uint32_t ptel)
 328 {
 329     return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
 330 }
 331
 332 /* PTEA : Page Translation Entry Assistance register */
 333 #define PTEA_SA_BITS (3)
 334 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
 335 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
 336 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
 337 #define PTEA_TC        (1 << 3)
 338 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
 339
 340 #define TB_FLAG_PENDING_MOVCA  (1 << 4)
 341
 342 static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
 343                                         target_ulong *cs_base, int *flags)
 344 {
 345     *pc = env->pc;
 346     *cs_base = 0;
 347     *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
 348                     | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME))   /* Bits  0- 3 */
 349             | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */
 350             | (env->sr & (SR_MD | SR_RB))                      /* Bits 29-30 */
 351             | (env->sr & SR_FD)                                /* Bit 15 */
 352             | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
 353 }
 354
 355 #include "exec/exec-all.h"
 356
 357 #endif                          /* _CPU_SH4_H */