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Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging
[qemu/ar7.git] / target / mips / tlb_helper.c
blob8d3ea497803232bc1cd6be448621d04cc002ad93
1 /*
2 * MIPS TLB (Translation lookaside buffer) helpers.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/log.h"
26 #include "hw/mips/cpudevs.h"
27
28 enum {
29 TLBRET_XI = -6,
30 TLBRET_RI = -5,
31 TLBRET_DIRTY = -4,
32 TLBRET_INVALID = -3,
33 TLBRET_NOMATCH = -2,
34 TLBRET_BADADDR = -1,
35 TLBRET_MATCH = 0
36 };
37
38 #if !defined(CONFIG_USER_ONLY)
39
40 /* no MMU emulation */
41 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
42 target_ulong address, MMUAccessType access_type)
43 {
44 *physical = address;
45 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
46 return TLBRET_MATCH;
47 }
48
49 /* fixed mapping MMU emulation */
50 int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
51 target_ulong address, MMUAccessType access_type)
52 {
53 if (address <= (int32_t)0x7FFFFFFFUL) {
54 if (!(env->CP0_Status & (1 << CP0St_ERL))) {
55 *physical = address + 0x40000000UL;
56 } else {
57 *physical = address;
58 }
59 } else if (address <= (int32_t)0xBFFFFFFFUL) {
60 *physical = address & 0x1FFFFFFF;
61 } else {
62 *physical = address;
63 }
64
65 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
66 return TLBRET_MATCH;
67 }
68
69 /* MIPS32/MIPS64 R4000-style MMU emulation */
70 int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
71 target_ulong address, MMUAccessType access_type)
72 {
73 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
74 uint32_t MMID = env->CP0_MemoryMapID;
75 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
76 uint32_t tlb_mmid;
77 int i;
78
79 MMID = mi ? MMID : (uint32_t) ASID;
80
81 for (i = 0; i < env->tlb->tlb_in_use; i++) {
82 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
83 /* 1k pages are not supported. */
84 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
85 target_ulong tag = address & ~mask;
86 target_ulong VPN = tlb->VPN & ~mask;
87 #if defined(TARGET_MIPS64)
88 tag &= env->SEGMask;
89 #endif
90
91 /* Check ASID/MMID, virtual page number & size */
92 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
93 if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) {
94 /* TLB match */
95 int n = !!(address & mask & ~(mask >> 1));
96 /* Check access rights */
97 if (!(n ? tlb->V1 : tlb->V0)) {
98 return TLBRET_INVALID;
99 }
100 if (access_type == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
101 return TLBRET_XI;
102 }
103 if (access_type == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
104 return TLBRET_RI;
105 }
106 if (access_type != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
107 *physical = tlb->PFN[n] | (address & (mask >> 1));
108 *prot = PAGE_READ;
109 if (n ? tlb->D1 : tlb->D0) {
110 *prot |= PAGE_WRITE;
111 }
112 if (!(n ? tlb->XI1 : tlb->XI0)) {
113 *prot |= PAGE_EXEC;
114 }
115 return TLBRET_MATCH;
116 }
117 return TLBRET_DIRTY;
118 }
119 }
120 return TLBRET_NOMATCH;
121 }
122
123 static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
124 {
125 env->tlb->nb_tlb = 1;
126 env->tlb->map_address = &no_mmu_map_address;
127 }
128
129 static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
130 {
131 env->tlb->nb_tlb = 1;
132 env->tlb->map_address = &fixed_mmu_map_address;
133 }
134
135 static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
136 {
137 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
138 env->tlb->map_address = &r4k_map_address;
139 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
140 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
141 env->tlb->helper_tlbp = r4k_helper_tlbp;
142 env->tlb->helper_tlbr = r4k_helper_tlbr;
143 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
144 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
145 }
146
147 void mmu_init(CPUMIPSState *env, const mips_def_t *def)
148 {
149 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
150
151 switch (def->mmu_type) {
152 case MMU_TYPE_NONE:
153 no_mmu_init(env, def);
154 break;
155 case MMU_TYPE_R4000:
156 r4k_mmu_init(env, def);
157 break;
158 case MMU_TYPE_FMT:
159 fixed_mmu_init(env, def);
160 break;
161 case MMU_TYPE_R3000:
162 case MMU_TYPE_R6000:
163 case MMU_TYPE_R8000:
164 default:
165 cpu_abort(env_cpu(env), "MMU type not supported\n");
166 }
167 }
168
169 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
170 {
171 /*
172 * Interpret access control mode and mmu_idx.
173 * AdE? TLB?
174 * AM K S U E K S U E
175 * UK 0 0 1 1 0 0 - - 0
176 * MK 1 0 1 1 0 1 - - !eu
177 * MSK 2 0 0 1 0 1 1 - !eu
178 * MUSK 3 0 0 0 0 1 1 1 !eu
179 * MUSUK 4 0 0 0 0 0 1 1 0
180 * USK 5 0 0 1 0 0 0 - 0
181 * - 6 - - - - - - - -
182 * UUSK 7 0 0 0 0 0 0 0 0
183 */
184 int32_t adetlb_mask;
185
186 switch (mmu_idx) {
187 case 3: /* ERL */
188 /* If EU is set, always unmapped */
189 if (eu) {
190 return 0;
191 }
192 /* fall through */
193 case MIPS_HFLAG_KM:
194 /* Never AdE, TLB mapped if AM={1,2,3} */
195 adetlb_mask = 0x70000000;
196 goto check_tlb;
197
198 case MIPS_HFLAG_SM:
199 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
200 adetlb_mask = 0xc0380000;
201 goto check_ade;
202
203 case MIPS_HFLAG_UM:
204 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
205 adetlb_mask = 0xe4180000;
206 /* fall through */
207 check_ade:
208 /* does this AM cause AdE in current execution mode */
209 if ((adetlb_mask << am) < 0) {
210 return TLBRET_BADADDR;
211 }
212 adetlb_mask <<= 8;
213 /* fall through */
214 check_tlb:
215 /* is this AM mapped in current execution mode */
216 return ((adetlb_mask << am) < 0);
217 default:
218 assert(0);
219 return TLBRET_BADADDR;
220 };
221 }
222
223 static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
224 int *prot, target_ulong real_address,
225 MMUAccessType access_type, int mmu_idx,
226 unsigned int am, bool eu,
227 target_ulong segmask,
228 hwaddr physical_base)
229 {
230 int mapped = is_seg_am_mapped(am, eu, mmu_idx);
231
232 if (mapped < 0) {
233 /* is_seg_am_mapped can report TLBRET_BADADDR */
234 return mapped;
235 } else if (mapped) {
236 /* The segment is TLB mapped */
237 return env->tlb->map_address(env, physical, prot, real_address,
238 access_type);
239 } else {
240 /* The segment is unmapped */
241 *physical = physical_base | (real_address & segmask);
242 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
243 return TLBRET_MATCH;
244 }
245 }
246
247 static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
248 int *prot, target_ulong real_address,
249 MMUAccessType access_type, int mmu_idx,
250 uint16_t segctl, target_ulong segmask)
251 {
252 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
253 bool eu = (segctl >> CP0SC_EU) & 1;
254 hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
255
256 return get_seg_physical_address(env, physical, prot, real_address,
257 access_type, mmu_idx, am, eu, segmask,
258 pa & ~(hwaddr)segmask);
259 }
260
261 static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
262 int *prot, target_ulong real_address,
263 MMUAccessType access_type, int mmu_idx)
264 {
265 /* User mode can only access useg/xuseg */
266 #if defined(TARGET_MIPS64)
267 int user_mode = mmu_idx == MIPS_HFLAG_UM;
268 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
269 int kernel_mode = !user_mode && !supervisor_mode;
270 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
271 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
272 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
273 #endif
274 int ret = TLBRET_MATCH;
275 /* effective address (modified for KVM T&E kernel segments) */
276 target_ulong address = real_address;
277
278 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
279 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
280 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
281 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
282 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
283
284 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
285 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
286
287 if (mips_um_ksegs_enabled()) {
288 /* KVM T&E adds guest kernel segments in useg */
289 if (real_address >= KVM_KSEG0_BASE) {
290 if (real_address < KVM_KSEG2_BASE) {
291 /* kseg0 */
292 address += KSEG0_BASE - KVM_KSEG0_BASE;
293 } else if (real_address <= USEG_LIMIT) {
294 /* kseg2/3 */
295 address += KSEG2_BASE - KVM_KSEG2_BASE;
296 }
297 }
298 }
299
300 if (address <= USEG_LIMIT) {
301 /* useg */
302 uint16_t segctl;
303
304 if (address >= 0x40000000UL) {
305 segctl = env->CP0_SegCtl2;
306 } else {
307 segctl = env->CP0_SegCtl2 >> 16;
308 }
309 ret = get_segctl_physical_address(env, physical, prot,
310 real_address, access_type,
311 mmu_idx, segctl, 0x3FFFFFFF);
312 #if defined(TARGET_MIPS64)
313 } else if (address < 0x4000000000000000ULL) {
314 /* xuseg */
315 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
316 ret = env->tlb->map_address(env, physical, prot,
317 real_address, access_type);
318 } else {
319 ret = TLBRET_BADADDR;
320 }
321 } else if (address < 0x8000000000000000ULL) {
322 /* xsseg */
323 if ((supervisor_mode || kernel_mode) &&
324 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
325 ret = env->tlb->map_address(env, physical, prot,
326 real_address, access_type);
327 } else {
328 ret = TLBRET_BADADDR;
329 }
330 } else if (address < 0xC000000000000000ULL) {
331 /* xkphys */
332 if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
333 /* KX/SX/UX bit to check for each xkphys EVA access mode */
334 static const uint8_t am_ksux[8] = {
335 [CP0SC_AM_UK] = (1u << CP0St_KX),
336 [CP0SC_AM_MK] = (1u << CP0St_KX),
337 [CP0SC_AM_MSK] = (1u << CP0St_SX),
338 [CP0SC_AM_MUSK] = (1u << CP0St_UX),
339 [CP0SC_AM_MUSUK] = (1u << CP0St_UX),
340 [CP0SC_AM_USK] = (1u << CP0St_SX),
341 [6] = (1u << CP0St_KX),
342 [CP0SC_AM_UUSK] = (1u << CP0St_UX),
343 };
344 unsigned int am = CP0SC_AM_UK;
345 unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
346
347 if (xr & (1 << ((address >> 59) & 0x7))) {
348 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
349 }
350 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */
351 if (env->CP0_Status & am_ksux[am]) {
352 ret = get_seg_physical_address(env, physical, prot,
353 real_address, access_type,
354 mmu_idx, am, false, env->PAMask,
355 0);
356 } else {
357 ret = TLBRET_BADADDR;
358 }
359 } else {
360 ret = TLBRET_BADADDR;
361 }
362 } else if (address < 0xFFFFFFFF80000000ULL) {
363 /* xkseg */
364 if (kernel_mode && KX &&
365 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
366 ret = env->tlb->map_address(env, physical, prot,
367 real_address, access_type);
368 } else {
369 ret = TLBRET_BADADDR;
370 }
371 #endif
372 } else if (address < KSEG1_BASE) {
373 /* kseg0 */
374 ret = get_segctl_physical_address(env, physical, prot, real_address,
375 access_type, mmu_idx,
376 env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
377 } else if (address < KSEG2_BASE) {
378 /* kseg1 */
379 ret = get_segctl_physical_address(env, physical, prot, real_address,
380 access_type, mmu_idx,
381 env->CP0_SegCtl1, 0x1FFFFFFF);
382 } else if (address < KSEG3_BASE) {
383 /* sseg (kseg2) */
384 ret = get_segctl_physical_address(env, physical, prot, real_address,
385 access_type, mmu_idx,
386 env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
387 } else {
388 /*
389 * kseg3
390 * XXX: debug segment is not emulated
391 */
392 ret = get_segctl_physical_address(env, physical, prot, real_address,
393 access_type, mmu_idx,
394 env->CP0_SegCtl0, 0x1FFFFFFF);
395 }
396 return ret;
397 }
398
399 void cpu_mips_tlb_flush(CPUMIPSState *env)
400 {
401 /* Flush qemu's TLB and discard all shadowed entries. */
402 tlb_flush(env_cpu(env));
403 env->tlb->tlb_in_use = env->tlb->nb_tlb;
404 }
405
406 #endif /* !CONFIG_USER_ONLY */
407
408 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
409 MMUAccessType access_type, int tlb_error)
410 {
411 CPUState *cs = env_cpu(env);
412 int exception = 0, error_code = 0;
413
414 if (access_type == MMU_INST_FETCH) {
415 error_code |= EXCP_INST_NOTAVAIL;
416 }
417
418 switch (tlb_error) {
419 default:
420 case TLBRET_BADADDR:
421 /* Reference to kernel address from user mode or supervisor mode */
422 /* Reference to supervisor address from user mode */
423 if (access_type == MMU_DATA_STORE) {
424 exception = EXCP_AdES;
425 } else {
426 exception = EXCP_AdEL;
427 }
428 break;
429 case TLBRET_NOMATCH:
430 /* No TLB match for a mapped address */
431 if (access_type == MMU_DATA_STORE) {
432 exception = EXCP_TLBS;
433 } else {
434 exception = EXCP_TLBL;
435 }
436 error_code |= EXCP_TLB_NOMATCH;
437 break;
438 case TLBRET_INVALID:
439 /* TLB match with no valid bit */
440 if (access_type == MMU_DATA_STORE) {
441 exception = EXCP_TLBS;
442 } else {
443 exception = EXCP_TLBL;
444 }
445 break;
446 case TLBRET_DIRTY:
447 /* TLB match but 'D' bit is cleared */
448 exception = EXCP_LTLBL;
449 break;
450 case TLBRET_XI:
451 /* Execute-Inhibit Exception */
452 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
453 exception = EXCP_TLBXI;
454 } else {
455 exception = EXCP_TLBL;
456 }
457 break;
458 case TLBRET_RI:
459 /* Read-Inhibit Exception */
460 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
461 exception = EXCP_TLBRI;
462 } else {
463 exception = EXCP_TLBL;
464 }
465 break;
466 }
467 /* Raise exception */
468 if (!(env->hflags & MIPS_HFLAG_DM)) {
469 env->CP0_BadVAddr = address;
470 }
471 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
472 ((address >> 9) & 0x007ffff0);
473 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
474 (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
475 (address & (TARGET_PAGE_MASK << 1));
476 #if defined(TARGET_MIPS64)
477 env->CP0_EntryHi &= env->SEGMask;
478 env->CP0_XContext =
479 (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */
480 (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */
481 (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */
482 #endif
483 cs->exception_index = exception;
484 env->error_code = error_code;
485 }
486
487 #if !defined(CONFIG_USER_ONLY)
488
489 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
490 {
491 MIPSCPU *cpu = MIPS_CPU(cs);
492 CPUMIPSState *env = &cpu->env;
493 hwaddr phys_addr;
494 int prot;
495
496 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
497 cpu_mmu_index(env, false)) != 0) {
498 return -1;
499 }
500 return phys_addr;
501 }
502
503 #if !defined(TARGET_MIPS64)
504
505 /*
506 * Perform hardware page table walk
507 *
508 * Memory accesses are performed using the KERNEL privilege level.
509 * Synchronous exceptions detected on memory accesses cause a silent exit
510 * from page table walking, resulting in a TLB or XTLB Refill exception.
511 *
512 * Implementations are not required to support page table walk memory
513 * accesses from mapped memory regions. When an unsupported access is
514 * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
515 * exception.
516 *
517 * Note that if an exception is caused by AddressTranslation or LoadMemory
518 * functions, the exception is not taken, a silent exit is taken,
519 * resulting in a TLB or XTLB Refill exception.
520 */
521
522 static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size,
523 uint64_t *pte)
524 {
525 if ((vaddr & ((entry_size >> 3) - 1)) != 0) {
526 return false;
527 }
528 if (entry_size == 64) {
529 *pte = cpu_ldq_code(env, vaddr);
530 } else {
531 *pte = cpu_ldl_code(env, vaddr);
532 }
533 return true;
534 }
535
536 static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry,
537 int entry_size, int ptei)
538 {
539 uint64_t result = entry;
540 uint64_t rixi;
541 if (ptei > entry_size) {
542 ptei -= 32;
543 }
544 result >>= (ptei - 2);
545 rixi = result & 3;
546 result >>= 2;
547 result |= rixi << CP0EnLo_XI;
548 return result;
549 }
550
551 static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
552 int directory_index, bool *huge_page, bool *hgpg_directory_hit,
553 uint64_t *pw_entrylo0, uint64_t *pw_entrylo1)
554 {
555 int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
556 int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
557 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
558 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
559 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
560 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
561 int directory_shift = (ptew > 1) ? -1 :
562 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
563 int leaf_shift = (ptew > 1) ? -1 :
564 (ptew == 1) ? native_shift + 1 : native_shift;
565 uint32_t direntry_size = 1 << (directory_shift + 3);
566 uint32_t leafentry_size = 1 << (leaf_shift + 3);
567 uint64_t entry;
568 uint64_t paddr;
569 int prot;
570 uint64_t lsb = 0;
571 uint64_t w = 0;
572
573 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD,
574 cpu_mmu_index(env, false)) !=
575 TLBRET_MATCH) {
576 /* wrong base address */
577 return 0;
578 }
579 if (!get_pte(env, *vaddr, direntry_size, &entry)) {
580 return 0;
581 }
582
583 if ((entry & (1 << psn)) && hugepg) {
584 *huge_page = true;
585 *hgpg_directory_hit = true;
586 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
587 w = directory_index - 1;
588 if (directory_index & 0x1) {
589 /* Generate adjacent page from same PTE for odd TLB page */
590 lsb = (1 << w) >> 6;
591 *pw_entrylo0 = entry & ~lsb; /* even page */
592 *pw_entrylo1 = entry | lsb; /* odd page */
593 } else if (dph) {
594 int oddpagebit = 1 << leaf_shift;
595 uint64_t vaddr2 = *vaddr ^ oddpagebit;
596 if (*vaddr & oddpagebit) {
597 *pw_entrylo1 = entry;
598 } else {
599 *pw_entrylo0 = entry;
600 }
601 if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD,
602 cpu_mmu_index(env, false)) !=
603 TLBRET_MATCH) {
604 return 0;
605 }
606 if (!get_pte(env, vaddr2, leafentry_size, &entry)) {
607 return 0;
608 }
609 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew);
610 if (*vaddr & oddpagebit) {
611 *pw_entrylo0 = entry;
612 } else {
613 *pw_entrylo1 = entry;
614 }
615 } else {
616 return 0;
617 }
618 return 1;
619 } else {
620 *vaddr = entry;
621 return 2;
622 }
623 }
624
625 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
626 int mmu_idx)
627 {
628 int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F;
629 int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F;
630 int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F;
631 int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F;
632 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
633
634 /* Initial values */
635 bool huge_page = false;
636 bool hgpg_bdhit = false;
637 bool hgpg_gdhit = false;
638 bool hgpg_udhit = false;
639 bool hgpg_mdhit = false;
640
641 int32_t pw_pagemask = 0;
642 target_ulong pw_entryhi = 0;
643 uint64_t pw_entrylo0 = 0;
644 uint64_t pw_entrylo1 = 0;
645
646 /* Native pointer size */
647 /*For the 32-bit architectures, this bit is fixed to 0.*/
648 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
649
650 /* Indices from PWField */
651 int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F;
652 int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F;
653 int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F;
654 int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F;
655 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
656
657 /* Indices computed from faulting address */
658 int gindex = (address >> pf_gdw) & ((1 << gdw) - 1);
659 int uindex = (address >> pf_udw) & ((1 << udw) - 1);
660 int mindex = (address >> pf_mdw) & ((1 << mdw) - 1);
661 int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1);
662
663 /* Other HTW configs */
664 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
665
666 /* HTW Shift values (depend on entry size) */
667 int directory_shift = (ptew > 1) ? -1 :
668 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
669 int leaf_shift = (ptew > 1) ? -1 :
670 (ptew == 1) ? native_shift + 1 : native_shift;
671
672 /* Offsets into tables */
673 int goffset = gindex << directory_shift;
674 int uoffset = uindex << directory_shift;
675 int moffset = mindex << directory_shift;
676 int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
677 int ptoffset1 = ptoffset0 | (1 << (leaf_shift));
678
679 uint32_t leafentry_size = 1 << (leaf_shift + 3);
680
681 /* Starting address - Page Table Base */
682 uint64_t vaddr = env->CP0_PWBase;
683
684 uint64_t dir_entry;
685 uint64_t paddr;
686 int prot;
687 int m;
688
689 if (!(env->CP0_Config3 & (1 << CP0C3_PW))) {
690 /* walker is unimplemented */
691 return false;
692 }
693 if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) {
694 /* walker is disabled */
695 return false;
696 }
697 if (!(gdw > 0 || udw > 0 || mdw > 0)) {
698 /* no structure to walk */
699 return false;
700 }
701 if ((directory_shift == -1) || (leaf_shift == -1)) {
702 return false;
703 }
704
705 /* Global Directory */
706 if (gdw > 0) {
707 vaddr |= goffset;
708 switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit,
709 &pw_entrylo0, &pw_entrylo1))
710 {
711 case 0:
712 return false;
713 case 1:
714 goto refill;
715 case 2:
716 default:
717 break;
718 }
719 }
720
721 /* Upper directory */
722 if (udw > 0) {
723 vaddr |= uoffset;
724 switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit,
725 &pw_entrylo0, &pw_entrylo1))
726 {
727 case 0:
728 return false;
729 case 1:
730 goto refill;
731 case 2:
732 default:
733 break;
734 }
735 }
736
737 /* Middle directory */
738 if (mdw > 0) {
739 vaddr |= moffset;
740 switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit,
741 &pw_entrylo0, &pw_entrylo1))
742 {
743 case 0:
744 return false;
745 case 1:
746 goto refill;
747 case 2:
748 default:
749 break;
750 }
751 }
752
753 /* Leaf Level Page Table - First half of PTE pair */
754 vaddr |= ptoffset0;
755 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
756 cpu_mmu_index(env, false)) !=
757 TLBRET_MATCH) {
758 return false;
759 }
760 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
761 return false;
762 }
763 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
764 pw_entrylo0 = dir_entry;
765
766 /* Leaf Level Page Table - Second half of PTE pair */
767 vaddr |= ptoffset1;
768 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
769 cpu_mmu_index(env, false)) !=
770 TLBRET_MATCH) {
771 return false;
772 }
773 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
774 return false;
775 }
776 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew);
777 pw_entrylo1 = dir_entry;
778
779 refill:
780
781 m = (1 << pf_ptw) - 1;
782
783 if (huge_page) {
784 switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 |
785 hgpg_mdhit)
786 {
787 case 4:
788 m = (1 << pf_gdw) - 1;
789 if (pf_gdw & 1) {
790 m >>= 1;
791 }
792 break;
793 case 2:
794 m = (1 << pf_udw) - 1;
795 if (pf_udw & 1) {
796 m >>= 1;
797 }
798 break;
799 case 1:
800 m = (1 << pf_mdw) - 1;
801 if (pf_mdw & 1) {
802 m >>= 1;
803 }
804 break;
805 }
806 }
807 pw_pagemask = m >> TARGET_PAGE_BITS_MIN;
808 update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask);
809 pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
810 {
811 target_ulong tmp_entryhi = env->CP0_EntryHi;
812 int32_t tmp_pagemask = env->CP0_PageMask;
813 uint64_t tmp_entrylo0 = env->CP0_EntryLo0;
814 uint64_t tmp_entrylo1 = env->CP0_EntryLo1;
815
816 env->CP0_EntryHi = pw_entryhi;
817 env->CP0_PageMask = pw_pagemask;
818 env->CP0_EntryLo0 = pw_entrylo0;
819 env->CP0_EntryLo1 = pw_entrylo1;
820
821 /*
822 * The hardware page walker inserts a page into the TLB in a manner
823 * identical to a TLBWR instruction as executed by the software refill
824 * handler.
825 */
826 r4k_helper_tlbwr(env);
827
828 env->CP0_EntryHi = tmp_entryhi;
829 env->CP0_PageMask = tmp_pagemask;
830 env->CP0_EntryLo0 = tmp_entrylo0;
831 env->CP0_EntryLo1 = tmp_entrylo1;
832 }
833 return true;
834 }
835 #endif
836 #endif /* !CONFIG_USER_ONLY */
837
838 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
839 MMUAccessType access_type, int mmu_idx,
840 bool probe, uintptr_t retaddr)
841 {
842 MIPSCPU *cpu = MIPS_CPU(cs);
843 CPUMIPSState *env = &cpu->env;
844 #if !defined(CONFIG_USER_ONLY)
845 hwaddr physical;
846 int prot;
847 #endif
848 int ret = TLBRET_BADADDR;
849
850 /* data access */
851 #if !defined(CONFIG_USER_ONLY)
852 /* XXX: put correct access by using cpu_restore_state() correctly */
853 ret = get_physical_address(env, &physical, &prot, address,
854 access_type, mmu_idx);
855 switch (ret) {
856 case TLBRET_MATCH:
857 qemu_log_mask(CPU_LOG_MMU,
858 "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
859 " prot %d\n", __func__, address, physical, prot);
860 break;
861 default:
862 qemu_log_mask(CPU_LOG_MMU,
863 "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
864 ret);
865 break;
866 }
867 if (ret == TLBRET_MATCH) {
868 tlb_set_page(cs, address & TARGET_PAGE_MASK,
869 physical & TARGET_PAGE_MASK, prot,
870 mmu_idx, TARGET_PAGE_SIZE);
871 return true;
872 }
873 #if !defined(TARGET_MIPS64)
874 if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
875 /*
876 * Memory reads during hardware page table walking are performed
877 * as if they were kernel-mode load instructions.
878 */
879 int mode = (env->hflags & MIPS_HFLAG_KSU);
880 bool ret_walker;
881 env->hflags &= ~MIPS_HFLAG_KSU;
882 ret_walker = page_table_walk_refill(env, address, mmu_idx);
883 env->hflags |= mode;
884 if (ret_walker) {
885 ret = get_physical_address(env, &physical, &prot, address,
886 access_type, mmu_idx);
887 if (ret == TLBRET_MATCH) {
888 tlb_set_page(cs, address & TARGET_PAGE_MASK,
889 physical & TARGET_PAGE_MASK, prot,
890 mmu_idx, TARGET_PAGE_SIZE);
891 return true;
892 }
893 }
894 }
895 #endif
896 if (probe) {
897 return false;
898 }
899 #endif
900
901 raise_mmu_exception(env, address, access_type, ret);
902 do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
903 }
904
905 #ifndef CONFIG_USER_ONLY
906 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
907 MMUAccessType access_type)
908 {
909 hwaddr physical;
910 int prot;
911 int ret = 0;
912
913 /* data access */
914 ret = get_physical_address(env, &physical, &prot, address, access_type,
915 cpu_mmu_index(env, false));
916 if (ret != TLBRET_MATCH) {
917 raise_mmu_exception(env, address, access_type, ret);
918 return -1LL;
919 } else {
920 return physical;
921 }
922 }
923
924 static void set_hflags_for_handler(CPUMIPSState *env)
925 {
926 /* Exception handlers are entered in 32-bit mode. */
927 env->hflags &= ~(MIPS_HFLAG_M16);
928 /* ...except that microMIPS lets you choose. */
929 if (env->insn_flags & ASE_MICROMIPS) {
930 env->hflags |= (!!(env->CP0_Config3 &
931 (1 << CP0C3_ISA_ON_EXC))
932 << MIPS_HFLAG_M16_SHIFT);
933 }
934 }
935
936 static inline void set_badinstr_registers(CPUMIPSState *env)
937 {
938 if (env->insn_flags & ISA_NANOMIPS32) {
939 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
940 uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
941 if ((instr & 0x10000000) == 0) {
942 instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
943 }
944 env->CP0_BadInstr = instr;
945
946 if ((instr & 0xFC000000) == 0x60000000) {
947 instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
948 env->CP0_BadInstrX = instr;
949 }
950 }
951 return;
952 }
953
954 if (env->hflags & MIPS_HFLAG_M16) {
955 /* TODO: add BadInstr support for microMIPS */
956 return;
957 }
958 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
959 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
960 }
961 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
962 (env->hflags & MIPS_HFLAG_BMASK)) {
963 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
964 }
965 }
966
967 #endif /* !CONFIG_USER_ONLY */
968
969 void mips_cpu_do_interrupt(CPUState *cs)
970 {
971 #if !defined(CONFIG_USER_ONLY)
972 MIPSCPU *cpu = MIPS_CPU(cs);
973 CPUMIPSState *env = &cpu->env;
974 bool update_badinstr = 0;
975 target_ulong offset;
976 int cause = -1;
977
978 if (qemu_loglevel_mask(CPU_LOG_INT)
979 && cs->exception_index != EXCP_EXT_INTERRUPT) {
980 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
981 " %s exception\n",
982 __func__, env->active_tc.PC, env->CP0_EPC,
983 mips_exception_name(cs->exception_index));
984 }
985 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
986 (env->hflags & MIPS_HFLAG_DM)) {
987 cs->exception_index = EXCP_DINT;
988 }
989 offset = 0x180;
990 switch (cs->exception_index) {
991 case EXCP_DSS:
992 env->CP0_Debug |= 1 << CP0DB_DSS;
993 /*
994 * Debug single step cannot be raised inside a delay slot and
995 * resume will always occur on the next instruction
996 * (but we assume the pc has always been updated during
997 * code translation).
998 */
999 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
1000 goto enter_debug_mode;
1001 case EXCP_DINT:
1002 env->CP0_Debug |= 1 << CP0DB_DINT;
1003 goto set_DEPC;
1004 case EXCP_DIB:
1005 env->CP0_Debug |= 1 << CP0DB_DIB;
1006 goto set_DEPC;
1007 case EXCP_DBp:
1008 env->CP0_Debug |= 1 << CP0DB_DBp;
1009 /* Setup DExcCode - SDBBP instruction */
1010 env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |
1011 (9 << CP0DB_DEC);
1012 goto set_DEPC;
1013 case EXCP_DDBS:
1014 env->CP0_Debug |= 1 << CP0DB_DDBS;
1015 goto set_DEPC;
1016 case EXCP_DDBL:
1017 env->CP0_Debug |= 1 << CP0DB_DDBL;
1018 set_DEPC:
1019 env->CP0_DEPC = exception_resume_pc(env);
1020 env->hflags &= ~MIPS_HFLAG_BMASK;
1021 enter_debug_mode:
1022 if (env->insn_flags & ISA_MIPS3) {
1023 env->hflags |= MIPS_HFLAG_64;
1024 if (!(env->insn_flags & ISA_MIPS_R6) ||
1025 env->CP0_Status & (1 << CP0St_KX)) {
1026 env->hflags &= ~MIPS_HFLAG_AWRAP;
1027 }
1028 }
1029 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
1030 env->hflags &= ~(MIPS_HFLAG_KSU);
1031 /* EJTAG probe trap enable is not implemented... */
1032 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1033 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1034 }
1035 env->active_tc.PC = env->exception_base + 0x480;
1036 set_hflags_for_handler(env);
1037 break;
1038 case EXCP_RESET:
1039 cpu_reset(CPU(cpu));
1040 break;
1041 case EXCP_SRESET:
1042 env->CP0_Status |= (1 << CP0St_SR);
1043 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
1044 goto set_error_EPC;
1045 case EXCP_NMI:
1046 env->CP0_Status |= (1 << CP0St_NMI);
1047 set_error_EPC:
1048 env->CP0_ErrorEPC = exception_resume_pc(env);
1049 env->hflags &= ~MIPS_HFLAG_BMASK;
1050 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
1051 if (env->insn_flags & ISA_MIPS3) {
1052 env->hflags |= MIPS_HFLAG_64;
1053 if (!(env->insn_flags & ISA_MIPS_R6) ||
1054 env->CP0_Status & (1 << CP0St_KX)) {
1055 env->hflags &= ~MIPS_HFLAG_AWRAP;
1056 }
1057 }
1058 env->hflags |= MIPS_HFLAG_CP0;
1059 env->hflags &= ~(MIPS_HFLAG_KSU);
1060 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1061 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1062 }
1063 env->active_tc.PC = env->exception_base;
1064 set_hflags_for_handler(env);
1065 break;
1066 case EXCP_EXT_INTERRUPT:
1067 cause = 0;
1068 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
1069 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
1070
1071 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
1072 offset = 0x200;
1073 } else {
1074 uint32_t vector = 0;
1075 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
1076
1077 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
1078 /*
1079 * For VEIC mode, the external interrupt controller feeds
1080 * the vector through the CP0Cause IP lines.
1081 */
1082 vector = pending;
1083 } else {
1084 /*
1085 * Vectored Interrupts
1086 * Mask with Status.IM7-IM0 to get enabled interrupts.
1087 */
1088 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
1089 /* Find the highest-priority interrupt. */
1090 while (pending >>= 1) {
1091 vector++;
1092 }
1093 }
1094 offset = 0x200 + (vector * (spacing << 5));
1095 }
1096 }
1097 goto set_EPC;
1098 case EXCP_LTLBL:
1099 cause = 1;
1100 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1101 goto set_EPC;
1102 case EXCP_TLBL:
1103 cause = 2;
1104 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1105 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1106 !(env->CP0_Status & (1 << CP0St_EXL))) {
1107 #if defined(TARGET_MIPS64)
1108 int R = env->CP0_BadVAddr >> 62;
1109 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1110 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1111
1112 if ((R != 0 || UX) && (R != 3 || KX) &&
1113 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1114 offset = 0x080;
1115 } else {
1116 #endif
1117 offset = 0x000;
1118 #if defined(TARGET_MIPS64)
1119 }
1120 #endif
1121 }
1122 goto set_EPC;
1123 case EXCP_TLBS:
1124 cause = 3;
1125 update_badinstr = 1;
1126 if ((env->error_code & EXCP_TLB_NOMATCH) &&
1127 !(env->CP0_Status & (1 << CP0St_EXL))) {
1128 #if defined(TARGET_MIPS64)
1129 int R = env->CP0_BadVAddr >> 62;
1130 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
1131 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
1132
1133 if ((R != 0 || UX) && (R != 3 || KX) &&
1134 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
1135 offset = 0x080;
1136 } else {
1137 #endif
1138 offset = 0x000;
1139 #if defined(TARGET_MIPS64)
1140 }
1141 #endif
1142 }
1143 goto set_EPC;
1144 case EXCP_AdEL:
1145 cause = 4;
1146 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
1147 goto set_EPC;
1148 case EXCP_AdES:
1149 cause = 5;
1150 update_badinstr = 1;
1151 goto set_EPC;
1152 case EXCP_IBE:
1153 cause = 6;
1154 goto set_EPC;
1155 case EXCP_DBE:
1156 cause = 7;
1157 goto set_EPC;
1158 case EXCP_SYSCALL:
1159 cause = 8;
1160 update_badinstr = 1;
1161 goto set_EPC;
1162 case EXCP_BREAK:
1163 cause = 9;
1164 update_badinstr = 1;
1165 goto set_EPC;
1166 case EXCP_RI:
1167 cause = 10;
1168 update_badinstr = 1;
1169 goto set_EPC;
1170 case EXCP_CpU:
1171 cause = 11;
1172 update_badinstr = 1;
1173 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
1174 (env->error_code << CP0Ca_CE);
1175 goto set_EPC;
1176 case EXCP_OVERFLOW:
1177 cause = 12;
1178 update_badinstr = 1;
1179 goto set_EPC;
1180 case EXCP_TRAP:
1181 cause = 13;
1182 update_badinstr = 1;
1183 goto set_EPC;
1184 case EXCP_MSAFPE:
1185 cause = 14;
1186 update_badinstr = 1;
1187 goto set_EPC;
1188 case EXCP_FPE:
1189 cause = 15;
1190 update_badinstr = 1;
1191 goto set_EPC;
1192 case EXCP_C2E:
1193 cause = 18;
1194 goto set_EPC;
1195 case EXCP_TLBRI:
1196 cause = 19;
1197 update_badinstr = 1;
1198 goto set_EPC;
1199 case EXCP_TLBXI:
1200 cause = 20;
1201 goto set_EPC;
1202 case EXCP_MSADIS:
1203 cause = 21;
1204 update_badinstr = 1;
1205 goto set_EPC;
1206 case EXCP_MDMX:
1207 cause = 22;
1208 goto set_EPC;
1209 case EXCP_DWATCH:
1210 cause = 23;
1211 /* XXX: TODO: manage deferred watch exceptions */
1212 goto set_EPC;
1213 case EXCP_MCHECK:
1214 cause = 24;
1215 goto set_EPC;
1216 case EXCP_THREAD:
1217 cause = 25;
1218 goto set_EPC;
1219 case EXCP_DSPDIS:
1220 cause = 26;
1221 goto set_EPC;
1222 case EXCP_CACHE:
1223 cause = 30;
1224 offset = 0x100;
1225 set_EPC:
1226 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
1227 env->CP0_EPC = exception_resume_pc(env);
1228 if (update_badinstr) {
1229 set_badinstr_registers(env);
1230 }
1231 if (env->hflags & MIPS_HFLAG_BMASK) {
1232 env->CP0_Cause |= (1U << CP0Ca_BD);
1233 } else {
1234 env->CP0_Cause &= ~(1U << CP0Ca_BD);
1235 }
1236 env->CP0_Status |= (1 << CP0St_EXL);
1237 if (env->insn_flags & ISA_MIPS3) {
1238 env->hflags |= MIPS_HFLAG_64;
1239 if (!(env->insn_flags & ISA_MIPS_R6) ||
1240 env->CP0_Status & (1 << CP0St_KX)) {
1241 env->hflags &= ~MIPS_HFLAG_AWRAP;
1242 }
1243 }
1244 env->hflags |= MIPS_HFLAG_CP0;
1245 env->hflags &= ~(MIPS_HFLAG_KSU);
1246 }
1247 env->hflags &= ~MIPS_HFLAG_BMASK;
1248 if (env->CP0_Status & (1 << CP0St_BEV)) {
1249 env->active_tc.PC = env->exception_base + 0x200;
1250 } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
1251 env->CP0_Config5 & (1 << CP0C5_CV))) {
1252 /* Force KSeg1 for cache errors */
1253 env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
1254 } else {
1255 env->active_tc.PC = env->CP0_EBase & ~0xfff;
1256 }
1257
1258 env->active_tc.PC += offset;
1259 set_hflags_for_handler(env);
1260 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |
1261 (cause << CP0Ca_EC);
1262 break;
1263 default:
1264 abort();
1265 }
1266 if (qemu_loglevel_mask(CPU_LOG_INT)
1267 && cs->exception_index != EXCP_EXT_INTERRUPT) {
1268 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
1269 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
1270 __func__, env->active_tc.PC, env->CP0_EPC, cause,
1271 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
1272 env->CP0_DEPC);
1273 }
1274 #endif
1275 cs->exception_index = EXCP_NONE;
1276 }
1277
1278 #if !defined(CONFIG_USER_ONLY)
1279 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
1280 {
1281 CPUState *cs = env_cpu(env);
1282 r4k_tlb_t *tlb;
1283 target_ulong addr;
1284 target_ulong end;
1285 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
1286 uint32_t MMID = env->CP0_MemoryMapID;
1287 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
1288 uint32_t tlb_mmid;
1289 target_ulong mask;
1290
1291 MMID = mi ? MMID : (uint32_t) ASID;
1292
1293 tlb = &env->tlb->mmu.r4k.tlb[idx];
1294 /*
1295 * The qemu TLB is flushed when the ASID/MMID changes, so no need to
1296 * flush these entries again.
1297 */
1298 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID;
1299 if (tlb->G == 0 && tlb_mmid != MMID) {
1300 return;
1301 }
1302
1303 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
1304 /*
1305 * For tlbwr, we can shadow the discarded entry into
1306 * a new (fake) TLB entry, as long as the guest can not
1307 * tell that it's there.
1308 */
1309 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
1310 env->tlb->tlb_in_use++;
1311 return;
1312 }
1313
1314 /* 1k pages are not supported. */
1315 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1316 if (tlb->V0) {
1317 addr = tlb->VPN & ~mask;
1318 #if defined(TARGET_MIPS64)
1319 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1320 addr |= 0x3FFFFF0000000000ULL;
1321 }
1322 #endif
1323 end = addr | (mask >> 1);
1324 while (addr < end) {
1325 tlb_flush_page(cs, addr);
1326 addr += TARGET_PAGE_SIZE;
1327 }
1328 }
1329 if (tlb->V1) {
1330 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
1331 #if defined(TARGET_MIPS64)
1332 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1333 addr |= 0x3FFFFF0000000000ULL;
1334 }
1335 #endif
1336 end = addr | mask;
1337 while (addr - 1 < end) {
1338 tlb_flush_page(cs, addr);
1339 addr += TARGET_PAGE_SIZE;
1340 }
1341 }
1342 }
1343 #endif /* !CONFIG_USER_ONLY */
AR7 emulation for QEMU