target/mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/cutils.h"
  23 #include "qemu/qemu-print.h"
  24 #include "qapi/error.h"
  25 #include "cpu.h"
  26 #include "internal.h"
  27 #include "kvm_mips.h"
  28 #include "qemu/module.h"
  29 #include "sysemu/kvm.h"
  30 #include "sysemu/qtest.h"
  31 #include "exec/exec-all.h"
  32 #include "hw/qdev-properties.h"
  33 #include "hw/qdev-clock.h"
  34 #include "semihosting/semihost.h"
  35 #include "qapi/qapi-commands-machine-target.h"
  36 #include "fpu_helper.h"
  37
  38 #if !defined(CONFIG_USER_ONLY)
  39
  40 /* Called for updates to CP0_Status.  */
  41 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
  42 {
  43     int32_t tcstatus, *tcst;
  44     uint32_t v = cpu->CP0_Status;
  45     uint32_t cu, mx, asid, ksu;
  46     uint32_t mask = ((1 << CP0TCSt_TCU3)
  47                        | (1 << CP0TCSt_TCU2)
  48                        | (1 << CP0TCSt_TCU1)
  49                        | (1 << CP0TCSt_TCU0)
  50                        | (1 << CP0TCSt_TMX)
  51                        | (3 << CP0TCSt_TKSU)
  52                        | (0xff << CP0TCSt_TASID));
  53
  54     cu = (v >> CP0St_CU0) & 0xf;
  55     mx = (v >> CP0St_MX) & 0x1;
  56     ksu = (v >> CP0St_KSU) & 0x3;
  57     asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
  58
  59     tcstatus = cu << CP0TCSt_TCU0;
  60     tcstatus |= mx << CP0TCSt_TMX;
  61     tcstatus |= ksu << CP0TCSt_TKSU;
  62     tcstatus |= asid;
  63
  64     if (tc == cpu->current_tc) {
  65         tcst = &cpu->active_tc.CP0_TCStatus;
  66     } else {
  67         tcst = &cpu->tcs[tc].CP0_TCStatus;
  68     }
  69
  70     *tcst &= ~mask;
  71     *tcst |= tcstatus;
  72     compute_hflags(cpu);
  73 }
  74
  75 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
  76 {
  77     uint32_t mask = env->CP0_Status_rw_bitmask;
  78     target_ulong old = env->CP0_Status;
  79
  80     if (env->insn_flags & ISA_MIPS_R6) {
  81         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
  82 #if defined(TARGET_MIPS64)
  83         uint32_t ksux = (1 << CP0St_KX) & val;
  84         ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
  85         ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
  86         val = (val & ~(7 << CP0St_UX)) | ksux;
  87 #endif
  88         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
  89             mask &= ~(3 << CP0St_KSU);
  90         }
  91         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
  92     }
  93
  94     env->CP0_Status = (old & ~mask) | (val & mask);
  95 #if defined(TARGET_MIPS64)
  96     if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
  97         /* Access to at least one of the 64-bit segments has been disabled */
  98         tlb_flush(env_cpu(env));
  99     }
 100 #endif
 101     if (ase_mt_available(env)) {
 102         sync_c0_status(env, env, env->current_tc);
 103     } else {
 104         compute_hflags(env);
 105     }
 106 }
 107
 108 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
 109 {
 110     uint32_t mask = 0x00C00300;
 111     uint32_t old = env->CP0_Cause;
 112     int i;
 113
 114     if (env->insn_flags & ISA_MIPS_R2) {
 115         mask |= 1 << CP0Ca_DC;
 116     }
 117     if (env->insn_flags & ISA_MIPS_R6) {
 118         mask &= ~((1 << CP0Ca_WP) & val);
 119     }
 120
 121     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
 122
 123     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
 124         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
 125             cpu_mips_stop_count(env);
 126         } else {
 127             cpu_mips_start_count(env);
 128         }
 129     }
 130
 131     /* Set/reset software interrupts */
 132     for (i = 0 ; i < 2 ; i++) {
 133         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
 134             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
 135         }
 136     }
 137 }
 138
 139 #endif /* !CONFIG_USER_ONLY */
 140
 141 static const char * const excp_names[EXCP_LAST + 1] = {
 142     [EXCP_RESET] = "reset",
 143     [EXCP_SRESET] = "soft reset",
 144     [EXCP_DSS] = "debug single step",
 145     [EXCP_DINT] = "debug interrupt",
 146     [EXCP_NMI] = "non-maskable interrupt",
 147     [EXCP_MCHECK] = "machine check",
 148     [EXCP_EXT_INTERRUPT] = "interrupt",
 149     [EXCP_DFWATCH] = "deferred watchpoint",
 150     [EXCP_DIB] = "debug instruction breakpoint",
 151     [EXCP_IWATCH] = "instruction fetch watchpoint",
 152     [EXCP_AdEL] = "address error load",
 153     [EXCP_AdES] = "address error store",
 154     [EXCP_TLBF] = "TLB refill",
 155     [EXCP_IBE] = "instruction bus error",
 156     [EXCP_DBp] = "debug breakpoint",
 157     [EXCP_SYSCALL] = "syscall",
 158     [EXCP_BREAK] = "break",
 159     [EXCP_CpU] = "coprocessor unusable",
 160     [EXCP_RI] = "reserved instruction",
 161     [EXCP_OVERFLOW] = "arithmetic overflow",
 162     [EXCP_TRAP] = "trap",
 163     [EXCP_FPE] = "floating point",
 164     [EXCP_DDBS] = "debug data break store",
 165     [EXCP_DWATCH] = "data watchpoint",
 166     [EXCP_LTLBL] = "TLB modify",
 167     [EXCP_TLBL] = "TLB load",
 168     [EXCP_TLBS] = "TLB store",
 169     [EXCP_DBE] = "data bus error",
 170     [EXCP_DDBL] = "debug data break load",
 171     [EXCP_THREAD] = "thread",
 172     [EXCP_MDMX] = "MDMX",
 173     [EXCP_C2E] = "precise coprocessor 2",
 174     [EXCP_CACHE] = "cache error",
 175     [EXCP_TLBXI] = "TLB execute-inhibit",
 176     [EXCP_TLBRI] = "TLB read-inhibit",
 177     [EXCP_MSADIS] = "MSA disabled",
 178     [EXCP_MSAFPE] = "MSA floating point",
 179 };
 180
 181 const char *mips_exception_name(int32_t exception)
 182 {
 183     if (exception < 0 || exception > EXCP_LAST) {
 184         return "unknown";
 185     }
 186     return excp_names[exception];
 187 }
 188
 189 void cpu_set_exception_base(int vp_index, target_ulong address)
 190 {
 191     MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
 192     vp->env.exception_base = address;
 193 }
 194
 195 target_ulong exception_resume_pc(CPUMIPSState *env)
 196 {
 197     target_ulong bad_pc;
 198     target_ulong isa_mode;
 199
 200     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 201     bad_pc = env->active_tc.PC | isa_mode;
 202     if (env->hflags & MIPS_HFLAG_BMASK) {
 203         /*
 204          * If the exception was raised from a delay slot, come back to
 205          * the jump.
 206          */
 207         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 208     }
 209
 210     return bad_pc;
 211 }
 212
 213 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 214 {
 215     if (interrupt_request & CPU_INTERRUPT_HARD) {
 216         MIPSCPU *cpu = MIPS_CPU(cs);
 217         CPUMIPSState *env = &cpu->env;
 218
 219         if (cpu_mips_hw_interrupts_enabled(env) &&
 220             cpu_mips_hw_interrupts_pending(env)) {
 221             /* Raise it */
 222             cs->exception_index = EXCP_EXT_INTERRUPT;
 223             env->error_code = 0;
 224             mips_cpu_do_interrupt(cs);
 225             return true;
 226         }
 227     }
 228     return false;
 229 }
 230
 231 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
 232                                           uint32_t exception,
 233                                           int error_code,
 234                                           uintptr_t pc)
 235 {
 236     CPUState *cs = env_cpu(env);
 237
 238     qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
 239                   __func__, exception, mips_exception_name(exception),
 240                   error_code);
 241     cs->exception_index = exception;
 242     env->error_code = error_code;
 243
 244     cpu_loop_exit_restore(cs, pc);
 245 }
 246
 247 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
 248 {
 249     MIPSCPU *cpu = MIPS_CPU(cs);
 250     CPUMIPSState *env = &cpu->env;
 251
 252     env->active_tc.PC = value & ~(target_ulong)1;
 253     if (value & 1) {
 254         env->hflags |= MIPS_HFLAG_M16;
 255     } else {
 256         env->hflags &= ~(MIPS_HFLAG_M16);
 257     }
 258 }
 259
 260 #ifdef CONFIG_TCG
 261 static void mips_cpu_synchronize_from_tb(CPUState *cs,
 262                                          const TranslationBlock *tb)
 263 {
 264     MIPSCPU *cpu = MIPS_CPU(cs);
 265     CPUMIPSState *env = &cpu->env;
 266
 267     env->active_tc.PC = tb->pc;
 268     env->hflags &= ~MIPS_HFLAG_BMASK;
 269     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
 270 }
 271
 272 # ifndef CONFIG_USER_ONLY
 273 static bool mips_io_recompile_replay_branch(CPUState *cs,
 274                                             const TranslationBlock *tb)
 275 {
 276     MIPSCPU *cpu = MIPS_CPU(cs);
 277     CPUMIPSState *env = &cpu->env;
 278
 279     if ((env->hflags & MIPS_HFLAG_BMASK) != 0
 280         && env->active_tc.PC != tb->pc) {
 281         env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 282         env->hflags &= ~MIPS_HFLAG_BMASK;
 283         return true;
 284     }
 285     return false;
 286 }
 287 # endif /* !CONFIG_USER_ONLY */
 288 #endif /* CONFIG_TCG */
 289
 290 static bool mips_cpu_has_work(CPUState *cs)
 291 {
 292     MIPSCPU *cpu = MIPS_CPU(cs);
 293     CPUMIPSState *env = &cpu->env;
 294     bool has_work = false;
 295
 296     /*
 297      * Prior to MIPS Release 6 it is implementation dependent if non-enabled
 298      * interrupts wake-up the CPU, however most of the implementations only
 299      * check for interrupts that can be taken.
 300      */
 301     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 302         cpu_mips_hw_interrupts_pending(env)) {
 303         if (cpu_mips_hw_interrupts_enabled(env) ||
 304             (env->insn_flags & ISA_MIPS_R6)) {
 305             has_work = true;
 306         }
 307     }
 308
 309     /* MIPS-MT has the ability to halt the CPU.  */
 310     if (ase_mt_available(env)) {
 311         /*
 312          * The QEMU model will issue an _WAKE request whenever the CPUs
 313          * should be woken up.
 314          */
 315         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
 316             has_work = true;
 317         }
 318
 319         if (!mips_vpe_active(env)) {
 320             has_work = false;
 321         }
 322     }
 323     /* MIPS Release 6 has the ability to halt the CPU.  */
 324     if (env->CP0_Config5 & (1 << CP0C5_VP)) {
 325         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
 326             has_work = true;
 327         }
 328         if (!mips_vp_active(env)) {
 329             has_work = false;
 330         }
 331     }
 332     return has_work;
 333 }
 334
 335 #include "cpu-defs.c.inc"
 336
 337 static void mips_cpu_reset(DeviceState *dev)
 338 {
 339     CPUState *cs = CPU(dev);
 340     MIPSCPU *cpu = MIPS_CPU(cs);
 341     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
 342     CPUMIPSState *env = &cpu->env;
 343
 344     mcc->parent_reset(dev);
 345
 346     memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 347
 348     /* Reset registers to their default values */
 349     env->CP0_PRid = env->cpu_model->CP0_PRid;
 350     env->CP0_Config0 = env->cpu_model->CP0_Config0;
 351 #ifdef TARGET_WORDS_BIGENDIAN
 352     env->CP0_Config0 |= (1 << CP0C0_BE);
 353 #endif
 354     env->CP0_Config1 = env->cpu_model->CP0_Config1;
 355     env->CP0_Config2 = env->cpu_model->CP0_Config2;
 356     env->CP0_Config3 = env->cpu_model->CP0_Config3;
 357     env->CP0_Config4 = env->cpu_model->CP0_Config4;
 358     env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
 359     env->CP0_Config5 = env->cpu_model->CP0_Config5;
 360     env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
 361     env->CP0_Config6 = env->cpu_model->CP0_Config6;
 362     env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
 363     env->CP0_Config7 = env->cpu_model->CP0_Config7;
 364     env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
 365     env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
 366                                  << env->cpu_model->CP0_LLAddr_shift;
 367     env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
 368     env->SYNCI_Step = env->cpu_model->SYNCI_Step;
 369     env->CCRes = env->cpu_model->CCRes;
 370     env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
 371     env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
 372     env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
 373     env->current_tc = 0;
 374     env->SEGBITS = env->cpu_model->SEGBITS;
 375     env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
 376 #if defined(TARGET_MIPS64)
 377     if (env->cpu_model->insn_flags & ISA_MIPS3) {
 378         env->SEGMask |= 3ULL << 62;
 379     }
 380 #endif
 381     env->PABITS = env->cpu_model->PABITS;
 382     env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
 383     env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
 384     env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
 385     env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
 386     env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
 387     env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
 388     env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
 389     env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
 390     env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
 391     env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
 392     env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
 393     env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
 394     env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
 395     env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
 396     env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
 397     env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
 398     env->msair = env->cpu_model->MSAIR;
 399     env->insn_flags = env->cpu_model->insn_flags;
 400
 401 #if defined(CONFIG_USER_ONLY)
 402     env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
 403 # ifdef TARGET_MIPS64
 404     /* Enable 64-bit register mode.  */
 405     env->CP0_Status |= (1 << CP0St_PX);
 406 # endif
 407 # ifdef TARGET_ABI_MIPSN64
 408     /* Enable 64-bit address mode.  */
 409     env->CP0_Status |= (1 << CP0St_UX);
 410 # endif
 411     /*
 412      * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
 413      * hardware registers.
 414      */
 415     env->CP0_HWREna |= 0x0000000F;
 416     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
 417         env->CP0_Status |= (1 << CP0St_CU1);
 418     }
 419     if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
 420         env->CP0_Status |= (1 << CP0St_MX);
 421     }
 422 # if defined(TARGET_MIPS64)
 423     /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
 424     if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
 425         (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
 426         env->CP0_Status |= (1 << CP0St_FR);
 427     }
 428 # endif
 429 #else /* !CONFIG_USER_ONLY */
 430     if (env->hflags & MIPS_HFLAG_BMASK) {
 431         /*
 432          * If the exception was raised from a delay slot,
 433          * come back to the jump.
 434          */
 435         env->CP0_ErrorEPC = (env->active_tc.PC
 436                              - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
 437     } else {
 438         env->CP0_ErrorEPC = env->active_tc.PC;
 439     }
 440     env->active_tc.PC = env->exception_base;
 441     env->CP0_Random = env->tlb->nb_tlb - 1;
 442     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 443     env->CP0_Wired = 0;
 444     env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
 445     env->CP0_EBase = (cs->cpu_index & 0x3FF);
 446     if (mips_um_ksegs_enabled()) {
 447         env->CP0_EBase |= 0x40000000;
 448     } else {
 449         env->CP0_EBase |= (int32_t)0x80000000;
 450     }
 451     if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
 452         env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
 453     }
 454     env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
 455             0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
 456     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
 457     /*
 458      * Vectored interrupts not implemented, timer on int 7,
 459      * no performance counters.
 460      */
 461     env->CP0_IntCtl = 0xe0000000;
 462     {
 463         int i;
 464
 465         for (i = 0; i < 7; i++) {
 466             env->CP0_WatchLo[i] = 0;
 467             env->CP0_WatchHi[i] = 0x80000000;
 468         }
 469         env->CP0_WatchLo[7] = 0;
 470         env->CP0_WatchHi[7] = 0;
 471     }
 472     /* Count register increments in debug mode, EJTAG version 1 */
 473     env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
 474
 475     cpu_mips_store_count(env, 1);
 476
 477     if (ase_mt_available(env)) {
 478         int i;
 479
 480         /* Only TC0 on VPE 0 starts as active.  */
 481         for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
 482             env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
 483             env->tcs[i].CP0_TCHalt = 1;
 484         }
 485         env->active_tc.CP0_TCHalt = 1;
 486         cs->halted = 1;
 487
 488         if (cs->cpu_index == 0) {
 489             /* VPE0 starts up enabled.  */
 490             env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
 491             env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 492
 493             /* TC0 starts up unhalted.  */
 494             cs->halted = 0;
 495             env->active_tc.CP0_TCHalt = 0;
 496             env->tcs[0].CP0_TCHalt = 0;
 497             /* With thread 0 active.  */
 498             env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
 499             env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
 500         }
 501     }
 502
 503     /*
 504      * Configure default legacy segmentation control. We use this regardless of
 505      * whether segmentation control is presented to the guest.
 506      */
 507     /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
 508     env->CP0_SegCtl0 =   (CP0SC_AM_MK << CP0SC_AM);
 509     /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
 510     env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
 511     /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
 512     env->CP0_SegCtl1 =   (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
 513                          (2 << CP0SC_C);
 514     /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
 515     env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
 516                          (3 << CP0SC_C)) << 16;
 517     /* USeg (seg4 0x40000000..0x7FFFFFFF) */
 518     env->CP0_SegCtl2 =   (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
 519                          (1 << CP0SC_EU) | (2 << CP0SC_C);
 520     /* USeg (seg5 0x00000000..0x3FFFFFFF) */
 521     env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
 522                          (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
 523     /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
 524     env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
 525 #endif /* !CONFIG_USER_ONLY */
 526     if ((env->insn_flags & ISA_MIPS_R6) &&
 527         (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
 528         /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
 529         env->CP0_Status |= (1 << CP0St_FR);
 530     }
 531
 532     if (env->insn_flags & ISA_MIPS_R6) {
 533         /* PTW  =  1 */
 534         env->CP0_PWSize = 0x40;
 535         /* GDI  = 12 */
 536         /* UDI  = 12 */
 537         /* MDI  = 12 */
 538         /* PRI  = 12 */
 539         /* PTEI =  2 */
 540         env->CP0_PWField = 0x0C30C302;
 541     } else {
 542         /* GDI  =  0 */
 543         /* UDI  =  0 */
 544         /* MDI  =  0 */
 545         /* PRI  =  0 */
 546         /* PTEI =  2 */
 547         env->CP0_PWField = 0x02;
 548     }
 549
 550     if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
 551         /*  microMIPS on reset when Config3.ISA is 3 */
 552         env->hflags |= MIPS_HFLAG_M16;
 553     }
 554
 555     msa_reset(env);
 556
 557     compute_hflags(env);
 558     restore_fp_status(env);
 559     restore_pamask(env);
 560     cs->exception_index = EXCP_NONE;
 561
 562     if (semihosting_get_argc()) {
 563         /* UHI interface can be used to obtain argc and argv */
 564         env->active_tc.gpr[4] = -1;
 565     }
 566
 567 #ifndef CONFIG_USER_ONLY
 568     if (kvm_enabled()) {
 569         kvm_mips_reset_vcpu(cpu);
 570     }
 571 #endif
 572 }
 573
 574 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 575 {
 576     MIPSCPU *cpu = MIPS_CPU(s);
 577     CPUMIPSState *env = &cpu->env;
 578
 579     if (!(env->insn_flags & ISA_NANOMIPS32)) {
 580 #ifdef TARGET_WORDS_BIGENDIAN
 581         info->print_insn = print_insn_big_mips;
 582 #else
 583         info->print_insn = print_insn_little_mips;
 584 #endif
 585     } else {
 586 #if defined(CONFIG_NANOMIPS_DIS)
 587         info->print_insn = print_insn_nanomips;
 588 #endif
 589     }
 590 }
 591
 592 /*
 593  * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
 594  */
 595 #define CPU_FREQ_HZ_DEFAULT     200000000
 596 #define CP0_COUNT_RATE_DEFAULT  2
 597
 598 static void mips_cp0_period_set(MIPSCPU *cpu)
 599 {
 600     CPUMIPSState *env = &cpu->env;
 601
 602     env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
 603                                           cpu->cp0_count_rate);
 604     assert(env->cp0_count_ns);
 605 }
 606
 607 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 608 {
 609     CPUState *cs = CPU(dev);
 610     MIPSCPU *cpu = MIPS_CPU(dev);
 611     CPUMIPSState *env = &cpu->env;
 612     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 613     Error *local_err = NULL;
 614
 615     if (!clock_get(cpu->clock)) {
 616 #ifndef CONFIG_USER_ONLY
 617         if (!qtest_enabled()) {
 618             g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT);
 619
 620             warn_report("CPU input clock is not connected to any output clock, "
 621                         "using default frequency of %s.", cpu_freq_str);
 622         }
 623 #endif
 624         /* Initialize the frequency in case the clock remains unconnected. */
 625         clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
 626     }
 627     mips_cp0_period_set(cpu);
 628
 629     cpu_exec_realizefn(cs, &local_err);
 630     if (local_err != NULL) {
 631         error_propagate(errp, local_err);
 632         return;
 633     }
 634
 635     env->exception_base = (int32_t)0xBFC00000;
 636
 637 #ifndef CONFIG_USER_ONLY
 638     mmu_init(env, env->cpu_model);
 639 #endif
 640     fpu_init(env, env->cpu_model);
 641     mvp_init(env);
 642
 643     cpu_reset(cs);
 644     qemu_init_vcpu(cs);
 645
 646     mcc->parent_realize(dev, errp);
 647 }
 648
 649 static void mips_cpu_initfn(Object *obj)
 650 {
 651     MIPSCPU *cpu = MIPS_CPU(obj);
 652     CPUMIPSState *env = &cpu->env;
 653     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
 654
 655     cpu_set_cpustate_pointers(cpu);
 656     cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
 657     env->cpu_model = mcc->cpu_def;
 658 }
 659
 660 static char *mips_cpu_type_name(const char *cpu_model)
 661 {
 662     return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
 663 }
 664
 665 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
 666 {
 667     ObjectClass *oc;
 668     char *typename;
 669
 670     typename = mips_cpu_type_name(cpu_model);
 671     oc = object_class_by_name(typename);
 672     g_free(typename);
 673     return oc;
 674 }
 675
 676 static Property mips_cpu_properties[] = {
 677     /* CP0 timer running at half the clock of the CPU */
 678     DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
 679                        CP0_COUNT_RATE_DEFAULT),
 680     DEFINE_PROP_END_OF_LIST()
 681 };
 682
 683 #ifdef CONFIG_TCG
 684 #include "hw/core/tcg-cpu-ops.h"
 685 /*
 686  * NB: cannot be const, as some elements are changed for specific
 687  * mips hardware (see hw/mips/jazz.c).
 688  */
 689 static struct TCGCPUOps mips_tcg_ops = {
 690     .initialize = mips_tcg_init,
 691     .synchronize_from_tb = mips_cpu_synchronize_from_tb,
 692     .cpu_exec_interrupt = mips_cpu_exec_interrupt,
 693     .tlb_fill = mips_cpu_tlb_fill,
 694
 695 #if !defined(CONFIG_USER_ONLY)
 696     .do_interrupt = mips_cpu_do_interrupt,
 697     .do_transaction_failed = mips_cpu_do_transaction_failed,
 698     .do_unaligned_access = mips_cpu_do_unaligned_access,
 699     .io_recompile_replay_branch = mips_io_recompile_replay_branch,
 700 #endif /* !CONFIG_USER_ONLY */
 701 };
 702 #endif /* CONFIG_TCG */
 703
 704 static void mips_cpu_class_init(ObjectClass *c, void *data)
 705 {
 706     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 707     CPUClass *cc = CPU_CLASS(c);
 708     DeviceClass *dc = DEVICE_CLASS(c);
 709
 710     device_class_set_parent_realize(dc, mips_cpu_realizefn,
 711                                     &mcc->parent_realize);
 712     device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
 713     device_class_set_props(dc, mips_cpu_properties);
 714
 715     cc->class_by_name = mips_cpu_class_by_name;
 716     cc->has_work = mips_cpu_has_work;
 717     cc->dump_state = mips_cpu_dump_state;
 718     cc->set_pc = mips_cpu_set_pc;
 719     cc->gdb_read_register = mips_cpu_gdb_read_register;
 720     cc->gdb_write_register = mips_cpu_gdb_write_register;
 721 #ifndef CONFIG_USER_ONLY
 722     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 723     cc->vmsd = &vmstate_mips_cpu;
 724 #endif
 725     cc->disas_set_info = mips_cpu_disas_set_info;
 726     cc->gdb_num_core_regs = 73;
 727     cc->gdb_stop_before_watchpoint = true;
 728 #ifdef CONFIG_TCG
 729     cc->tcg_ops = &mips_tcg_ops;
 730 #endif /* CONFIG_TCG */
 731 }
 732
 733 static const TypeInfo mips_cpu_type_info = {
 734     .name = TYPE_MIPS_CPU,
 735     .parent = TYPE_CPU,
 736     .instance_size = sizeof(MIPSCPU),
 737     .instance_init = mips_cpu_initfn,
 738     .abstract = true,
 739     .class_size = sizeof(MIPSCPUClass),
 740     .class_init = mips_cpu_class_init,
 741 };
 742
 743 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 744 {
 745     MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
 746     mcc->cpu_def = data;
 747 }
 748
 749 static void mips_register_cpudef_type(const struct mips_def_t *def)
 750 {
 751     char *typename = mips_cpu_type_name(def->name);
 752     TypeInfo ti = {
 753         .name = typename,
 754         .parent = TYPE_MIPS_CPU,
 755         .class_init = mips_cpu_cpudef_class_init,
 756         .class_data = (void *)def,
 757     };
 758
 759     type_register(&ti);
 760     g_free(typename);
 761 }
 762
 763 static void mips_cpu_register_types(void)
 764 {
 765     int i;
 766
 767     type_register_static(&mips_cpu_type_info);
 768     for (i = 0; i < mips_defs_number; i++) {
 769         mips_register_cpudef_type(&mips_defs[i]);
 770     }
 771 }
 772
 773 type_init(mips_cpu_register_types)
 774
 775 static void mips_cpu_add_definition(gpointer data, gpointer user_data)
 776 {
 777     ObjectClass *oc = data;
 778     CpuDefinitionInfoList **cpu_list = user_data;
 779     CpuDefinitionInfo *info;
 780     const char *typename;
 781
 782     typename = object_class_get_name(oc);
 783     info = g_malloc0(sizeof(*info));
 784     info->name = g_strndup(typename,
 785                            strlen(typename) - strlen("-" TYPE_MIPS_CPU));
 786     info->q_typename = g_strdup(typename);
 787
 788     QAPI_LIST_PREPEND(*cpu_list, info);
 789 }
 790
 791 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 792 {
 793     CpuDefinitionInfoList *cpu_list = NULL;
 794     GSList *list;
 795
 796     list = object_class_get_list(TYPE_MIPS_CPU, false);
 797     g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
 798     g_slist_free(list);
 799
 800     return cpu_list;
 801 }
 802
 803 /* Could be used by generic CPU object */
 804 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
 805 {
 806     DeviceState *cpu;
 807
 808     cpu = DEVICE(object_new(cpu_type));
 809     qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
 810     qdev_realize(cpu, NULL, &error_abort);
 811
 812     return MIPS_CPU(cpu);
 813 }
 814
 815 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
 816 {
 817     return (env->cpu_model->insn_flags & isa_mask) != 0;
 818 }
 819
 820 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
 821 {
 822     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
 823     return (mcc->cpu_def->insn_flags & isa) != 0;
 824 }
 825
 826 bool cpu_type_supports_cps_smp(const char *cpu_type)
 827 {
 828     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
 829     return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 830 }