net: set a default value for sndbuf=
[qemu/aliguori-queue.git] / hw / ppce500_mpc8544ds.c
blobc0e367de6327e71b866de9cc44dfd58f2b4f271a
1 /*
2 * Qemu PowerPC MPC8544DS board emualtion
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <dirent.h>
19 #include "config.h"
20 #include "qemu-common.h"
21 #include "net.h"
22 #include "hw.h"
23 #include "pc.h"
24 #include "pci.h"
25 #include "boards.h"
26 #include "sysemu.h"
27 #include "kvm.h"
28 #include "kvm_ppc.h"
29 #include "device_tree.h"
30 #include "openpic.h"
31 #include "ppce500.h"
33 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
34 #define UIMAGE_LOAD_BASE 0
35 #define DTB_LOAD_BASE 0x600000
36 #define INITRD_LOAD_BASE 0x2000000
38 #define RAM_SIZES_ALIGN (64UL << 20)
40 #define MPC8544_CCSRBAR_BASE 0xE0000000
41 #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000)
42 #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500)
43 #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600)
44 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000)
45 #define MPC8544_PCI_REGS_SIZE 0x1000
46 #define MPC8544_PCI_IO 0xE1000000
47 #define MPC8544_PCI_IOLEN 0x10000
49 #ifdef HAVE_FDT
50 static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop)
52 uint32_t cell;
53 int ret;
55 ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
56 if (ret < 0) {
57 fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
58 goto out;
61 ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
62 prop, cell);
63 if (ret < 0) {
64 fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop);
65 goto out;
68 out:
69 return ret;
71 #endif
73 static void *mpc8544_load_device_tree(target_phys_addr_t addr,
74 uint32_t ramsize,
75 target_phys_addr_t initrd_base,
76 target_phys_addr_t initrd_size,
77 const char *kernel_cmdline)
79 void *fdt = NULL;
80 #ifdef HAVE_FDT
81 uint32_t mem_reg_property[] = {0, ramsize};
82 char *filename;
83 int fdt_size;
84 int ret;
86 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
87 if (!filename) {
88 goto out;
90 fdt = load_device_tree(filename, &fdt_size);
91 qemu_free(filename);
92 if (fdt == NULL) {
93 goto out;
96 /* Manipulate device tree in memory. */
97 ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
98 sizeof(mem_reg_property));
99 if (ret < 0)
100 fprintf(stderr, "couldn't set /memory/reg\n");
102 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
103 initrd_base);
104 if (ret < 0)
105 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
107 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
108 (initrd_base + initrd_size));
109 if (ret < 0)
110 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
112 ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
113 kernel_cmdline);
114 if (ret < 0)
115 fprintf(stderr, "couldn't set /chosen/bootargs\n");
117 if (kvm_enabled()) {
118 struct dirent *dirp;
119 DIR *dp;
120 char buf[128];
122 if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) {
123 printf("Can't open directory /proc/device-tree/cpus/\n");
124 goto out;
127 buf[0] = '\0';
128 while ((dirp = readdir(dp)) != NULL) {
129 if (strncmp(dirp->d_name, "PowerPC", 7) == 0) {
130 snprintf(buf, 128, "/cpus/%s", dirp->d_name);
131 break;
134 closedir(dp);
135 if (buf[0] == '\0') {
136 printf("Unknow host!\n");
137 goto out;
140 mpc8544_copy_soc_cell(fdt, buf, "clock-frequency");
141 mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency");
144 cpu_physical_memory_write (addr, (void *)fdt, fdt_size);
146 out:
147 #endif
149 return fdt;
152 static void mpc8544ds_init(ram_addr_t ram_size,
153 const char *boot_device,
154 const char *kernel_filename,
155 const char *kernel_cmdline,
156 const char *initrd_filename,
157 const char *cpu_model)
159 PCIBus *pci_bus;
160 PCIDevice *pci_dev;
161 CPUState *env;
162 uint64_t elf_entry;
163 uint64_t elf_lowaddr;
164 target_ulong entry=0;
165 target_ulong loadaddr=UIMAGE_LOAD_BASE;
166 target_long kernel_size=0;
167 target_ulong dt_base=DTB_LOAD_BASE;
168 target_ulong initrd_base=INITRD_LOAD_BASE;
169 target_long initrd_size=0;
170 void *fdt;
171 int i=0;
172 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
173 qemu_irq *irqs, *mpic, *pci_irqs;
174 SerialState * serial[2];
176 /* Setup CPU */
177 env = cpu_ppc_init("e500v2_v30");
178 if (!env) {
179 fprintf(stderr, "Unable to initialize CPU!\n");
180 exit(1);
183 /* Fixup Memory size on a alignment boundary */
184 ram_size &= ~(RAM_SIZES_ALIGN - 1);
186 /* Register Memory */
187 cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(ram_size));
189 /* MPIC */
190 irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
191 irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT];
192 irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT];
193 mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
195 /* Serial */
196 if (serial_hds[0])
197 serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
198 0, mpic[12+26], 399193,
199 serial_hds[0], 1);
201 if (serial_hds[1])
202 serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
203 0, mpic[12+26], 399193,
204 serial_hds[0], 1);
206 /* PCI */
207 pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
208 pci_irqs[0] = mpic[pci_irq_nrs[0]];
209 pci_irqs[1] = mpic[pci_irq_nrs[1]];
210 pci_irqs[2] = mpic[pci_irq_nrs[2]];
211 pci_irqs[3] = mpic[pci_irq_nrs[3]];
212 pci_bus = ppce500_pci_init(pci_irqs, MPC8544_PCI_REGS_BASE);
213 if (!pci_bus)
214 printf("couldn't create PCI controller!\n");
216 isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
218 if (pci_bus) {
219 int unit_id = 0;
221 /* Add virtio block devices. */
222 while ((i = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
223 pci_dev = pci_create("virtio-blk-pci", drives_table[i].devaddr);
224 qdev_init(&pci_dev->qdev);
225 unit_id++;
228 /* Register network interfaces. */
229 for (i = 0; i < nb_nics; i++) {
230 pci_nic_init(&nd_table[i], "virtio", NULL);
234 /* Load kernel. */
235 if (kernel_filename) {
236 kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
237 if (kernel_size < 0) {
238 kernel_size = load_elf(kernel_filename, 0, &elf_entry, &elf_lowaddr,
239 NULL);
240 entry = elf_entry;
241 loadaddr = elf_lowaddr;
243 /* XXX try again as binary */
244 if (kernel_size < 0) {
245 fprintf(stderr, "qemu: could not load kernel '%s'\n",
246 kernel_filename);
247 exit(1);
251 /* Load initrd. */
252 if (initrd_filename) {
253 initrd_size = load_image_targphys(initrd_filename, initrd_base,
254 ram_size - initrd_base);
256 if (initrd_size < 0) {
257 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
258 initrd_filename);
259 exit(1);
263 /* If we're loading a kernel directly, we must load the device tree too. */
264 if (kernel_filename) {
265 fdt = mpc8544_load_device_tree(dt_base, ram_size,
266 initrd_base, initrd_size, kernel_cmdline);
267 if (fdt == NULL) {
268 fprintf(stderr, "couldn't load device tree\n");
269 exit(1);
272 /* Set initial guest state. */
273 env->gpr[1] = (16<<20) - 8;
274 env->gpr[3] = dt_base;
275 env->nip = entry;
276 /* XXX we currently depend on KVM to create some initial TLB entries. */
279 if (kvm_enabled())
280 kvmppc_init();
282 return;
285 static QEMUMachine mpc8544ds_machine = {
286 .name = "mpc8544ds",
287 .desc = "mpc8544ds",
288 .init = mpc8544ds_init,
291 static void mpc8544ds_machine_init(void)
293 qemu_register_machine(&mpc8544ds_machine);
296 machine_init(mpc8544ds_machine_init);