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qemu: make cirrus init value pci spec compliant
[qemu/aliguori-queue.git] / hw / e1000.c
blobb65a74fe9eafcc3ec770a8e87a727a2692e8901b
1 /*
2 * QEMU e1000 emulation
3 *
4 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
5 * Copyright (c) 2008 Qumranet
6 * Based on work done by:
7 * Copyright (c) 2007 Dan Aloni
8 * Copyright (c) 2004 Antony T Curtis
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24
25 #include "hw.h"
26 #include "pci.h"
27 #include "net.h"
28 #include "net/checksum.h"
29 #include "loader.h"
30
31 #include "e1000_hw.h"
32
33 #define DEBUG
34
35 #ifdef DEBUG
36 enum {
37 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
38 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
39 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
40 DEBUG_RXFILTER, DEBUG_NOTYET,
41 };
42 #define DBGBIT(x) (1<<DEBUG_##x)
43 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
44
45 #define DBGOUT(what, fmt, ...) do { \
46 if (debugflags & DBGBIT(what)) \
47 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
48 } while (0)
49 #else
50 #define DBGOUT(what, fmt, ...) do {} while (0)
51 #endif
52
53 #define IOPORT_SIZE 0x40
54 #define PNPMMIO_SIZE 0x20000
55
56 /*
57 * HW models:
58 * E1000_DEV_ID_82540EM works with Windows and Linux
59 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
60 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
61 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
62 * Others never tested
63 */
64 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
65
66 /*
67 * May need to specify additional MAC-to-PHY entries --
68 * Intel's Windows driver refuses to initialize unless they match
69 */
70 enum {
71 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
72 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
73 /* default to E1000_DEV_ID_82540EM */ 0xc20
74 };
75
76 typedef struct E1000State_st {
77 PCIDevice dev;
78 NICState *nic;
79 NICConf conf;
80 int mmio_index;
81
82 uint32_t mac_reg[0x8000];
83 uint16_t phy_reg[0x20];
84 uint16_t eeprom_data[64];
85
86 uint32_t rxbuf_size;
87 uint32_t rxbuf_min_shift;
88 int check_rxov;
89 struct e1000_tx {
90 unsigned char header[256];
91 unsigned char vlan_header[4];
92 unsigned char vlan[4];
93 unsigned char data[0x10000];
94 uint16_t size;
95 unsigned char sum_needed;
96 unsigned char vlan_needed;
97 uint8_t ipcss;
98 uint8_t ipcso;
99 uint16_t ipcse;
100 uint8_t tucss;
101 uint8_t tucso;
102 uint16_t tucse;
103 uint8_t hdr_len;
104 uint16_t mss;
105 uint32_t paylen;
106 uint16_t tso_frames;
107 char tse;
108 int8_t ip;
109 int8_t tcp;
110 char cptse; // current packet tse bit
111 } tx;
112
113 struct {
114 uint32_t val_in; // shifted in from guest driver
115 uint16_t bitnum_in;
116 uint16_t bitnum_out;
117 uint16_t reading;
118 uint32_t old_eecd;
119 } eecd_state;
120 } E1000State;
121
122 #define defreg(x) x = (E1000_##x>>2)
123 enum {
124 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
125 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
126 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
127 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
128 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
129 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
130 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
131 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
132 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
133 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
134 defreg(VET),
135 };
136
137 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
138 static const char phy_regcap[0x20] = {
139 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
140 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
141 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
142 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
143 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
144 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
145 };
146
147 static void
148 ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
149 pcibus_t size, int type)
150 {
151 DBGOUT(IO, "e1000_ioport_map addr=0x%04"FMT_PCIBUS
152 " size=0x%08"FMT_PCIBUS"\n", addr, size);
153 }
154
155 static void
156 set_interrupt_cause(E1000State *s, int index, uint32_t val)
157 {
158 if (val)
159 val |= E1000_ICR_INT_ASSERTED;
160 s->mac_reg[ICR] = val;
161 s->mac_reg[ICS] = val;
162 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
163 }
164
165 static void
166 set_ics(E1000State *s, int index, uint32_t val)
167 {
168 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
169 s->mac_reg[IMS]);
170 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
171 }
172
173 static int
174 rxbufsize(uint32_t v)
175 {
176 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
177 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
178 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
179 switch (v) {
180 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
181 return 16384;
182 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
183 return 8192;
184 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
185 return 4096;
186 case E1000_RCTL_SZ_1024:
187 return 1024;
188 case E1000_RCTL_SZ_512:
189 return 512;
190 case E1000_RCTL_SZ_256:
191 return 256;
192 }
193 return 2048;
194 }
195
196 static void
197 set_ctrl(E1000State *s, int index, uint32_t val)
198 {
199 /* RST is self clearing */
200 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
201 }
202
203 static void
204 set_rx_control(E1000State *s, int index, uint32_t val)
205 {
206 s->mac_reg[RCTL] = val;
207 s->rxbuf_size = rxbufsize(val);
208 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
209 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
210 s->mac_reg[RCTL]);
211 }
212
213 static void
214 set_mdic(E1000State *s, int index, uint32_t val)
215 {
216 uint32_t data = val & E1000_MDIC_DATA_MASK;
217 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
218
219 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
220 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
221 else if (val & E1000_MDIC_OP_READ) {
222 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
223 if (!(phy_regcap[addr] & PHY_R)) {
224 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
225 val |= E1000_MDIC_ERROR;
226 } else
227 val = (val ^ data) | s->phy_reg[addr];
228 } else if (val & E1000_MDIC_OP_WRITE) {
229 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
230 if (!(phy_regcap[addr] & PHY_W)) {
231 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
232 val |= E1000_MDIC_ERROR;
233 } else
234 s->phy_reg[addr] = data;
235 }
236 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
237 set_ics(s, 0, E1000_ICR_MDAC);
238 }
239
240 static uint32_t
241 get_eecd(E1000State *s, int index)
242 {
243 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
244
245 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
246 s->eecd_state.bitnum_out, s->eecd_state.reading);
247 if (!s->eecd_state.reading ||
248 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
249 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
250 ret |= E1000_EECD_DO;
251 return ret;
252 }
253
254 static void
255 set_eecd(E1000State *s, int index, uint32_t val)
256 {
257 uint32_t oldval = s->eecd_state.old_eecd;
258
259 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
260 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
261 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
262 return;
263 if (!(E1000_EECD_SK & val)) { // falling edge
264 s->eecd_state.bitnum_out++;
265 return;
266 }
267 if (!(val & E1000_EECD_CS)) { // rising, no CS (EEPROM reset)
268 memset(&s->eecd_state, 0, sizeof s->eecd_state);
269 /*
270 * restore old_eecd's E1000_EECD_SK (known to be on)
271 * to avoid false detection of a clock edge
272 */
273 s->eecd_state.old_eecd = E1000_EECD_SK;
274 return;
275 }
276 s->eecd_state.val_in <<= 1;
277 if (val & E1000_EECD_DI)
278 s->eecd_state.val_in |= 1;
279 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
280 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
281 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
282 EEPROM_READ_OPCODE_MICROWIRE);
283 }
284 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
285 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
286 s->eecd_state.reading);
287 }
288
289 static uint32_t
290 flash_eerd_read(E1000State *s, int x)
291 {
292 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
293
294 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
295 return (s->mac_reg[EERD]);
296
297 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
298 return (E1000_EEPROM_RW_REG_DONE | r);
299
300 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
301 E1000_EEPROM_RW_REG_DONE | r);
302 }
303
304 static void
305 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
306 {
307 uint32_t sum;
308
309 if (cse && cse < n)
310 n = cse + 1;
311 if (sloc < n-1) {
312 sum = net_checksum_add(n-css, data+css);
313 cpu_to_be16wu((uint16_t *)(data + sloc),
314 net_checksum_finish(sum));
315 }
316 }
317
318 static inline int
319 vlan_enabled(E1000State *s)
320 {
321 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
322 }
323
324 static inline int
325 vlan_rx_filter_enabled(E1000State *s)
326 {
327 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
328 }
329
330 static inline int
331 is_vlan_packet(E1000State *s, const uint8_t *buf)
332 {
333 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
334 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
335 }
336
337 static inline int
338 is_vlan_txd(uint32_t txd_lower)
339 {
340 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
341 }
342
343 static void
344 xmit_seg(E1000State *s)
345 {
346 uint16_t len, *sp;
347 unsigned int frames = s->tx.tso_frames, css, sofar, n;
348 struct e1000_tx *tp = &s->tx;
349
350 if (tp->tse && tp->cptse) {
351 css = tp->ipcss;
352 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
353 frames, tp->size, css);
354 if (tp->ip) { // IPv4
355 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
356 tp->size - css);
357 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
358 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
359 } else // IPv6
360 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
361 tp->size - css);
362 css = tp->tucss;
363 len = tp->size - css;
364 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
365 if (tp->tcp) {
366 sofar = frames * tp->mss;
367 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
368 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
369 if (tp->paylen - sofar > tp->mss)
370 tp->data[css + 13] &= ~9; // PSH, FIN
371 } else // UDP
372 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
373 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
374 // add pseudo-header length before checksum calculation
375 sp = (uint16_t *)(tp->data + tp->tucso);
376 cpu_to_be16wu(sp, be16_to_cpup(sp) + len);
377 }
378 tp->tso_frames++;
379 }
380
381 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
382 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
383 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
384 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
385 if (tp->vlan_needed) {
386 memmove(tp->vlan, tp->data, 12);
387 memcpy(tp->data + 8, tp->vlan_header, 4);
388 qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
389 } else
390 qemu_send_packet(&s->nic->nc, tp->data, tp->size);
391 s->mac_reg[TPT]++;
392 s->mac_reg[GPTC]++;
393 n = s->mac_reg[TOTL];
394 if ((s->mac_reg[TOTL] += s->tx.size) < n)
395 s->mac_reg[TOTH]++;
396 }
397
398 static void
399 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
400 {
401 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
402 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
403 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
404 unsigned int msh = 0xfffff, hdr = 0;
405 uint64_t addr;
406 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
407 struct e1000_tx *tp = &s->tx;
408
409 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
410 op = le32_to_cpu(xp->cmd_and_length);
411 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
412 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
413 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
414 tp->tucss = xp->upper_setup.tcp_fields.tucss;
415 tp->tucso = xp->upper_setup.tcp_fields.tucso;
416 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
417 tp->paylen = op & 0xfffff;
418 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
419 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
420 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
421 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
422 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
423 tp->tso_frames = 0;
424 if (tp->tucso == 0) { // this is probably wrong
425 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
426 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
427 }
428 return;
429 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
430 // data descriptor
431 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
432 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
433 } else
434 // legacy descriptor
435 tp->cptse = 0;
436
437 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
438 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
439 tp->vlan_needed = 1;
440 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
441 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
442 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
443 le16_to_cpu(dp->upper.fields.special));
444 }
445
446 addr = le64_to_cpu(dp->buffer_addr);
447 if (tp->tse && tp->cptse) {
448 hdr = tp->hdr_len;
449 msh = hdr + tp->mss;
450 do {
451 bytes = split_size;
452 if (tp->size + bytes > msh)
453 bytes = msh - tp->size;
454 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
455 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
456 memmove(tp->header, tp->data, hdr);
457 tp->size = sz;
458 addr += bytes;
459 if (sz == msh) {
460 xmit_seg(s);
461 memmove(tp->data, tp->header, hdr);
462 tp->size = hdr;
463 }
464 } while (split_size -= bytes);
465 } else if (!tp->tse && tp->cptse) {
466 // context descriptor TSE is not set, while data descriptor TSE is set
467 DBGOUT(TXERR, "TCP segmentaion Error\n");
468 } else {
469 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
470 tp->size += split_size;
471 }
472
473 if (!(txd_lower & E1000_TXD_CMD_EOP))
474 return;
475 if (!(tp->tse && tp->cptse && tp->size < hdr))
476 xmit_seg(s);
477 tp->tso_frames = 0;
478 tp->sum_needed = 0;
479 tp->vlan_needed = 0;
480 tp->size = 0;
481 tp->cptse = 0;
482 }
483
484 static uint32_t
485 txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
486 {
487 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
488
489 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
490 return 0;
491 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
492 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
493 dp->upper.data = cpu_to_le32(txd_upper);
494 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
495 (void *)&dp->upper, sizeof(dp->upper));
496 return E1000_ICR_TXDW;
497 }
498
499 static void
500 start_xmit(E1000State *s)
501 {
502 target_phys_addr_t base;
503 struct e1000_tx_desc desc;
504 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
505
506 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
507 DBGOUT(TX, "tx disabled\n");
508 return;
509 }
510
511 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
512 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
513 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
514 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
515
516 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
517 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
518 desc.upper.data);
519
520 process_tx_desc(s, &desc);
521 cause |= txdesc_writeback(base, &desc);
522
523 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
524 s->mac_reg[TDH] = 0;
525 /*
526 * the following could happen only if guest sw assigns
527 * bogus values to TDT/TDLEN.
528 * there's nothing too intelligent we could do about this.
529 */
530 if (s->mac_reg[TDH] == tdh_start) {
531 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
532 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
533 break;
534 }
535 }
536 set_ics(s, 0, cause);
537 }
538
539 static int
540 receive_filter(E1000State *s, const uint8_t *buf, int size)
541 {
542 static uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
543 static int mta_shift[] = {4, 3, 2, 0};
544 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
545
546 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
547 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
548 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
549 ((vid >> 5) & 0x7f));
550 if ((vfta & (1 << (vid & 0x1f))) == 0)
551 return 0;
552 }
553
554 if (rctl & E1000_RCTL_UPE) // promiscuous
555 return 1;
556
557 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
558 return 1;
559
560 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
561 return 1;
562
563 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
564 if (!(rp[1] & E1000_RAH_AV))
565 continue;
566 ra[0] = cpu_to_le32(rp[0]);
567 ra[1] = cpu_to_le32(rp[1]);
568 if (!memcmp(buf, (uint8_t *)ra, 6)) {
569 DBGOUT(RXFILTER,
570 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
571 (int)(rp - s->mac_reg - RA)/2,
572 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
573 return 1;
574 }
575 }
576 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
577 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
578
579 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
580 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
581 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
582 return 1;
583 DBGOUT(RXFILTER,
584 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
585 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
586 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
587 s->mac_reg[MTA + (f >> 5)]);
588
589 return 0;
590 }
591
592 static void
593 e1000_set_link_status(VLANClientState *nc)
594 {
595 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
596 uint32_t old_status = s->mac_reg[STATUS];
597
598 if (nc->link_down)
599 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
600 else
601 s->mac_reg[STATUS] |= E1000_STATUS_LU;
602
603 if (s->mac_reg[STATUS] != old_status)
604 set_ics(s, 0, E1000_ICR_LSC);
605 }
606
607 static int
608 e1000_can_receive(VLANClientState *nc)
609 {
610 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
611
612 return (s->mac_reg[RCTL] & E1000_RCTL_EN);
613 }
614
615 static ssize_t
616 e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
617 {
618 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
619 struct e1000_rx_desc desc;
620 target_phys_addr_t base;
621 unsigned int n, rdt;
622 uint32_t rdh_start;
623 uint16_t vlan_special = 0;
624 uint8_t vlan_status = 0, vlan_offset = 0;
625
626 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
627 return -1;
628
629 if (size > s->rxbuf_size) {
630 DBGOUT(RX, "packet too large for buffers (%lu > %d)\n",
631 (unsigned long)size, s->rxbuf_size);
632 return -1;
633 }
634
635 if (!receive_filter(s, buf, size))
636 return size;
637
638 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
639 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
640 memmove((void *)(buf + 4), buf, 12);
641 vlan_status = E1000_RXD_STAT_VP;
642 vlan_offset = 4;
643 size -= 4;
644 }
645
646 rdh_start = s->mac_reg[RDH];
647 size += 4; // for the header
648 do {
649 if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) {
650 set_ics(s, 0, E1000_ICS_RXO);
651 return -1;
652 }
653 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
654 sizeof(desc) * s->mac_reg[RDH];
655 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
656 desc.special = vlan_special;
657 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
658 if (desc.buffer_addr) {
659 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
660 (void *)(buf + vlan_offset), size);
661 desc.length = cpu_to_le16(size);
662 desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM;
663 } else // as per intel docs; skip descriptors with null buf addr
664 DBGOUT(RX, "Null RX descriptor!!\n");
665 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
666
667 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
668 s->mac_reg[RDH] = 0;
669 s->check_rxov = 1;
670 /* see comment in start_xmit; same here */
671 if (s->mac_reg[RDH] == rdh_start) {
672 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
673 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
674 set_ics(s, 0, E1000_ICS_RXO);
675 return -1;
676 }
677 } while (desc.buffer_addr == 0);
678
679 s->mac_reg[GPRC]++;
680 s->mac_reg[TPR]++;
681 n = s->mac_reg[TORL];
682 if ((s->mac_reg[TORL] += size) < n)
683 s->mac_reg[TORH]++;
684
685 n = E1000_ICS_RXT0;
686 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
687 rdt += s->mac_reg[RDLEN] / sizeof(desc);
688 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
689 s->rxbuf_min_shift)
690 n |= E1000_ICS_RXDMT0;
691
692 set_ics(s, 0, n);
693
694 return size;
695 }
696
697 static uint32_t
698 mac_readreg(E1000State *s, int index)
699 {
700 return s->mac_reg[index];
701 }
702
703 static uint32_t
704 mac_icr_read(E1000State *s, int index)
705 {
706 uint32_t ret = s->mac_reg[ICR];
707
708 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
709 set_interrupt_cause(s, 0, 0);
710 return ret;
711 }
712
713 static uint32_t
714 mac_read_clr4(E1000State *s, int index)
715 {
716 uint32_t ret = s->mac_reg[index];
717
718 s->mac_reg[index] = 0;
719 return ret;
720 }
721
722 static uint32_t
723 mac_read_clr8(E1000State *s, int index)
724 {
725 uint32_t ret = s->mac_reg[index];
726
727 s->mac_reg[index] = 0;
728 s->mac_reg[index-1] = 0;
729 return ret;
730 }
731
732 static void
733 mac_writereg(E1000State *s, int index, uint32_t val)
734 {
735 s->mac_reg[index] = val;
736 }
737
738 static void
739 set_rdt(E1000State *s, int index, uint32_t val)
740 {
741 s->check_rxov = 0;
742 s->mac_reg[index] = val & 0xffff;
743 }
744
745 static void
746 set_16bit(E1000State *s, int index, uint32_t val)
747 {
748 s->mac_reg[index] = val & 0xffff;
749 }
750
751 static void
752 set_dlen(E1000State *s, int index, uint32_t val)
753 {
754 s->mac_reg[index] = val & 0xfff80;
755 }
756
757 static void
758 set_tctl(E1000State *s, int index, uint32_t val)
759 {
760 s->mac_reg[index] = val;
761 s->mac_reg[TDT] &= 0xffff;
762 start_xmit(s);
763 }
764
765 static void
766 set_icr(E1000State *s, int index, uint32_t val)
767 {
768 DBGOUT(INTERRUPT, "set_icr %x\n", val);
769 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
770 }
771
772 static void
773 set_imc(E1000State *s, int index, uint32_t val)
774 {
775 s->mac_reg[IMS] &= ~val;
776 set_ics(s, 0, 0);
777 }
778
779 static void
780 set_ims(E1000State *s, int index, uint32_t val)
781 {
782 s->mac_reg[IMS] |= val;
783 set_ics(s, 0, 0);
784 }
785
786 #define getreg(x) [x] = mac_readreg
787 static uint32_t (*macreg_readops[])(E1000State *, int) = {
788 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
789 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
790 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
791 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
792 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
793 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
794 getreg(TDLEN), getreg(RDLEN),
795
796 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
797 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
798 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
799 [CRCERRS ... MPC] = &mac_readreg,
800 [RA ... RA+31] = &mac_readreg,
801 [MTA ... MTA+127] = &mac_readreg,
802 [VFTA ... VFTA+127] = &mac_readreg,
803 };
804 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
805
806 #define putreg(x) [x] = mac_writereg
807 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
808 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
809 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
810 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
811 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
812 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
813 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
814 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
815 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
816 [RA ... RA+31] = &mac_writereg,
817 [MTA ... MTA+127] = &mac_writereg,
818 [VFTA ... VFTA+127] = &mac_writereg,
819 };
820 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
821
822 static void
823 e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
824 {
825 E1000State *s = opaque;
826 unsigned int index = (addr & 0x1ffff) >> 2;
827
828 #ifdef TARGET_WORDS_BIGENDIAN
829 val = bswap32(val);
830 #endif
831 if (index < NWRITEOPS && macreg_writeops[index])
832 macreg_writeops[index](s, index, val);
833 else if (index < NREADOPS && macreg_readops[index])
834 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
835 else
836 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
837 index<<2, val);
838 }
839
840 static void
841 e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
842 {
843 // emulate hw without byte enables: no RMW
844 e1000_mmio_writel(opaque, addr & ~3,
845 (val & 0xffff) << (8*(addr & 3)));
846 }
847
848 static void
849 e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
850 {
851 // emulate hw without byte enables: no RMW
852 e1000_mmio_writel(opaque, addr & ~3,
853 (val & 0xff) << (8*(addr & 3)));
854 }
855
856 static uint32_t
857 e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
858 {
859 E1000State *s = opaque;
860 unsigned int index = (addr & 0x1ffff) >> 2;
861
862 if (index < NREADOPS && macreg_readops[index])
863 {
864 uint32_t val = macreg_readops[index](s, index);
865 #ifdef TARGET_WORDS_BIGENDIAN
866 val = bswap32(val);
867 #endif
868 return val;
869 }
870 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
871 return 0;
872 }
873
874 static uint32_t
875 e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
876 {
877 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
878 (8 * (addr & 3))) & 0xff;
879 }
880
881 static uint32_t
882 e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
883 {
884 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
885 (8 * (addr & 3))) & 0xffff;
886 }
887
888 static bool is_version_1(void *opaque, int version_id)
889 {
890 return version_id == 1;
891 }
892
893 static const VMStateDescription vmstate_e1000 = {
894 .name = "e1000",
895 .version_id = 2,
896 .minimum_version_id = 1,
897 .minimum_version_id_old = 1,
898 .fields = (VMStateField []) {
899 VMSTATE_PCI_DEVICE(dev, E1000State),
900 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
901 VMSTATE_UNUSED(4), /* Was mmio_base. */
902 VMSTATE_UINT32(rxbuf_size, E1000State),
903 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
904 VMSTATE_UINT32(eecd_state.val_in, E1000State),
905 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
906 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
907 VMSTATE_UINT16(eecd_state.reading, E1000State),
908 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
909 VMSTATE_UINT8(tx.ipcss, E1000State),
910 VMSTATE_UINT8(tx.ipcso, E1000State),
911 VMSTATE_UINT16(tx.ipcse, E1000State),
912 VMSTATE_UINT8(tx.tucss, E1000State),
913 VMSTATE_UINT8(tx.tucso, E1000State),
914 VMSTATE_UINT16(tx.tucse, E1000State),
915 VMSTATE_UINT32(tx.paylen, E1000State),
916 VMSTATE_UINT8(tx.hdr_len, E1000State),
917 VMSTATE_UINT16(tx.mss, E1000State),
918 VMSTATE_UINT16(tx.size, E1000State),
919 VMSTATE_UINT16(tx.tso_frames, E1000State),
920 VMSTATE_UINT8(tx.sum_needed, E1000State),
921 VMSTATE_INT8(tx.ip, E1000State),
922 VMSTATE_INT8(tx.tcp, E1000State),
923 VMSTATE_BUFFER(tx.header, E1000State),
924 VMSTATE_BUFFER(tx.data, E1000State),
925 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
926 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
927 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
928 VMSTATE_UINT32(mac_reg[EECD], E1000State),
929 VMSTATE_UINT32(mac_reg[EERD], E1000State),
930 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
931 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
932 VMSTATE_UINT32(mac_reg[ICR], E1000State),
933 VMSTATE_UINT32(mac_reg[ICS], E1000State),
934 VMSTATE_UINT32(mac_reg[IMC], E1000State),
935 VMSTATE_UINT32(mac_reg[IMS], E1000State),
936 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
937 VMSTATE_UINT32(mac_reg[MANC], E1000State),
938 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
939 VMSTATE_UINT32(mac_reg[MPC], E1000State),
940 VMSTATE_UINT32(mac_reg[PBA], E1000State),
941 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
942 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
943 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
944 VMSTATE_UINT32(mac_reg[RDH], E1000State),
945 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
946 VMSTATE_UINT32(mac_reg[RDT], E1000State),
947 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
948 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
949 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
950 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
951 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
952 VMSTATE_UINT32(mac_reg[TDH], E1000State),
953 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
954 VMSTATE_UINT32(mac_reg[TDT], E1000State),
955 VMSTATE_UINT32(mac_reg[TORH], E1000State),
956 VMSTATE_UINT32(mac_reg[TORL], E1000State),
957 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
958 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
959 VMSTATE_UINT32(mac_reg[TPR], E1000State),
960 VMSTATE_UINT32(mac_reg[TPT], E1000State),
961 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
962 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
963 VMSTATE_UINT32(mac_reg[VET], E1000State),
964 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
965 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
966 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
967 VMSTATE_END_OF_LIST()
968 }
969 };
970
971 static const uint16_t e1000_eeprom_template[64] = {
972 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
973 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
974 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
975 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
976 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
977 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
978 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
979 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
980 };
981
982 static const uint16_t phy_reg_init[] = {
983 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
984 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
985 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
986 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
987 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
988 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
989 };
990
991 static const uint32_t mac_reg_init[] = {
992 [PBA] = 0x00100030,
993 [LEDCTL] = 0x602,
994 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
995 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
996 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
997 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
998 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
999 E1000_STATUS_LU,
1000 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1001 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1002 E1000_MANC_RMCP_EN,
1003 };
1004
1005 /* PCI interface */
1006
1007 static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
1008 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
1009 };
1010
1011 static CPUReadMemoryFunc * const e1000_mmio_read[] = {
1012 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
1013 };
1014
1015 static void
1016 e1000_mmio_map(PCIDevice *pci_dev, int region_num,
1017 pcibus_t addr, pcibus_t size, int type)
1018 {
1019 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1020 int i;
1021 const uint32_t excluded_regs[] = {
1022 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1023 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1024 };
1025
1026
1027 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
1028 addr, size);
1029
1030 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
1031 qemu_register_coalesced_mmio(addr, excluded_regs[0]);
1032
1033 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1034 qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
1035 excluded_regs[i + 1] -
1036 excluded_regs[i] - 4);
1037 }
1038
1039 static void
1040 e1000_cleanup(VLANClientState *nc)
1041 {
1042 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1043
1044 s->nic = NULL;
1045 }
1046
1047 static int
1048 pci_e1000_uninit(PCIDevice *dev)
1049 {
1050 E1000State *d = DO_UPCAST(E1000State, dev, dev);
1051
1052 cpu_unregister_io_memory(d->mmio_index);
1053 qemu_del_vlan_client(&d->nic->nc);
1054 return 0;
1055 }
1056
1057 static void e1000_reset(void *opaque)
1058 {
1059 E1000State *d = opaque;
1060
1061 memset(d->phy_reg, 0, sizeof d->phy_reg);
1062 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1063 memset(d->mac_reg, 0, sizeof d->mac_reg);
1064 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1065 d->rxbuf_min_shift = 1;
1066 memset(&d->tx, 0, sizeof d->tx);
1067 }
1068
1069 static NetClientInfo net_e1000_info = {
1070 .type = NET_CLIENT_TYPE_NIC,
1071 .size = sizeof(NICState),
1072 .can_receive = e1000_can_receive,
1073 .receive = e1000_receive,
1074 .cleanup = e1000_cleanup,
1075 .link_status_changed = e1000_set_link_status,
1076 };
1077
1078 static int pci_e1000_init(PCIDevice *pci_dev)
1079 {
1080 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1081 uint8_t *pci_conf;
1082 uint16_t checksum = 0;
1083 int i;
1084 uint8_t *macaddr;
1085
1086 pci_conf = d->dev.config;
1087
1088 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1089 pci_config_set_device_id(pci_conf, E1000_DEVID);
1090 *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407);
1091 *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010);
1092 pci_conf[0x08] = 0x03;
1093 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
1094 pci_conf[0x0c] = 0x10;
1095
1096 pci_conf[0x3d] = 1; // interrupt pin 0
1097
1098 d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
1099 e1000_mmio_write, d);
1100
1101 pci_register_bar((PCIDevice *)d, 0, PNPMMIO_SIZE,
1102 PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);
1103
1104 pci_register_bar((PCIDevice *)d, 1, IOPORT_SIZE,
1105 PCI_BASE_ADDRESS_SPACE_IO, ioport_map);
1106
1107 memmove(d->eeprom_data, e1000_eeprom_template,
1108 sizeof e1000_eeprom_template);
1109 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1110 macaddr = d->conf.macaddr.a;
1111 for (i = 0; i < 3; i++)
1112 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
1113 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1114 checksum += d->eeprom_data[i];
1115 checksum = (uint16_t) EEPROM_SUM - checksum;
1116 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1117
1118 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1119 d->dev.qdev.info->name, d->dev.qdev.id, d);
1120
1121 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1122
1123 if (!pci_dev->qdev.hotplugged) {
1124 static int loaded = 0;
1125 if (!loaded) {
1126 rom_add_option("pxe-e1000.bin");
1127 loaded = 1;
1128 }
1129 }
1130 return 0;
1131 }
1132
1133 static void qdev_e1000_reset(DeviceState *dev)
1134 {
1135 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1136 e1000_reset(d);
1137 }
1138
1139 static PCIDeviceInfo e1000_info = {
1140 .qdev.name = "e1000",
1141 .qdev.desc = "Intel Gigabit Ethernet",
1142 .qdev.size = sizeof(E1000State),
1143 .qdev.reset = qdev_e1000_reset,
1144 .qdev.vmsd = &vmstate_e1000,
1145 .init = pci_e1000_init,
1146 .exit = pci_e1000_uninit,
1147 .qdev.props = (Property[]) {
1148 DEFINE_NIC_PROPERTIES(E1000State, conf),
1149 DEFINE_PROP_END_OF_LIST(),
1150 }
1151 };
1152
1153 static void e1000_register_devices(void)
1154 {
1155 pci_qdev_register(&e1000_info);
1156 }
1157
1158 device_init(e1000_register_devices)
Anthony Liguori's QEMU queue