hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "pci.h"
  29 #include "vmware_vga.h"
  30 #include "usb-uhci.h"
  31 #include "usb-ohci.h"
  32 #include "prep_pci.h"
  33 #include "apb_pci.h"
  34 #include "block.h"
  35 #include "sysemu.h"
  36 #include "audio/audio.h"
  37 #include "net.h"
  38 #include "smbus.h"
  39 #include "boards.h"
  40 #include "monitor.h"
  41 #include "fw_cfg.h"
  42 #include "hpet_emul.h"
  43 #include "watchdog.h"
  44 #include "smbios.h"
  45 #include "ide.h"
  46 #include "loader.h"
  47 #include "elf.h"
  48 #include "multiboot.h"
  49 #include "kvm.h"
  50
  51 /* output Bochs bios info messages */
  52 //#define DEBUG_BIOS
  53
  54 #define BIOS_FILENAME "bios.bin"
  55
  56 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  57
  58 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  59 #define ACPI_DATA_SIZE       0x10000
  60 #define BIOS_CFG_IOPORT 0x510
  61 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  62 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  63 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  64 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  65
  66 #define MAX_IDE_BUS 2
  67
  68 #define E820_NR_ENTRIES         16
  69
  70 struct e820_entry {
  71     uint64_t address;
  72     uint64_t length;
  73     uint32_t type;
  74 };
  75
  76 struct e820_table {
  77     uint32_t count;
  78     struct e820_entry entry[E820_NR_ENTRIES];
  79 };
  80
  81 static struct e820_table e820_table;
  82
  83 typedef struct isa_irq_state {
  84     qemu_irq *i8259;
  85     qemu_irq *ioapic;
  86 } IsaIrqState;
  87
  88 static void isa_irq_handler(void *opaque, int n, int level)
  89 {
  90     IsaIrqState *isa = (IsaIrqState *)opaque;
  91
  92     if (n < 16) {
  93         qemu_set_irq(isa->i8259[n], level);
  94     }
  95     if (isa->ioapic)
  96         qemu_set_irq(isa->ioapic[n], level);
  97 };
  98
  99 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 100 {
 101 }
 102
 103 /* MSDOS compatibility mode FPU exception support */
 104 static qemu_irq ferr_irq;
 105
 106 void pc_register_ferr_irq(qemu_irq irq)
 107 {
 108     ferr_irq = irq;
 109 }
 110
 111 /* XXX: add IGNNE support */
 112 void cpu_set_ferr(CPUX86State *s)
 113 {
 114     qemu_irq_raise(ferr_irq);
 115 }
 116
 117 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 118 {
 119     qemu_irq_lower(ferr_irq);
 120 }
 121
 122 /* TSC handling */
 123 uint64_t cpu_get_tsc(CPUX86State *env)
 124 {
 125     return cpu_get_ticks();
 126 }
 127
 128 /* SMM support */
 129
 130 static cpu_set_smm_t smm_set;
 131 static void *smm_arg;
 132
 133 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 134 {
 135     assert(smm_set == NULL);
 136     assert(smm_arg == NULL);
 137     smm_set = callback;
 138     smm_arg = arg;
 139 }
 140
 141 void cpu_smm_update(CPUState *env)
 142 {
 143     if (smm_set && smm_arg && env == first_cpu)
 144         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 145 }
 146
 147
 148 /* IRQ handling */
 149 int cpu_get_pic_interrupt(CPUState *env)
 150 {
 151     int intno;
 152
 153     intno = apic_get_interrupt(env);
 154     if (intno >= 0) {
 155         /* set irq request if a PIC irq is still pending */
 156         /* XXX: improve that */
 157         pic_update_irq(isa_pic);
 158         return intno;
 159     }
 160     /* read the irq from the PIC */
 161     if (!apic_accept_pic_intr(env))
 162         return -1;
 163
 164     intno = pic_read_irq(isa_pic);
 165     return intno;
 166 }
 167
 168 static void pic_irq_request(void *opaque, int irq, int level)
 169 {
 170     CPUState *env = first_cpu;
 171
 172     if (env->apic_state) {
 173         while (env) {
 174             if (apic_accept_pic_intr(env))
 175                 apic_deliver_pic_intr(env, level);
 176             env = env->next_cpu;
 177         }
 178     } else {
 179         if (level)
 180             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 181         else
 182             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 183     }
 184 }
 185
 186 /* PC cmos mappings */
 187
 188 #define REG_EQUIPMENT_BYTE          0x14
 189
 190 static int cmos_get_fd_drive_type(int fd0)
 191 {
 192     int val;
 193
 194     switch (fd0) {
 195     case 0:
 196         /* 1.44 Mb 3"5 drive */
 197         val = 4;
 198         break;
 199     case 1:
 200         /* 2.88 Mb 3"5 drive */
 201         val = 5;
 202         break;
 203     case 2:
 204         /* 1.2 Mb 5"5 drive */
 205         val = 2;
 206         break;
 207     default:
 208         val = 0;
 209         break;
 210     }
 211     return val;
 212 }
 213
 214 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 215                          RTCState *s)
 216 {
 217     int cylinders, heads, sectors;
 218     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 219     rtc_set_memory(s, type_ofs, 47);
 220     rtc_set_memory(s, info_ofs, cylinders);
 221     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 222     rtc_set_memory(s, info_ofs + 2, heads);
 223     rtc_set_memory(s, info_ofs + 3, 0xff);
 224     rtc_set_memory(s, info_ofs + 4, 0xff);
 225     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 226     rtc_set_memory(s, info_ofs + 6, cylinders);
 227     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 228     rtc_set_memory(s, info_ofs + 8, sectors);
 229 }
 230
 231 /* convert boot_device letter to something recognizable by the bios */
 232 static int boot_device2nibble(char boot_device)
 233 {
 234     switch(boot_device) {
 235     case 'a':
 236     case 'b':
 237         return 0x01; /* floppy boot */
 238     case 'c':
 239         return 0x02; /* hard drive boot */
 240     case 'd':
 241         return 0x03; /* CD-ROM boot */
 242     case 'n':
 243         return 0x04; /* Network boot */
 244     }
 245     return 0;
 246 }
 247
 248 static int set_boot_dev(RTCState *s, const char *boot_device, int fd_bootchk)
 249 {
 250 #define PC_MAX_BOOT_DEVICES 3
 251     int nbds, bds[3] = { 0, };
 252     int i;
 253
 254     nbds = strlen(boot_device);
 255     if (nbds > PC_MAX_BOOT_DEVICES) {
 256         error_report("Too many boot devices for PC");
 257         return(1);
 258     }
 259     for (i = 0; i < nbds; i++) {
 260         bds[i] = boot_device2nibble(boot_device[i]);
 261         if (bds[i] == 0) {
 262             error_report("Invalid boot device for PC: '%c'",
 263                          boot_device[i]);
 264             return(1);
 265         }
 266     }
 267     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 268     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 269     return(0);
 270 }
 271
 272 static int pc_boot_set(void *opaque, const char *boot_device)
 273 {
 274     return set_boot_dev(opaque, boot_device, 0);
 275 }
 276
 277 /* hd_table must contain 4 block drivers */
 278 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 279                       const char *boot_device, DriveInfo **hd_table,
 280                       FDCtrl *floppy_controller, RTCState *s)
 281 {
 282     int val;
 283     int fd0, fd1, nb;
 284     int i;
 285
 286     /* various important CMOS locations needed by PC/Bochs bios */
 287
 288     /* memory size */
 289     val = 640; /* base memory in K */
 290     rtc_set_memory(s, 0x15, val);
 291     rtc_set_memory(s, 0x16, val >> 8);
 292
 293     val = (ram_size / 1024) - 1024;
 294     if (val > 65535)
 295         val = 65535;
 296     rtc_set_memory(s, 0x17, val);
 297     rtc_set_memory(s, 0x18, val >> 8);
 298     rtc_set_memory(s, 0x30, val);
 299     rtc_set_memory(s, 0x31, val >> 8);
 300
 301     if (above_4g_mem_size) {
 302         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 303         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 304         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 305     }
 306
 307     if (ram_size > (16 * 1024 * 1024))
 308         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 309     else
 310         val = 0;
 311     if (val > 65535)
 312         val = 65535;
 313     rtc_set_memory(s, 0x34, val);
 314     rtc_set_memory(s, 0x35, val >> 8);
 315
 316     /* set the number of CPU */
 317     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 318
 319     /* set boot devices, and disable floppy signature check if requested */
 320     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 321         exit(1);
 322     }
 323
 324     /* floppy type */
 325
 326     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 327     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 328
 329     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 330     rtc_set_memory(s, 0x10, val);
 331
 332     val = 0;
 333     nb = 0;
 334     if (fd0 < 3)
 335         nb++;
 336     if (fd1 < 3)
 337         nb++;
 338     switch (nb) {
 339     case 0:
 340         break;
 341     case 1:
 342         val |= 0x01; /* 1 drive, ready for boot */
 343         break;
 344     case 2:
 345         val |= 0x41; /* 2 drives, ready for boot */
 346         break;
 347     }
 348     val |= 0x02; /* FPU is there */
 349     val |= 0x04; /* PS/2 mouse installed */
 350     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 351
 352     /* hard drives */
 353
 354     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 355     if (hd_table[0])
 356         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv, s);
 357     if (hd_table[1])
 358         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv, s);
 359
 360     val = 0;
 361     for (i = 0; i < 4; i++) {
 362         if (hd_table[i]) {
 363             int cylinders, heads, sectors, translation;
 364             /* NOTE: bdrv_get_geometry_hint() returns the physical
 365                 geometry.  It is always such that: 1 <= sects <= 63, 1
 366                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 367                 geometry can be different if a translation is done. */
 368             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 369             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 370                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 371                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 372                     /* No translation. */
 373                     translation = 0;
 374                 } else {
 375                     /* LBA translation. */
 376                     translation = 1;
 377                 }
 378             } else {
 379                 translation--;
 380             }
 381             val |= translation << (i * 2);
 382         }
 383     }
 384     rtc_set_memory(s, 0x39, val);
 385 }
 386
 387 void ioport_set_a20(int enable)
 388 {
 389     /* XXX: send to all CPUs ? */
 390     cpu_x86_set_a20(first_cpu, enable);
 391 }
 392
 393 int ioport_get_a20(void)
 394 {
 395     return ((first_cpu->a20_mask >> 20) & 1);
 396 }
 397
 398 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 399 {
 400     ioport_set_a20((val >> 1) & 1);
 401     /* XXX: bit 0 is fast reset */
 402 }
 403
 404 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 405 {
 406     return ioport_get_a20() << 1;
 407 }
 408
 409 /***********************************************************/
 410 /* Bochs BIOS debug ports */
 411
 412 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 413 {
 414     static const char shutdown_str[8] = "Shutdown";
 415     static int shutdown_index = 0;
 416
 417     switch(addr) {
 418         /* Bochs BIOS messages */
 419     case 0x400:
 420     case 0x401:
 421         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 422         exit(1);
 423     case 0x402:
 424     case 0x403:
 425 #ifdef DEBUG_BIOS
 426         fprintf(stderr, "%c", val);
 427 #endif
 428         break;
 429     case 0x8900:
 430         /* same as Bochs power off */
 431         if (val == shutdown_str[shutdown_index]) {
 432             shutdown_index++;
 433             if (shutdown_index == 8) {
 434                 shutdown_index = 0;
 435                 qemu_system_shutdown_request();
 436             }
 437         } else {
 438             shutdown_index = 0;
 439         }
 440         break;
 441
 442         /* LGPL'ed VGA BIOS messages */
 443     case 0x501:
 444     case 0x502:
 445         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 446         exit(1);
 447     case 0x500:
 448     case 0x503:
 449 #ifdef DEBUG_BIOS
 450         fprintf(stderr, "%c", val);
 451 #endif
 452         break;
 453     }
 454 }
 455
 456 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 457 {
 458     int index = e820_table.count;
 459     struct e820_entry *entry;
 460
 461     if (index >= E820_NR_ENTRIES)
 462         return -EBUSY;
 463     entry = &e820_table.entry[index];
 464
 465     entry->address = address;
 466     entry->length = length;
 467     entry->type = type;
 468
 469     e820_table.count++;
 470     return e820_table.count;
 471 }
 472
 473 static void *bochs_bios_init(void)
 474 {
 475     void *fw_cfg;
 476     uint8_t *smbios_table;
 477     size_t smbios_len;
 478     uint64_t *numa_fw_cfg;
 479     int i, j;
 480
 481     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 482     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 483     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 484     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 485     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 486
 487     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 488     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 489     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 490     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 491
 492     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 493
 494     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 495     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 496     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 497                      acpi_tables_len);
 498     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 499
 500     smbios_table = smbios_get_table(&smbios_len);
 501     if (smbios_table)
 502         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 503                          smbios_table, smbios_len);
 504     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 505                      sizeof(struct e820_table));
 506
 507     /* allocate memory for the NUMA channel: one (64bit) word for the number
 508      * of nodes, one word for each VCPU->node and one word for each node to
 509      * hold the amount of memory.
 510      */
 511     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 512     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 513     for (i = 0; i < smp_cpus; i++) {
 514         for (j = 0; j < nb_numa_nodes; j++) {
 515             if (node_cpumask[j] & (1 << i)) {
 516                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 517                 break;
 518             }
 519         }
 520     }
 521     for (i = 0; i < nb_numa_nodes; i++) {
 522         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 523     }
 524     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 525                      (1 + smp_cpus + nb_numa_nodes) * 8);
 526
 527     return fw_cfg;
 528 }
 529
 530 static long get_file_size(FILE *f)
 531 {
 532     long where, size;
 533
 534     /* XXX: on Unix systems, using fstat() probably makes more sense */
 535
 536     where = ftell(f);
 537     fseek(f, 0, SEEK_END);
 538     size = ftell(f);
 539     fseek(f, where, SEEK_SET);
 540
 541     return size;
 542 }
 543
 544 static void load_linux(void *fw_cfg,
 545                        const char *kernel_filename,
 546                        const char *initrd_filename,
 547                        const char *kernel_cmdline,
 548                        target_phys_addr_t max_ram_size)
 549 {
 550     uint16_t protocol;
 551     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 552     uint32_t initrd_max;
 553     uint8_t header[8192], *setup, *kernel, *initrd_data;
 554     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 555     FILE *f;
 556     char *vmode;
 557
 558     /* Align to 16 bytes as a paranoia measure */
 559     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 560
 561     /* load the kernel header */
 562     f = fopen(kernel_filename, "rb");
 563     if (!f || !(kernel_size = get_file_size(f)) ||
 564         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 565         MIN(ARRAY_SIZE(header), kernel_size)) {
 566         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 567                 kernel_filename, strerror(errno));
 568         exit(1);
 569     }
 570
 571     /* kernel protocol version */
 572 #if 0
 573     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 574 #endif
 575     if (ldl_p(header+0x202) == 0x53726448)
 576         protocol = lduw_p(header+0x206);
 577     else {
 578         /* This looks like a multiboot kernel. If it is, let's stop
 579            treating it like a Linux kernel. */
 580         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 581                            kernel_cmdline, kernel_size, header))
 582             return;
 583         protocol = 0;
 584     }
 585
 586     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 587         /* Low kernel */
 588         real_addr    = 0x90000;
 589         cmdline_addr = 0x9a000 - cmdline_size;
 590         prot_addr    = 0x10000;
 591     } else if (protocol < 0x202) {
 592         /* High but ancient kernel */
 593         real_addr    = 0x90000;
 594         cmdline_addr = 0x9a000 - cmdline_size;
 595         prot_addr    = 0x100000;
 596     } else {
 597         /* High and recent kernel */
 598         real_addr    = 0x10000;
 599         cmdline_addr = 0x20000;
 600         prot_addr    = 0x100000;
 601     }
 602
 603 #if 0
 604     fprintf(stderr,
 605             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 606             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 607             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 608             real_addr,
 609             cmdline_addr,
 610             prot_addr);
 611 #endif
 612
 613     /* highest address for loading the initrd */
 614     if (protocol >= 0x203)
 615         initrd_max = ldl_p(header+0x22c);
 616     else
 617         initrd_max = 0x37ffffff;
 618
 619     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 620         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 621
 622     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 623     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 624     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 625                      (uint8_t*)strdup(kernel_cmdline),
 626                      strlen(kernel_cmdline)+1);
 627
 628     if (protocol >= 0x202) {
 629         stl_p(header+0x228, cmdline_addr);
 630     } else {
 631         stw_p(header+0x20, 0xA33F);
 632         stw_p(header+0x22, cmdline_addr-real_addr);
 633     }
 634
 635     /* handle vga= parameter */
 636     vmode = strstr(kernel_cmdline, "vga=");
 637     if (vmode) {
 638         unsigned int video_mode;
 639         /* skip "vga=" */
 640         vmode += 4;
 641         if (!strncmp(vmode, "normal", 6)) {
 642             video_mode = 0xffff;
 643         } else if (!strncmp(vmode, "ext", 3)) {
 644             video_mode = 0xfffe;
 645         } else if (!strncmp(vmode, "ask", 3)) {
 646             video_mode = 0xfffd;
 647         } else {
 648             video_mode = strtol(vmode, NULL, 0);
 649         }
 650         stw_p(header+0x1fa, video_mode);
 651     }
 652
 653     /* loader type */
 654     /* High nybble = B reserved for Qemu; low nybble is revision number.
 655        If this code is substantially changed, you may want to consider
 656        incrementing the revision. */
 657     if (protocol >= 0x200)
 658         header[0x210] = 0xB0;
 659
 660     /* heap */
 661     if (protocol >= 0x201) {
 662         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 663         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 664     }
 665
 666     /* load initrd */
 667     if (initrd_filename) {
 668         if (protocol < 0x200) {
 669             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 670             exit(1);
 671         }
 672
 673         initrd_size = get_image_size(initrd_filename);
 674         if (initrd_size < 0) {
 675             fprintf(stderr, "qemu: error reading initrd %s\n",
 676                     initrd_filename);
 677             exit(1);
 678         }
 679
 680         initrd_addr = (initrd_max-initrd_size) & ~4095;
 681
 682         initrd_data = qemu_malloc(initrd_size);
 683         load_image(initrd_filename, initrd_data);
 684
 685         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 686         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 687         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 688
 689         stl_p(header+0x218, initrd_addr);
 690         stl_p(header+0x21c, initrd_size);
 691     }
 692
 693     /* load kernel and setup */
 694     setup_size = header[0x1f1];
 695     if (setup_size == 0)
 696         setup_size = 4;
 697     setup_size = (setup_size+1)*512;
 698     kernel_size -= setup_size;
 699
 700     setup  = qemu_malloc(setup_size);
 701     kernel = qemu_malloc(kernel_size);
 702     fseek(f, 0, SEEK_SET);
 703     if (fread(setup, 1, setup_size, f) != setup_size) {
 704         fprintf(stderr, "fread() failed\n");
 705         exit(1);
 706     }
 707     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 708         fprintf(stderr, "fread() failed\n");
 709         exit(1);
 710     }
 711     fclose(f);
 712     memcpy(setup, header, MIN(sizeof(header), setup_size));
 713
 714     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 715     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 716     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 717
 718     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 719     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 720     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 721
 722     option_rom[nb_option_roms] = "linuxboot.bin";
 723     nb_option_roms++;
 724 }
 725
 726 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 727 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 728 static const int ide_irq[2] = { 14, 15 };
 729
 730 #define NE2000_NB_MAX 6
 731
 732 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 733                                               0x280, 0x380 };
 734 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 735
 736 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 737 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 738
 739 #ifdef HAS_AUDIO
 740 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 741 {
 742     struct soundhw *c;
 743
 744     for (c = soundhw; c->name; ++c) {
 745         if (c->enabled) {
 746             if (c->isa) {
 747                 c->init.init_isa(pic);
 748             } else {
 749                 if (pci_bus) {
 750                     c->init.init_pci(pci_bus);
 751                 }
 752             }
 753         }
 754     }
 755 }
 756 #endif
 757
 758 static void pc_init_ne2k_isa(NICInfo *nd)
 759 {
 760     static int nb_ne2k = 0;
 761
 762     if (nb_ne2k == NE2000_NB_MAX)
 763         return;
 764     isa_ne2000_init(ne2000_io[nb_ne2k],
 765                     ne2000_irq[nb_ne2k], nd);
 766     nb_ne2k++;
 767 }
 768
 769 int cpu_is_bsp(CPUState *env)
 770 {
 771     /* We hard-wire the BSP to the first CPU. */
 772     return env->cpu_index == 0;
 773 }
 774
 775 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 776    BIOS will read it and start S3 resume at POST Entry */
 777 static void cmos_set_s3_resume(void *opaque, int irq, int level)
 778 {
 779     RTCState *s = opaque;
 780
 781     if (level) {
 782         rtc_set_memory(s, 0xF, 0xFE);
 783     }
 784 }
 785
 786 static void acpi_smi_interrupt(void *opaque, int irq, int level)
 787 {
 788     CPUState *s = opaque;
 789
 790     if (level) {
 791         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 792     }
 793 }
 794
 795 static CPUState *pc_new_cpu(const char *cpu_model)
 796 {
 797     CPUState *env;
 798
 799     env = cpu_init(cpu_model);
 800     if (!env) {
 801         fprintf(stderr, "Unable to find x86 CPU definition\n");
 802         exit(1);
 803     }
 804     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 805         env->cpuid_apic_id = env->cpu_index;
 806         /* APIC reset callback resets cpu */
 807         apic_init(env);
 808     } else {
 809         qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
 810     }
 811     return env;
 812 }
 813
 814 static void pc_cpus_init(const char *cpu_model)
 815 {
 816     int i;
 817
 818     /* init CPUs */
 819     if (cpu_model == NULL) {
 820 #ifdef TARGET_X86_64
 821         cpu_model = "qemu64";
 822 #else
 823         cpu_model = "qemu32";
 824 #endif
 825     }
 826
 827     for(i = 0; i < smp_cpus; i++) {
 828         pc_new_cpu(cpu_model);
 829     }
 830 }
 831
 832 static qemu_irq *pc_allocate_cpu_irq(void)
 833 {
 834     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 835 }
 836
 837 static void pc_memory_init(ram_addr_t ram_size,
 838                            const char *kernel_filename,
 839                            const char *kernel_cmdline,
 840                            const char *initrd_filename,
 841                            ram_addr_t *below_4g_mem_size_p,
 842                            ram_addr_t *above_4g_mem_size_p)
 843 {
 844     char *filename;
 845     int ret, linux_boot, i;
 846     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 847     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 848     int bios_size, isa_bios_size;
 849     void **fw_cfg;
 850
 851     if (ram_size >= 0xe0000000 ) {
 852         above_4g_mem_size = ram_size - 0xe0000000;
 853         below_4g_mem_size = 0xe0000000;
 854     } else {
 855         below_4g_mem_size = ram_size;
 856     }
 857     *above_4g_mem_size_p = above_4g_mem_size;
 858     *below_4g_mem_size_p = below_4g_mem_size;
 859
 860     linux_boot = (kernel_filename != NULL);
 861
 862     /* allocate RAM */
 863     ram_addr = qemu_ram_alloc(below_4g_mem_size);
 864     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 865     cpu_register_physical_memory(0x100000,
 866                  below_4g_mem_size - 0x100000,
 867                  ram_addr + 0x100000);
 868
 869     /* above 4giga memory allocation */
 870     if (above_4g_mem_size > 0) {
 871 #if TARGET_PHYS_ADDR_BITS == 32
 872         hw_error("To much RAM for 32-bit physical address");
 873 #else
 874         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 875         cpu_register_physical_memory(0x100000000ULL,
 876                                      above_4g_mem_size,
 877                                      ram_addr);
 878 #endif
 879     }
 880
 881
 882     /* BIOS load */
 883     if (bios_name == NULL)
 884         bios_name = BIOS_FILENAME;
 885     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 886     if (filename) {
 887         bios_size = get_image_size(filename);
 888     } else {
 889         bios_size = -1;
 890     }
 891     if (bios_size <= 0 ||
 892         (bios_size % 65536) != 0) {
 893         goto bios_error;
 894     }
 895     bios_offset = qemu_ram_alloc(bios_size);
 896     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 897     if (ret != 0) {
 898     bios_error:
 899         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 900         exit(1);
 901     }
 902     if (filename) {
 903         qemu_free(filename);
 904     }
 905     /* map the last 128KB of the BIOS in ISA space */
 906     isa_bios_size = bios_size;
 907     if (isa_bios_size > (128 * 1024))
 908         isa_bios_size = 128 * 1024;
 909     cpu_register_physical_memory(0x100000 - isa_bios_size,
 910                                  isa_bios_size,
 911                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 912
 913     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
 914     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 915
 916     /* map all the bios at the top of memory */
 917     cpu_register_physical_memory((uint32_t)(-bios_size),
 918                                  bios_size, bios_offset | IO_MEM_ROM);
 919
 920     fw_cfg = bochs_bios_init();
 921     rom_set_fw(fw_cfg);
 922
 923     if (linux_boot) {
 924         load_linux(*fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 925     }
 926
 927     for (i = 0; i < nb_option_roms; i++) {
 928         rom_add_option(option_rom[i]);
 929     }
 930 }
 931
 932 static void pc_vga_init(PCIBus *pci_bus)
 933 {
 934     if (cirrus_vga_enabled) {
 935         if (pci_bus) {
 936             pci_cirrus_vga_init(pci_bus);
 937         } else {
 938             isa_cirrus_vga_init();
 939         }
 940     } else if (vmsvga_enabled) {
 941         if (pci_bus)
 942             pci_vmsvga_init(pci_bus);
 943         else
 944             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 945     } else if (std_vga_enabled) {
 946         if (pci_bus) {
 947             pci_vga_init(pci_bus, 0, 0);
 948         } else {
 949             isa_vga_init();
 950         }
 951     }
 952 }
 953
 954 static void pc_basic_device_init(qemu_irq *isa_irq,
 955                                  FDCtrl **floppy_controller,
 956                                  RTCState **rtc_state)
 957 {
 958     int i;
 959     DriveInfo *fd[MAX_FD];
 960     PITState *pit;
 961
 962     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 963
 964     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 965
 966     *rtc_state = rtc_init(2000);
 967
 968     qemu_register_boot_set(pc_boot_set, *rtc_state);
 969
 970     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
 971     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
 972
 973     pit = pit_init(0x40, isa_reserve_irq(0));
 974     pcspk_init(pit);
 975     if (!no_hpet) {
 976         hpet_init(isa_irq);
 977     }
 978
 979     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 980         if (serial_hds[i]) {
 981             serial_isa_init(i, serial_hds[i]);
 982         }
 983     }
 984
 985     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 986         if (parallel_hds[i]) {
 987             parallel_init(i, parallel_hds[i]);
 988         }
 989     }
 990
 991     isa_create_simple("i8042");
 992     DMA_init(0);
 993
 994     for(i = 0; i < MAX_FD; i++) {
 995         fd[i] = drive_get(IF_FLOPPY, 0, i);
 996     }
 997     *floppy_controller = fdctrl_init_isa(fd);
 998 }
 999
1000 static void pc_pci_device_init(PCIBus *pci_bus)
1001 {
1002     int max_bus;
1003     int bus;
1004
1005     max_bus = drive_get_max_bus(IF_SCSI);
1006     for (bus = 0; bus <= max_bus; bus++) {
1007         pci_create_simple(pci_bus, -1, "lsi53c895a");
1008     }
1009 }
1010
1011 /* PC hardware initialisation */
1012 static void pc_init1(ram_addr_t ram_size,
1013                      const char *boot_device,
1014                      const char *kernel_filename,
1015                      const char *kernel_cmdline,
1016                      const char *initrd_filename,
1017                      const char *cpu_model,
1018                      int pci_enabled)
1019 {
1020     int i;
1021     ram_addr_t below_4g_mem_size, above_4g_mem_size;
1022     PCIBus *pci_bus;
1023     PCII440FXState *i440fx_state;
1024     int piix3_devfn = -1;
1025     qemu_irq *cpu_irq;
1026     qemu_irq *isa_irq;
1027     qemu_irq *i8259;
1028     qemu_irq *cmos_s3;
1029     qemu_irq *smi_irq;
1030     IsaIrqState *isa_irq_state;
1031     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
1032     FDCtrl *floppy_controller;
1033     RTCState *rtc_state;
1034
1035     pc_cpus_init(cpu_model);
1036
1037     vmport_init();
1038
1039     /* allocate ram and load rom/bios */
1040     pc_memory_init(ram_size, kernel_filename, kernel_cmdline, initrd_filename,
1041                    &below_4g_mem_size, &above_4g_mem_size);
1042
1043     cpu_irq = pc_allocate_cpu_irq();
1044     i8259 = i8259_init(cpu_irq[0]);
1045     isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
1046     isa_irq_state->i8259 = i8259;
1047     if (pci_enabled) {
1048         isa_irq_state->ioapic = ioapic_init();
1049     }
1050     isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
1051
1052     if (pci_enabled) {
1053         pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size);
1054     } else {
1055         pci_bus = NULL;
1056         isa_bus_new(NULL);
1057     }
1058     isa_bus_irqs(isa_irq);
1059
1060     pc_register_ferr_irq(isa_reserve_irq(13));
1061
1062     pc_vga_init(pci_enabled? pci_bus: NULL);
1063
1064     /* init basic PC hardware */
1065     pc_basic_device_init(isa_irq, &floppy_controller, &rtc_state);
1066
1067     for(i = 0; i < nb_nics; i++) {
1068         NICInfo *nd = &nd_table[i];
1069
1070         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1071             pc_init_ne2k_isa(nd);
1072         else
1073             pci_nic_init_nofail(nd, "e1000", NULL);
1074     }
1075
1076     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1077         fprintf(stderr, "qemu: too many IDE bus\n");
1078         exit(1);
1079     }
1080
1081     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1082         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1083     }
1084
1085     if (pci_enabled) {
1086         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
1087     } else {
1088         for(i = 0; i < MAX_IDE_BUS; i++) {
1089             isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
1090                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1091         }
1092     }
1093
1094 #ifdef HAS_AUDIO
1095     audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
1096 #endif
1097
1098     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd,
1099               floppy_controller, rtc_state);
1100
1101     if (pci_enabled && usb_enabled) {
1102         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1103     }
1104
1105     if (pci_enabled && acpi_enabled) {
1106         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1107         i2c_bus *smbus;
1108
1109         cmos_s3 = qemu_allocate_irqs(cmos_set_s3_resume, rtc_state, 1);
1110         smi_irq = qemu_allocate_irqs(acpi_smi_interrupt, first_cpu, 1);
1111         /* TODO: Populate SPD eeprom data.  */
1112         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1113                               isa_reserve_irq(9), *cmos_s3, *smi_irq,
1114                               kvm_enabled());
1115         for (i = 0; i < 8; i++) {
1116             DeviceState *eeprom;
1117             eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1118             qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
1119             qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1120             qdev_init_nofail(eeprom);
1121         }
1122         piix4_acpi_system_hot_add_init(pci_bus);
1123     }
1124
1125     if (i440fx_state) {
1126         i440fx_init_memory_mappings(i440fx_state);
1127     }
1128
1129     if (pci_enabled) {
1130         pc_pci_device_init(pci_bus);
1131     }
1132 }
1133
1134 static void pc_init_pci(ram_addr_t ram_size,
1135                         const char *boot_device,
1136                         const char *kernel_filename,
1137                         const char *kernel_cmdline,
1138                         const char *initrd_filename,
1139                         const char *cpu_model)
1140 {
1141     pc_init1(ram_size, boot_device,
1142              kernel_filename, kernel_cmdline,
1143              initrd_filename, cpu_model, 1);
1144 }
1145
1146 static void pc_init_isa(ram_addr_t ram_size,
1147                         const char *boot_device,
1148                         const char *kernel_filename,
1149                         const char *kernel_cmdline,
1150                         const char *initrd_filename,
1151                         const char *cpu_model)
1152 {
1153     if (cpu_model == NULL)
1154         cpu_model = "486";
1155     pc_init1(ram_size, boot_device,
1156              kernel_filename, kernel_cmdline,
1157              initrd_filename, cpu_model, 0);
1158 }
1159
1160 static QEMUMachine pc_machine = {
1161     .name = "pc-0.13",
1162     .alias = "pc",
1163     .desc = "Standard PC",
1164     .init = pc_init_pci,
1165     .max_cpus = 255,
1166     .is_default = 1,
1167 };
1168
1169 static QEMUMachine pc_machine_v0_12 = {
1170     .name = "pc-0.12",
1171     .desc = "Standard PC",
1172     .init = pc_init_pci,
1173     .max_cpus = 255,
1174     .compat_props = (GlobalProperty[]) {
1175         {
1176             .driver   = "virtio-serial-pci",
1177             .property = "max_nr_ports",
1178             .value    = stringify(1),
1179         },{
1180             .driver   = "virtio-serial-pci",
1181             .property = "vectors",
1182             .value    = stringify(0),
1183         },
1184         { /* end of list */ }
1185     }
1186 };
1187
1188 static QEMUMachine pc_machine_v0_11 = {
1189     .name = "pc-0.11",
1190     .desc = "Standard PC, qemu 0.11",
1191     .init = pc_init_pci,
1192     .max_cpus = 255,
1193     .compat_props = (GlobalProperty[]) {
1194         {
1195             .driver   = "virtio-blk-pci",
1196             .property = "vectors",
1197             .value    = stringify(0),
1198         },{
1199             .driver   = "virtio-serial-pci",
1200             .property = "max_nr_ports",
1201             .value    = stringify(1),
1202         },{
1203             .driver   = "virtio-serial-pci",
1204             .property = "vectors",
1205             .value    = stringify(0),
1206         },{
1207             .driver   = "ide-drive",
1208             .property = "ver",
1209             .value    = "0.11",
1210         },{
1211             .driver   = "scsi-disk",
1212             .property = "ver",
1213             .value    = "0.11",
1214         },{
1215             .driver   = "PCI",
1216             .property = "rombar",
1217             .value    = stringify(0),
1218         },
1219         { /* end of list */ }
1220     }
1221 };
1222
1223 static QEMUMachine pc_machine_v0_10 = {
1224     .name = "pc-0.10",
1225     .desc = "Standard PC, qemu 0.10",
1226     .init = pc_init_pci,
1227     .max_cpus = 255,
1228     .compat_props = (GlobalProperty[]) {
1229         {
1230             .driver   = "virtio-blk-pci",
1231             .property = "class",
1232             .value    = stringify(PCI_CLASS_STORAGE_OTHER),
1233         },{
1234             .driver   = "virtio-serial-pci",
1235             .property = "class",
1236             .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
1237         },{
1238             .driver   = "virtio-serial-pci",
1239             .property = "max_nr_ports",
1240             .value    = stringify(1),
1241         },{
1242             .driver   = "virtio-serial-pci",
1243             .property = "vectors",
1244             .value    = stringify(0),
1245         },{
1246             .driver   = "virtio-net-pci",
1247             .property = "vectors",
1248             .value    = stringify(0),
1249         },{
1250             .driver   = "virtio-blk-pci",
1251             .property = "vectors",
1252             .value    = stringify(0),
1253         },{
1254             .driver   = "ide-drive",
1255             .property = "ver",
1256             .value    = "0.10",
1257         },{
1258             .driver   = "scsi-disk",
1259             .property = "ver",
1260             .value    = "0.10",
1261         },{
1262             .driver   = "PCI",
1263             .property = "rombar",
1264             .value    = stringify(0),
1265         },
1266         { /* end of list */ }
1267     },
1268 };
1269
1270 static QEMUMachine isapc_machine = {
1271     .name = "isapc",
1272     .desc = "ISA-only PC",
1273     .init = pc_init_isa,
1274     .max_cpus = 1,
1275 };
1276
1277 static void pc_machine_init(void)
1278 {
1279     qemu_register_machine(&pc_machine);
1280     qemu_register_machine(&pc_machine_v0_12);
1281     qemu_register_machine(&pc_machine_v0_11);
1282     qemu_register_machine(&pc_machine_v0_10);
1283     qemu_register_machine(&isapc_machine);
1284 }
1285
1286 machine_init(pc_machine_init);