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target-alpha: Reduce internal processor registers for user-mode.
[qemu/aliguori-queue.git] / target-ppc / helper.c
blobcd1c9fea0ec0f11448f4e609e54508343f413f70
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "helper_regs.h"
29 #include "qemu-common.h"
30 #include "kvm.h"
31
32 //#define DEBUG_MMU
33 //#define DEBUG_BATS
34 //#define DEBUG_SLB
35 //#define DEBUG_SOFTWARE_TLB
36 //#define DUMP_PAGE_TABLES
37 //#define DEBUG_EXCEPTIONS
38 //#define FLUSH_ALL_TLBS
39
40 #ifdef DEBUG_MMU
41 # define LOG_MMU(...) qemu_log(__VA_ARGS__)
42 # define LOG_MMU_STATE(env) log_cpu_state((env), 0)
43 #else
44 # define LOG_MMU(...) do { } while (0)
45 # define LOG_MMU_STATE(...) do { } while (0)
46 #endif
47
48
49 #ifdef DEBUG_SOFTWARE_TLB
50 # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
51 #else
52 # define LOG_SWTLB(...) do { } while (0)
53 #endif
54
55 #ifdef DEBUG_BATS
56 # define LOG_BATS(...) qemu_log(__VA_ARGS__)
57 #else
58 # define LOG_BATS(...) do { } while (0)
59 #endif
60
61 #ifdef DEBUG_SLB
62 # define LOG_SLB(...) qemu_log(__VA_ARGS__)
63 #else
64 # define LOG_SLB(...) do { } while (0)
65 #endif
66
67 #ifdef DEBUG_EXCEPTIONS
68 # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
69 #else
70 # define LOG_EXCP(...) do { } while (0)
71 #endif
72
73
74 /*****************************************************************************/
75 /* PowerPC MMU emulation */
76
77 #if defined(CONFIG_USER_ONLY)
78 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
79 int mmu_idx, int is_softmmu)
80 {
81 int exception, error_code;
82
83 if (rw == 2) {
84 exception = POWERPC_EXCP_ISI;
85 error_code = 0x40000000;
86 } else {
87 exception = POWERPC_EXCP_DSI;
88 error_code = 0x40000000;
89 if (rw)
90 error_code |= 0x02000000;
91 env->spr[SPR_DAR] = address;
92 env->spr[SPR_DSISR] = error_code;
93 }
94 env->exception_index = exception;
95 env->error_code = error_code;
96
97 return 1;
98 }
99
100 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
101 {
102 return addr;
103 }
104
105 #else
106 /* Common routines used by software and hardware TLBs emulation */
107 static inline int pte_is_valid(target_ulong pte0)
108 {
109 return pte0 & 0x80000000 ? 1 : 0;
110 }
111
112 static inline void pte_invalidate(target_ulong *pte0)
113 {
114 *pte0 &= ~0x80000000;
115 }
116
117 #if defined(TARGET_PPC64)
118 static inline int pte64_is_valid(target_ulong pte0)
119 {
120 return pte0 & 0x0000000000000001ULL ? 1 : 0;
121 }
122
123 static inline void pte64_invalidate(target_ulong *pte0)
124 {
125 *pte0 &= ~0x0000000000000001ULL;
126 }
127 #endif
128
129 #define PTE_PTEM_MASK 0x7FFFFFBF
130 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
131 #if defined(TARGET_PPC64)
132 #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
133 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
134 #endif
135
136 static inline int pp_check(int key, int pp, int nx)
137 {
138 int access;
139
140 /* Compute access rights */
141 /* When pp is 3/7, the result is undefined. Set it to noaccess */
142 access = 0;
143 if (key == 0) {
144 switch (pp) {
145 case 0x0:
146 case 0x1:
147 case 0x2:
148 access |= PAGE_WRITE;
149 /* No break here */
150 case 0x3:
151 case 0x6:
152 access |= PAGE_READ;
153 break;
154 }
155 } else {
156 switch (pp) {
157 case 0x0:
158 case 0x6:
159 access = 0;
160 break;
161 case 0x1:
162 case 0x3:
163 access = PAGE_READ;
164 break;
165 case 0x2:
166 access = PAGE_READ | PAGE_WRITE;
167 break;
168 }
169 }
170 if (nx == 0)
171 access |= PAGE_EXEC;
172
173 return access;
174 }
175
176 static inline int check_prot(int prot, int rw, int access_type)
177 {
178 int ret;
179
180 if (access_type == ACCESS_CODE) {
181 if (prot & PAGE_EXEC)
182 ret = 0;
183 else
184 ret = -2;
185 } else if (rw) {
186 if (prot & PAGE_WRITE)
187 ret = 0;
188 else
189 ret = -2;
190 } else {
191 if (prot & PAGE_READ)
192 ret = 0;
193 else
194 ret = -2;
195 }
196
197 return ret;
198 }
199
200 static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
201 target_ulong pte1, int h, int rw, int type)
202 {
203 target_ulong ptem, mmask;
204 int access, ret, pteh, ptev, pp;
205
206 access = 0;
207 ret = -1;
208 /* Check validity and table match */
209 #if defined(TARGET_PPC64)
210 if (is_64b) {
211 ptev = pte64_is_valid(pte0);
212 pteh = (pte0 >> 1) & 1;
213 } else
214 #endif
215 {
216 ptev = pte_is_valid(pte0);
217 pteh = (pte0 >> 6) & 1;
218 }
219 if (ptev && h == pteh) {
220 /* Check vsid & api */
221 #if defined(TARGET_PPC64)
222 if (is_64b) {
223 ptem = pte0 & PTE64_PTEM_MASK;
224 mmask = PTE64_CHECK_MASK;
225 pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
226 ctx->nx = (pte1 >> 2) & 1; /* No execute bit */
227 ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
228 } else
229 #endif
230 {
231 ptem = pte0 & PTE_PTEM_MASK;
232 mmask = PTE_CHECK_MASK;
233 pp = pte1 & 0x00000003;
234 }
235 if (ptem == ctx->ptem) {
236 if (ctx->raddr != (target_phys_addr_t)-1ULL) {
237 /* all matches should have equal RPN, WIMG & PP */
238 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
239 qemu_log("Bad RPN/WIMG/PP\n");
240 return -3;
241 }
242 }
243 /* Compute access rights */
244 access = pp_check(ctx->key, pp, ctx->nx);
245 /* Keep the matching PTE informations */
246 ctx->raddr = pte1;
247 ctx->prot = access;
248 ret = check_prot(ctx->prot, rw, type);
249 if (ret == 0) {
250 /* Access granted */
251 LOG_MMU("PTE access granted !\n");
252 } else {
253 /* Access right violation */
254 LOG_MMU("PTE access rejected\n");
255 }
256 }
257 }
258
259 return ret;
260 }
261
262 static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
263 target_ulong pte1, int h, int rw, int type)
264 {
265 return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
266 }
267
268 #if defined(TARGET_PPC64)
269 static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
270 target_ulong pte1, int h, int rw, int type)
271 {
272 return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
273 }
274 #endif
275
276 static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
277 int ret, int rw)
278 {
279 int store = 0;
280
281 /* Update page flags */
282 if (!(*pte1p & 0x00000100)) {
283 /* Update accessed flag */
284 *pte1p |= 0x00000100;
285 store = 1;
286 }
287 if (!(*pte1p & 0x00000080)) {
288 if (rw == 1 && ret == 0) {
289 /* Update changed flag */
290 *pte1p |= 0x00000080;
291 store = 1;
292 } else {
293 /* Force page fault for first write access */
294 ctx->prot &= ~PAGE_WRITE;
295 }
296 }
297
298 return store;
299 }
300
301 /* Software driven TLB helpers */
302 static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
303 int is_code)
304 {
305 int nr;
306
307 /* Select TLB num in a way from address */
308 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
309 /* Select TLB way */
310 nr += env->tlb_per_way * way;
311 /* 6xx have separate TLBs for instructions and data */
312 if (is_code && env->id_tlbs == 1)
313 nr += env->nb_tlb;
314
315 return nr;
316 }
317
318 static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
319 {
320 ppc6xx_tlb_t *tlb;
321 int nr, max;
322
323 //LOG_SWTLB("Invalidate all TLBs\n");
324 /* Invalidate all defined software TLB */
325 max = env->nb_tlb;
326 if (env->id_tlbs == 1)
327 max *= 2;
328 for (nr = 0; nr < max; nr++) {
329 tlb = &env->tlb[nr].tlb6;
330 pte_invalidate(&tlb->pte0);
331 }
332 tlb_flush(env, 1);
333 }
334
335 static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
336 target_ulong eaddr,
337 int is_code, int match_epn)
338 {
339 #if !defined(FLUSH_ALL_TLBS)
340 ppc6xx_tlb_t *tlb;
341 int way, nr;
342
343 /* Invalidate ITLB + DTLB, all ways */
344 for (way = 0; way < env->nb_ways; way++) {
345 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
346 tlb = &env->tlb[nr].tlb6;
347 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
348 LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
349 env->nb_tlb, eaddr);
350 pte_invalidate(&tlb->pte0);
351 tlb_flush_page(env, tlb->EPN);
352 }
353 }
354 #else
355 /* XXX: PowerPC specification say this is valid as well */
356 ppc6xx_tlb_invalidate_all(env);
357 #endif
358 }
359
360 static inline void ppc6xx_tlb_invalidate_virt(CPUState *env,
361 target_ulong eaddr, int is_code)
362 {
363 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
364 }
365
366 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
367 target_ulong pte0, target_ulong pte1)
368 {
369 ppc6xx_tlb_t *tlb;
370 int nr;
371
372 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
373 tlb = &env->tlb[nr].tlb6;
374 LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
375 " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
376 /* Invalidate any pending reference in Qemu for this virtual address */
377 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
378 tlb->pte0 = pte0;
379 tlb->pte1 = pte1;
380 tlb->EPN = EPN;
381 /* Store last way for LRU mechanism */
382 env->last_way = way;
383 }
384
385 static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
386 target_ulong eaddr, int rw, int access_type)
387 {
388 ppc6xx_tlb_t *tlb;
389 int nr, best, way;
390 int ret;
391
392 best = -1;
393 ret = -1; /* No TLB found */
394 for (way = 0; way < env->nb_ways; way++) {
395 nr = ppc6xx_tlb_getnum(env, eaddr, way,
396 access_type == ACCESS_CODE ? 1 : 0);
397 tlb = &env->tlb[nr].tlb6;
398 /* This test "emulates" the PTE index match for hardware TLBs */
399 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
400 LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
401 "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,
402 pte_is_valid(tlb->pte0) ? "valid" : "inval",
403 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
404 continue;
405 }
406 LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "
407 TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
408 pte_is_valid(tlb->pte0) ? "valid" : "inval",
409 tlb->EPN, eaddr, tlb->pte1,
410 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
411 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
412 case -3:
413 /* TLB inconsistency */
414 return -1;
415 case -2:
416 /* Access violation */
417 ret = -2;
418 best = nr;
419 break;
420 case -1:
421 default:
422 /* No match */
423 break;
424 case 0:
425 /* access granted */
426 /* XXX: we should go on looping to check all TLBs consistency
427 * but we can speed-up the whole thing as the
428 * result would be undefined if TLBs are not consistent.
429 */
430 ret = 0;
431 best = nr;
432 goto done;
433 }
434 }
435 if (best != -1) {
436 done:
437 LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
438 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
439 /* Update page flags */
440 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
441 }
442
443 return ret;
444 }
445
446 /* Perform BAT hit & translation */
447 static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
448 int *protp, target_ulong *BATu,
449 target_ulong *BATl)
450 {
451 target_ulong bl;
452 int pp, valid, prot;
453
454 bl = (*BATu & 0x00001FFC) << 15;
455 valid = 0;
456 prot = 0;
457 if (((msr_pr == 0) && (*BATu & 0x00000002)) ||
458 ((msr_pr != 0) && (*BATu & 0x00000001))) {
459 valid = 1;
460 pp = *BATl & 0x00000003;
461 if (pp != 0) {
462 prot = PAGE_READ | PAGE_EXEC;
463 if (pp == 0x2)
464 prot |= PAGE_WRITE;
465 }
466 }
467 *blp = bl;
468 *validp = valid;
469 *protp = prot;
470 }
471
472 static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
473 int *validp, int *protp,
474 target_ulong *BATu, target_ulong *BATl)
475 {
476 target_ulong bl;
477 int key, pp, valid, prot;
478
479 bl = (*BATl & 0x0000003F) << 17;
480 LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",
481 (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
482 prot = 0;
483 valid = (*BATl >> 6) & 1;
484 if (valid) {
485 pp = *BATu & 0x00000003;
486 if (msr_pr == 0)
487 key = (*BATu >> 3) & 1;
488 else
489 key = (*BATu >> 2) & 1;
490 prot = pp_check(key, pp, 0);
491 }
492 *blp = bl;
493 *validp = valid;
494 *protp = prot;
495 }
496
497 static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
498 int rw, int type)
499 {
500 target_ulong *BATlt, *BATut, *BATu, *BATl;
501 target_ulong base, BEPIl, BEPIu, bl;
502 int i, valid, prot;
503 int ret = -1;
504
505 LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
506 type == ACCESS_CODE ? 'I' : 'D', virtual);
507 switch (type) {
508 case ACCESS_CODE:
509 BATlt = env->IBAT[1];
510 BATut = env->IBAT[0];
511 break;
512 default:
513 BATlt = env->DBAT[1];
514 BATut = env->DBAT[0];
515 break;
516 }
517 base = virtual & 0xFFFC0000;
518 for (i = 0; i < env->nb_BATs; i++) {
519 BATu = &BATut[i];
520 BATl = &BATlt[i];
521 BEPIu = *BATu & 0xF0000000;
522 BEPIl = *BATu & 0x0FFE0000;
523 if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
524 bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);
525 } else {
526 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
527 }
528 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
529 " BATl " TARGET_FMT_lx "\n", __func__,
530 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
531 if ((virtual & 0xF0000000) == BEPIu &&
532 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
533 /* BAT matches */
534 if (valid != 0) {
535 /* Get physical address */
536 ctx->raddr = (*BATl & 0xF0000000) |
537 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
538 (virtual & 0x0001F000);
539 /* Compute access rights */
540 ctx->prot = prot;
541 ret = check_prot(ctx->prot, rw, type);
542 if (ret == 0)
543 LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
544 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
545 ctx->prot & PAGE_WRITE ? 'W' : '-');
546 break;
547 }
548 }
549 }
550 if (ret < 0) {
551 #if defined(DEBUG_BATS)
552 if (qemu_log_enabled()) {
553 LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
554 for (i = 0; i < 4; i++) {
555 BATu = &BATut[i];
556 BATl = &BATlt[i];
557 BEPIu = *BATu & 0xF0000000;
558 BEPIl = *BATu & 0x0FFE0000;
559 bl = (*BATu & 0x00001FFC) << 15;
560 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
561 " BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " "
562 TARGET_FMT_lx " " TARGET_FMT_lx "\n",
563 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
564 *BATu, *BATl, BEPIu, BEPIl, bl);
565 }
566 }
567 #endif
568 }
569 /* No hit */
570 return ret;
571 }
572
573 /* PTE table lookup */
574 static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
575 int type, int target_page_bits)
576 {
577 target_ulong base, pte0, pte1;
578 int i, good = -1;
579 int ret, r;
580
581 ret = -1; /* No entry found */
582 base = ctx->pg_addr[h];
583 for (i = 0; i < 8; i++) {
584 #if defined(TARGET_PPC64)
585 if (is_64b) {
586 pte0 = ldq_phys(base + (i * 16));
587 pte1 = ldq_phys(base + (i * 16) + 8);
588
589 /* We have a TLB that saves 4K pages, so let's
590 * split a huge page to 4k chunks */
591 if (target_page_bits != TARGET_PAGE_BITS)
592 pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1))
593 & TARGET_PAGE_MASK;
594
595 r = pte64_check(ctx, pte0, pte1, h, rw, type);
596 LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
597 TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
598 base + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
599 (int)((pte0 >> 1) & 1), ctx->ptem);
600 } else
601 #endif
602 {
603 pte0 = ldl_phys(base + (i * 8));
604 pte1 = ldl_phys(base + (i * 8) + 4);
605 r = pte32_check(ctx, pte0, pte1, h, rw, type);
606 LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
607 TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
608 base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
609 (int)((pte0 >> 6) & 1), ctx->ptem);
610 }
611 switch (r) {
612 case -3:
613 /* PTE inconsistency */
614 return -1;
615 case -2:
616 /* Access violation */
617 ret = -2;
618 good = i;
619 break;
620 case -1:
621 default:
622 /* No PTE match */
623 break;
624 case 0:
625 /* access granted */
626 /* XXX: we should go on looping to check all PTEs consistency
627 * but if we can speed-up the whole thing as the
628 * result would be undefined if PTEs are not consistent.
629 */
630 ret = 0;
631 good = i;
632 goto done;
633 }
634 }
635 if (good != -1) {
636 done:
637 LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n",
638 ctx->raddr, ctx->prot, ret);
639 /* Update page flags */
640 pte1 = ctx->raddr;
641 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
642 #if defined(TARGET_PPC64)
643 if (is_64b) {
644 stq_phys_notdirty(base + (good * 16) + 8, pte1);
645 } else
646 #endif
647 {
648 stl_phys_notdirty(base + (good * 8) + 4, pte1);
649 }
650 }
651 }
652
653 return ret;
654 }
655
656 static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type,
657 int target_page_bits)
658 {
659 return _find_pte(ctx, 0, h, rw, type, target_page_bits);
660 }
661
662 #if defined(TARGET_PPC64)
663 static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type,
664 int target_page_bits)
665 {
666 return _find_pte(ctx, 1, h, rw, type, target_page_bits);
667 }
668 #endif
669
670 static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
671 int type, int target_page_bits)
672 {
673 #if defined(TARGET_PPC64)
674 if (env->mmu_model & POWERPC_MMU_64)
675 return find_pte64(ctx, h, rw, type, target_page_bits);
676 #endif
677
678 return find_pte32(ctx, h, rw, type, target_page_bits);
679 }
680
681 #if defined(TARGET_PPC64)
682 static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr)
683 {
684 ppc_slb_t *retval = &env->slb[nr];
685
686 #if 0 // XXX implement bridge mode?
687 if (env->spr[SPR_ASR] & 1) {
688 target_phys_addr_t sr_base;
689
690 sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000;
691 sr_base += (12 * nr);
692
693 retval->tmp64 = ldq_phys(sr_base);
694 retval->tmp = ldl_phys(sr_base + 8);
695 }
696 #endif
697
698 return retval;
699 }
700
701 static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb)
702 {
703 ppc_slb_t *entry = &env->slb[nr];
704
705 if (slb == entry)
706 return;
707
708 entry->tmp64 = slb->tmp64;
709 entry->tmp = slb->tmp;
710 }
711
712 static inline int slb_is_valid(ppc_slb_t *slb)
713 {
714 return (int)(slb->tmp64 & 0x0000000008000000ULL);
715 }
716
717 static inline void slb_invalidate(ppc_slb_t *slb)
718 {
719 slb->tmp64 &= ~0x0000000008000000ULL;
720 }
721
722 static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr,
723 target_ulong *vsid, target_ulong *page_mask,
724 int *attr, int *target_page_bits)
725 {
726 target_ulong mask;
727 int n, ret;
728
729 ret = -5;
730 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
731 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
732 for (n = 0; n < env->slb_nr; n++) {
733 ppc_slb_t *slb = slb_get_entry(env, n);
734
735 LOG_SLB("%s: seg %d %016" PRIx64 " %08"
736 PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp);
737 if (slb_is_valid(slb)) {
738 /* SLB entry is valid */
739 mask = 0xFFFFFFFFF0000000ULL;
740 if (slb->tmp & 0x8) {
741 /* 16 MB PTEs */
742 if (target_page_bits)
743 *target_page_bits = 24;
744 } else {
745 /* 4 KB PTEs */
746 if (target_page_bits)
747 *target_page_bits = TARGET_PAGE_BITS;
748 }
749 if ((eaddr & mask) == (slb->tmp64 & mask)) {
750 /* SLB match */
751 *vsid = ((slb->tmp64 << 24) | (slb->tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
752 *page_mask = ~mask;
753 *attr = slb->tmp & 0xFF;
754 ret = n;
755 break;
756 }
757 }
758 }
759
760 return ret;
761 }
762
763 void ppc_slb_invalidate_all (CPUPPCState *env)
764 {
765 int n, do_invalidate;
766
767 do_invalidate = 0;
768 /* XXX: Warning: slbia never invalidates the first segment */
769 for (n = 1; n < env->slb_nr; n++) {
770 ppc_slb_t *slb = slb_get_entry(env, n);
771
772 if (slb_is_valid(slb)) {
773 slb_invalidate(slb);
774 slb_set_entry(env, n, slb);
775 /* XXX: given the fact that segment size is 256 MB or 1TB,
776 * and we still don't have a tlb_flush_mask(env, n, mask)
777 * in Qemu, we just invalidate all TLBs
778 */
779 do_invalidate = 1;
780 }
781 }
782 if (do_invalidate)
783 tlb_flush(env, 1);
784 }
785
786 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
787 {
788 target_ulong vsid, page_mask;
789 int attr;
790 int n;
791
792 n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
793 if (n >= 0) {
794 ppc_slb_t *slb = slb_get_entry(env, n);
795
796 if (slb_is_valid(slb)) {
797 slb_invalidate(slb);
798 slb_set_entry(env, n, slb);
799 /* XXX: given the fact that segment size is 256 MB or 1TB,
800 * and we still don't have a tlb_flush_mask(env, n, mask)
801 * in Qemu, we just invalidate all TLBs
802 */
803 tlb_flush(env, 1);
804 }
805 }
806 }
807
808 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
809 {
810 target_ulong rt;
811 ppc_slb_t *slb = slb_get_entry(env, slb_nr);
812
813 if (slb_is_valid(slb)) {
814 /* SLB entry is valid */
815 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
816 rt = slb->tmp >> 8; /* 65:88 => 40:63 */
817 rt |= (slb->tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
818 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
819 rt |= ((slb->tmp >> 4) & 0xF) << 27;
820 } else {
821 rt = 0;
822 }
823 LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d "
824 TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
825
826 return rt;
827 }
828
829 void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
830 {
831 ppc_slb_t *slb;
832
833 uint64_t vsid;
834 uint64_t esid;
835 int flags, valid, slb_nr;
836
837 vsid = rs >> 12;
838 flags = ((rs >> 8) & 0xf);
839
840 esid = rb >> 28;
841 valid = (rb & (1 << 27));
842 slb_nr = rb & 0xfff;
843
844 slb = slb_get_entry(env, slb_nr);
845 slb->tmp64 = (esid << 28) | valid | (vsid >> 24);
846 slb->tmp = (vsid << 8) | (flags << 3);
847
848 LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
849 " %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64,
850 slb->tmp);
851
852 slb_set_entry(env, slb_nr, slb);
853 }
854 #endif /* defined(TARGET_PPC64) */
855
856 /* Perform segment based translation */
857 static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
858 int sdr_sh,
859 target_phys_addr_t hash,
860 target_phys_addr_t mask)
861 {
862 return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
863 }
864
865 static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
866 target_ulong eaddr, int rw, int type)
867 {
868 target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
869 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
870 #if defined(TARGET_PPC64)
871 int attr;
872 #endif
873 int ds, vsid_sh, sdr_sh, pr, target_page_bits;
874 int ret, ret2;
875
876 pr = msr_pr;
877 #if defined(TARGET_PPC64)
878 if (env->mmu_model & POWERPC_MMU_64) {
879 LOG_MMU("Check SLBs\n");
880 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr,
881 &target_page_bits);
882 if (ret < 0)
883 return ret;
884 ctx->key = ((attr & 0x40) && (pr != 0)) ||
885 ((attr & 0x80) && (pr == 0)) ? 1 : 0;
886 ds = 0;
887 ctx->nx = attr & 0x10 ? 1 : 0;
888 ctx->eaddr = eaddr;
889 vsid_mask = 0x00003FFFFFFFFF80ULL;
890 vsid_sh = 7;
891 sdr_sh = 18;
892 sdr_mask = 0x3FF80;
893 } else
894 #endif /* defined(TARGET_PPC64) */
895 {
896 sr = env->sr[eaddr >> 28];
897 page_mask = 0x0FFFFFFF;
898 ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
899 ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
900 ds = sr & 0x80000000 ? 1 : 0;
901 ctx->nx = sr & 0x10000000 ? 1 : 0;
902 vsid = sr & 0x00FFFFFF;
903 vsid_mask = 0x01FFFFC0;
904 vsid_sh = 6;
905 sdr_sh = 16;
906 sdr_mask = 0xFFC0;
907 target_page_bits = TARGET_PAGE_BITS;
908 LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
909 TARGET_FMT_lx " lr=" TARGET_FMT_lx
910 " ir=%d dr=%d pr=%d %d t=%d\n",
911 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
912 (int)msr_dr, pr != 0 ? 1 : 0, rw, type);
913 }
914 LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
915 ctx->key, ds, ctx->nx, vsid);
916 ret = -1;
917 if (!ds) {
918 /* Check if instruction fetch is allowed, if needed */
919 if (type != ACCESS_CODE || ctx->nx == 0) {
920 /* Page address translation */
921 /* Primary table address */
922 sdr = env->sdr1;
923 pgidx = (eaddr & page_mask) >> target_page_bits;
924 #if defined(TARGET_PPC64)
925 if (env->mmu_model & POWERPC_MMU_64) {
926 htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
927 /* XXX: this is false for 1 TB segments */
928 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
929 } else
930 #endif
931 {
932 htab_mask = sdr & 0x000001FF;
933 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
934 }
935 mask = (htab_mask << sdr_sh) | sdr_mask;
936 LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
937 " mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
938 sdr, sdr_sh, hash, mask, page_mask);
939 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
940 /* Secondary table address */
941 hash = (~hash) & vsid_mask;
942 LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
943 " mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask);
944 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
945 #if defined(TARGET_PPC64)
946 if (env->mmu_model & POWERPC_MMU_64) {
947 /* Only 5 bits of the page index are used in the AVPN */
948 if (target_page_bits > 23) {
949 ctx->ptem = (vsid << 12) |
950 ((pgidx << (target_page_bits - 16)) & 0xF80);
951 } else {
952 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
953 }
954 } else
955 #endif
956 {
957 ctx->ptem = (vsid << 7) | (pgidx >> 10);
958 }
959 /* Initialize real address with an invalid value */
960 ctx->raddr = (target_phys_addr_t)-1ULL;
961 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
962 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
963 /* Software TLB search */
964 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
965 } else {
966 LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
967 "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
968 " pg_addr=" TARGET_FMT_plx "\n",
969 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
970 /* Primary table lookup */
971 ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
972 if (ret < 0) {
973 /* Secondary table lookup */
974 if (eaddr != 0xEFFFFFFF)
975 LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
976 "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
977 " pg_addr=" TARGET_FMT_plx "\n", sdr, vsid,
978 pgidx, hash, ctx->pg_addr[1]);
979 ret2 = find_pte(env, ctx, 1, rw, type,
980 target_page_bits);
981 if (ret2 != -1)
982 ret = ret2;
983 }
984 }
985 #if defined (DUMP_PAGE_TABLES)
986 if (qemu_log_enabled()) {
987 target_phys_addr_t curaddr;
988 uint32_t a0, a1, a2, a3;
989 qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
990 "\n", sdr, mask + 0x80);
991 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
992 curaddr += 16) {
993 a0 = ldl_phys(curaddr);
994 a1 = ldl_phys(curaddr + 4);
995 a2 = ldl_phys(curaddr + 8);
996 a3 = ldl_phys(curaddr + 12);
997 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
998 qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
999 curaddr, a0, a1, a2, a3);
1000 }
1001 }
1002 }
1003 #endif
1004 } else {
1005 LOG_MMU("No access allowed\n");
1006 ret = -3;
1007 }
1008 } else {
1009 LOG_MMU("direct store...\n");
1010 /* Direct-store segment : absolutely *BUGGY* for now */
1011 switch (type) {
1012 case ACCESS_INT:
1013 /* Integer load/store : only access allowed */
1014 break;
1015 case ACCESS_CODE:
1016 /* No code fetch is allowed in direct-store areas */
1017 return -4;
1018 case ACCESS_FLOAT:
1019 /* Floating point load/store */
1020 return -4;
1021 case ACCESS_RES:
1022 /* lwarx, ldarx or srwcx. */
1023 return -4;
1024 case ACCESS_CACHE:
1025 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
1026 /* Should make the instruction do no-op.
1027 * As it already do no-op, it's quite easy :-)
1028 */
1029 ctx->raddr = eaddr;
1030 return 0;
1031 case ACCESS_EXT:
1032 /* eciwx or ecowx */
1033 return -4;
1034 default:
1035 qemu_log("ERROR: instruction should not need "
1036 "address translation\n");
1037 return -4;
1038 }
1039 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
1040 ctx->raddr = eaddr;
1041 ret = 2;
1042 } else {
1043 ret = -2;
1044 }
1045 }
1046
1047 return ret;
1048 }
1049
1050 /* Generic TLB check function for embedded PowerPC implementations */
1051 static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
1052 target_phys_addr_t *raddrp,
1053 target_ulong address, uint32_t pid, int ext,
1054 int i)
1055 {
1056 target_ulong mask;
1057
1058 /* Check valid flag */
1059 if (!(tlb->prot & PAGE_VALID)) {
1060 qemu_log("%s: TLB %d not valid\n", __func__, i);
1061 return -1;
1062 }
1063 mask = ~(tlb->size - 1);
1064 LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx
1065 " " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN,
1066 mask, (uint32_t)tlb->PID);
1067 /* Check PID */
1068 if (tlb->PID != 0 && tlb->PID != pid)
1069 return -1;
1070 /* Check effective address */
1071 if ((address & mask) != tlb->EPN)
1072 return -1;
1073 *raddrp = (tlb->RPN & mask) | (address & ~mask);
1074 #if (TARGET_PHYS_ADDR_BITS >= 36)
1075 if (ext) {
1076 /* Extend the physical address to 36 bits */
1077 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
1078 }
1079 #endif
1080
1081 return 0;
1082 }
1083
1084 /* Generic TLB search function for PowerPC embedded implementations */
1085 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
1086 {
1087 ppcemb_tlb_t *tlb;
1088 target_phys_addr_t raddr;
1089 int i, ret;
1090
1091 /* Default return value is no match */
1092 ret = -1;
1093 for (i = 0; i < env->nb_tlb; i++) {
1094 tlb = &env->tlb[i].tlbe;
1095 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
1096 ret = i;
1097 break;
1098 }
1099 }
1100
1101 return ret;
1102 }
1103
1104 /* Helpers specific to PowerPC 40x implementations */
1105 static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
1106 {
1107 ppcemb_tlb_t *tlb;
1108 int i;
1109
1110 for (i = 0; i < env->nb_tlb; i++) {
1111 tlb = &env->tlb[i].tlbe;
1112 tlb->prot &= ~PAGE_VALID;
1113 }
1114 tlb_flush(env, 1);
1115 }
1116
1117 static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
1118 target_ulong eaddr, uint32_t pid)
1119 {
1120 #if !defined(FLUSH_ALL_TLBS)
1121 ppcemb_tlb_t *tlb;
1122 target_phys_addr_t raddr;
1123 target_ulong page, end;
1124 int i;
1125
1126 for (i = 0; i < env->nb_tlb; i++) {
1127 tlb = &env->tlb[i].tlbe;
1128 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
1129 end = tlb->EPN + tlb->size;
1130 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1131 tlb_flush_page(env, page);
1132 tlb->prot &= ~PAGE_VALID;
1133 break;
1134 }
1135 }
1136 #else
1137 ppc4xx_tlb_invalidate_all(env);
1138 #endif
1139 }
1140
1141 static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1142 target_ulong address, int rw, int access_type)
1143 {
1144 ppcemb_tlb_t *tlb;
1145 target_phys_addr_t raddr;
1146 int i, ret, zsel, zpr, pr;
1147
1148 ret = -1;
1149 raddr = (target_phys_addr_t)-1ULL;
1150 pr = msr_pr;
1151 for (i = 0; i < env->nb_tlb; i++) {
1152 tlb = &env->tlb[i].tlbe;
1153 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1154 env->spr[SPR_40x_PID], 0, i) < 0)
1155 continue;
1156 zsel = (tlb->attr >> 4) & 0xF;
1157 zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3;
1158 LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1159 __func__, i, zsel, zpr, rw, tlb->attr);
1160 /* Check execute enable bit */
1161 switch (zpr) {
1162 case 0x2:
1163 if (pr != 0)
1164 goto check_perms;
1165 /* No break here */
1166 case 0x3:
1167 /* All accesses granted */
1168 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1169 ret = 0;
1170 break;
1171 case 0x0:
1172 if (pr != 0) {
1173 /* Raise Zone protection fault. */
1174 env->spr[SPR_40x_ESR] = 1 << 22;
1175 ctx->prot = 0;
1176 ret = -2;
1177 break;
1178 }
1179 /* No break here */
1180 case 0x1:
1181 check_perms:
1182 /* Check from TLB entry */
1183 /* XXX: there is a problem here or in the TLB fill code... */
1184 ctx->prot = tlb->prot;
1185 ctx->prot |= PAGE_EXEC;
1186 ret = check_prot(ctx->prot, rw, access_type);
1187 if (ret == -2)
1188 env->spr[SPR_40x_ESR] = 0;
1189 break;
1190 }
1191 if (ret >= 0) {
1192 ctx->raddr = raddr;
1193 LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
1194 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1195 ret);
1196 return 0;
1197 }
1198 }
1199 LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
1200 " %d %d\n", __func__, address, raddr, ctx->prot, ret);
1201
1202 return ret;
1203 }
1204
1205 void store_40x_sler (CPUPPCState *env, uint32_t val)
1206 {
1207 /* XXX: TO BE FIXED */
1208 if (val != 0x00000000) {
1209 cpu_abort(env, "Little-endian regions are not supported by now\n");
1210 }
1211 env->spr[SPR_405_SLER] = val;
1212 }
1213
1214 static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1215 target_ulong address, int rw,
1216 int access_type)
1217 {
1218 ppcemb_tlb_t *tlb;
1219 target_phys_addr_t raddr;
1220 int i, prot, ret;
1221
1222 ret = -1;
1223 raddr = (target_phys_addr_t)-1ULL;
1224 for (i = 0; i < env->nb_tlb; i++) {
1225 tlb = &env->tlb[i].tlbe;
1226 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1227 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1228 continue;
1229 if (msr_pr != 0)
1230 prot = tlb->prot & 0xF;
1231 else
1232 prot = (tlb->prot >> 4) & 0xF;
1233 /* Check the address space */
1234 if (access_type == ACCESS_CODE) {
1235 if (msr_ir != (tlb->attr & 1))
1236 continue;
1237 ctx->prot = prot;
1238 if (prot & PAGE_EXEC) {
1239 ret = 0;
1240 break;
1241 }
1242 ret = -3;
1243 } else {
1244 if (msr_dr != (tlb->attr & 1))
1245 continue;
1246 ctx->prot = prot;
1247 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1248 ret = 0;
1249 break;
1250 }
1251 ret = -2;
1252 }
1253 }
1254 if (ret >= 0)
1255 ctx->raddr = raddr;
1256
1257 return ret;
1258 }
1259
1260 static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
1261 target_ulong eaddr, int rw)
1262 {
1263 int in_plb, ret;
1264
1265 ctx->raddr = eaddr;
1266 ctx->prot = PAGE_READ | PAGE_EXEC;
1267 ret = 0;
1268 switch (env->mmu_model) {
1269 case POWERPC_MMU_32B:
1270 case POWERPC_MMU_601:
1271 case POWERPC_MMU_SOFT_6xx:
1272 case POWERPC_MMU_SOFT_74xx:
1273 case POWERPC_MMU_SOFT_4xx:
1274 case POWERPC_MMU_REAL:
1275 case POWERPC_MMU_BOOKE:
1276 ctx->prot |= PAGE_WRITE;
1277 break;
1278 #if defined(TARGET_PPC64)
1279 case POWERPC_MMU_620:
1280 case POWERPC_MMU_64B:
1281 /* Real address are 60 bits long */
1282 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1283 ctx->prot |= PAGE_WRITE;
1284 break;
1285 #endif
1286 case POWERPC_MMU_SOFT_4xx_Z:
1287 if (unlikely(msr_pe != 0)) {
1288 /* 403 family add some particular protections,
1289 * using PBL/PBU registers for accesses with no translation.
1290 */
1291 in_plb =
1292 /* Check PLB validity */
1293 (env->pb[0] < env->pb[1] &&
1294 /* and address in plb area */
1295 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1296 (env->pb[2] < env->pb[3] &&
1297 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1298 if (in_plb ^ msr_px) {
1299 /* Access in protected area */
1300 if (rw == 1) {
1301 /* Access is not allowed */
1302 ret = -2;
1303 }
1304 } else {
1305 /* Read-write access is allowed */
1306 ctx->prot |= PAGE_WRITE;
1307 }
1308 }
1309 break;
1310 case POWERPC_MMU_MPC8xx:
1311 /* XXX: TODO */
1312 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1313 break;
1314 case POWERPC_MMU_BOOKE_FSL:
1315 /* XXX: TODO */
1316 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1317 break;
1318 default:
1319 cpu_abort(env, "Unknown or invalid MMU model\n");
1320 return -1;
1321 }
1322
1323 return ret;
1324 }
1325
1326 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1327 int rw, int access_type)
1328 {
1329 int ret;
1330
1331 #if 0
1332 qemu_log("%s\n", __func__);
1333 #endif
1334 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1335 (access_type != ACCESS_CODE && msr_dr == 0)) {
1336 /* No address translation */
1337 ret = check_physical(env, ctx, eaddr, rw);
1338 } else {
1339 ret = -1;
1340 switch (env->mmu_model) {
1341 case POWERPC_MMU_32B:
1342 case POWERPC_MMU_601:
1343 case POWERPC_MMU_SOFT_6xx:
1344 case POWERPC_MMU_SOFT_74xx:
1345 /* Try to find a BAT */
1346 if (env->nb_BATs != 0)
1347 ret = get_bat(env, ctx, eaddr, rw, access_type);
1348 #if defined(TARGET_PPC64)
1349 case POWERPC_MMU_620:
1350 case POWERPC_MMU_64B:
1351 #endif
1352 if (ret < 0) {
1353 /* We didn't match any BAT entry or don't have BATs */
1354 ret = get_segment(env, ctx, eaddr, rw, access_type);
1355 }
1356 break;
1357 case POWERPC_MMU_SOFT_4xx:
1358 case POWERPC_MMU_SOFT_4xx_Z:
1359 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1360 rw, access_type);
1361 break;
1362 case POWERPC_MMU_BOOKE:
1363 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1364 rw, access_type);
1365 break;
1366 case POWERPC_MMU_MPC8xx:
1367 /* XXX: TODO */
1368 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1369 break;
1370 case POWERPC_MMU_BOOKE_FSL:
1371 /* XXX: TODO */
1372 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1373 return -1;
1374 case POWERPC_MMU_REAL:
1375 cpu_abort(env, "PowerPC in real mode do not do any translation\n");
1376 return -1;
1377 default:
1378 cpu_abort(env, "Unknown or invalid MMU model\n");
1379 return -1;
1380 }
1381 }
1382 #if 0
1383 qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
1384 __func__, eaddr, ret, ctx->raddr);
1385 #endif
1386
1387 return ret;
1388 }
1389
1390 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1391 {
1392 mmu_ctx_t ctx;
1393
1394 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0))
1395 return -1;
1396
1397 return ctx.raddr & TARGET_PAGE_MASK;
1398 }
1399
1400 /* Perform address translation */
1401 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1402 int mmu_idx, int is_softmmu)
1403 {
1404 mmu_ctx_t ctx;
1405 int access_type;
1406 int ret = 0;
1407
1408 if (rw == 2) {
1409 /* code access */
1410 rw = 0;
1411 access_type = ACCESS_CODE;
1412 } else {
1413 /* data access */
1414 access_type = env->access_type;
1415 }
1416 ret = get_physical_address(env, &ctx, address, rw, access_type);
1417 if (ret == 0) {
1418 ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK,
1419 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1420 mmu_idx, is_softmmu);
1421 } else if (ret < 0) {
1422 LOG_MMU_STATE(env);
1423 if (access_type == ACCESS_CODE) {
1424 switch (ret) {
1425 case -1:
1426 /* No matches in page tables or TLB */
1427 switch (env->mmu_model) {
1428 case POWERPC_MMU_SOFT_6xx:
1429 env->exception_index = POWERPC_EXCP_IFTLB;
1430 env->error_code = 1 << 18;
1431 env->spr[SPR_IMISS] = address;
1432 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1433 goto tlb_miss;
1434 case POWERPC_MMU_SOFT_74xx:
1435 env->exception_index = POWERPC_EXCP_IFTLB;
1436 goto tlb_miss_74xx;
1437 case POWERPC_MMU_SOFT_4xx:
1438 case POWERPC_MMU_SOFT_4xx_Z:
1439 env->exception_index = POWERPC_EXCP_ITLB;
1440 env->error_code = 0;
1441 env->spr[SPR_40x_DEAR] = address;
1442 env->spr[SPR_40x_ESR] = 0x00000000;
1443 break;
1444 case POWERPC_MMU_32B:
1445 case POWERPC_MMU_601:
1446 #if defined(TARGET_PPC64)
1447 case POWERPC_MMU_620:
1448 case POWERPC_MMU_64B:
1449 #endif
1450 env->exception_index = POWERPC_EXCP_ISI;
1451 env->error_code = 0x40000000;
1452 break;
1453 case POWERPC_MMU_BOOKE:
1454 /* XXX: TODO */
1455 cpu_abort(env, "BookE MMU model is not implemented\n");
1456 return -1;
1457 case POWERPC_MMU_BOOKE_FSL:
1458 /* XXX: TODO */
1459 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1460 return -1;
1461 case POWERPC_MMU_MPC8xx:
1462 /* XXX: TODO */
1463 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1464 break;
1465 case POWERPC_MMU_REAL:
1466 cpu_abort(env, "PowerPC in real mode should never raise "
1467 "any MMU exceptions\n");
1468 return -1;
1469 default:
1470 cpu_abort(env, "Unknown or invalid MMU model\n");
1471 return -1;
1472 }
1473 break;
1474 case -2:
1475 /* Access rights violation */
1476 env->exception_index = POWERPC_EXCP_ISI;
1477 env->error_code = 0x08000000;
1478 break;
1479 case -3:
1480 /* No execute protection violation */
1481 env->exception_index = POWERPC_EXCP_ISI;
1482 env->error_code = 0x10000000;
1483 break;
1484 case -4:
1485 /* Direct store exception */
1486 /* No code fetch is allowed in direct-store areas */
1487 env->exception_index = POWERPC_EXCP_ISI;
1488 env->error_code = 0x10000000;
1489 break;
1490 #if defined(TARGET_PPC64)
1491 case -5:
1492 /* No match in segment table */
1493 if (env->mmu_model == POWERPC_MMU_620) {
1494 env->exception_index = POWERPC_EXCP_ISI;
1495 /* XXX: this might be incorrect */
1496 env->error_code = 0x40000000;
1497 } else {
1498 env->exception_index = POWERPC_EXCP_ISEG;
1499 env->error_code = 0;
1500 }
1501 break;
1502 #endif
1503 }
1504 } else {
1505 switch (ret) {
1506 case -1:
1507 /* No matches in page tables or TLB */
1508 switch (env->mmu_model) {
1509 case POWERPC_MMU_SOFT_6xx:
1510 if (rw == 1) {
1511 env->exception_index = POWERPC_EXCP_DSTLB;
1512 env->error_code = 1 << 16;
1513 } else {
1514 env->exception_index = POWERPC_EXCP_DLTLB;
1515 env->error_code = 0;
1516 }
1517 env->spr[SPR_DMISS] = address;
1518 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1519 tlb_miss:
1520 env->error_code |= ctx.key << 19;
1521 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1522 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1523 break;
1524 case POWERPC_MMU_SOFT_74xx:
1525 if (rw == 1) {
1526 env->exception_index = POWERPC_EXCP_DSTLB;
1527 } else {
1528 env->exception_index = POWERPC_EXCP_DLTLB;
1529 }
1530 tlb_miss_74xx:
1531 /* Implement LRU algorithm */
1532 env->error_code = ctx.key << 19;
1533 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1534 ((env->last_way + 1) & (env->nb_ways - 1));
1535 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
1536 break;
1537 case POWERPC_MMU_SOFT_4xx:
1538 case POWERPC_MMU_SOFT_4xx_Z:
1539 env->exception_index = POWERPC_EXCP_DTLB;
1540 env->error_code = 0;
1541 env->spr[SPR_40x_DEAR] = address;
1542 if (rw)
1543 env->spr[SPR_40x_ESR] = 0x00800000;
1544 else
1545 env->spr[SPR_40x_ESR] = 0x00000000;
1546 break;
1547 case POWERPC_MMU_32B:
1548 case POWERPC_MMU_601:
1549 #if defined(TARGET_PPC64)
1550 case POWERPC_MMU_620:
1551 case POWERPC_MMU_64B:
1552 #endif
1553 env->exception_index = POWERPC_EXCP_DSI;
1554 env->error_code = 0;
1555 env->spr[SPR_DAR] = address;
1556 if (rw == 1)
1557 env->spr[SPR_DSISR] = 0x42000000;
1558 else
1559 env->spr[SPR_DSISR] = 0x40000000;
1560 break;
1561 case POWERPC_MMU_MPC8xx:
1562 /* XXX: TODO */
1563 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1564 break;
1565 case POWERPC_MMU_BOOKE:
1566 /* XXX: TODO */
1567 cpu_abort(env, "BookE MMU model is not implemented\n");
1568 return -1;
1569 case POWERPC_MMU_BOOKE_FSL:
1570 /* XXX: TODO */
1571 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1572 return -1;
1573 case POWERPC_MMU_REAL:
1574 cpu_abort(env, "PowerPC in real mode should never raise "
1575 "any MMU exceptions\n");
1576 return -1;
1577 default:
1578 cpu_abort(env, "Unknown or invalid MMU model\n");
1579 return -1;
1580 }
1581 break;
1582 case -2:
1583 /* Access rights violation */
1584 env->exception_index = POWERPC_EXCP_DSI;
1585 env->error_code = 0;
1586 if (env->mmu_model == POWERPC_MMU_SOFT_4xx
1587 || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
1588 env->spr[SPR_40x_DEAR] = address;
1589 if (rw) {
1590 env->spr[SPR_40x_ESR] |= 0x00800000;
1591 }
1592 } else {
1593 env->spr[SPR_DAR] = address;
1594 if (rw == 1) {
1595 env->spr[SPR_DSISR] = 0x0A000000;
1596 } else {
1597 env->spr[SPR_DSISR] = 0x08000000;
1598 }
1599 }
1600 break;
1601 case -4:
1602 /* Direct store exception */
1603 switch (access_type) {
1604 case ACCESS_FLOAT:
1605 /* Floating point load/store */
1606 env->exception_index = POWERPC_EXCP_ALIGN;
1607 env->error_code = POWERPC_EXCP_ALIGN_FP;
1608 env->spr[SPR_DAR] = address;
1609 break;
1610 case ACCESS_RES:
1611 /* lwarx, ldarx or stwcx. */
1612 env->exception_index = POWERPC_EXCP_DSI;
1613 env->error_code = 0;
1614 env->spr[SPR_DAR] = address;
1615 if (rw == 1)
1616 env->spr[SPR_DSISR] = 0x06000000;
1617 else
1618 env->spr[SPR_DSISR] = 0x04000000;
1619 break;
1620 case ACCESS_EXT:
1621 /* eciwx or ecowx */
1622 env->exception_index = POWERPC_EXCP_DSI;
1623 env->error_code = 0;
1624 env->spr[SPR_DAR] = address;
1625 if (rw == 1)
1626 env->spr[SPR_DSISR] = 0x06100000;
1627 else
1628 env->spr[SPR_DSISR] = 0x04100000;
1629 break;
1630 default:
1631 printf("DSI: invalid exception (%d)\n", ret);
1632 env->exception_index = POWERPC_EXCP_PROGRAM;
1633 env->error_code =
1634 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1635 env->spr[SPR_DAR] = address;
1636 break;
1637 }
1638 break;
1639 #if defined(TARGET_PPC64)
1640 case -5:
1641 /* No match in segment table */
1642 if (env->mmu_model == POWERPC_MMU_620) {
1643 env->exception_index = POWERPC_EXCP_DSI;
1644 env->error_code = 0;
1645 env->spr[SPR_DAR] = address;
1646 /* XXX: this might be incorrect */
1647 if (rw == 1)
1648 env->spr[SPR_DSISR] = 0x42000000;
1649 else
1650 env->spr[SPR_DSISR] = 0x40000000;
1651 } else {
1652 env->exception_index = POWERPC_EXCP_DSEG;
1653 env->error_code = 0;
1654 env->spr[SPR_DAR] = address;
1655 }
1656 break;
1657 #endif
1658 }
1659 }
1660 #if 0
1661 printf("%s: set exception to %d %02x\n", __func__,
1662 env->exception, env->error_code);
1663 #endif
1664 ret = 1;
1665 }
1666
1667 return ret;
1668 }
1669
1670 /*****************************************************************************/
1671 /* BATs management */
1672 #if !defined(FLUSH_ALL_TLBS)
1673 static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
1674 target_ulong mask)
1675 {
1676 target_ulong base, end, page;
1677
1678 base = BATu & ~0x0001FFFF;
1679 end = base + mask + 0x00020000;
1680 LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
1681 TARGET_FMT_lx ")\n", base, end, mask);
1682 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1683 tlb_flush_page(env, page);
1684 LOG_BATS("Flush done\n");
1685 }
1686 #endif
1687
1688 static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
1689 target_ulong value)
1690 {
1691 LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
1692 nr, ul == 0 ? 'u' : 'l', value, env->nip);
1693 }
1694
1695 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1696 {
1697 target_ulong mask;
1698
1699 dump_store_bat(env, 'I', 0, nr, value);
1700 if (env->IBAT[0][nr] != value) {
1701 mask = (value << 15) & 0x0FFE0000UL;
1702 #if !defined(FLUSH_ALL_TLBS)
1703 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1704 #endif
1705 /* When storing valid upper BAT, mask BEPI and BRPN
1706 * and invalidate all TLBs covered by this BAT
1707 */
1708 mask = (value << 15) & 0x0FFE0000UL;
1709 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1710 (value & ~0x0001FFFFUL & ~mask);
1711 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1712 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1713 #if !defined(FLUSH_ALL_TLBS)
1714 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1715 #else
1716 tlb_flush(env, 1);
1717 #endif
1718 }
1719 }
1720
1721 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1722 {
1723 dump_store_bat(env, 'I', 1, nr, value);
1724 env->IBAT[1][nr] = value;
1725 }
1726
1727 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1728 {
1729 target_ulong mask;
1730
1731 dump_store_bat(env, 'D', 0, nr, value);
1732 if (env->DBAT[0][nr] != value) {
1733 /* When storing valid upper BAT, mask BEPI and BRPN
1734 * and invalidate all TLBs covered by this BAT
1735 */
1736 mask = (value << 15) & 0x0FFE0000UL;
1737 #if !defined(FLUSH_ALL_TLBS)
1738 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1739 #endif
1740 mask = (value << 15) & 0x0FFE0000UL;
1741 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1742 (value & ~0x0001FFFFUL & ~mask);
1743 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1744 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1745 #if !defined(FLUSH_ALL_TLBS)
1746 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1747 #else
1748 tlb_flush(env, 1);
1749 #endif
1750 }
1751 }
1752
1753 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1754 {
1755 dump_store_bat(env, 'D', 1, nr, value);
1756 env->DBAT[1][nr] = value;
1757 }
1758
1759 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
1760 {
1761 target_ulong mask;
1762 int do_inval;
1763
1764 dump_store_bat(env, 'I', 0, nr, value);
1765 if (env->IBAT[0][nr] != value) {
1766 do_inval = 0;
1767 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1768 if (env->IBAT[1][nr] & 0x40) {
1769 /* Invalidate BAT only if it is valid */
1770 #if !defined(FLUSH_ALL_TLBS)
1771 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1772 #else
1773 do_inval = 1;
1774 #endif
1775 }
1776 /* When storing valid upper BAT, mask BEPI and BRPN
1777 * and invalidate all TLBs covered by this BAT
1778 */
1779 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1780 (value & ~0x0001FFFFUL & ~mask);
1781 env->DBAT[0][nr] = env->IBAT[0][nr];
1782 if (env->IBAT[1][nr] & 0x40) {
1783 #if !defined(FLUSH_ALL_TLBS)
1784 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1785 #else
1786 do_inval = 1;
1787 #endif
1788 }
1789 #if defined(FLUSH_ALL_TLBS)
1790 if (do_inval)
1791 tlb_flush(env, 1);
1792 #endif
1793 }
1794 }
1795
1796 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
1797 {
1798 target_ulong mask;
1799 int do_inval;
1800
1801 dump_store_bat(env, 'I', 1, nr, value);
1802 if (env->IBAT[1][nr] != value) {
1803 do_inval = 0;
1804 if (env->IBAT[1][nr] & 0x40) {
1805 #if !defined(FLUSH_ALL_TLBS)
1806 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1807 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1808 #else
1809 do_inval = 1;
1810 #endif
1811 }
1812 if (value & 0x40) {
1813 #if !defined(FLUSH_ALL_TLBS)
1814 mask = (value << 17) & 0x0FFE0000UL;
1815 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1816 #else
1817 do_inval = 1;
1818 #endif
1819 }
1820 env->IBAT[1][nr] = value;
1821 env->DBAT[1][nr] = value;
1822 #if defined(FLUSH_ALL_TLBS)
1823 if (do_inval)
1824 tlb_flush(env, 1);
1825 #endif
1826 }
1827 }
1828
1829 /*****************************************************************************/
1830 /* TLB management */
1831 void ppc_tlb_invalidate_all (CPUPPCState *env)
1832 {
1833 switch (env->mmu_model) {
1834 case POWERPC_MMU_SOFT_6xx:
1835 case POWERPC_MMU_SOFT_74xx:
1836 ppc6xx_tlb_invalidate_all(env);
1837 break;
1838 case POWERPC_MMU_SOFT_4xx:
1839 case POWERPC_MMU_SOFT_4xx_Z:
1840 ppc4xx_tlb_invalidate_all(env);
1841 break;
1842 case POWERPC_MMU_REAL:
1843 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1844 break;
1845 case POWERPC_MMU_MPC8xx:
1846 /* XXX: TODO */
1847 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1848 break;
1849 case POWERPC_MMU_BOOKE:
1850 /* XXX: TODO */
1851 cpu_abort(env, "BookE MMU model is not implemented\n");
1852 break;
1853 case POWERPC_MMU_BOOKE_FSL:
1854 /* XXX: TODO */
1855 if (!kvm_enabled())
1856 cpu_abort(env, "BookE MMU model is not implemented\n");
1857 break;
1858 case POWERPC_MMU_32B:
1859 case POWERPC_MMU_601:
1860 #if defined(TARGET_PPC64)
1861 case POWERPC_MMU_620:
1862 case POWERPC_MMU_64B:
1863 #endif /* defined(TARGET_PPC64) */
1864 tlb_flush(env, 1);
1865 break;
1866 default:
1867 /* XXX: TODO */
1868 cpu_abort(env, "Unknown MMU model\n");
1869 break;
1870 }
1871 }
1872
1873 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1874 {
1875 #if !defined(FLUSH_ALL_TLBS)
1876 addr &= TARGET_PAGE_MASK;
1877 switch (env->mmu_model) {
1878 case POWERPC_MMU_SOFT_6xx:
1879 case POWERPC_MMU_SOFT_74xx:
1880 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1881 if (env->id_tlbs == 1)
1882 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1883 break;
1884 case POWERPC_MMU_SOFT_4xx:
1885 case POWERPC_MMU_SOFT_4xx_Z:
1886 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1887 break;
1888 case POWERPC_MMU_REAL:
1889 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1890 break;
1891 case POWERPC_MMU_MPC8xx:
1892 /* XXX: TODO */
1893 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1894 break;
1895 case POWERPC_MMU_BOOKE:
1896 /* XXX: TODO */
1897 cpu_abort(env, "BookE MMU model is not implemented\n");
1898 break;
1899 case POWERPC_MMU_BOOKE_FSL:
1900 /* XXX: TODO */
1901 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1902 break;
1903 case POWERPC_MMU_32B:
1904 case POWERPC_MMU_601:
1905 /* tlbie invalidate TLBs for all segments */
1906 addr &= ~((target_ulong)-1ULL << 28);
1907 /* XXX: this case should be optimized,
1908 * giving a mask to tlb_flush_page
1909 */
1910 tlb_flush_page(env, addr | (0x0 << 28));
1911 tlb_flush_page(env, addr | (0x1 << 28));
1912 tlb_flush_page(env, addr | (0x2 << 28));
1913 tlb_flush_page(env, addr | (0x3 << 28));
1914 tlb_flush_page(env, addr | (0x4 << 28));
1915 tlb_flush_page(env, addr | (0x5 << 28));
1916 tlb_flush_page(env, addr | (0x6 << 28));
1917 tlb_flush_page(env, addr | (0x7 << 28));
1918 tlb_flush_page(env, addr | (0x8 << 28));
1919 tlb_flush_page(env, addr | (0x9 << 28));
1920 tlb_flush_page(env, addr | (0xA << 28));
1921 tlb_flush_page(env, addr | (0xB << 28));
1922 tlb_flush_page(env, addr | (0xC << 28));
1923 tlb_flush_page(env, addr | (0xD << 28));
1924 tlb_flush_page(env, addr | (0xE << 28));
1925 tlb_flush_page(env, addr | (0xF << 28));
1926 break;
1927 #if defined(TARGET_PPC64)
1928 case POWERPC_MMU_620:
1929 case POWERPC_MMU_64B:
1930 /* tlbie invalidate TLBs for all segments */
1931 /* XXX: given the fact that there are too many segments to invalidate,
1932 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
1933 * we just invalidate all TLBs
1934 */
1935 tlb_flush(env, 1);
1936 break;
1937 #endif /* defined(TARGET_PPC64) */
1938 default:
1939 /* XXX: TODO */
1940 cpu_abort(env, "Unknown MMU model\n");
1941 break;
1942 }
1943 #else
1944 ppc_tlb_invalidate_all(env);
1945 #endif
1946 }
1947
1948 /*****************************************************************************/
1949 /* Special registers manipulation */
1950 #if defined(TARGET_PPC64)
1951 void ppc_store_asr (CPUPPCState *env, target_ulong value)
1952 {
1953 if (env->asr != value) {
1954 env->asr = value;
1955 tlb_flush(env, 1);
1956 }
1957 }
1958 #endif
1959
1960 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
1961 {
1962 LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
1963 if (env->sdr1 != value) {
1964 /* XXX: for PowerPC 64, should check that the HTABSIZE value
1965 * is <= 28
1966 */
1967 env->sdr1 = value;
1968 tlb_flush(env, 1);
1969 }
1970 }
1971
1972 #if defined(TARGET_PPC64)
1973 target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
1974 {
1975 // XXX
1976 return 0;
1977 }
1978 #endif
1979
1980 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1981 {
1982 LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
1983 srnum, value, env->sr[srnum]);
1984 #if defined(TARGET_PPC64)
1985 if (env->mmu_model & POWERPC_MMU_64) {
1986 uint64_t rb = 0, rs = 0;
1987
1988 /* ESID = srnum */
1989 rb |= ((uint32_t)srnum & 0xf) << 28;
1990 /* Set the valid bit */
1991 rb |= 1 << 27;
1992 /* Index = ESID */
1993 rb |= (uint32_t)srnum;
1994
1995 /* VSID = VSID */
1996 rs |= (value & 0xfffffff) << 12;
1997 /* flags = flags */
1998 rs |= ((value >> 27) & 0xf) << 9;
1999
2000 ppc_store_slb(env, rb, rs);
2001 } else
2002 #endif
2003 if (env->sr[srnum] != value) {
2004 env->sr[srnum] = value;
2005 /* Invalidating 256MB of virtual memory in 4kB pages is way longer than
2006 flusing the whole TLB. */
2007 #if !defined(FLUSH_ALL_TLBS) && 0
2008 {
2009 target_ulong page, end;
2010 /* Invalidate 256 MB of virtual memory */
2011 page = (16 << 20) * srnum;
2012 end = page + (16 << 20);
2013 for (; page != end; page += TARGET_PAGE_SIZE)
2014 tlb_flush_page(env, page);
2015 }
2016 #else
2017 tlb_flush(env, 1);
2018 #endif
2019 }
2020 }
2021 #endif /* !defined (CONFIG_USER_ONLY) */
2022
2023 /* GDBstub can read and write MSR... */
2024 void ppc_store_msr (CPUPPCState *env, target_ulong value)
2025 {
2026 hreg_store_msr(env, value, 0);
2027 }
2028
2029 /*****************************************************************************/
2030 /* Exception processing */
2031 #if defined (CONFIG_USER_ONLY)
2032 void do_interrupt (CPUState *env)
2033 {
2034 env->exception_index = POWERPC_EXCP_NONE;
2035 env->error_code = 0;
2036 }
2037
2038 void ppc_hw_interrupt (CPUState *env)
2039 {
2040 env->exception_index = POWERPC_EXCP_NONE;
2041 env->error_code = 0;
2042 }
2043 #else /* defined (CONFIG_USER_ONLY) */
2044 static inline void dump_syscall(CPUState *env)
2045 {
2046 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
2047 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
2048 " nip=" TARGET_FMT_lx "\n",
2049 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
2050 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
2051 ppc_dump_gpr(env, 6), env->nip);
2052 }
2053
2054 /* Note that this function should be greatly optimized
2055 * when called with a constant excp, from ppc_hw_interrupt
2056 */
2057 static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
2058 {
2059 target_ulong msr, new_msr, vector;
2060 int srr0, srr1, asrr0, asrr1;
2061 int lpes0, lpes1, lev;
2062
2063 if (0) {
2064 /* XXX: find a suitable condition to enable the hypervisor mode */
2065 lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
2066 lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
2067 } else {
2068 /* Those values ensure we won't enter the hypervisor mode */
2069 lpes0 = 0;
2070 lpes1 = 1;
2071 }
2072
2073 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
2074 " => %08x (%02x)\n", env->nip, excp, env->error_code);
2075 msr = env->msr;
2076 new_msr = msr;
2077 srr0 = SPR_SRR0;
2078 srr1 = SPR_SRR1;
2079 asrr0 = -1;
2080 asrr1 = -1;
2081 msr &= ~((target_ulong)0x783F0000);
2082 switch (excp) {
2083 case POWERPC_EXCP_NONE:
2084 /* Should never happen */
2085 return;
2086 case POWERPC_EXCP_CRITICAL: /* Critical input */
2087 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2088 switch (excp_model) {
2089 case POWERPC_EXCP_40x:
2090 srr0 = SPR_40x_SRR2;
2091 srr1 = SPR_40x_SRR3;
2092 break;
2093 case POWERPC_EXCP_BOOKE:
2094 srr0 = SPR_BOOKE_CSRR0;
2095 srr1 = SPR_BOOKE_CSRR1;
2096 break;
2097 case POWERPC_EXCP_G2:
2098 break;
2099 default:
2100 goto excp_invalid;
2101 }
2102 goto store_next;
2103 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2104 if (msr_me == 0) {
2105 /* Machine check exception is not enabled.
2106 * Enter checkstop state.
2107 */
2108 if (qemu_log_enabled()) {
2109 qemu_log("Machine check while not allowed. "
2110 "Entering checkstop state\n");
2111 } else {
2112 fprintf(stderr, "Machine check while not allowed. "
2113 "Entering checkstop state\n");
2114 }
2115 env->halted = 1;
2116 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2117 }
2118 new_msr &= ~((target_ulong)1 << MSR_RI);
2119 new_msr &= ~((target_ulong)1 << MSR_ME);
2120 if (0) {
2121 /* XXX: find a suitable condition to enable the hypervisor mode */
2122 new_msr |= (target_ulong)MSR_HVB;
2123 }
2124 /* XXX: should also have something loaded in DAR / DSISR */
2125 switch (excp_model) {
2126 case POWERPC_EXCP_40x:
2127 srr0 = SPR_40x_SRR2;
2128 srr1 = SPR_40x_SRR3;
2129 break;
2130 case POWERPC_EXCP_BOOKE:
2131 srr0 = SPR_BOOKE_MCSRR0;
2132 srr1 = SPR_BOOKE_MCSRR1;
2133 asrr0 = SPR_BOOKE_CSRR0;
2134 asrr1 = SPR_BOOKE_CSRR1;
2135 break;
2136 default:
2137 break;
2138 }
2139 goto store_next;
2140 case POWERPC_EXCP_DSI: /* Data storage exception */
2141 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
2142 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
2143 new_msr &= ~((target_ulong)1 << MSR_RI);
2144 if (lpes1 == 0)
2145 new_msr |= (target_ulong)MSR_HVB;
2146 goto store_next;
2147 case POWERPC_EXCP_ISI: /* Instruction storage exception */
2148 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
2149 "\n", msr, env->nip);
2150 new_msr &= ~((target_ulong)1 << MSR_RI);
2151 if (lpes1 == 0)
2152 new_msr |= (target_ulong)MSR_HVB;
2153 msr |= env->error_code;
2154 goto store_next;
2155 case POWERPC_EXCP_EXTERNAL: /* External input */
2156 new_msr &= ~((target_ulong)1 << MSR_RI);
2157 if (lpes0 == 1)
2158 new_msr |= (target_ulong)MSR_HVB;
2159 goto store_next;
2160 case POWERPC_EXCP_ALIGN: /* Alignment exception */
2161 new_msr &= ~((target_ulong)1 << MSR_RI);
2162 if (lpes1 == 0)
2163 new_msr |= (target_ulong)MSR_HVB;
2164 /* XXX: this is false */
2165 /* Get rS/rD and rA from faulting opcode */
2166 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
2167 goto store_current;
2168 case POWERPC_EXCP_PROGRAM: /* Program exception */
2169 switch (env->error_code & ~0xF) {
2170 case POWERPC_EXCP_FP:
2171 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2172 LOG_EXCP("Ignore floating point exception\n");
2173 env->exception_index = POWERPC_EXCP_NONE;
2174 env->error_code = 0;
2175 return;
2176 }
2177 new_msr &= ~((target_ulong)1 << MSR_RI);
2178 if (lpes1 == 0)
2179 new_msr |= (target_ulong)MSR_HVB;
2180 msr |= 0x00100000;
2181 if (msr_fe0 == msr_fe1)
2182 goto store_next;
2183 msr |= 0x00010000;
2184 break;
2185 case POWERPC_EXCP_INVAL:
2186 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
2187 new_msr &= ~((target_ulong)1 << MSR_RI);
2188 if (lpes1 == 0)
2189 new_msr |= (target_ulong)MSR_HVB;
2190 msr |= 0x00080000;
2191 break;
2192 case POWERPC_EXCP_PRIV:
2193 new_msr &= ~((target_ulong)1 << MSR_RI);
2194 if (lpes1 == 0)
2195 new_msr |= (target_ulong)MSR_HVB;
2196 msr |= 0x00040000;
2197 break;
2198 case POWERPC_EXCP_TRAP:
2199 new_msr &= ~((target_ulong)1 << MSR_RI);
2200 if (lpes1 == 0)
2201 new_msr |= (target_ulong)MSR_HVB;
2202 msr |= 0x00020000;
2203 break;
2204 default:
2205 /* Should never occur */
2206 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2207 env->error_code);
2208 break;
2209 }
2210 goto store_current;
2211 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2212 new_msr &= ~((target_ulong)1 << MSR_RI);
2213 if (lpes1 == 0)
2214 new_msr |= (target_ulong)MSR_HVB;
2215 goto store_current;
2216 case POWERPC_EXCP_SYSCALL: /* System call exception */
2217 /* NOTE: this is a temporary hack to support graphics OSI
2218 calls from the MOL driver */
2219 /* XXX: To be removed */
2220 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2221 env->osi_call) {
2222 if (env->osi_call(env) != 0) {
2223 env->exception_index = POWERPC_EXCP_NONE;
2224 env->error_code = 0;
2225 return;
2226 }
2227 }
2228 dump_syscall(env);
2229 new_msr &= ~((target_ulong)1 << MSR_RI);
2230 lev = env->error_code;
2231 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2232 new_msr |= (target_ulong)MSR_HVB;
2233 goto store_next;
2234 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2235 new_msr &= ~((target_ulong)1 << MSR_RI);
2236 goto store_current;
2237 case POWERPC_EXCP_DECR: /* Decrementer exception */
2238 new_msr &= ~((target_ulong)1 << MSR_RI);
2239 if (lpes1 == 0)
2240 new_msr |= (target_ulong)MSR_HVB;
2241 goto store_next;
2242 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2243 /* FIT on 4xx */
2244 LOG_EXCP("FIT exception\n");
2245 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2246 goto store_next;
2247 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2248 LOG_EXCP("WDT exception\n");
2249 switch (excp_model) {
2250 case POWERPC_EXCP_BOOKE:
2251 srr0 = SPR_BOOKE_CSRR0;
2252 srr1 = SPR_BOOKE_CSRR1;
2253 break;
2254 default:
2255 break;
2256 }
2257 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2258 goto store_next;
2259 case POWERPC_EXCP_DTLB: /* Data TLB error */
2260 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2261 goto store_next;
2262 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2263 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2264 goto store_next;
2265 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2266 switch (excp_model) {
2267 case POWERPC_EXCP_BOOKE:
2268 srr0 = SPR_BOOKE_DSRR0;
2269 srr1 = SPR_BOOKE_DSRR1;
2270 asrr0 = SPR_BOOKE_CSRR0;
2271 asrr1 = SPR_BOOKE_CSRR1;
2272 break;
2273 default:
2274 break;
2275 }
2276 /* XXX: TODO */
2277 cpu_abort(env, "Debug exception is not implemented yet !\n");
2278 goto store_next;
2279 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2280 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2281 goto store_current;
2282 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2283 /* XXX: TODO */
2284 cpu_abort(env, "Embedded floating point data exception "
2285 "is not implemented yet !\n");
2286 goto store_next;
2287 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2288 /* XXX: TODO */
2289 cpu_abort(env, "Embedded floating point round exception "
2290 "is not implemented yet !\n");
2291 goto store_next;
2292 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2293 new_msr &= ~((target_ulong)1 << MSR_RI);
2294 /* XXX: TODO */
2295 cpu_abort(env,
2296 "Performance counter exception is not implemented yet !\n");
2297 goto store_next;
2298 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
2299 /* XXX: TODO */
2300 cpu_abort(env,
2301 "Embedded doorbell interrupt is not implemented yet !\n");
2302 goto store_next;
2303 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2304 switch (excp_model) {
2305 case POWERPC_EXCP_BOOKE:
2306 srr0 = SPR_BOOKE_CSRR0;
2307 srr1 = SPR_BOOKE_CSRR1;
2308 break;
2309 default:
2310 break;
2311 }
2312 /* XXX: TODO */
2313 cpu_abort(env, "Embedded doorbell critical interrupt "
2314 "is not implemented yet !\n");
2315 goto store_next;
2316 case POWERPC_EXCP_RESET: /* System reset exception */
2317 new_msr &= ~((target_ulong)1 << MSR_RI);
2318 if (0) {
2319 /* XXX: find a suitable condition to enable the hypervisor mode */
2320 new_msr |= (target_ulong)MSR_HVB;
2321 }
2322 goto store_next;
2323 case POWERPC_EXCP_DSEG: /* Data segment exception */
2324 new_msr &= ~((target_ulong)1 << MSR_RI);
2325 if (lpes1 == 0)
2326 new_msr |= (target_ulong)MSR_HVB;
2327 goto store_next;
2328 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2329 new_msr &= ~((target_ulong)1 << MSR_RI);
2330 if (lpes1 == 0)
2331 new_msr |= (target_ulong)MSR_HVB;
2332 goto store_next;
2333 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2334 srr0 = SPR_HSRR0;
2335 srr1 = SPR_HSRR1;
2336 new_msr |= (target_ulong)MSR_HVB;
2337 goto store_next;
2338 case POWERPC_EXCP_TRACE: /* Trace exception */
2339 new_msr &= ~((target_ulong)1 << MSR_RI);
2340 if (lpes1 == 0)
2341 new_msr |= (target_ulong)MSR_HVB;
2342 goto store_next;
2343 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2344 srr0 = SPR_HSRR0;
2345 srr1 = SPR_HSRR1;
2346 new_msr |= (target_ulong)MSR_HVB;
2347 goto store_next;
2348 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2349 srr0 = SPR_HSRR0;
2350 srr1 = SPR_HSRR1;
2351 new_msr |= (target_ulong)MSR_HVB;
2352 goto store_next;
2353 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2354 srr0 = SPR_HSRR0;
2355 srr1 = SPR_HSRR1;
2356 new_msr |= (target_ulong)MSR_HVB;
2357 goto store_next;
2358 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2359 srr0 = SPR_HSRR0;
2360 srr1 = SPR_HSRR1;
2361 new_msr |= (target_ulong)MSR_HVB;
2362 goto store_next;
2363 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2364 new_msr &= ~((target_ulong)1 << MSR_RI);
2365 if (lpes1 == 0)
2366 new_msr |= (target_ulong)MSR_HVB;
2367 goto store_current;
2368 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
2369 LOG_EXCP("PIT exception\n");
2370 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2371 goto store_next;
2372 case POWERPC_EXCP_IO: /* IO error exception */
2373 /* XXX: TODO */
2374 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2375 goto store_next;
2376 case POWERPC_EXCP_RUNM: /* Run mode exception */
2377 /* XXX: TODO */
2378 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2379 goto store_next;
2380 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2381 /* XXX: TODO */
2382 cpu_abort(env, "602 emulation trap exception "
2383 "is not implemented yet !\n");
2384 goto store_next;
2385 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2386 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2387 if (lpes1 == 0) /* XXX: check this */
2388 new_msr |= (target_ulong)MSR_HVB;
2389 switch (excp_model) {
2390 case POWERPC_EXCP_602:
2391 case POWERPC_EXCP_603:
2392 case POWERPC_EXCP_603E:
2393 case POWERPC_EXCP_G2:
2394 goto tlb_miss_tgpr;
2395 case POWERPC_EXCP_7x5:
2396 goto tlb_miss;
2397 case POWERPC_EXCP_74xx:
2398 goto tlb_miss_74xx;
2399 default:
2400 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2401 break;
2402 }
2403 break;
2404 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2405 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2406 if (lpes1 == 0) /* XXX: check this */
2407 new_msr |= (target_ulong)MSR_HVB;
2408 switch (excp_model) {
2409 case POWERPC_EXCP_602:
2410 case POWERPC_EXCP_603:
2411 case POWERPC_EXCP_603E:
2412 case POWERPC_EXCP_G2:
2413 goto tlb_miss_tgpr;
2414 case POWERPC_EXCP_7x5:
2415 goto tlb_miss;
2416 case POWERPC_EXCP_74xx:
2417 goto tlb_miss_74xx;
2418 default:
2419 cpu_abort(env, "Invalid data load TLB miss exception\n");
2420 break;
2421 }
2422 break;
2423 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2424 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2425 if (lpes1 == 0) /* XXX: check this */
2426 new_msr |= (target_ulong)MSR_HVB;
2427 switch (excp_model) {
2428 case POWERPC_EXCP_602:
2429 case POWERPC_EXCP_603:
2430 case POWERPC_EXCP_603E:
2431 case POWERPC_EXCP_G2:
2432 tlb_miss_tgpr:
2433 /* Swap temporary saved registers with GPRs */
2434 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
2435 new_msr |= (target_ulong)1 << MSR_TGPR;
2436 hreg_swap_gpr_tgpr(env);
2437 }
2438 goto tlb_miss;
2439 case POWERPC_EXCP_7x5:
2440 tlb_miss:
2441 #if defined (DEBUG_SOFTWARE_TLB)
2442 if (qemu_log_enabled()) {
2443 const char *es;
2444 target_ulong *miss, *cmp;
2445 int en;
2446 if (excp == POWERPC_EXCP_IFTLB) {
2447 es = "I";
2448 en = 'I';
2449 miss = &env->spr[SPR_IMISS];
2450 cmp = &env->spr[SPR_ICMP];
2451 } else {
2452 if (excp == POWERPC_EXCP_DLTLB)
2453 es = "DL";
2454 else
2455 es = "DS";
2456 en = 'D';
2457 miss = &env->spr[SPR_DMISS];
2458 cmp = &env->spr[SPR_DCMP];
2459 }
2460 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
2461 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
2462 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
2463 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2464 env->error_code);
2465 }
2466 #endif
2467 msr |= env->crf[0] << 28;
2468 msr |= env->error_code; /* key, D/I, S/L bits */
2469 /* Set way using a LRU mechanism */
2470 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2471 break;
2472 case POWERPC_EXCP_74xx:
2473 tlb_miss_74xx:
2474 #if defined (DEBUG_SOFTWARE_TLB)
2475 if (qemu_log_enabled()) {
2476 const char *es;
2477 target_ulong *miss, *cmp;
2478 int en;
2479 if (excp == POWERPC_EXCP_IFTLB) {
2480 es = "I";
2481 en = 'I';
2482 miss = &env->spr[SPR_TLBMISS];
2483 cmp = &env->spr[SPR_PTEHI];
2484 } else {
2485 if (excp == POWERPC_EXCP_DLTLB)
2486 es = "DL";
2487 else
2488 es = "DS";
2489 en = 'D';
2490 miss = &env->spr[SPR_TLBMISS];
2491 cmp = &env->spr[SPR_PTEHI];
2492 }
2493 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
2494 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
2495 env->error_code);
2496 }
2497 #endif
2498 msr |= env->error_code; /* key bit */
2499 break;
2500 default:
2501 cpu_abort(env, "Invalid data store TLB miss exception\n");
2502 break;
2503 }
2504 goto store_next;
2505 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2506 /* XXX: TODO */
2507 cpu_abort(env, "Floating point assist exception "
2508 "is not implemented yet !\n");
2509 goto store_next;
2510 case POWERPC_EXCP_DABR: /* Data address breakpoint */
2511 /* XXX: TODO */
2512 cpu_abort(env, "DABR exception is not implemented yet !\n");
2513 goto store_next;
2514 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2515 /* XXX: TODO */
2516 cpu_abort(env, "IABR exception is not implemented yet !\n");
2517 goto store_next;
2518 case POWERPC_EXCP_SMI: /* System management interrupt */
2519 /* XXX: TODO */
2520 cpu_abort(env, "SMI exception is not implemented yet !\n");
2521 goto store_next;
2522 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2523 /* XXX: TODO */
2524 cpu_abort(env, "Thermal management exception "
2525 "is not implemented yet !\n");
2526 goto store_next;
2527 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2528 new_msr &= ~((target_ulong)1 << MSR_RI);
2529 if (lpes1 == 0)
2530 new_msr |= (target_ulong)MSR_HVB;
2531 /* XXX: TODO */
2532 cpu_abort(env,
2533 "Performance counter exception is not implemented yet !\n");
2534 goto store_next;
2535 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2536 /* XXX: TODO */
2537 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2538 goto store_next;
2539 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2540 /* XXX: TODO */
2541 cpu_abort(env,
2542 "970 soft-patch exception is not implemented yet !\n");
2543 goto store_next;
2544 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2545 /* XXX: TODO */
2546 cpu_abort(env,
2547 "970 maintenance exception is not implemented yet !\n");
2548 goto store_next;
2549 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
2550 /* XXX: TODO */
2551 cpu_abort(env, "Maskable external exception "
2552 "is not implemented yet !\n");
2553 goto store_next;
2554 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
2555 /* XXX: TODO */
2556 cpu_abort(env, "Non maskable external exception "
2557 "is not implemented yet !\n");
2558 goto store_next;
2559 default:
2560 excp_invalid:
2561 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2562 break;
2563 store_current:
2564 /* save current instruction location */
2565 env->spr[srr0] = env->nip - 4;
2566 break;
2567 store_next:
2568 /* save next instruction location */
2569 env->spr[srr0] = env->nip;
2570 break;
2571 }
2572 /* Save MSR */
2573 env->spr[srr1] = msr;
2574 /* If any alternate SRR register are defined, duplicate saved values */
2575 if (asrr0 != -1)
2576 env->spr[asrr0] = env->spr[srr0];
2577 if (asrr1 != -1)
2578 env->spr[asrr1] = env->spr[srr1];
2579 /* If we disactivated any translation, flush TLBs */
2580 if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
2581 tlb_flush(env, 1);
2582 /* reload MSR with correct bits */
2583 new_msr &= ~((target_ulong)1 << MSR_EE);
2584 new_msr &= ~((target_ulong)1 << MSR_PR);
2585 new_msr &= ~((target_ulong)1 << MSR_FP);
2586 new_msr &= ~((target_ulong)1 << MSR_FE0);
2587 new_msr &= ~((target_ulong)1 << MSR_SE);
2588 new_msr &= ~((target_ulong)1 << MSR_BE);
2589 new_msr &= ~((target_ulong)1 << MSR_FE1);
2590 new_msr &= ~((target_ulong)1 << MSR_IR);
2591 new_msr &= ~((target_ulong)1 << MSR_DR);
2592 #if 0 /* Fix this: not on all targets */
2593 new_msr &= ~((target_ulong)1 << MSR_PMM);
2594 #endif
2595 new_msr &= ~((target_ulong)1 << MSR_LE);
2596 if (msr_ile)
2597 new_msr |= (target_ulong)1 << MSR_LE;
2598 else
2599 new_msr &= ~((target_ulong)1 << MSR_LE);
2600 /* Jump to handler */
2601 vector = env->excp_vectors[excp];
2602 if (vector == (target_ulong)-1ULL) {
2603 cpu_abort(env, "Raised an exception without defined vector %d\n",
2604 excp);
2605 }
2606 vector |= env->excp_prefix;
2607 #if defined(TARGET_PPC64)
2608 if (excp_model == POWERPC_EXCP_BOOKE) {
2609 if (!msr_icm) {
2610 new_msr &= ~((target_ulong)1 << MSR_CM);
2611 vector = (uint32_t)vector;
2612 } else {
2613 new_msr |= (target_ulong)1 << MSR_CM;
2614 }
2615 } else {
2616 if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
2617 new_msr &= ~((target_ulong)1 << MSR_SF);
2618 vector = (uint32_t)vector;
2619 } else {
2620 new_msr |= (target_ulong)1 << MSR_SF;
2621 }
2622 }
2623 #endif
2624 /* XXX: we don't use hreg_store_msr here as already have treated
2625 * any special case that could occur. Just store MSR and update hflags
2626 */
2627 env->msr = new_msr & env->msr_mask;
2628 hreg_compute_hflags(env);
2629 env->nip = vector;
2630 /* Reset exception state */
2631 env->exception_index = POWERPC_EXCP_NONE;
2632 env->error_code = 0;
2633 }
2634
2635 void do_interrupt (CPUState *env)
2636 {
2637 powerpc_excp(env, env->excp_model, env->exception_index);
2638 }
2639
2640 void ppc_hw_interrupt (CPUPPCState *env)
2641 {
2642 int hdice;
2643
2644 #if 0
2645 qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
2646 __func__, env, env->pending_interrupts,
2647 env->interrupt_request, (int)msr_me, (int)msr_ee);
2648 #endif
2649 /* External reset */
2650 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2651 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2652 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2653 return;
2654 }
2655 /* Machine check exception */
2656 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2657 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2658 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2659 return;
2660 }
2661 #if 0 /* TODO */
2662 /* External debug exception */
2663 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2664 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2665 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2666 return;
2667 }
2668 #endif
2669 if (0) {
2670 /* XXX: find a suitable condition to enable the hypervisor mode */
2671 hdice = env->spr[SPR_LPCR] & 1;
2672 } else {
2673 hdice = 0;
2674 }
2675 if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
2676 /* Hypervisor decrementer exception */
2677 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2678 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2679 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2680 return;
2681 }
2682 }
2683 if (msr_ce != 0) {
2684 /* External critical interrupt */
2685 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2686 /* Taking a critical external interrupt does not clear the external
2687 * critical interrupt status
2688 */
2689 #if 0
2690 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2691 #endif
2692 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2693 return;
2694 }
2695 }
2696 if (msr_ee != 0) {
2697 /* Watchdog timer on embedded PowerPC */
2698 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2699 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2700 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2701 return;
2702 }
2703 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2704 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2705 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2706 return;
2707 }
2708 /* Fixed interval timer on embedded PowerPC */
2709 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2710 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2711 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2712 return;
2713 }
2714 /* Programmable interval timer on embedded PowerPC */
2715 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2716 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2717 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2718 return;
2719 }
2720 /* Decrementer exception */
2721 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2722 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2723 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2724 return;
2725 }
2726 /* External interrupt */
2727 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2728 /* Taking an external interrupt does not clear the external
2729 * interrupt status
2730 */
2731 #if 0
2732 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2733 #endif
2734 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2735 return;
2736 }
2737 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2738 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2739 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2740 return;
2741 }
2742 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2743 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2744 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2745 return;
2746 }
2747 /* Thermal interrupt */
2748 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2749 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2750 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2751 return;
2752 }
2753 }
2754 }
2755 #endif /* !CONFIG_USER_ONLY */
2756
2757 void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2758 {
2759 qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
2760 TARGET_FMT_lx "\n", RA, msr);
2761 }
2762
2763 void cpu_reset(CPUPPCState *env)
2764 {
2765 target_ulong msr;
2766
2767 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
2768 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
2769 log_cpu_state(env, 0);
2770 }
2771
2772 msr = (target_ulong)0;
2773 if (0) {
2774 /* XXX: find a suitable condition to enable the hypervisor mode */
2775 msr |= (target_ulong)MSR_HVB;
2776 }
2777 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
2778 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
2779 msr |= (target_ulong)1 << MSR_EP;
2780 #if defined (DO_SINGLE_STEP) && 0
2781 /* Single step trace mode */
2782 msr |= (target_ulong)1 << MSR_SE;
2783 msr |= (target_ulong)1 << MSR_BE;
2784 #endif
2785 #if defined(CONFIG_USER_ONLY)
2786 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
2787 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
2788 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
2789 msr |= (target_ulong)1 << MSR_PR;
2790 #else
2791 env->excp_prefix = env->hreset_excp_prefix;
2792 env->nip = env->hreset_vector | env->excp_prefix;
2793 if (env->mmu_model != POWERPC_MMU_REAL)
2794 ppc_tlb_invalidate_all(env);
2795 #endif
2796 env->msr = msr & env->msr_mask;
2797 #if defined(TARGET_PPC64)
2798 if (env->mmu_model & POWERPC_MMU_64)
2799 env->msr |= (1ULL << MSR_SF);
2800 #endif
2801 hreg_compute_hflags(env);
2802 env->reserve_addr = (target_ulong)-1ULL;
2803 /* Be sure no exception or interrupt is pending */
2804 env->pending_interrupts = 0;
2805 env->exception_index = POWERPC_EXCP_NONE;
2806 env->error_code = 0;
2807 /* Flush all TLBs */
2808 tlb_flush(env, 1);
2809 }
2810
2811 CPUPPCState *cpu_ppc_init (const char *cpu_model)
2812 {
2813 CPUPPCState *env;
2814 const ppc_def_t *def;
2815
2816 def = cpu_ppc_find_by_name(cpu_model);
2817 if (!def)
2818 return NULL;
2819
2820 env = qemu_mallocz(sizeof(CPUPPCState));
2821 cpu_exec_init(env);
2822 ppc_translate_init();
2823 env->cpu_model_str = cpu_model;
2824 cpu_ppc_register_internal(env, def);
2825
2826 qemu_init_vcpu(env);
2827
2828 return env;
2829 }
2830
2831 void cpu_ppc_close (CPUPPCState *env)
2832 {
2833 /* Should also remove all opcode tables... */
2834 qemu_free(env);
2835 }
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