2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "helper_regs.h"
29 #include "qemu-common.h"
35 //#define DEBUG_SOFTWARE_TLB
36 //#define DUMP_PAGE_TABLES
37 //#define DEBUG_EXCEPTIONS
38 //#define FLUSH_ALL_TLBS
41 # define LOG_MMU(...) qemu_log(__VA_ARGS__)
42 # define LOG_MMU_STATE(env) log_cpu_state((env), 0)
44 # define LOG_MMU(...) do { } while (0)
45 # define LOG_MMU_STATE(...) do { } while (0)
49 #ifdef DEBUG_SOFTWARE_TLB
50 # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
52 # define LOG_SWTLB(...) do { } while (0)
56 # define LOG_BATS(...) qemu_log(__VA_ARGS__)
58 # define LOG_BATS(...) do { } while (0)
62 # define LOG_SLB(...) qemu_log(__VA_ARGS__)
64 # define LOG_SLB(...) do { } while (0)
67 #ifdef DEBUG_EXCEPTIONS
68 # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
70 # define LOG_EXCP(...) do { } while (0)
74 /*****************************************************************************/
75 /* PowerPC MMU emulation */
77 #if defined(CONFIG_USER_ONLY)
78 int cpu_ppc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
79 int mmu_idx
, int is_softmmu
)
81 int exception
, error_code
;
84 exception
= POWERPC_EXCP_ISI
;
85 error_code
= 0x40000000;
87 exception
= POWERPC_EXCP_DSI
;
88 error_code
= 0x40000000;
90 error_code
|= 0x02000000;
91 env
->spr
[SPR_DAR
] = address
;
92 env
->spr
[SPR_DSISR
] = error_code
;
94 env
->exception_index
= exception
;
95 env
->error_code
= error_code
;
101 /* Common routines used by software and hardware TLBs emulation */
102 static inline int pte_is_valid(target_ulong pte0
)
104 return pte0
& 0x80000000 ? 1 : 0;
107 static inline void pte_invalidate(target_ulong
*pte0
)
109 *pte0
&= ~0x80000000;
112 #if defined(TARGET_PPC64)
113 static inline int pte64_is_valid(target_ulong pte0
)
115 return pte0
& 0x0000000000000001ULL
? 1 : 0;
118 static inline void pte64_invalidate(target_ulong
*pte0
)
120 *pte0
&= ~0x0000000000000001ULL
;
124 #define PTE_PTEM_MASK 0x7FFFFFBF
125 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
126 #if defined(TARGET_PPC64)
127 #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
128 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
131 static inline int pp_check(int key
, int pp
, int nx
)
135 /* Compute access rights */
136 /* When pp is 3/7, the result is undefined. Set it to noaccess */
143 access
|= PAGE_WRITE
;
161 access
= PAGE_READ
| PAGE_WRITE
;
171 static inline int check_prot(int prot
, int rw
, int access_type
)
175 if (access_type
== ACCESS_CODE
) {
176 if (prot
& PAGE_EXEC
)
181 if (prot
& PAGE_WRITE
)
186 if (prot
& PAGE_READ
)
195 static inline int _pte_check(mmu_ctx_t
*ctx
, int is_64b
, target_ulong pte0
,
196 target_ulong pte1
, int h
, int rw
, int type
)
198 target_ulong ptem
, mmask
;
199 int access
, ret
, pteh
, ptev
, pp
;
202 /* Check validity and table match */
203 #if defined(TARGET_PPC64)
205 ptev
= pte64_is_valid(pte0
);
206 pteh
= (pte0
>> 1) & 1;
210 ptev
= pte_is_valid(pte0
);
211 pteh
= (pte0
>> 6) & 1;
213 if (ptev
&& h
== pteh
) {
214 /* Check vsid & api */
215 #if defined(TARGET_PPC64)
217 ptem
= pte0
& PTE64_PTEM_MASK
;
218 mmask
= PTE64_CHECK_MASK
;
219 pp
= (pte1
& 0x00000003) | ((pte1
>> 61) & 0x00000004);
220 ctx
->nx
= (pte1
>> 2) & 1; /* No execute bit */
221 ctx
->nx
|= (pte1
>> 3) & 1; /* Guarded bit */
225 ptem
= pte0
& PTE_PTEM_MASK
;
226 mmask
= PTE_CHECK_MASK
;
227 pp
= pte1
& 0x00000003;
229 if (ptem
== ctx
->ptem
) {
230 if (ctx
->raddr
!= (target_phys_addr_t
)-1ULL) {
231 /* all matches should have equal RPN, WIMG & PP */
232 if ((ctx
->raddr
& mmask
) != (pte1
& mmask
)) {
233 qemu_log("Bad RPN/WIMG/PP\n");
237 /* Compute access rights */
238 access
= pp_check(ctx
->key
, pp
, ctx
->nx
);
239 /* Keep the matching PTE informations */
242 ret
= check_prot(ctx
->prot
, rw
, type
);
245 LOG_MMU("PTE access granted !\n");
247 /* Access right violation */
248 LOG_MMU("PTE access rejected\n");
256 static inline int pte32_check(mmu_ctx_t
*ctx
, target_ulong pte0
,
257 target_ulong pte1
, int h
, int rw
, int type
)
259 return _pte_check(ctx
, 0, pte0
, pte1
, h
, rw
, type
);
262 #if defined(TARGET_PPC64)
263 static inline int pte64_check(mmu_ctx_t
*ctx
, target_ulong pte0
,
264 target_ulong pte1
, int h
, int rw
, int type
)
266 return _pte_check(ctx
, 1, pte0
, pte1
, h
, rw
, type
);
270 static inline int pte_update_flags(mmu_ctx_t
*ctx
, target_ulong
*pte1p
,
275 /* Update page flags */
276 if (!(*pte1p
& 0x00000100)) {
277 /* Update accessed flag */
278 *pte1p
|= 0x00000100;
281 if (!(*pte1p
& 0x00000080)) {
282 if (rw
== 1 && ret
== 0) {
283 /* Update changed flag */
284 *pte1p
|= 0x00000080;
287 /* Force page fault for first write access */
288 ctx
->prot
&= ~PAGE_WRITE
;
295 /* Software driven TLB helpers */
296 static inline int ppc6xx_tlb_getnum(CPUState
*env
, target_ulong eaddr
, int way
,
301 /* Select TLB num in a way from address */
302 nr
= (eaddr
>> TARGET_PAGE_BITS
) & (env
->tlb_per_way
- 1);
304 nr
+= env
->tlb_per_way
* way
;
305 /* 6xx have separate TLBs for instructions and data */
306 if (is_code
&& env
->id_tlbs
== 1)
312 static inline void ppc6xx_tlb_invalidate_all(CPUState
*env
)
317 //LOG_SWTLB("Invalidate all TLBs\n");
318 /* Invalidate all defined software TLB */
320 if (env
->id_tlbs
== 1)
322 for (nr
= 0; nr
< max
; nr
++) {
323 tlb
= &env
->tlb
[nr
].tlb6
;
324 pte_invalidate(&tlb
->pte0
);
329 static inline void __ppc6xx_tlb_invalidate_virt(CPUState
*env
,
331 int is_code
, int match_epn
)
333 #if !defined(FLUSH_ALL_TLBS)
337 /* Invalidate ITLB + DTLB, all ways */
338 for (way
= 0; way
< env
->nb_ways
; way
++) {
339 nr
= ppc6xx_tlb_getnum(env
, eaddr
, way
, is_code
);
340 tlb
= &env
->tlb
[nr
].tlb6
;
341 if (pte_is_valid(tlb
->pte0
) && (match_epn
== 0 || eaddr
== tlb
->EPN
)) {
342 LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx
"\n", nr
,
344 pte_invalidate(&tlb
->pte0
);
345 tlb_flush_page(env
, tlb
->EPN
);
349 /* XXX: PowerPC specification say this is valid as well */
350 ppc6xx_tlb_invalidate_all(env
);
354 static inline void ppc6xx_tlb_invalidate_virt(CPUState
*env
,
355 target_ulong eaddr
, int is_code
)
357 __ppc6xx_tlb_invalidate_virt(env
, eaddr
, is_code
, 0);
360 void ppc6xx_tlb_store (CPUState
*env
, target_ulong EPN
, int way
, int is_code
,
361 target_ulong pte0
, target_ulong pte1
)
366 nr
= ppc6xx_tlb_getnum(env
, EPN
, way
, is_code
);
367 tlb
= &env
->tlb
[nr
].tlb6
;
368 LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx
" PTE0 " TARGET_FMT_lx
369 " PTE1 " TARGET_FMT_lx
"\n", nr
, env
->nb_tlb
, EPN
, pte0
, pte1
);
370 /* Invalidate any pending reference in Qemu for this virtual address */
371 __ppc6xx_tlb_invalidate_virt(env
, EPN
, is_code
, 1);
375 /* Store last way for LRU mechanism */
379 static inline int ppc6xx_tlb_check(CPUState
*env
, mmu_ctx_t
*ctx
,
380 target_ulong eaddr
, int rw
, int access_type
)
387 ret
= -1; /* No TLB found */
388 for (way
= 0; way
< env
->nb_ways
; way
++) {
389 nr
= ppc6xx_tlb_getnum(env
, eaddr
, way
,
390 access_type
== ACCESS_CODE
? 1 : 0);
391 tlb
= &env
->tlb
[nr
].tlb6
;
392 /* This test "emulates" the PTE index match for hardware TLBs */
393 if ((eaddr
& TARGET_PAGE_MASK
) != tlb
->EPN
) {
394 LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx
" " TARGET_FMT_lx
395 "] <> " TARGET_FMT_lx
"\n", nr
, env
->nb_tlb
,
396 pte_is_valid(tlb
->pte0
) ? "valid" : "inval",
397 tlb
->EPN
, tlb
->EPN
+ TARGET_PAGE_SIZE
, eaddr
);
400 LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx
" <> " TARGET_FMT_lx
" "
401 TARGET_FMT_lx
" %c %c\n", nr
, env
->nb_tlb
,
402 pte_is_valid(tlb
->pte0
) ? "valid" : "inval",
403 tlb
->EPN
, eaddr
, tlb
->pte1
,
404 rw
? 'S' : 'L', access_type
== ACCESS_CODE
? 'I' : 'D');
405 switch (pte32_check(ctx
, tlb
->pte0
, tlb
->pte1
, 0, rw
, access_type
)) {
407 /* TLB inconsistency */
410 /* Access violation */
420 /* XXX: we should go on looping to check all TLBs consistency
421 * but we can speed-up the whole thing as the
422 * result would be undefined if TLBs are not consistent.
431 LOG_SWTLB("found TLB at addr " TARGET_FMT_plx
" prot=%01x ret=%d\n",
432 ctx
->raddr
& TARGET_PAGE_MASK
, ctx
->prot
, ret
);
433 /* Update page flags */
434 pte_update_flags(ctx
, &env
->tlb
[best
].tlb6
.pte1
, ret
, rw
);
440 /* Perform BAT hit & translation */
441 static inline void bat_size_prot(CPUState
*env
, target_ulong
*blp
, int *validp
,
442 int *protp
, target_ulong
*BATu
,
448 bl
= (*BATu
& 0x00001FFC) << 15;
451 if (((msr_pr
== 0) && (*BATu
& 0x00000002)) ||
452 ((msr_pr
!= 0) && (*BATu
& 0x00000001))) {
454 pp
= *BATl
& 0x00000003;
456 prot
= PAGE_READ
| PAGE_EXEC
;
466 static inline void bat_601_size_prot(CPUState
*env
, target_ulong
*blp
,
467 int *validp
, int *protp
,
468 target_ulong
*BATu
, target_ulong
*BATl
)
471 int key
, pp
, valid
, prot
;
473 bl
= (*BATl
& 0x0000003F) << 17;
474 LOG_BATS("b %02x ==> bl " TARGET_FMT_lx
" msk " TARGET_FMT_lx
"\n",
475 (uint8_t)(*BATl
& 0x0000003F), bl
, ~bl
);
477 valid
= (*BATl
>> 6) & 1;
479 pp
= *BATu
& 0x00000003;
481 key
= (*BATu
>> 3) & 1;
483 key
= (*BATu
>> 2) & 1;
484 prot
= pp_check(key
, pp
, 0);
491 static inline int get_bat(CPUState
*env
, mmu_ctx_t
*ctx
, target_ulong
virtual,
494 target_ulong
*BATlt
, *BATut
, *BATu
, *BATl
;
495 target_ulong BEPIl
, BEPIu
, bl
;
499 LOG_BATS("%s: %cBAT v " TARGET_FMT_lx
"\n", __func__
,
500 type
== ACCESS_CODE
? 'I' : 'D', virtual);
503 BATlt
= env
->IBAT
[1];
504 BATut
= env
->IBAT
[0];
507 BATlt
= env
->DBAT
[1];
508 BATut
= env
->DBAT
[0];
511 for (i
= 0; i
< env
->nb_BATs
; i
++) {
514 BEPIu
= *BATu
& 0xF0000000;
515 BEPIl
= *BATu
& 0x0FFE0000;
516 if (unlikely(env
->mmu_model
== POWERPC_MMU_601
)) {
517 bat_601_size_prot(env
, &bl
, &valid
, &prot
, BATu
, BATl
);
519 bat_size_prot(env
, &bl
, &valid
, &prot
, BATu
, BATl
);
521 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx
" BATu " TARGET_FMT_lx
522 " BATl " TARGET_FMT_lx
"\n", __func__
,
523 type
== ACCESS_CODE
? 'I' : 'D', i
, virtual, *BATu
, *BATl
);
524 if ((virtual & 0xF0000000) == BEPIu
&&
525 ((virtual & 0x0FFE0000) & ~bl
) == BEPIl
) {
528 /* Get physical address */
529 ctx
->raddr
= (*BATl
& 0xF0000000) |
530 ((virtual & 0x0FFE0000 & bl
) | (*BATl
& 0x0FFE0000)) |
531 (virtual & 0x0001F000);
532 /* Compute access rights */
534 ret
= check_prot(ctx
->prot
, rw
, type
);
536 LOG_BATS("BAT %d match: r " TARGET_FMT_plx
" prot=%c%c\n",
537 i
, ctx
->raddr
, ctx
->prot
& PAGE_READ
? 'R' : '-',
538 ctx
->prot
& PAGE_WRITE
? 'W' : '-');
544 #if defined(DEBUG_BATS)
545 if (qemu_log_enabled()) {
546 LOG_BATS("no BAT match for " TARGET_FMT_lx
":\n", virtual);
547 for (i
= 0; i
< 4; i
++) {
550 BEPIu
= *BATu
& 0xF0000000;
551 BEPIl
= *BATu
& 0x0FFE0000;
552 bl
= (*BATu
& 0x00001FFC) << 15;
553 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx
" BATu " TARGET_FMT_lx
554 " BATl " TARGET_FMT_lx
" \n\t" TARGET_FMT_lx
" "
555 TARGET_FMT_lx
" " TARGET_FMT_lx
"\n",
556 __func__
, type
== ACCESS_CODE
? 'I' : 'D', i
, virtual,
557 *BATu
, *BATl
, BEPIu
, BEPIl
, bl
);
566 /* PTE table lookup */
567 static inline int _find_pte(mmu_ctx_t
*ctx
, int is_64b
, int h
, int rw
,
568 int type
, int target_page_bits
)
570 target_ulong base
, pte0
, pte1
;
574 ret
= -1; /* No entry found */
575 base
= ctx
->pg_addr
[h
];
576 for (i
= 0; i
< 8; i
++) {
577 #if defined(TARGET_PPC64)
579 pte0
= ldq_phys(base
+ (i
* 16));
580 pte1
= ldq_phys(base
+ (i
* 16) + 8);
582 /* We have a TLB that saves 4K pages, so let's
583 * split a huge page to 4k chunks */
584 if (target_page_bits
!= TARGET_PAGE_BITS
)
585 pte1
|= (ctx
->eaddr
& (( 1 << target_page_bits
) - 1))
588 r
= pte64_check(ctx
, pte0
, pte1
, h
, rw
, type
);
589 LOG_MMU("Load pte from " TARGET_FMT_lx
" => " TARGET_FMT_lx
" "
590 TARGET_FMT_lx
" %d %d %d " TARGET_FMT_lx
"\n",
591 base
+ (i
* 16), pte0
, pte1
, (int)(pte0
& 1), h
,
592 (int)((pte0
>> 1) & 1), ctx
->ptem
);
596 pte0
= ldl_phys(base
+ (i
* 8));
597 pte1
= ldl_phys(base
+ (i
* 8) + 4);
598 r
= pte32_check(ctx
, pte0
, pte1
, h
, rw
, type
);
599 LOG_MMU("Load pte from " TARGET_FMT_lx
" => " TARGET_FMT_lx
" "
600 TARGET_FMT_lx
" %d %d %d " TARGET_FMT_lx
"\n",
601 base
+ (i
* 8), pte0
, pte1
, (int)(pte0
>> 31), h
,
602 (int)((pte0
>> 6) & 1), ctx
->ptem
);
606 /* PTE inconsistency */
609 /* Access violation */
619 /* XXX: we should go on looping to check all PTEs consistency
620 * but if we can speed-up the whole thing as the
621 * result would be undefined if PTEs are not consistent.
630 LOG_MMU("found PTE at addr " TARGET_FMT_lx
" prot=%01x ret=%d\n",
631 ctx
->raddr
, ctx
->prot
, ret
);
632 /* Update page flags */
634 if (pte_update_flags(ctx
, &pte1
, ret
, rw
) == 1) {
635 #if defined(TARGET_PPC64)
637 stq_phys_notdirty(base
+ (good
* 16) + 8, pte1
);
641 stl_phys_notdirty(base
+ (good
* 8) + 4, pte1
);
649 static inline int find_pte32(mmu_ctx_t
*ctx
, int h
, int rw
, int type
,
650 int target_page_bits
)
652 return _find_pte(ctx
, 0, h
, rw
, type
, target_page_bits
);
655 #if defined(TARGET_PPC64)
656 static inline int find_pte64(mmu_ctx_t
*ctx
, int h
, int rw
, int type
,
657 int target_page_bits
)
659 return _find_pte(ctx
, 1, h
, rw
, type
, target_page_bits
);
663 static inline int find_pte(CPUState
*env
, mmu_ctx_t
*ctx
, int h
, int rw
,
664 int type
, int target_page_bits
)
666 #if defined(TARGET_PPC64)
667 if (env
->mmu_model
& POWERPC_MMU_64
)
668 return find_pte64(ctx
, h
, rw
, type
, target_page_bits
);
671 return find_pte32(ctx
, h
, rw
, type
, target_page_bits
);
674 #if defined(TARGET_PPC64)
675 static ppc_slb_t
*slb_get_entry(CPUPPCState
*env
, int nr
)
677 ppc_slb_t
*retval
= &env
->slb
[nr
];
679 #if 0 // XXX implement bridge mode?
680 if (env
->spr
[SPR_ASR
] & 1) {
681 target_phys_addr_t sr_base
;
683 sr_base
= env
->spr
[SPR_ASR
] & 0xfffffffffffff000;
684 sr_base
+= (12 * nr
);
686 retval
->tmp64
= ldq_phys(sr_base
);
687 retval
->tmp
= ldl_phys(sr_base
+ 8);
694 static void slb_set_entry(CPUPPCState
*env
, int nr
, ppc_slb_t
*slb
)
696 ppc_slb_t
*entry
= &env
->slb
[nr
];
701 entry
->tmp64
= slb
->tmp64
;
702 entry
->tmp
= slb
->tmp
;
705 static inline int slb_is_valid(ppc_slb_t
*slb
)
707 return (int)(slb
->tmp64
& 0x0000000008000000ULL
);
710 static inline void slb_invalidate(ppc_slb_t
*slb
)
712 slb
->tmp64
&= ~0x0000000008000000ULL
;
715 static inline int slb_lookup(CPUPPCState
*env
, target_ulong eaddr
,
716 target_ulong
*vsid
, target_ulong
*page_mask
,
717 int *attr
, int *target_page_bits
)
723 LOG_SLB("%s: eaddr " TARGET_FMT_lx
"\n", __func__
, eaddr
);
724 mask
= 0x0000000000000000ULL
; /* Avoid gcc warning */
725 for (n
= 0; n
< env
->slb_nr
; n
++) {
726 ppc_slb_t
*slb
= slb_get_entry(env
, n
);
728 LOG_SLB("%s: seg %d %016" PRIx64
" %08"
729 PRIx32
"\n", __func__
, n
, slb
->tmp64
, slb
->tmp
);
730 if (slb_is_valid(slb
)) {
731 /* SLB entry is valid */
732 mask
= 0xFFFFFFFFF0000000ULL
;
733 if (slb
->tmp
& 0x8) {
735 if (target_page_bits
)
736 *target_page_bits
= 24;
739 if (target_page_bits
)
740 *target_page_bits
= TARGET_PAGE_BITS
;
742 if ((eaddr
& mask
) == (slb
->tmp64
& mask
)) {
744 *vsid
= ((slb
->tmp64
<< 24) | (slb
->tmp
>> 8)) & 0x0003FFFFFFFFFFFFULL
;
746 *attr
= slb
->tmp
& 0xFF;
756 void ppc_slb_invalidate_all (CPUPPCState
*env
)
758 int n
, do_invalidate
;
761 /* XXX: Warning: slbia never invalidates the first segment */
762 for (n
= 1; n
< env
->slb_nr
; n
++) {
763 ppc_slb_t
*slb
= slb_get_entry(env
, n
);
765 if (slb_is_valid(slb
)) {
767 slb_set_entry(env
, n
, slb
);
768 /* XXX: given the fact that segment size is 256 MB or 1TB,
769 * and we still don't have a tlb_flush_mask(env, n, mask)
770 * in Qemu, we just invalidate all TLBs
779 void ppc_slb_invalidate_one (CPUPPCState
*env
, uint64_t T0
)
781 target_ulong vsid
, page_mask
;
785 n
= slb_lookup(env
, T0
, &vsid
, &page_mask
, &attr
, NULL
);
787 ppc_slb_t
*slb
= slb_get_entry(env
, n
);
789 if (slb_is_valid(slb
)) {
791 slb_set_entry(env
, n
, slb
);
792 /* XXX: given the fact that segment size is 256 MB or 1TB,
793 * and we still don't have a tlb_flush_mask(env, n, mask)
794 * in Qemu, we just invalidate all TLBs
801 target_ulong
ppc_load_slb (CPUPPCState
*env
, int slb_nr
)
804 ppc_slb_t
*slb
= slb_get_entry(env
, slb_nr
);
806 if (slb_is_valid(slb
)) {
807 /* SLB entry is valid */
808 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
809 rt
= slb
->tmp
>> 8; /* 65:88 => 40:63 */
810 rt
|= (slb
->tmp64
& 0x7) << 24; /* 62:64 => 37:39 */
811 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
812 rt
|= ((slb
->tmp
>> 4) & 0xF) << 27;
816 LOG_SLB("%s: %016" PRIx64
" %08" PRIx32
" => %d "
817 TARGET_FMT_lx
"\n", __func__
, slb
->tmp64
, slb
->tmp
, slb_nr
, rt
);
822 void ppc_store_slb (CPUPPCState
*env
, target_ulong rb
, target_ulong rs
)
828 int flags
, valid
, slb_nr
;
831 flags
= ((rs
>> 8) & 0xf);
834 valid
= (rb
& (1 << 27));
837 slb
= slb_get_entry(env
, slb_nr
);
838 slb
->tmp64
= (esid
<< 28) | valid
| (vsid
>> 24);
839 slb
->tmp
= (vsid
<< 8) | (flags
<< 3);
841 LOG_SLB("%s: %d " TARGET_FMT_lx
" - " TARGET_FMT_lx
" => %016" PRIx64
842 " %08" PRIx32
"\n", __func__
, slb_nr
, rb
, rs
, slb
->tmp64
,
845 slb_set_entry(env
, slb_nr
, slb
);
847 #endif /* defined(TARGET_PPC64) */
849 /* Perform segment based translation */
850 static inline target_phys_addr_t
get_pgaddr(target_phys_addr_t sdr1
,
852 target_phys_addr_t hash
,
853 target_phys_addr_t mask
)
855 return (sdr1
& ((target_phys_addr_t
)(-1ULL) << sdr_sh
)) | (hash
& mask
);
858 static inline int get_segment(CPUState
*env
, mmu_ctx_t
*ctx
,
859 target_ulong eaddr
, int rw
, int type
)
861 target_phys_addr_t sdr
, hash
, mask
, sdr_mask
, htab_mask
;
862 target_ulong sr
, vsid
, vsid_mask
, pgidx
, page_mask
;
863 #if defined(TARGET_PPC64)
866 int ds
, vsid_sh
, sdr_sh
, pr
, target_page_bits
;
870 #if defined(TARGET_PPC64)
871 if (env
->mmu_model
& POWERPC_MMU_64
) {
872 LOG_MMU("Check SLBs\n");
873 ret
= slb_lookup(env
, eaddr
, &vsid
, &page_mask
, &attr
,
877 ctx
->key
= ((attr
& 0x40) && (pr
!= 0)) ||
878 ((attr
& 0x80) && (pr
== 0)) ? 1 : 0;
880 ctx
->nx
= attr
& 0x10 ? 1 : 0;
882 vsid_mask
= 0x00003FFFFFFFFF80ULL
;
887 #endif /* defined(TARGET_PPC64) */
889 sr
= env
->sr
[eaddr
>> 28];
890 page_mask
= 0x0FFFFFFF;
891 ctx
->key
= (((sr
& 0x20000000) && (pr
!= 0)) ||
892 ((sr
& 0x40000000) && (pr
== 0))) ? 1 : 0;
893 ds
= sr
& 0x80000000 ? 1 : 0;
894 ctx
->nx
= sr
& 0x10000000 ? 1 : 0;
895 vsid
= sr
& 0x00FFFFFF;
896 vsid_mask
= 0x01FFFFC0;
900 target_page_bits
= TARGET_PAGE_BITS
;
901 LOG_MMU("Check segment v=" TARGET_FMT_lx
" %d " TARGET_FMT_lx
" nip="
902 TARGET_FMT_lx
" lr=" TARGET_FMT_lx
903 " ir=%d dr=%d pr=%d %d t=%d\n",
904 eaddr
, (int)(eaddr
>> 28), sr
, env
->nip
, env
->lr
, (int)msr_ir
,
905 (int)msr_dr
, pr
!= 0 ? 1 : 0, rw
, type
);
907 LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx
"\n",
908 ctx
->key
, ds
, ctx
->nx
, vsid
);
911 /* Check if instruction fetch is allowed, if needed */
912 if (type
!= ACCESS_CODE
|| ctx
->nx
== 0) {
913 /* Page address translation */
914 /* Primary table address */
916 pgidx
= (eaddr
& page_mask
) >> target_page_bits
;
917 #if defined(TARGET_PPC64)
918 if (env
->mmu_model
& POWERPC_MMU_64
) {
919 htab_mask
= 0x0FFFFFFF >> (28 - (sdr
& 0x1F));
920 /* XXX: this is false for 1 TB segments */
921 hash
= ((vsid
^ pgidx
) << vsid_sh
) & vsid_mask
;
925 htab_mask
= sdr
& 0x000001FF;
926 hash
= ((vsid
^ pgidx
) << vsid_sh
) & vsid_mask
;
928 mask
= (htab_mask
<< sdr_sh
) | sdr_mask
;
929 LOG_MMU("sdr " TARGET_FMT_plx
" sh %d hash " TARGET_FMT_plx
930 " mask " TARGET_FMT_plx
" " TARGET_FMT_lx
"\n",
931 sdr
, sdr_sh
, hash
, mask
, page_mask
);
932 ctx
->pg_addr
[0] = get_pgaddr(sdr
, sdr_sh
, hash
, mask
);
933 /* Secondary table address */
934 hash
= (~hash
) & vsid_mask
;
935 LOG_MMU("sdr " TARGET_FMT_plx
" sh %d hash " TARGET_FMT_plx
936 " mask " TARGET_FMT_plx
"\n", sdr
, sdr_sh
, hash
, mask
);
937 ctx
->pg_addr
[1] = get_pgaddr(sdr
, sdr_sh
, hash
, mask
);
938 #if defined(TARGET_PPC64)
939 if (env
->mmu_model
& POWERPC_MMU_64
) {
940 /* Only 5 bits of the page index are used in the AVPN */
941 if (target_page_bits
> 23) {
942 ctx
->ptem
= (vsid
<< 12) |
943 ((pgidx
<< (target_page_bits
- 16)) & 0xF80);
945 ctx
->ptem
= (vsid
<< 12) | ((pgidx
>> 4) & 0x0F80);
950 ctx
->ptem
= (vsid
<< 7) | (pgidx
>> 10);
952 /* Initialize real address with an invalid value */
953 ctx
->raddr
= (target_phys_addr_t
)-1ULL;
954 if (unlikely(env
->mmu_model
== POWERPC_MMU_SOFT_6xx
||
955 env
->mmu_model
== POWERPC_MMU_SOFT_74xx
)) {
956 /* Software TLB search */
957 ret
= ppc6xx_tlb_check(env
, ctx
, eaddr
, rw
, type
);
959 LOG_MMU("0 sdr1=" TARGET_FMT_plx
" vsid=" TARGET_FMT_lx
" "
960 "api=" TARGET_FMT_lx
" hash=" TARGET_FMT_plx
961 " pg_addr=" TARGET_FMT_plx
"\n",
962 sdr
, vsid
, pgidx
, hash
, ctx
->pg_addr
[0]);
963 /* Primary table lookup */
964 ret
= find_pte(env
, ctx
, 0, rw
, type
, target_page_bits
);
966 /* Secondary table lookup */
967 if (eaddr
!= 0xEFFFFFFF)
968 LOG_MMU("1 sdr1=" TARGET_FMT_plx
" vsid=" TARGET_FMT_lx
" "
969 "api=" TARGET_FMT_lx
" hash=" TARGET_FMT_plx
970 " pg_addr=" TARGET_FMT_plx
"\n", sdr
, vsid
,
971 pgidx
, hash
, ctx
->pg_addr
[1]);
972 ret2
= find_pte(env
, ctx
, 1, rw
, type
,
978 #if defined (DUMP_PAGE_TABLES)
979 if (qemu_log_enabled()) {
980 target_phys_addr_t curaddr
;
981 uint32_t a0
, a1
, a2
, a3
;
982 qemu_log("Page table: " TARGET_FMT_plx
" len " TARGET_FMT_plx
983 "\n", sdr
, mask
+ 0x80);
984 for (curaddr
= sdr
; curaddr
< (sdr
+ mask
+ 0x80);
986 a0
= ldl_phys(curaddr
);
987 a1
= ldl_phys(curaddr
+ 4);
988 a2
= ldl_phys(curaddr
+ 8);
989 a3
= ldl_phys(curaddr
+ 12);
990 if (a0
!= 0 || a1
!= 0 || a2
!= 0 || a3
!= 0) {
991 qemu_log(TARGET_FMT_plx
": %08x %08x %08x %08x\n",
992 curaddr
, a0
, a1
, a2
, a3
);
998 LOG_MMU("No access allowed\n");
1002 LOG_MMU("direct store...\n");
1003 /* Direct-store segment : absolutely *BUGGY* for now */
1006 /* Integer load/store : only access allowed */
1009 /* No code fetch is allowed in direct-store areas */
1012 /* Floating point load/store */
1015 /* lwarx, ldarx or srwcx. */
1018 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
1019 /* Should make the instruction do no-op.
1020 * As it already do no-op, it's quite easy :-)
1025 /* eciwx or ecowx */
1028 qemu_log("ERROR: instruction should not need "
1029 "address translation\n");
1032 if ((rw
== 1 || ctx
->key
!= 1) && (rw
== 0 || ctx
->key
!= 0)) {
1043 /* Generic TLB check function for embedded PowerPC implementations */
1044 static inline int ppcemb_tlb_check(CPUState
*env
, ppcemb_tlb_t
*tlb
,
1045 target_phys_addr_t
*raddrp
,
1046 target_ulong address
, uint32_t pid
, int ext
,
1051 /* Check valid flag */
1052 if (!(tlb
->prot
& PAGE_VALID
)) {
1053 qemu_log("%s: TLB %d not valid\n", __func__
, i
);
1056 mask
= ~(tlb
->size
- 1);
1057 LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx
" PID %u <=> " TARGET_FMT_lx
1058 " " TARGET_FMT_lx
" %u\n", __func__
, i
, address
, pid
, tlb
->EPN
,
1059 mask
, (uint32_t)tlb
->PID
);
1061 if (tlb
->PID
!= 0 && tlb
->PID
!= pid
)
1063 /* Check effective address */
1064 if ((address
& mask
) != tlb
->EPN
)
1066 *raddrp
= (tlb
->RPN
& mask
) | (address
& ~mask
);
1067 #if (TARGET_PHYS_ADDR_BITS >= 36)
1069 /* Extend the physical address to 36 bits */
1070 *raddrp
|= (target_phys_addr_t
)(tlb
->RPN
& 0xF) << 32;
1077 /* Generic TLB search function for PowerPC embedded implementations */
1078 int ppcemb_tlb_search (CPUPPCState
*env
, target_ulong address
, uint32_t pid
)
1081 target_phys_addr_t raddr
;
1084 /* Default return value is no match */
1086 for (i
= 0; i
< env
->nb_tlb
; i
++) {
1087 tlb
= &env
->tlb
[i
].tlbe
;
1088 if (ppcemb_tlb_check(env
, tlb
, &raddr
, address
, pid
, 0, i
) == 0) {
1097 /* Helpers specific to PowerPC 40x implementations */
1098 static inline void ppc4xx_tlb_invalidate_all(CPUState
*env
)
1103 for (i
= 0; i
< env
->nb_tlb
; i
++) {
1104 tlb
= &env
->tlb
[i
].tlbe
;
1105 tlb
->prot
&= ~PAGE_VALID
;
1110 static inline void ppc4xx_tlb_invalidate_virt(CPUState
*env
,
1111 target_ulong eaddr
, uint32_t pid
)
1113 #if !defined(FLUSH_ALL_TLBS)
1115 target_phys_addr_t raddr
;
1116 target_ulong page
, end
;
1119 for (i
= 0; i
< env
->nb_tlb
; i
++) {
1120 tlb
= &env
->tlb
[i
].tlbe
;
1121 if (ppcemb_tlb_check(env
, tlb
, &raddr
, eaddr
, pid
, 0, i
) == 0) {
1122 end
= tlb
->EPN
+ tlb
->size
;
1123 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
1124 tlb_flush_page(env
, page
);
1125 tlb
->prot
&= ~PAGE_VALID
;
1130 ppc4xx_tlb_invalidate_all(env
);
1134 static int mmu40x_get_physical_address (CPUState
*env
, mmu_ctx_t
*ctx
,
1135 target_ulong address
, int rw
, int access_type
)
1138 target_phys_addr_t raddr
;
1139 int i
, ret
, zsel
, zpr
, pr
;
1142 raddr
= (target_phys_addr_t
)-1ULL;
1144 for (i
= 0; i
< env
->nb_tlb
; i
++) {
1145 tlb
= &env
->tlb
[i
].tlbe
;
1146 if (ppcemb_tlb_check(env
, tlb
, &raddr
, address
,
1147 env
->spr
[SPR_40x_PID
], 0, i
) < 0)
1149 zsel
= (tlb
->attr
>> 4) & 0xF;
1150 zpr
= (env
->spr
[SPR_40x_ZPR
] >> (30 - (2 * zsel
))) & 0x3;
1151 LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1152 __func__
, i
, zsel
, zpr
, rw
, tlb
->attr
);
1153 /* Check execute enable bit */
1160 /* All accesses granted */
1161 ctx
->prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1166 /* Raise Zone protection fault. */
1167 env
->spr
[SPR_40x_ESR
] = 1 << 22;
1175 /* Check from TLB entry */
1176 /* XXX: there is a problem here or in the TLB fill code... */
1177 ctx
->prot
= tlb
->prot
;
1178 ctx
->prot
|= PAGE_EXEC
;
1179 ret
= check_prot(ctx
->prot
, rw
, access_type
);
1181 env
->spr
[SPR_40x_ESR
] = 0;
1186 LOG_SWTLB("%s: access granted " TARGET_FMT_lx
" => " TARGET_FMT_plx
1187 " %d %d\n", __func__
, address
, ctx
->raddr
, ctx
->prot
,
1192 LOG_SWTLB("%s: access refused " TARGET_FMT_lx
" => " TARGET_FMT_plx
1193 " %d %d\n", __func__
, address
, raddr
, ctx
->prot
, ret
);
1198 void store_40x_sler (CPUPPCState
*env
, uint32_t val
)
1200 /* XXX: TO BE FIXED */
1201 if (val
!= 0x00000000) {
1202 cpu_abort(env
, "Little-endian regions are not supported by now\n");
1204 env
->spr
[SPR_405_SLER
] = val
;
1207 static int mmubooke_get_physical_address (CPUState
*env
, mmu_ctx_t
*ctx
,
1208 target_ulong address
, int rw
,
1212 target_phys_addr_t raddr
;
1216 raddr
= (target_phys_addr_t
)-1ULL;
1217 for (i
= 0; i
< env
->nb_tlb
; i
++) {
1218 tlb
= &env
->tlb
[i
].tlbe
;
1219 if (ppcemb_tlb_check(env
, tlb
, &raddr
, address
,
1220 env
->spr
[SPR_BOOKE_PID
], 1, i
) < 0)
1223 prot
= tlb
->prot
& 0xF;
1225 prot
= (tlb
->prot
>> 4) & 0xF;
1226 /* Check the address space */
1227 if (access_type
== ACCESS_CODE
) {
1228 if (msr_ir
!= (tlb
->attr
& 1))
1231 if (prot
& PAGE_EXEC
) {
1237 if (msr_dr
!= (tlb
->attr
& 1))
1240 if ((!rw
&& prot
& PAGE_READ
) || (rw
&& (prot
& PAGE_WRITE
))) {
1253 static inline int check_physical(CPUState
*env
, mmu_ctx_t
*ctx
,
1254 target_ulong eaddr
, int rw
)
1259 ctx
->prot
= PAGE_READ
| PAGE_EXEC
;
1261 switch (env
->mmu_model
) {
1262 case POWERPC_MMU_32B
:
1263 case POWERPC_MMU_601
:
1264 case POWERPC_MMU_SOFT_6xx
:
1265 case POWERPC_MMU_SOFT_74xx
:
1266 case POWERPC_MMU_SOFT_4xx
:
1267 case POWERPC_MMU_REAL
:
1268 case POWERPC_MMU_BOOKE
:
1269 ctx
->prot
|= PAGE_WRITE
;
1271 #if defined(TARGET_PPC64)
1272 case POWERPC_MMU_620
:
1273 case POWERPC_MMU_64B
:
1274 /* Real address are 60 bits long */
1275 ctx
->raddr
&= 0x0FFFFFFFFFFFFFFFULL
;
1276 ctx
->prot
|= PAGE_WRITE
;
1279 case POWERPC_MMU_SOFT_4xx_Z
:
1280 if (unlikely(msr_pe
!= 0)) {
1281 /* 403 family add some particular protections,
1282 * using PBL/PBU registers for accesses with no translation.
1285 /* Check PLB validity */
1286 (env
->pb
[0] < env
->pb
[1] &&
1287 /* and address in plb area */
1288 eaddr
>= env
->pb
[0] && eaddr
< env
->pb
[1]) ||
1289 (env
->pb
[2] < env
->pb
[3] &&
1290 eaddr
>= env
->pb
[2] && eaddr
< env
->pb
[3]) ? 1 : 0;
1291 if (in_plb
^ msr_px
) {
1292 /* Access in protected area */
1294 /* Access is not allowed */
1298 /* Read-write access is allowed */
1299 ctx
->prot
|= PAGE_WRITE
;
1303 case POWERPC_MMU_MPC8xx
:
1305 cpu_abort(env
, "MPC8xx MMU model is not implemented\n");
1307 case POWERPC_MMU_BOOKE_FSL
:
1309 cpu_abort(env
, "BookE FSL MMU model not implemented\n");
1312 cpu_abort(env
, "Unknown or invalid MMU model\n");
1319 int get_physical_address (CPUState
*env
, mmu_ctx_t
*ctx
, target_ulong eaddr
,
1320 int rw
, int access_type
)
1325 qemu_log("%s\n", __func__
);
1327 if ((access_type
== ACCESS_CODE
&& msr_ir
== 0) ||
1328 (access_type
!= ACCESS_CODE
&& msr_dr
== 0)) {
1329 /* No address translation */
1330 ret
= check_physical(env
, ctx
, eaddr
, rw
);
1333 switch (env
->mmu_model
) {
1334 case POWERPC_MMU_32B
:
1335 case POWERPC_MMU_601
:
1336 case POWERPC_MMU_SOFT_6xx
:
1337 case POWERPC_MMU_SOFT_74xx
:
1338 /* Try to find a BAT */
1339 if (env
->nb_BATs
!= 0)
1340 ret
= get_bat(env
, ctx
, eaddr
, rw
, access_type
);
1341 #if defined(TARGET_PPC64)
1342 case POWERPC_MMU_620
:
1343 case POWERPC_MMU_64B
:
1346 /* We didn't match any BAT entry or don't have BATs */
1347 ret
= get_segment(env
, ctx
, eaddr
, rw
, access_type
);
1350 case POWERPC_MMU_SOFT_4xx
:
1351 case POWERPC_MMU_SOFT_4xx_Z
:
1352 ret
= mmu40x_get_physical_address(env
, ctx
, eaddr
,
1355 case POWERPC_MMU_BOOKE
:
1356 ret
= mmubooke_get_physical_address(env
, ctx
, eaddr
,
1359 case POWERPC_MMU_MPC8xx
:
1361 cpu_abort(env
, "MPC8xx MMU model is not implemented\n");
1363 case POWERPC_MMU_BOOKE_FSL
:
1365 cpu_abort(env
, "BookE FSL MMU model not implemented\n");
1367 case POWERPC_MMU_REAL
:
1368 cpu_abort(env
, "PowerPC in real mode do not do any translation\n");
1371 cpu_abort(env
, "Unknown or invalid MMU model\n");
1376 qemu_log("%s address " TARGET_FMT_lx
" => %d " TARGET_FMT_plx
"\n",
1377 __func__
, eaddr
, ret
, ctx
->raddr
);
1383 target_phys_addr_t
cpu_get_phys_page_debug (CPUState
*env
, target_ulong addr
)
1387 if (unlikely(get_physical_address(env
, &ctx
, addr
, 0, ACCESS_INT
) != 0))
1390 return ctx
.raddr
& TARGET_PAGE_MASK
;
1393 /* Perform address translation */
1394 int cpu_ppc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
1395 int mmu_idx
, int is_softmmu
)
1404 access_type
= ACCESS_CODE
;
1407 access_type
= env
->access_type
;
1409 ret
= get_physical_address(env
, &ctx
, address
, rw
, access_type
);
1411 tlb_set_page(env
, address
& TARGET_PAGE_MASK
,
1412 ctx
.raddr
& TARGET_PAGE_MASK
, ctx
.prot
,
1413 mmu_idx
, TARGET_PAGE_SIZE
);
1415 } else if (ret
< 0) {
1417 if (access_type
== ACCESS_CODE
) {
1420 /* No matches in page tables or TLB */
1421 switch (env
->mmu_model
) {
1422 case POWERPC_MMU_SOFT_6xx
:
1423 env
->exception_index
= POWERPC_EXCP_IFTLB
;
1424 env
->error_code
= 1 << 18;
1425 env
->spr
[SPR_IMISS
] = address
;
1426 env
->spr
[SPR_ICMP
] = 0x80000000 | ctx
.ptem
;
1428 case POWERPC_MMU_SOFT_74xx
:
1429 env
->exception_index
= POWERPC_EXCP_IFTLB
;
1431 case POWERPC_MMU_SOFT_4xx
:
1432 case POWERPC_MMU_SOFT_4xx_Z
:
1433 env
->exception_index
= POWERPC_EXCP_ITLB
;
1434 env
->error_code
= 0;
1435 env
->spr
[SPR_40x_DEAR
] = address
;
1436 env
->spr
[SPR_40x_ESR
] = 0x00000000;
1438 case POWERPC_MMU_32B
:
1439 case POWERPC_MMU_601
:
1440 #if defined(TARGET_PPC64)
1441 case POWERPC_MMU_620
:
1442 case POWERPC_MMU_64B
:
1444 env
->exception_index
= POWERPC_EXCP_ISI
;
1445 env
->error_code
= 0x40000000;
1447 case POWERPC_MMU_BOOKE
:
1449 cpu_abort(env
, "BookE MMU model is not implemented\n");
1451 case POWERPC_MMU_BOOKE_FSL
:
1453 cpu_abort(env
, "BookE FSL MMU model is not implemented\n");
1455 case POWERPC_MMU_MPC8xx
:
1457 cpu_abort(env
, "MPC8xx MMU model is not implemented\n");
1459 case POWERPC_MMU_REAL
:
1460 cpu_abort(env
, "PowerPC in real mode should never raise "
1461 "any MMU exceptions\n");
1464 cpu_abort(env
, "Unknown or invalid MMU model\n");
1469 /* Access rights violation */
1470 env
->exception_index
= POWERPC_EXCP_ISI
;
1471 env
->error_code
= 0x08000000;
1474 /* No execute protection violation */
1475 env
->exception_index
= POWERPC_EXCP_ISI
;
1476 env
->error_code
= 0x10000000;
1479 /* Direct store exception */
1480 /* No code fetch is allowed in direct-store areas */
1481 env
->exception_index
= POWERPC_EXCP_ISI
;
1482 env
->error_code
= 0x10000000;
1484 #if defined(TARGET_PPC64)
1486 /* No match in segment table */
1487 if (env
->mmu_model
== POWERPC_MMU_620
) {
1488 env
->exception_index
= POWERPC_EXCP_ISI
;
1489 /* XXX: this might be incorrect */
1490 env
->error_code
= 0x40000000;
1492 env
->exception_index
= POWERPC_EXCP_ISEG
;
1493 env
->error_code
= 0;
1501 /* No matches in page tables or TLB */
1502 switch (env
->mmu_model
) {
1503 case POWERPC_MMU_SOFT_6xx
:
1505 env
->exception_index
= POWERPC_EXCP_DSTLB
;
1506 env
->error_code
= 1 << 16;
1508 env
->exception_index
= POWERPC_EXCP_DLTLB
;
1509 env
->error_code
= 0;
1511 env
->spr
[SPR_DMISS
] = address
;
1512 env
->spr
[SPR_DCMP
] = 0x80000000 | ctx
.ptem
;
1514 env
->error_code
|= ctx
.key
<< 19;
1515 env
->spr
[SPR_HASH1
] = ctx
.pg_addr
[0];
1516 env
->spr
[SPR_HASH2
] = ctx
.pg_addr
[1];
1518 case POWERPC_MMU_SOFT_74xx
:
1520 env
->exception_index
= POWERPC_EXCP_DSTLB
;
1522 env
->exception_index
= POWERPC_EXCP_DLTLB
;
1525 /* Implement LRU algorithm */
1526 env
->error_code
= ctx
.key
<< 19;
1527 env
->spr
[SPR_TLBMISS
] = (address
& ~((target_ulong
)0x3)) |
1528 ((env
->last_way
+ 1) & (env
->nb_ways
- 1));
1529 env
->spr
[SPR_PTEHI
] = 0x80000000 | ctx
.ptem
;
1531 case POWERPC_MMU_SOFT_4xx
:
1532 case POWERPC_MMU_SOFT_4xx_Z
:
1533 env
->exception_index
= POWERPC_EXCP_DTLB
;
1534 env
->error_code
= 0;
1535 env
->spr
[SPR_40x_DEAR
] = address
;
1537 env
->spr
[SPR_40x_ESR
] = 0x00800000;
1539 env
->spr
[SPR_40x_ESR
] = 0x00000000;
1541 case POWERPC_MMU_32B
:
1542 case POWERPC_MMU_601
:
1543 #if defined(TARGET_PPC64)
1544 case POWERPC_MMU_620
:
1545 case POWERPC_MMU_64B
:
1547 env
->exception_index
= POWERPC_EXCP_DSI
;
1548 env
->error_code
= 0;
1549 env
->spr
[SPR_DAR
] = address
;
1551 env
->spr
[SPR_DSISR
] = 0x42000000;
1553 env
->spr
[SPR_DSISR
] = 0x40000000;
1555 case POWERPC_MMU_MPC8xx
:
1557 cpu_abort(env
, "MPC8xx MMU model is not implemented\n");
1559 case POWERPC_MMU_BOOKE
:
1561 cpu_abort(env
, "BookE MMU model is not implemented\n");
1563 case POWERPC_MMU_BOOKE_FSL
:
1565 cpu_abort(env
, "BookE FSL MMU model is not implemented\n");
1567 case POWERPC_MMU_REAL
:
1568 cpu_abort(env
, "PowerPC in real mode should never raise "
1569 "any MMU exceptions\n");
1572 cpu_abort(env
, "Unknown or invalid MMU model\n");
1577 /* Access rights violation */
1578 env
->exception_index
= POWERPC_EXCP_DSI
;
1579 env
->error_code
= 0;
1580 if (env
->mmu_model
== POWERPC_MMU_SOFT_4xx
1581 || env
->mmu_model
== POWERPC_MMU_SOFT_4xx_Z
) {
1582 env
->spr
[SPR_40x_DEAR
] = address
;
1584 env
->spr
[SPR_40x_ESR
] |= 0x00800000;
1587 env
->spr
[SPR_DAR
] = address
;
1589 env
->spr
[SPR_DSISR
] = 0x0A000000;
1591 env
->spr
[SPR_DSISR
] = 0x08000000;
1596 /* Direct store exception */
1597 switch (access_type
) {
1599 /* Floating point load/store */
1600 env
->exception_index
= POWERPC_EXCP_ALIGN
;
1601 env
->error_code
= POWERPC_EXCP_ALIGN_FP
;
1602 env
->spr
[SPR_DAR
] = address
;
1605 /* lwarx, ldarx or stwcx. */
1606 env
->exception_index
= POWERPC_EXCP_DSI
;
1607 env
->error_code
= 0;
1608 env
->spr
[SPR_DAR
] = address
;
1610 env
->spr
[SPR_DSISR
] = 0x06000000;
1612 env
->spr
[SPR_DSISR
] = 0x04000000;
1615 /* eciwx or ecowx */
1616 env
->exception_index
= POWERPC_EXCP_DSI
;
1617 env
->error_code
= 0;
1618 env
->spr
[SPR_DAR
] = address
;
1620 env
->spr
[SPR_DSISR
] = 0x06100000;
1622 env
->spr
[SPR_DSISR
] = 0x04100000;
1625 printf("DSI: invalid exception (%d)\n", ret
);
1626 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
1628 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
;
1629 env
->spr
[SPR_DAR
] = address
;
1633 #if defined(TARGET_PPC64)
1635 /* No match in segment table */
1636 if (env
->mmu_model
== POWERPC_MMU_620
) {
1637 env
->exception_index
= POWERPC_EXCP_DSI
;
1638 env
->error_code
= 0;
1639 env
->spr
[SPR_DAR
] = address
;
1640 /* XXX: this might be incorrect */
1642 env
->spr
[SPR_DSISR
] = 0x42000000;
1644 env
->spr
[SPR_DSISR
] = 0x40000000;
1646 env
->exception_index
= POWERPC_EXCP_DSEG
;
1647 env
->error_code
= 0;
1648 env
->spr
[SPR_DAR
] = address
;
1655 printf("%s: set exception to %d %02x\n", __func__
,
1656 env
->exception
, env
->error_code
);
1664 /*****************************************************************************/
1665 /* BATs management */
1666 #if !defined(FLUSH_ALL_TLBS)
1667 static inline void do_invalidate_BAT(CPUPPCState
*env
, target_ulong BATu
,
1670 target_ulong base
, end
, page
;
1672 base
= BATu
& ~0x0001FFFF;
1673 end
= base
+ mask
+ 0x00020000;
1674 LOG_BATS("Flush BAT from " TARGET_FMT_lx
" to " TARGET_FMT_lx
" ("
1675 TARGET_FMT_lx
")\n", base
, end
, mask
);
1676 for (page
= base
; page
!= end
; page
+= TARGET_PAGE_SIZE
)
1677 tlb_flush_page(env
, page
);
1678 LOG_BATS("Flush done\n");
1682 static inline void dump_store_bat(CPUPPCState
*env
, char ID
, int ul
, int nr
,
1685 LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx
" (" TARGET_FMT_lx
")\n", ID
,
1686 nr
, ul
== 0 ? 'u' : 'l', value
, env
->nip
);
1689 void ppc_store_ibatu (CPUPPCState
*env
, int nr
, target_ulong value
)
1693 dump_store_bat(env
, 'I', 0, nr
, value
);
1694 if (env
->IBAT
[0][nr
] != value
) {
1695 mask
= (value
<< 15) & 0x0FFE0000UL
;
1696 #if !defined(FLUSH_ALL_TLBS)
1697 do_invalidate_BAT(env
, env
->IBAT
[0][nr
], mask
);
1699 /* When storing valid upper BAT, mask BEPI and BRPN
1700 * and invalidate all TLBs covered by this BAT
1702 mask
= (value
<< 15) & 0x0FFE0000UL
;
1703 env
->IBAT
[0][nr
] = (value
& 0x00001FFFUL
) |
1704 (value
& ~0x0001FFFFUL
& ~mask
);
1705 env
->IBAT
[1][nr
] = (env
->IBAT
[1][nr
] & 0x0000007B) |
1706 (env
->IBAT
[1][nr
] & ~0x0001FFFF & ~mask
);
1707 #if !defined(FLUSH_ALL_TLBS)
1708 do_invalidate_BAT(env
, env
->IBAT
[0][nr
], mask
);
1715 void ppc_store_ibatl (CPUPPCState
*env
, int nr
, target_ulong value
)
1717 dump_store_bat(env
, 'I', 1, nr
, value
);
1718 env
->IBAT
[1][nr
] = value
;
1721 void ppc_store_dbatu (CPUPPCState
*env
, int nr
, target_ulong value
)
1725 dump_store_bat(env
, 'D', 0, nr
, value
);
1726 if (env
->DBAT
[0][nr
] != value
) {
1727 /* When storing valid upper BAT, mask BEPI and BRPN
1728 * and invalidate all TLBs covered by this BAT
1730 mask
= (value
<< 15) & 0x0FFE0000UL
;
1731 #if !defined(FLUSH_ALL_TLBS)
1732 do_invalidate_BAT(env
, env
->DBAT
[0][nr
], mask
);
1734 mask
= (value
<< 15) & 0x0FFE0000UL
;
1735 env
->DBAT
[0][nr
] = (value
& 0x00001FFFUL
) |
1736 (value
& ~0x0001FFFFUL
& ~mask
);
1737 env
->DBAT
[1][nr
] = (env
->DBAT
[1][nr
] & 0x0000007B) |
1738 (env
->DBAT
[1][nr
] & ~0x0001FFFF & ~mask
);
1739 #if !defined(FLUSH_ALL_TLBS)
1740 do_invalidate_BAT(env
, env
->DBAT
[0][nr
], mask
);
1747 void ppc_store_dbatl (CPUPPCState
*env
, int nr
, target_ulong value
)
1749 dump_store_bat(env
, 'D', 1, nr
, value
);
1750 env
->DBAT
[1][nr
] = value
;
1753 void ppc_store_ibatu_601 (CPUPPCState
*env
, int nr
, target_ulong value
)
1756 #if defined(FLUSH_ALL_TLBS)
1760 dump_store_bat(env
, 'I', 0, nr
, value
);
1761 if (env
->IBAT
[0][nr
] != value
) {
1762 #if defined(FLUSH_ALL_TLBS)
1765 mask
= (env
->IBAT
[1][nr
] << 17) & 0x0FFE0000UL
;
1766 if (env
->IBAT
[1][nr
] & 0x40) {
1767 /* Invalidate BAT only if it is valid */
1768 #if !defined(FLUSH_ALL_TLBS)
1769 do_invalidate_BAT(env
, env
->IBAT
[0][nr
], mask
);
1774 /* When storing valid upper BAT, mask BEPI and BRPN
1775 * and invalidate all TLBs covered by this BAT
1777 env
->IBAT
[0][nr
] = (value
& 0x00001FFFUL
) |
1778 (value
& ~0x0001FFFFUL
& ~mask
);
1779 env
->DBAT
[0][nr
] = env
->IBAT
[0][nr
];
1780 if (env
->IBAT
[1][nr
] & 0x40) {
1781 #if !defined(FLUSH_ALL_TLBS)
1782 do_invalidate_BAT(env
, env
->IBAT
[0][nr
], mask
);
1787 #if defined(FLUSH_ALL_TLBS)
1794 void ppc_store_ibatl_601 (CPUPPCState
*env
, int nr
, target_ulong value
)
1797 #if defined(FLUSH_ALL_TLBS)
1801 dump_store_bat(env
, 'I', 1, nr
, value
);
1802 if (env
->IBAT
[1][nr
] != value
) {
1803 #if defined(FLUSH_ALL_TLBS)
1806 if (env
->IBAT
[1][nr
] & 0x40) {
1807 #if !defined(FLUSH_ALL_TLBS)
1808 mask
= (env
->IBAT
[1][nr
] << 17) & 0x0FFE0000UL
;
1809 do_invalidate_BAT(env
, env
->IBAT
[0][nr
], mask
);
1815 #if !defined(FLUSH_ALL_TLBS)
1816 mask
= (value
<< 17) & 0x0FFE0000UL
;
1817 do_invalidate_BAT(env
, env
->IBAT
[0][nr
], mask
);
1822 env
->IBAT
[1][nr
] = value
;
1823 env
->DBAT
[1][nr
] = value
;
1824 #if defined(FLUSH_ALL_TLBS)
1831 /*****************************************************************************/
1832 /* TLB management */
1833 void ppc_tlb_invalidate_all (CPUPPCState
*env
)
1835 switch (env
->mmu_model
) {
1836 case POWERPC_MMU_SOFT_6xx
:
1837 case POWERPC_MMU_SOFT_74xx
:
1838 ppc6xx_tlb_invalidate_all(env
);
1840 case POWERPC_MMU_SOFT_4xx
:
1841 case POWERPC_MMU_SOFT_4xx_Z
:
1842 ppc4xx_tlb_invalidate_all(env
);
1844 case POWERPC_MMU_REAL
:
1845 cpu_abort(env
, "No TLB for PowerPC 4xx in real mode\n");
1847 case POWERPC_MMU_MPC8xx
:
1849 cpu_abort(env
, "MPC8xx MMU model is not implemented\n");
1851 case POWERPC_MMU_BOOKE
:
1853 cpu_abort(env
, "BookE MMU model is not implemented\n");
1855 case POWERPC_MMU_BOOKE_FSL
:
1858 cpu_abort(env
, "BookE MMU model is not implemented\n");
1860 case POWERPC_MMU_32B
:
1861 case POWERPC_MMU_601
:
1862 #if defined(TARGET_PPC64)
1863 case POWERPC_MMU_620
:
1864 case POWERPC_MMU_64B
:
1865 #endif /* defined(TARGET_PPC64) */
1870 cpu_abort(env
, "Unknown MMU model\n");
1875 void ppc_tlb_invalidate_one (CPUPPCState
*env
, target_ulong addr
)
1877 #if !defined(FLUSH_ALL_TLBS)
1878 addr
&= TARGET_PAGE_MASK
;
1879 switch (env
->mmu_model
) {
1880 case POWERPC_MMU_SOFT_6xx
:
1881 case POWERPC_MMU_SOFT_74xx
:
1882 ppc6xx_tlb_invalidate_virt(env
, addr
, 0);
1883 if (env
->id_tlbs
== 1)
1884 ppc6xx_tlb_invalidate_virt(env
, addr
, 1);
1886 case POWERPC_MMU_SOFT_4xx
:
1887 case POWERPC_MMU_SOFT_4xx_Z
:
1888 ppc4xx_tlb_invalidate_virt(env
, addr
, env
->spr
[SPR_40x_PID
]);
1890 case POWERPC_MMU_REAL
:
1891 cpu_abort(env
, "No TLB for PowerPC 4xx in real mode\n");
1893 case POWERPC_MMU_MPC8xx
:
1895 cpu_abort(env
, "MPC8xx MMU model is not implemented\n");
1897 case POWERPC_MMU_BOOKE
:
1899 cpu_abort(env
, "BookE MMU model is not implemented\n");
1901 case POWERPC_MMU_BOOKE_FSL
:
1903 cpu_abort(env
, "BookE FSL MMU model is not implemented\n");
1905 case POWERPC_MMU_32B
:
1906 case POWERPC_MMU_601
:
1907 /* tlbie invalidate TLBs for all segments */
1908 addr
&= ~((target_ulong
)-1ULL << 28);
1909 /* XXX: this case should be optimized,
1910 * giving a mask to tlb_flush_page
1912 tlb_flush_page(env
, addr
| (0x0 << 28));
1913 tlb_flush_page(env
, addr
| (0x1 << 28));
1914 tlb_flush_page(env
, addr
| (0x2 << 28));
1915 tlb_flush_page(env
, addr
| (0x3 << 28));
1916 tlb_flush_page(env
, addr
| (0x4 << 28));
1917 tlb_flush_page(env
, addr
| (0x5 << 28));
1918 tlb_flush_page(env
, addr
| (0x6 << 28));
1919 tlb_flush_page(env
, addr
| (0x7 << 28));
1920 tlb_flush_page(env
, addr
| (0x8 << 28));
1921 tlb_flush_page(env
, addr
| (0x9 << 28));
1922 tlb_flush_page(env
, addr
| (0xA << 28));
1923 tlb_flush_page(env
, addr
| (0xB << 28));
1924 tlb_flush_page(env
, addr
| (0xC << 28));
1925 tlb_flush_page(env
, addr
| (0xD << 28));
1926 tlb_flush_page(env
, addr
| (0xE << 28));
1927 tlb_flush_page(env
, addr
| (0xF << 28));
1929 #if defined(TARGET_PPC64)
1930 case POWERPC_MMU_620
:
1931 case POWERPC_MMU_64B
:
1932 /* tlbie invalidate TLBs for all segments */
1933 /* XXX: given the fact that there are too many segments to invalidate,
1934 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
1935 * we just invalidate all TLBs
1939 #endif /* defined(TARGET_PPC64) */
1942 cpu_abort(env
, "Unknown MMU model\n");
1946 ppc_tlb_invalidate_all(env
);
1950 /*****************************************************************************/
1951 /* Special registers manipulation */
1952 #if defined(TARGET_PPC64)
1953 void ppc_store_asr (CPUPPCState
*env
, target_ulong value
)
1955 if (env
->asr
!= value
) {
1962 void ppc_store_sdr1 (CPUPPCState
*env
, target_ulong value
)
1964 LOG_MMU("%s: " TARGET_FMT_lx
"\n", __func__
, value
);
1965 if (env
->sdr1
!= value
) {
1966 /* XXX: for PowerPC 64, should check that the HTABSIZE value
1974 #if defined(TARGET_PPC64)
1975 target_ulong
ppc_load_sr (CPUPPCState
*env
, int slb_nr
)
1982 void ppc_store_sr (CPUPPCState
*env
, int srnum
, target_ulong value
)
1984 LOG_MMU("%s: reg=%d " TARGET_FMT_lx
" " TARGET_FMT_lx
"\n", __func__
,
1985 srnum
, value
, env
->sr
[srnum
]);
1986 #if defined(TARGET_PPC64)
1987 if (env
->mmu_model
& POWERPC_MMU_64
) {
1988 uint64_t rb
= 0, rs
= 0;
1991 rb
|= ((uint32_t)srnum
& 0xf) << 28;
1992 /* Set the valid bit */
1995 rb
|= (uint32_t)srnum
;
1998 rs
|= (value
& 0xfffffff) << 12;
2000 rs
|= ((value
>> 27) & 0xf) << 9;
2002 ppc_store_slb(env
, rb
, rs
);
2005 if (env
->sr
[srnum
] != value
) {
2006 env
->sr
[srnum
] = value
;
2007 /* Invalidating 256MB of virtual memory in 4kB pages is way longer than
2008 flusing the whole TLB. */
2009 #if !defined(FLUSH_ALL_TLBS) && 0
2011 target_ulong page
, end
;
2012 /* Invalidate 256 MB of virtual memory */
2013 page
= (16 << 20) * srnum
;
2014 end
= page
+ (16 << 20);
2015 for (; page
!= end
; page
+= TARGET_PAGE_SIZE
)
2016 tlb_flush_page(env
, page
);
2023 #endif /* !defined (CONFIG_USER_ONLY) */
2025 /* GDBstub can read and write MSR... */
2026 void ppc_store_msr (CPUPPCState
*env
, target_ulong value
)
2028 hreg_store_msr(env
, value
, 0);
2031 /*****************************************************************************/
2032 /* Exception processing */
2033 #if defined (CONFIG_USER_ONLY)
2034 void do_interrupt (CPUState
*env
)
2036 env
->exception_index
= POWERPC_EXCP_NONE
;
2037 env
->error_code
= 0;
2040 void ppc_hw_interrupt (CPUState
*env
)
2042 env
->exception_index
= POWERPC_EXCP_NONE
;
2043 env
->error_code
= 0;
2045 #else /* defined (CONFIG_USER_ONLY) */
2046 static inline void dump_syscall(CPUState
*env
)
2048 qemu_log_mask(CPU_LOG_INT
, "syscall r0=%016" PRIx64
" r3=%016" PRIx64
2049 " r4=%016" PRIx64
" r5=%016" PRIx64
" r6=%016" PRIx64
2050 " nip=" TARGET_FMT_lx
"\n",
2051 ppc_dump_gpr(env
, 0), ppc_dump_gpr(env
, 3),
2052 ppc_dump_gpr(env
, 4), ppc_dump_gpr(env
, 5),
2053 ppc_dump_gpr(env
, 6), env
->nip
);
2056 /* Note that this function should be greatly optimized
2057 * when called with a constant excp, from ppc_hw_interrupt
2059 static inline void powerpc_excp(CPUState
*env
, int excp_model
, int excp
)
2061 target_ulong msr
, new_msr
, vector
;
2062 int srr0
, srr1
, asrr0
, asrr1
;
2063 int lpes0
, lpes1
, lev
;
2066 /* XXX: find a suitable condition to enable the hypervisor mode */
2067 lpes0
= (env
->spr
[SPR_LPCR
] >> 1) & 1;
2068 lpes1
= (env
->spr
[SPR_LPCR
] >> 2) & 1;
2070 /* Those values ensure we won't enter the hypervisor mode */
2075 qemu_log_mask(CPU_LOG_INT
, "Raise exception at " TARGET_FMT_lx
2076 " => %08x (%02x)\n", env
->nip
, excp
, env
->error_code
);
2083 msr
&= ~((target_ulong
)0x783F0000);
2085 case POWERPC_EXCP_NONE
:
2086 /* Should never happen */
2088 case POWERPC_EXCP_CRITICAL
: /* Critical input */
2089 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2090 switch (excp_model
) {
2091 case POWERPC_EXCP_40x
:
2092 srr0
= SPR_40x_SRR2
;
2093 srr1
= SPR_40x_SRR3
;
2095 case POWERPC_EXCP_BOOKE
:
2096 srr0
= SPR_BOOKE_CSRR0
;
2097 srr1
= SPR_BOOKE_CSRR1
;
2099 case POWERPC_EXCP_G2
:
2105 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
2107 /* Machine check exception is not enabled.
2108 * Enter checkstop state.
2110 if (qemu_log_enabled()) {
2111 qemu_log("Machine check while not allowed. "
2112 "Entering checkstop state\n");
2114 fprintf(stderr
, "Machine check while not allowed. "
2115 "Entering checkstop state\n");
2118 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
2120 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2121 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
2123 /* XXX: find a suitable condition to enable the hypervisor mode */
2124 new_msr
|= (target_ulong
)MSR_HVB
;
2126 /* XXX: should also have something loaded in DAR / DSISR */
2127 switch (excp_model
) {
2128 case POWERPC_EXCP_40x
:
2129 srr0
= SPR_40x_SRR2
;
2130 srr1
= SPR_40x_SRR3
;
2132 case POWERPC_EXCP_BOOKE
:
2133 srr0
= SPR_BOOKE_MCSRR0
;
2134 srr1
= SPR_BOOKE_MCSRR1
;
2135 asrr0
= SPR_BOOKE_CSRR0
;
2136 asrr1
= SPR_BOOKE_CSRR1
;
2142 case POWERPC_EXCP_DSI
: /* Data storage exception */
2143 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx
" DAR=" TARGET_FMT_lx
2144 "\n", env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
2145 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2147 new_msr
|= (target_ulong
)MSR_HVB
;
2149 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
2150 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx
", nip=" TARGET_FMT_lx
2151 "\n", msr
, env
->nip
);
2152 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2154 new_msr
|= (target_ulong
)MSR_HVB
;
2155 msr
|= env
->error_code
;
2157 case POWERPC_EXCP_EXTERNAL
: /* External input */
2158 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2160 new_msr
|= (target_ulong
)MSR_HVB
;
2162 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
2163 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2165 new_msr
|= (target_ulong
)MSR_HVB
;
2166 /* XXX: this is false */
2167 /* Get rS/rD and rA from faulting opcode */
2168 env
->spr
[SPR_DSISR
] |= (ldl_code((env
->nip
- 4)) & 0x03FF0000) >> 16;
2170 case POWERPC_EXCP_PROGRAM
: /* Program exception */
2171 switch (env
->error_code
& ~0xF) {
2172 case POWERPC_EXCP_FP
:
2173 if ((msr_fe0
== 0 && msr_fe1
== 0) || msr_fp
== 0) {
2174 LOG_EXCP("Ignore floating point exception\n");
2175 env
->exception_index
= POWERPC_EXCP_NONE
;
2176 env
->error_code
= 0;
2179 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2181 new_msr
|= (target_ulong
)MSR_HVB
;
2183 if (msr_fe0
== msr_fe1
)
2187 case POWERPC_EXCP_INVAL
:
2188 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx
"\n", env
->nip
);
2189 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2191 new_msr
|= (target_ulong
)MSR_HVB
;
2194 case POWERPC_EXCP_PRIV
:
2195 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2197 new_msr
|= (target_ulong
)MSR_HVB
;
2200 case POWERPC_EXCP_TRAP
:
2201 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2203 new_msr
|= (target_ulong
)MSR_HVB
;
2207 /* Should never occur */
2208 cpu_abort(env
, "Invalid program exception %d. Aborting\n",
2213 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
2214 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2216 new_msr
|= (target_ulong
)MSR_HVB
;
2218 case POWERPC_EXCP_SYSCALL
: /* System call exception */
2219 /* NOTE: this is a temporary hack to support graphics OSI
2220 calls from the MOL driver */
2221 /* XXX: To be removed */
2222 if (env
->gpr
[3] == 0x113724fa && env
->gpr
[4] == 0x77810f9b &&
2224 if (env
->osi_call(env
) != 0) {
2225 env
->exception_index
= POWERPC_EXCP_NONE
;
2226 env
->error_code
= 0;
2231 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2232 lev
= env
->error_code
;
2233 if (lev
== 1 || (lpes0
== 0 && lpes1
== 0))
2234 new_msr
|= (target_ulong
)MSR_HVB
;
2236 case POWERPC_EXCP_APU
: /* Auxiliary processor unavailable */
2237 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2239 case POWERPC_EXCP_DECR
: /* Decrementer exception */
2240 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2242 new_msr
|= (target_ulong
)MSR_HVB
;
2244 case POWERPC_EXCP_FIT
: /* Fixed-interval timer interrupt */
2246 LOG_EXCP("FIT exception\n");
2247 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2249 case POWERPC_EXCP_WDT
: /* Watchdog timer interrupt */
2250 LOG_EXCP("WDT exception\n");
2251 switch (excp_model
) {
2252 case POWERPC_EXCP_BOOKE
:
2253 srr0
= SPR_BOOKE_CSRR0
;
2254 srr1
= SPR_BOOKE_CSRR1
;
2259 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2261 case POWERPC_EXCP_DTLB
: /* Data TLB error */
2262 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2264 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
2265 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2267 case POWERPC_EXCP_DEBUG
: /* Debug interrupt */
2268 switch (excp_model
) {
2269 case POWERPC_EXCP_BOOKE
:
2270 srr0
= SPR_BOOKE_DSRR0
;
2271 srr1
= SPR_BOOKE_DSRR1
;
2272 asrr0
= SPR_BOOKE_CSRR0
;
2273 asrr1
= SPR_BOOKE_CSRR1
;
2279 cpu_abort(env
, "Debug exception is not implemented yet !\n");
2281 case POWERPC_EXCP_SPEU
: /* SPE/embedded floating-point unavailable */
2282 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2284 case POWERPC_EXCP_EFPDI
: /* Embedded floating-point data interrupt */
2286 cpu_abort(env
, "Embedded floating point data exception "
2287 "is not implemented yet !\n");
2289 case POWERPC_EXCP_EFPRI
: /* Embedded floating-point round interrupt */
2291 cpu_abort(env
, "Embedded floating point round exception "
2292 "is not implemented yet !\n");
2294 case POWERPC_EXCP_EPERFM
: /* Embedded performance monitor interrupt */
2295 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2298 "Performance counter exception is not implemented yet !\n");
2300 case POWERPC_EXCP_DOORI
: /* Embedded doorbell interrupt */
2303 "Embedded doorbell interrupt is not implemented yet !\n");
2305 case POWERPC_EXCP_DOORCI
: /* Embedded doorbell critical interrupt */
2306 switch (excp_model
) {
2307 case POWERPC_EXCP_BOOKE
:
2308 srr0
= SPR_BOOKE_CSRR0
;
2309 srr1
= SPR_BOOKE_CSRR1
;
2315 cpu_abort(env
, "Embedded doorbell critical interrupt "
2316 "is not implemented yet !\n");
2318 case POWERPC_EXCP_RESET
: /* System reset exception */
2319 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2321 /* XXX: find a suitable condition to enable the hypervisor mode */
2322 new_msr
|= (target_ulong
)MSR_HVB
;
2325 case POWERPC_EXCP_DSEG
: /* Data segment exception */
2326 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2328 new_msr
|= (target_ulong
)MSR_HVB
;
2330 case POWERPC_EXCP_ISEG
: /* Instruction segment exception */
2331 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2333 new_msr
|= (target_ulong
)MSR_HVB
;
2335 case POWERPC_EXCP_HDECR
: /* Hypervisor decrementer exception */
2338 new_msr
|= (target_ulong
)MSR_HVB
;
2340 case POWERPC_EXCP_TRACE
: /* Trace exception */
2341 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2343 new_msr
|= (target_ulong
)MSR_HVB
;
2345 case POWERPC_EXCP_HDSI
: /* Hypervisor data storage exception */
2348 new_msr
|= (target_ulong
)MSR_HVB
;
2350 case POWERPC_EXCP_HISI
: /* Hypervisor instruction storage exception */
2353 new_msr
|= (target_ulong
)MSR_HVB
;
2355 case POWERPC_EXCP_HDSEG
: /* Hypervisor data segment exception */
2358 new_msr
|= (target_ulong
)MSR_HVB
;
2360 case POWERPC_EXCP_HISEG
: /* Hypervisor instruction segment exception */
2363 new_msr
|= (target_ulong
)MSR_HVB
;
2365 case POWERPC_EXCP_VPU
: /* Vector unavailable exception */
2366 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2368 new_msr
|= (target_ulong
)MSR_HVB
;
2370 case POWERPC_EXCP_PIT
: /* Programmable interval timer interrupt */
2371 LOG_EXCP("PIT exception\n");
2372 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2374 case POWERPC_EXCP_IO
: /* IO error exception */
2376 cpu_abort(env
, "601 IO error exception is not implemented yet !\n");
2378 case POWERPC_EXCP_RUNM
: /* Run mode exception */
2380 cpu_abort(env
, "601 run mode exception is not implemented yet !\n");
2382 case POWERPC_EXCP_EMUL
: /* Emulation trap exception */
2384 cpu_abort(env
, "602 emulation trap exception "
2385 "is not implemented yet !\n");
2387 case POWERPC_EXCP_IFTLB
: /* Instruction fetch TLB error */
2388 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2389 if (lpes1
== 0) /* XXX: check this */
2390 new_msr
|= (target_ulong
)MSR_HVB
;
2391 switch (excp_model
) {
2392 case POWERPC_EXCP_602
:
2393 case POWERPC_EXCP_603
:
2394 case POWERPC_EXCP_603E
:
2395 case POWERPC_EXCP_G2
:
2397 case POWERPC_EXCP_7x5
:
2399 case POWERPC_EXCP_74xx
:
2402 cpu_abort(env
, "Invalid instruction TLB miss exception\n");
2406 case POWERPC_EXCP_DLTLB
: /* Data load TLB miss */
2407 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2408 if (lpes1
== 0) /* XXX: check this */
2409 new_msr
|= (target_ulong
)MSR_HVB
;
2410 switch (excp_model
) {
2411 case POWERPC_EXCP_602
:
2412 case POWERPC_EXCP_603
:
2413 case POWERPC_EXCP_603E
:
2414 case POWERPC_EXCP_G2
:
2416 case POWERPC_EXCP_7x5
:
2418 case POWERPC_EXCP_74xx
:
2421 cpu_abort(env
, "Invalid data load TLB miss exception\n");
2425 case POWERPC_EXCP_DSTLB
: /* Data store TLB miss */
2426 new_msr
&= ~((target_ulong
)1 << MSR_RI
); /* XXX: check this */
2427 if (lpes1
== 0) /* XXX: check this */
2428 new_msr
|= (target_ulong
)MSR_HVB
;
2429 switch (excp_model
) {
2430 case POWERPC_EXCP_602
:
2431 case POWERPC_EXCP_603
:
2432 case POWERPC_EXCP_603E
:
2433 case POWERPC_EXCP_G2
:
2435 /* Swap temporary saved registers with GPRs */
2436 if (!(new_msr
& ((target_ulong
)1 << MSR_TGPR
))) {
2437 new_msr
|= (target_ulong
)1 << MSR_TGPR
;
2438 hreg_swap_gpr_tgpr(env
);
2441 case POWERPC_EXCP_7x5
:
2443 #if defined (DEBUG_SOFTWARE_TLB)
2444 if (qemu_log_enabled()) {
2446 target_ulong
*miss
, *cmp
;
2448 if (excp
== POWERPC_EXCP_IFTLB
) {
2451 miss
= &env
->spr
[SPR_IMISS
];
2452 cmp
= &env
->spr
[SPR_ICMP
];
2454 if (excp
== POWERPC_EXCP_DLTLB
)
2459 miss
= &env
->spr
[SPR_DMISS
];
2460 cmp
= &env
->spr
[SPR_DCMP
];
2462 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx
" %cC "
2463 TARGET_FMT_lx
" H1 " TARGET_FMT_lx
" H2 "
2464 TARGET_FMT_lx
" %08x\n", es
, en
, *miss
, en
, *cmp
,
2465 env
->spr
[SPR_HASH1
], env
->spr
[SPR_HASH2
],
2469 msr
|= env
->crf
[0] << 28;
2470 msr
|= env
->error_code
; /* key, D/I, S/L bits */
2471 /* Set way using a LRU mechanism */
2472 msr
|= ((env
->last_way
+ 1) & (env
->nb_ways
- 1)) << 17;
2474 case POWERPC_EXCP_74xx
:
2476 #if defined (DEBUG_SOFTWARE_TLB)
2477 if (qemu_log_enabled()) {
2479 target_ulong
*miss
, *cmp
;
2481 if (excp
== POWERPC_EXCP_IFTLB
) {
2484 miss
= &env
->spr
[SPR_TLBMISS
];
2485 cmp
= &env
->spr
[SPR_PTEHI
];
2487 if (excp
== POWERPC_EXCP_DLTLB
)
2492 miss
= &env
->spr
[SPR_TLBMISS
];
2493 cmp
= &env
->spr
[SPR_PTEHI
];
2495 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx
" %cC "
2496 TARGET_FMT_lx
" %08x\n", es
, en
, *miss
, en
, *cmp
,
2500 msr
|= env
->error_code
; /* key bit */
2503 cpu_abort(env
, "Invalid data store TLB miss exception\n");
2507 case POWERPC_EXCP_FPA
: /* Floating-point assist exception */
2509 cpu_abort(env
, "Floating point assist exception "
2510 "is not implemented yet !\n");
2512 case POWERPC_EXCP_DABR
: /* Data address breakpoint */
2514 cpu_abort(env
, "DABR exception is not implemented yet !\n");
2516 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
2518 cpu_abort(env
, "IABR exception is not implemented yet !\n");
2520 case POWERPC_EXCP_SMI
: /* System management interrupt */
2522 cpu_abort(env
, "SMI exception is not implemented yet !\n");
2524 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
2526 cpu_abort(env
, "Thermal management exception "
2527 "is not implemented yet !\n");
2529 case POWERPC_EXCP_PERFM
: /* Embedded performance monitor interrupt */
2530 new_msr
&= ~((target_ulong
)1 << MSR_RI
);
2532 new_msr
|= (target_ulong
)MSR_HVB
;
2535 "Performance counter exception is not implemented yet !\n");
2537 case POWERPC_EXCP_VPUA
: /* Vector assist exception */
2539 cpu_abort(env
, "VPU assist exception is not implemented yet !\n");
2541 case POWERPC_EXCP_SOFTP
: /* Soft patch exception */
2544 "970 soft-patch exception is not implemented yet !\n");
2546 case POWERPC_EXCP_MAINT
: /* Maintenance exception */
2549 "970 maintenance exception is not implemented yet !\n");
2551 case POWERPC_EXCP_MEXTBR
: /* Maskable external breakpoint */
2553 cpu_abort(env
, "Maskable external exception "
2554 "is not implemented yet !\n");
2556 case POWERPC_EXCP_NMEXTBR
: /* Non maskable external breakpoint */
2558 cpu_abort(env
, "Non maskable external exception "
2559 "is not implemented yet !\n");
2563 cpu_abort(env
, "Invalid PowerPC exception %d. Aborting\n", excp
);
2566 /* save current instruction location */
2567 env
->spr
[srr0
] = env
->nip
- 4;
2570 /* save next instruction location */
2571 env
->spr
[srr0
] = env
->nip
;
2575 env
->spr
[srr1
] = msr
;
2576 /* If any alternate SRR register are defined, duplicate saved values */
2578 env
->spr
[asrr0
] = env
->spr
[srr0
];
2580 env
->spr
[asrr1
] = env
->spr
[srr1
];
2581 /* If we disactivated any translation, flush TLBs */
2582 if (new_msr
& ((1 << MSR_IR
) | (1 << MSR_DR
)))
2584 /* reload MSR with correct bits */
2585 new_msr
&= ~((target_ulong
)1 << MSR_EE
);
2586 new_msr
&= ~((target_ulong
)1 << MSR_PR
);
2587 new_msr
&= ~((target_ulong
)1 << MSR_FP
);
2588 new_msr
&= ~((target_ulong
)1 << MSR_FE0
);
2589 new_msr
&= ~((target_ulong
)1 << MSR_SE
);
2590 new_msr
&= ~((target_ulong
)1 << MSR_BE
);
2591 new_msr
&= ~((target_ulong
)1 << MSR_FE1
);
2592 new_msr
&= ~((target_ulong
)1 << MSR_IR
);
2593 new_msr
&= ~((target_ulong
)1 << MSR_DR
);
2594 #if 0 /* Fix this: not on all targets */
2595 new_msr
&= ~((target_ulong
)1 << MSR_PMM
);
2597 new_msr
&= ~((target_ulong
)1 << MSR_LE
);
2599 new_msr
|= (target_ulong
)1 << MSR_LE
;
2601 new_msr
&= ~((target_ulong
)1 << MSR_LE
);
2602 /* Jump to handler */
2603 vector
= env
->excp_vectors
[excp
];
2604 if (vector
== (target_ulong
)-1ULL) {
2605 cpu_abort(env
, "Raised an exception without defined vector %d\n",
2608 vector
|= env
->excp_prefix
;
2609 #if defined(TARGET_PPC64)
2610 if (excp_model
== POWERPC_EXCP_BOOKE
) {
2612 new_msr
&= ~((target_ulong
)1 << MSR_CM
);
2613 vector
= (uint32_t)vector
;
2615 new_msr
|= (target_ulong
)1 << MSR_CM
;
2618 if (!msr_isf
&& !(env
->mmu_model
& POWERPC_MMU_64
)) {
2619 new_msr
&= ~((target_ulong
)1 << MSR_SF
);
2620 vector
= (uint32_t)vector
;
2622 new_msr
|= (target_ulong
)1 << MSR_SF
;
2626 /* XXX: we don't use hreg_store_msr here as already have treated
2627 * any special case that could occur. Just store MSR and update hflags
2629 env
->msr
= new_msr
& env
->msr_mask
;
2630 hreg_compute_hflags(env
);
2632 /* Reset exception state */
2633 env
->exception_index
= POWERPC_EXCP_NONE
;
2634 env
->error_code
= 0;
2637 void do_interrupt (CPUState
*env
)
2639 powerpc_excp(env
, env
->excp_model
, env
->exception_index
);
2642 void ppc_hw_interrupt (CPUPPCState
*env
)
2647 qemu_log_mask(CPU_LOG_INT
, "%s: %p pending %08x req %08x me %d ee %d\n",
2648 __func__
, env
, env
->pending_interrupts
,
2649 env
->interrupt_request
, (int)msr_me
, (int)msr_ee
);
2651 /* External reset */
2652 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_RESET
)) {
2653 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_RESET
);
2654 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_RESET
);
2657 /* Machine check exception */
2658 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_MCK
)) {
2659 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_MCK
);
2660 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_MCHECK
);
2664 /* External debug exception */
2665 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_DEBUG
)) {
2666 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_DEBUG
);
2667 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_DEBUG
);
2672 /* XXX: find a suitable condition to enable the hypervisor mode */
2673 hdice
= env
->spr
[SPR_LPCR
] & 1;
2677 if ((msr_ee
!= 0 || msr_hv
== 0 || msr_pr
!= 0) && hdice
!= 0) {
2678 /* Hypervisor decrementer exception */
2679 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_HDECR
)) {
2680 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_HDECR
);
2681 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_HDECR
);
2686 /* External critical interrupt */
2687 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_CEXT
)) {
2688 /* Taking a critical external interrupt does not clear the external
2689 * critical interrupt status
2692 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_CEXT
);
2694 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_CRITICAL
);
2699 /* Watchdog timer on embedded PowerPC */
2700 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_WDT
)) {
2701 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_WDT
);
2702 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_WDT
);
2705 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_CDOORBELL
)) {
2706 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_CDOORBELL
);
2707 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_DOORCI
);
2710 /* Fixed interval timer on embedded PowerPC */
2711 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_FIT
)) {
2712 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_FIT
);
2713 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_FIT
);
2716 /* Programmable interval timer on embedded PowerPC */
2717 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_PIT
)) {
2718 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_PIT
);
2719 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_PIT
);
2722 /* Decrementer exception */
2723 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_DECR
)) {
2724 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_DECR
);
2725 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_DECR
);
2728 /* External interrupt */
2729 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_EXT
)) {
2730 /* Taking an external interrupt does not clear the external
2734 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_EXT
);
2736 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_EXTERNAL
);
2739 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_DOORBELL
)) {
2740 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_DOORBELL
);
2741 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_DOORI
);
2744 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_PERFM
)) {
2745 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_PERFM
);
2746 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_PERFM
);
2749 /* Thermal interrupt */
2750 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_THERM
)) {
2751 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_THERM
);
2752 powerpc_excp(env
, env
->excp_model
, POWERPC_EXCP_THERM
);
2757 #endif /* !CONFIG_USER_ONLY */
2759 void cpu_dump_rfi (target_ulong RA
, target_ulong msr
)
2761 qemu_log("Return from exception at " TARGET_FMT_lx
" with flags "
2762 TARGET_FMT_lx
"\n", RA
, msr
);
2765 void cpu_reset(CPUPPCState
*env
)
2769 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
2770 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
2771 log_cpu_state(env
, 0);
2774 msr
= (target_ulong
)0;
2776 /* XXX: find a suitable condition to enable the hypervisor mode */
2777 msr
|= (target_ulong
)MSR_HVB
;
2779 msr
|= (target_ulong
)0 << MSR_AP
; /* TO BE CHECKED */
2780 msr
|= (target_ulong
)0 << MSR_SA
; /* TO BE CHECKED */
2781 msr
|= (target_ulong
)1 << MSR_EP
;
2782 #if defined (DO_SINGLE_STEP) && 0
2783 /* Single step trace mode */
2784 msr
|= (target_ulong
)1 << MSR_SE
;
2785 msr
|= (target_ulong
)1 << MSR_BE
;
2787 #if defined(CONFIG_USER_ONLY)
2788 msr
|= (target_ulong
)1 << MSR_FP
; /* Allow floating point usage */
2789 msr
|= (target_ulong
)1 << MSR_VR
; /* Allow altivec usage */
2790 msr
|= (target_ulong
)1 << MSR_SPE
; /* Allow SPE usage */
2791 msr
|= (target_ulong
)1 << MSR_PR
;
2793 env
->excp_prefix
= env
->hreset_excp_prefix
;
2794 env
->nip
= env
->hreset_vector
| env
->excp_prefix
;
2795 if (env
->mmu_model
!= POWERPC_MMU_REAL
)
2796 ppc_tlb_invalidate_all(env
);
2798 env
->msr
= msr
& env
->msr_mask
;
2799 #if defined(TARGET_PPC64)
2800 if (env
->mmu_model
& POWERPC_MMU_64
)
2801 env
->msr
|= (1ULL << MSR_SF
);
2803 hreg_compute_hflags(env
);
2804 env
->reserve_addr
= (target_ulong
)-1ULL;
2805 /* Be sure no exception or interrupt is pending */
2806 env
->pending_interrupts
= 0;
2807 env
->exception_index
= POWERPC_EXCP_NONE
;
2808 env
->error_code
= 0;
2809 /* Flush all TLBs */
2813 CPUPPCState
*cpu_ppc_init (const char *cpu_model
)
2816 const ppc_def_t
*def
;
2818 def
= cpu_ppc_find_by_name(cpu_model
);
2822 env
= qemu_mallocz(sizeof(CPUPPCState
));
2824 ppc_translate_init();
2825 env
->cpu_model_str
= cpu_model
;
2826 cpu_ppc_register_internal(env
, def
);
2828 qemu_init_vcpu(env
);
2833 void cpu_ppc_close (CPUPPCState
*env
)
2835 /* Should also remove all opcode tables... */