tcg/sparc/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef NDEBUG
  26 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  27     "%g0",
  28     "%g1",
  29     "%g2",
  30     "%g3",
  31     "%g4",
  32     "%g5",
  33     "%g6",
  34     "%g7",
  35     "%o0",
  36     "%o1",
  37     "%o2",
  38     "%o3",
  39     "%o4",
  40     "%o5",
  41     "%o6",
  42     "%o7",
  43     "%l0",
  44     "%l1",
  45     "%l2",
  46     "%l3",
  47     "%l4",
  48     "%l5",
  49     "%l6",
  50     "%l7",
  51     "%i0",
  52     "%i1",
  53     "%i2",
  54     "%i3",
  55     "%i4",
  56     "%i5",
  57     "%i6",
  58     "%i7",
  59 };
  60 #endif
  61
  62 static const int tcg_target_reg_alloc_order[] = {
  63     TCG_REG_L0,
  64     TCG_REG_L1,
  65     TCG_REG_L2,
  66     TCG_REG_L3,
  67     TCG_REG_L4,
  68     TCG_REG_L5,
  69     TCG_REG_L6,
  70     TCG_REG_L7,
  71     TCG_REG_I0,
  72     TCG_REG_I1,
  73     TCG_REG_I2,
  74     TCG_REG_I3,
  75     TCG_REG_I4,
  76 };
  77
  78 static const int tcg_target_call_iarg_regs[6] = {
  79     TCG_REG_O0,
  80     TCG_REG_O1,
  81     TCG_REG_O2,
  82     TCG_REG_O3,
  83     TCG_REG_O4,
  84     TCG_REG_O5,
  85 };
  86
  87 static const int tcg_target_call_oarg_regs[2] = {
  88     TCG_REG_O0,
  89     TCG_REG_O1,
  90 };
  91
  92 static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
  93 {
  94     return (val << ((sizeof(tcg_target_long) * 8 - bits))
  95             >> (sizeof(tcg_target_long) * 8 - bits)) == val;
  96 }
  97
  98 static inline int check_fit_i32(uint32_t val, unsigned int bits)
  99 {
 100     return ((val << (32 - bits)) >> (32 - bits)) == val;
 101 }
 102
 103 static void patch_reloc(uint8_t *code_ptr, int type,
 104                         tcg_target_long value, tcg_target_long addend)
 105 {
 106     value += addend;
 107     switch (type) {
 108     case R_SPARC_32:
 109         if (value != (uint32_t)value)
 110             tcg_abort();
 111         *(uint32_t *)code_ptr = value;
 112         break;
 113     case R_SPARC_WDISP22:
 114         value -= (long)code_ptr;
 115         value >>= 2;
 116         if (!check_fit_tl(value, 22))
 117             tcg_abort();
 118         *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
 119         break;
 120     case R_SPARC_WDISP19:
 121         value -= (long)code_ptr;
 122         value >>= 2;
 123         if (!check_fit_tl(value, 19))
 124             tcg_abort();
 125         *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
 126         break;
 127     default:
 128         tcg_abort();
 129     }
 130 }
 131
 132 /* maximum number of register used for input function arguments */
 133 static inline int tcg_target_get_call_iarg_regs_count(int flags)
 134 {
 135     return 6;
 136 }
 137
 138 /* parse target specific constraints */
 139 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 140 {
 141     const char *ct_str;
 142
 143     ct_str = *pct_str;
 144     switch (ct_str[0]) {
 145     case 'r':
 146         ct->ct |= TCG_CT_REG;
 147         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 148         break;
 149     case 'L': /* qemu_ld/st constraint */
 150         ct->ct |= TCG_CT_REG;
 151         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
 152         // Helper args
 153         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
 154         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
 155         tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
 156         break;
 157     case 'I':
 158         ct->ct |= TCG_CT_CONST_S11;
 159         break;
 160     case 'J':
 161         ct->ct |= TCG_CT_CONST_S13;
 162         break;
 163     default:
 164         return -1;
 165     }
 166     ct_str++;
 167     *pct_str = ct_str;
 168     return 0;
 169 }
 170
 171 /* test if a constant matches the constraint */
 172 static inline int tcg_target_const_match(tcg_target_long val,
 173                                          const TCGArgConstraint *arg_ct)
 174 {
 175     int ct;
 176
 177     ct = arg_ct->ct;
 178     if (ct & TCG_CT_CONST)
 179         return 1;
 180     else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
 181         return 1;
 182     else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
 183         return 1;
 184     else
 185         return 0;
 186 }
 187
 188 #define INSN_OP(x)  ((x) << 30)
 189 #define INSN_OP2(x) ((x) << 22)
 190 #define INSN_OP3(x) ((x) << 19)
 191 #define INSN_OPF(x) ((x) << 5)
 192 #define INSN_RD(x)  ((x) << 25)
 193 #define INSN_RS1(x) ((x) << 14)
 194 #define INSN_RS2(x) (x)
 195 #define INSN_ASI(x) ((x) << 5)
 196
 197 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
 198 #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
 199 #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
 200
 201 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
 202 #define COND_N     0x0
 203 #define COND_E     0x1
 204 #define COND_LE    0x2
 205 #define COND_L     0x3
 206 #define COND_LEU   0x4
 207 #define COND_CS    0x5
 208 #define COND_NEG   0x6
 209 #define COND_VS    0x7
 210 #define COND_A     0x8
 211 #define COND_NE    0x9
 212 #define COND_G     0xa
 213 #define COND_GE    0xb
 214 #define COND_GU    0xc
 215 #define COND_CC    0xd
 216 #define COND_POS   0xe
 217 #define COND_VC    0xf
 218 #define BA         (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
 219
 220 #define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
 221 #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
 222 #define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
 223 #define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
 224 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
 225 #define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
 226 #define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
 227 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
 228 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
 229 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
 230 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
 231 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
 232 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
 233 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
 234 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
 235 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
 236
 237 #define SHIFT_SLL  (INSN_OP(2) | INSN_OP3(0x25))
 238 #define SHIFT_SRL  (INSN_OP(2) | INSN_OP3(0x26))
 239 #define SHIFT_SRA  (INSN_OP(2) | INSN_OP3(0x27))
 240
 241 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
 242 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
 243 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
 244
 245 #define RDY        (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
 246 #define WRY        (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
 247 #define JMPL       (INSN_OP(2) | INSN_OP3(0x38))
 248 #define SAVE       (INSN_OP(2) | INSN_OP3(0x3c))
 249 #define RESTORE    (INSN_OP(2) | INSN_OP3(0x3d))
 250 #define SETHI      (INSN_OP(0) | INSN_OP2(0x4))
 251 #define CALL       INSN_OP(1)
 252 #define LDUB       (INSN_OP(3) | INSN_OP3(0x01))
 253 #define LDSB       (INSN_OP(3) | INSN_OP3(0x09))
 254 #define LDUH       (INSN_OP(3) | INSN_OP3(0x02))
 255 #define LDSH       (INSN_OP(3) | INSN_OP3(0x0a))
 256 #define LDUW       (INSN_OP(3) | INSN_OP3(0x00))
 257 #define LDSW       (INSN_OP(3) | INSN_OP3(0x08))
 258 #define LDX        (INSN_OP(3) | INSN_OP3(0x0b))
 259 #define STB        (INSN_OP(3) | INSN_OP3(0x05))
 260 #define STH        (INSN_OP(3) | INSN_OP3(0x06))
 261 #define STW        (INSN_OP(3) | INSN_OP3(0x04))
 262 #define STX        (INSN_OP(3) | INSN_OP3(0x0e))
 263 #define LDUBA      (INSN_OP(3) | INSN_OP3(0x11))
 264 #define LDSBA      (INSN_OP(3) | INSN_OP3(0x19))
 265 #define LDUHA      (INSN_OP(3) | INSN_OP3(0x12))
 266 #define LDSHA      (INSN_OP(3) | INSN_OP3(0x1a))
 267 #define LDUWA      (INSN_OP(3) | INSN_OP3(0x10))
 268 #define LDSWA      (INSN_OP(3) | INSN_OP3(0x18))
 269 #define LDXA       (INSN_OP(3) | INSN_OP3(0x1b))
 270 #define STBA       (INSN_OP(3) | INSN_OP3(0x15))
 271 #define STHA       (INSN_OP(3) | INSN_OP3(0x16))
 272 #define STWA       (INSN_OP(3) | INSN_OP3(0x14))
 273 #define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
 274
 275 #ifndef ASI_PRIMARY_LITTLE
 276 #define ASI_PRIMARY_LITTLE 0x88
 277 #endif
 278
 279 static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
 280                                  int op)
 281 {
 282     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 283               INSN_RS2(rs2));
 284 }
 285
 286 static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1,
 287                                   uint32_t offset, int op)
 288 {
 289     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
 290               INSN_IMM13(offset));
 291 }
 292
 293 static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
 294                            int val2, int val2const, int op)
 295 {
 296     tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
 297               | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
 298 }
 299
 300 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
 301 {
 302     tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
 303 }
 304
 305 static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
 306 {
 307     tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
 308 }
 309
 310 static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
 311 {
 312     tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
 313 }
 314
 315 static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
 316 {
 317     if (check_fit_tl(arg, 13))
 318         tcg_out_movi_imm13(s, ret, arg);
 319     else {
 320         tcg_out_sethi(s, ret, arg);
 321         if (arg & 0x3ff)
 322             tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
 323     }
 324 }
 325
 326 static inline void tcg_out_movi(TCGContext *s, TCGType type,
 327                                 int ret, tcg_target_long arg)
 328 {
 329     /* All 32-bit constants, as well as 64-bit constants with
 330        no high bits set go through movi_imm32.  */
 331     if (TCG_TARGET_REG_BITS == 32
 332         || type == TCG_TYPE_I32
 333         || (arg & ~(tcg_target_long)0xffffffff) == 0) {
 334         tcg_out_movi_imm32(s, ret, arg);
 335     } else if (check_fit_tl(arg, 13)) {
 336         /* A 13-bit constant sign-extended to 64-bits.  */
 337         tcg_out_movi_imm13(s, ret, arg);
 338     } else if (check_fit_tl(arg, 32)) {
 339         /* A 32-bit constant sign-extended to 64-bits.  */
 340         tcg_out_sethi(s, ret, ~arg);
 341         tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
 342     } else {
 343         tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
 344         tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
 345         tcg_out_movi_imm32(s, ret, arg);
 346         tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
 347     }
 348 }
 349
 350 static inline void tcg_out_ld_raw(TCGContext *s, int ret,
 351                                   tcg_target_long arg)
 352 {
 353     tcg_out_sethi(s, ret, arg);
 354     tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
 355               INSN_IMM13(arg & 0x3ff));
 356 }
 357
 358 static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
 359                                   tcg_target_long arg)
 360 {
 361     if (!check_fit_tl(arg, 10))
 362         tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
 363     if (TCG_TARGET_REG_BITS == 64) {
 364         tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
 365                   INSN_IMM13(arg & 0x3ff));
 366     } else {
 367         tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
 368                   INSN_IMM13(arg & 0x3ff));
 369     }
 370 }
 371
 372 static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
 373 {
 374     if (check_fit_tl(offset, 13))
 375         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
 376                   INSN_IMM13(offset));
 377     else {
 378         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
 379         tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
 380                   INSN_RS2(addr));
 381     }
 382 }
 383
 384 static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
 385                                     int offset, int op, int asi)
 386 {
 387     tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
 388     tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
 389               INSN_ASI(asi) | INSN_RS2(addr));
 390 }
 391
 392 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
 393                               int arg1, tcg_target_long arg2)
 394 {
 395     if (type == TCG_TYPE_I32)
 396         tcg_out_ldst(s, ret, arg1, arg2, LDUW);
 397     else
 398         tcg_out_ldst(s, ret, arg1, arg2, LDX);
 399 }
 400
 401 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
 402                               int arg1, tcg_target_long arg2)
 403 {
 404     if (type == TCG_TYPE_I32)
 405         tcg_out_ldst(s, arg, arg1, arg2, STW);
 406     else
 407         tcg_out_ldst(s, arg, arg1, arg2, STX);
 408 }
 409
 410 static inline void tcg_out_sety(TCGContext *s, int rs)
 411 {
 412     tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
 413 }
 414
 415 static inline void tcg_out_rdy(TCGContext *s, int rd)
 416 {
 417     tcg_out32(s, RDY | INSN_RD(rd));
 418 }
 419
 420 static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
 421 {
 422     if (val != 0) {
 423         if (check_fit_tl(val, 13))
 424             tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
 425         else {
 426             tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
 427             tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
 428         }
 429     }
 430 }
 431
 432 static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
 433 {
 434     if (val != 0) {
 435         if (check_fit_tl(val, 13))
 436             tcg_out_arithi(s, reg, reg, val, ARITH_AND);
 437         else {
 438             tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
 439             tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
 440         }
 441     }
 442 }
 443
 444 static void tcg_out_div32(TCGContext *s, int rd, int rs1,
 445                           int val2, int val2const, int uns)
 446 {
 447     /* Load Y with the sign/zero extension of RS1 to 64-bits.  */
 448     if (uns) {
 449         tcg_out_sety(s, TCG_REG_G0);
 450     } else {
 451         tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
 452         tcg_out_sety(s, TCG_REG_I5);
 453     }
 454
 455     tcg_out_arithc(s, rd, rs1, val2, val2const,
 456                    uns ? ARITH_UDIV : ARITH_SDIV);
 457 }
 458
 459 static inline void tcg_out_nop(TCGContext *s)
 460 {
 461     tcg_out_sethi(s, TCG_REG_G0, 0);
 462 }
 463
 464 static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
 465 {
 466     int32_t val;
 467     TCGLabel *l = &s->labels[label_index];
 468
 469     if (l->has_value) {
 470         val = l->u.value - (tcg_target_long)s->code_ptr;
 471         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
 472                       | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
 473     } else {
 474         tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
 475         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
 476     }
 477 }
 478
 479 #if TCG_TARGET_REG_BITS == 64
 480 static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
 481 {
 482     int32_t val;
 483     TCGLabel *l = &s->labels[label_index];
 484
 485     if (l->has_value) {
 486         val = l->u.value - (tcg_target_long)s->code_ptr;
 487         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
 488                       (0x5 << 19) |
 489                       INSN_OFF19(l->u.value - (unsigned long)s->code_ptr)));
 490     } else {
 491         tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
 492         tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
 493                       (0x5 << 19) | 0));
 494     }
 495 }
 496 #endif
 497
 498 static const uint8_t tcg_cond_to_bcond[10] = {
 499     [TCG_COND_EQ] = COND_E,
 500     [TCG_COND_NE] = COND_NE,
 501     [TCG_COND_LT] = COND_L,
 502     [TCG_COND_GE] = COND_GE,
 503     [TCG_COND_LE] = COND_LE,
 504     [TCG_COND_GT] = COND_G,
 505     [TCG_COND_LTU] = COND_CS,
 506     [TCG_COND_GEU] = COND_CC,
 507     [TCG_COND_LEU] = COND_LEU,
 508     [TCG_COND_GTU] = COND_GU,
 509 };
 510
 511 static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
 512 {
 513     tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
 514 }
 515
 516 static void tcg_out_brcond_i32(TCGContext *s, int cond,
 517                                TCGArg arg1, TCGArg arg2, int const_arg2,
 518                                int label_index)
 519 {
 520     tcg_out_cmp(s, arg1, arg2, const_arg2);
 521     tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
 522     tcg_out_nop(s);
 523 }
 524
 525 #if TCG_TARGET_REG_BITS == 64
 526 static void tcg_out_brcond_i64(TCGContext *s, int cond,
 527                                TCGArg arg1, TCGArg arg2, int const_arg2,
 528                                int label_index)
 529 {
 530     tcg_out_cmp(s, arg1, arg2, const_arg2);
 531     tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
 532     tcg_out_nop(s);
 533 }
 534 #else
 535 static void tcg_out_brcond2_i32(TCGContext *s, int cond,
 536                                 TCGArg al, TCGArg ah,
 537                                 TCGArg bl, int blconst,
 538                                 TCGArg bh, int bhconst, int label_dest)
 539 {
 540     int cc, label_next = gen_new_label();
 541
 542     tcg_out_cmp(s, ah, bh, bhconst);
 543
 544     /* Note that we fill one of the delay slots with the second compare.  */
 545     switch (cond) {
 546     case TCG_COND_EQ:
 547         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
 548         tcg_out_branch_i32(s, cc, label_next);
 549         tcg_out_cmp(s, al, bl, blconst);
 550         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
 551         tcg_out_branch_i32(s, cc, label_dest);
 552         break;
 553
 554     case TCG_COND_NE:
 555         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
 556         tcg_out_branch_i32(s, cc, label_dest);
 557         tcg_out_cmp(s, al, bl, blconst);
 558         tcg_out_branch_i32(s, cc, label_dest);
 559         break;
 560
 561     default:
 562         /* ??? One could fairly easily special-case 64-bit unsigned
 563            compares against 32-bit zero-extended constants.  For instance,
 564            we know that (unsigned)AH < 0 is false and need not emit it.
 565            Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
 566            second branch will never be taken.  */
 567         cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
 568         tcg_out_branch_i32(s, cc, label_dest);
 569         tcg_out_nop(s);
 570         cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
 571         tcg_out_branch_i32(s, cc, label_next);
 572         tcg_out_cmp(s, al, bl, blconst);
 573         cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
 574         tcg_out_branch_i32(s, cc, label_dest);
 575         break;
 576     }
 577     tcg_out_nop(s);
 578
 579     tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
 580 }
 581 #endif
 582
 583 /* Generate global QEMU prologue and epilogue code */
 584 void tcg_target_qemu_prologue(TCGContext *s)
 585 {
 586     tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
 587               INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
 588     tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
 589               INSN_RS2(TCG_REG_G0));
 590     tcg_out_nop(s);
 591 }
 592
 593 #if defined(CONFIG_SOFTMMU)
 594
 595 #include "../../softmmu_defs.h"
 596
 597 static const void * const qemu_ld_helpers[4] = {
 598     __ldb_mmu,
 599     __ldw_mmu,
 600     __ldl_mmu,
 601     __ldq_mmu,
 602 };
 603
 604 static const void * const qemu_st_helpers[4] = {
 605     __stb_mmu,
 606     __stw_mmu,
 607     __stl_mmu,
 608     __stq_mmu,
 609 };
 610 #endif
 611
 612 #if TARGET_LONG_BITS == 32
 613 #define TARGET_LD_OP LDUW
 614 #else
 615 #define TARGET_LD_OP LDX
 616 #endif
 617
 618 #if TARGET_PHYS_ADDR_BITS == 32
 619 #define TARGET_ADDEND_LD_OP LDUW
 620 #else
 621 #define TARGET_ADDEND_LD_OP LDX
 622 #endif
 623
 624 #ifdef __arch64__
 625 #define HOST_LD_OP LDX
 626 #define HOST_ST_OP STX
 627 #define HOST_SLL_OP SHIFT_SLLX
 628 #define HOST_SRA_OP SHIFT_SRAX
 629 #else
 630 #define HOST_LD_OP LDUW
 631 #define HOST_ST_OP STW
 632 #define HOST_SLL_OP SHIFT_SLL
 633 #define HOST_SRA_OP SHIFT_SRA
 634 #endif
 635
 636 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
 637                             int opc)
 638 {
 639     int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
 640 #if defined(CONFIG_SOFTMMU)
 641     uint32_t *label1_ptr, *label2_ptr;
 642 #endif
 643
 644     data_reg = *args++;
 645     addr_reg = *args++;
 646     mem_index = *args;
 647     s_bits = opc & 3;
 648
 649     arg0 = TCG_REG_O0;
 650     arg1 = TCG_REG_O1;
 651     arg2 = TCG_REG_O2;
 652
 653 #if defined(CONFIG_SOFTMMU)
 654     /* srl addr_reg, x, arg1 */
 655     tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
 656                    SHIFT_SRL);
 657     /* and addr_reg, x, arg0 */
 658     tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 659                    ARITH_AND);
 660
 661     /* and arg1, x, arg1 */
 662     tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
 663
 664     /* add arg1, x, arg1 */
 665     tcg_out_addi(s, arg1, offsetof(CPUState,
 666                                    tlb_table[mem_index][0].addr_read));
 667
 668     /* add env, arg1, arg1 */
 669     tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
 670
 671     /* ld [arg1], arg2 */
 672     tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
 673               INSN_RS2(TCG_REG_G0));
 674
 675     /* subcc arg0, arg2, %g0 */
 676     tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
 677
 678     /* will become:
 679        be label1
 680         or
 681        be,pt %xcc label1 */
 682     label1_ptr = (uint32_t *)s->code_ptr;
 683     tcg_out32(s, 0);
 684
 685     /* mov (delay slot) */
 686     tcg_out_mov(s, arg0, addr_reg);
 687
 688     /* mov */
 689     tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
 690
 691     /* XXX: move that code at the end of the TB */
 692     /* qemu_ld_helper[s_bits](arg0, arg1) */
 693     tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
 694                            - (tcg_target_ulong)s->code_ptr) >> 2)
 695                          & 0x3fffffff));
 696     /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
 697        global registers */
 698     // delay slot
 699     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 700                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
 701                  sizeof(long), HOST_ST_OP);
 702     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 703                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
 704                  sizeof(long), HOST_LD_OP);
 705
 706     /* data_reg = sign_extend(arg0) */
 707     switch(opc) {
 708     case 0 | 4:
 709         /* sll arg0, 24/56, data_reg */
 710         tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
 711                        HOST_SLL_OP);
 712         /* sra data_reg, 24/56, data_reg */
 713         tcg_out_arithi(s, data_reg, data_reg,
 714                        (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
 715         break;
 716     case 1 | 4:
 717         /* sll arg0, 16/48, data_reg */
 718         tcg_out_arithi(s, data_reg, arg0,
 719                        (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
 720         /* sra data_reg, 16/48, data_reg */
 721         tcg_out_arithi(s, data_reg, data_reg,
 722                        (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
 723         break;
 724     case 2 | 4:
 725         /* sll arg0, 32, data_reg */
 726         tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
 727         /* sra data_reg, 32, data_reg */
 728         tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
 729         break;
 730     case 0:
 731     case 1:
 732     case 2:
 733     case 3:
 734     default:
 735         /* mov */
 736         tcg_out_mov(s, data_reg, arg0);
 737         break;
 738     }
 739
 740     /* will become:
 741        ba label2 */
 742     label2_ptr = (uint32_t *)s->code_ptr;
 743     tcg_out32(s, 0);
 744
 745     /* nop (delay slot */
 746     tcg_out_nop(s);
 747
 748     /* label1: */
 749 #if TARGET_LONG_BITS == 32
 750     /* be label1 */
 751     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
 752                    INSN_OFF22((unsigned long)s->code_ptr -
 753                               (unsigned long)label1_ptr));
 754 #else
 755     /* be,pt %xcc label1 */
 756     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
 757                    (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
 758                               (unsigned long)label1_ptr));
 759 #endif
 760
 761     /* ld [arg1 + x], arg1 */
 762     tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
 763                  offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
 764
 765 #if TARGET_LONG_BITS == 32
 766     /* and addr_reg, x, arg0 */
 767     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
 768     tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
 769     /* add arg0, arg1, arg0 */
 770     tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
 771 #else
 772     /* add addr_reg, arg1, arg0 */
 773     tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
 774 #endif
 775
 776 #else
 777     arg0 = addr_reg;
 778 #endif
 779
 780     switch(opc) {
 781     case 0:
 782         /* ldub [arg0], data_reg */
 783         tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
 784         break;
 785     case 0 | 4:
 786         /* ldsb [arg0], data_reg */
 787         tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
 788         break;
 789     case 1:
 790 #ifdef TARGET_WORDS_BIGENDIAN
 791         /* lduh [arg0], data_reg */
 792         tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
 793 #else
 794         /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
 795         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
 796 #endif
 797         break;
 798     case 1 | 4:
 799 #ifdef TARGET_WORDS_BIGENDIAN
 800         /* ldsh [arg0], data_reg */
 801         tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
 802 #else
 803         /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
 804         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
 805 #endif
 806         break;
 807     case 2:
 808 #ifdef TARGET_WORDS_BIGENDIAN
 809         /* lduw [arg0], data_reg */
 810         tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
 811 #else
 812         /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
 813         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
 814 #endif
 815         break;
 816     case 2 | 4:
 817 #ifdef TARGET_WORDS_BIGENDIAN
 818         /* ldsw [arg0], data_reg */
 819         tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
 820 #else
 821         /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
 822         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
 823 #endif
 824         break;
 825     case 3:
 826 #ifdef TARGET_WORDS_BIGENDIAN
 827         /* ldx [arg0], data_reg */
 828         tcg_out_ldst(s, data_reg, arg0, 0, LDX);
 829 #else
 830         /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
 831         tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
 832 #endif
 833         break;
 834     default:
 835         tcg_abort();
 836     }
 837
 838 #if defined(CONFIG_SOFTMMU)
 839     /* label2: */
 840     *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
 841                    INSN_OFF22((unsigned long)s->code_ptr -
 842                               (unsigned long)label2_ptr));
 843 #endif
 844 }
 845
 846 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
 847                             int opc)
 848 {
 849     int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
 850 #if defined(CONFIG_SOFTMMU)
 851     uint32_t *label1_ptr, *label2_ptr;
 852 #endif
 853
 854     data_reg = *args++;
 855     addr_reg = *args++;
 856     mem_index = *args;
 857
 858     s_bits = opc;
 859
 860     arg0 = TCG_REG_O0;
 861     arg1 = TCG_REG_O1;
 862     arg2 = TCG_REG_O2;
 863
 864 #if defined(CONFIG_SOFTMMU)
 865     /* srl addr_reg, x, arg1 */
 866     tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
 867                    SHIFT_SRL);
 868
 869     /* and addr_reg, x, arg0 */
 870     tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
 871                    ARITH_AND);
 872
 873     /* and arg1, x, arg1 */
 874     tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
 875
 876     /* add arg1, x, arg1 */
 877     tcg_out_addi(s, arg1, offsetof(CPUState,
 878                                    tlb_table[mem_index][0].addr_write));
 879
 880     /* add env, arg1, arg1 */
 881     tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
 882
 883     /* ld [arg1], arg2 */
 884     tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
 885               INSN_RS2(TCG_REG_G0));
 886
 887     /* subcc arg0, arg2, %g0 */
 888     tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
 889
 890     /* will become:
 891        be label1
 892         or
 893        be,pt %xcc label1 */
 894     label1_ptr = (uint32_t *)s->code_ptr;
 895     tcg_out32(s, 0);
 896
 897     /* mov (delay slot) */
 898     tcg_out_mov(s, arg0, addr_reg);
 899
 900     /* mov */
 901     tcg_out_mov(s, arg1, data_reg);
 902
 903     /* mov */
 904     tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
 905
 906     /* XXX: move that code at the end of the TB */
 907     /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
 908     tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
 909                            - (tcg_target_ulong)s->code_ptr) >> 2)
 910                          & 0x3fffffff));
 911     /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
 912        global registers */
 913     // delay slot
 914     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 915                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
 916                  sizeof(long), HOST_ST_OP);
 917     tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
 918                  TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
 919                  sizeof(long), HOST_LD_OP);
 920
 921     /* will become:
 922        ba label2 */
 923     label2_ptr = (uint32_t *)s->code_ptr;
 924     tcg_out32(s, 0);
 925
 926     /* nop (delay slot) */
 927     tcg_out_nop(s);
 928
 929 #if TARGET_LONG_BITS == 32
 930     /* be label1 */
 931     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
 932                    INSN_OFF22((unsigned long)s->code_ptr -
 933                               (unsigned long)label1_ptr));
 934 #else
 935     /* be,pt %xcc label1 */
 936     *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
 937                    (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
 938                               (unsigned long)label1_ptr));
 939 #endif
 940
 941     /* ld [arg1 + x], arg1 */
 942     tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
 943                  offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
 944
 945 #if TARGET_LONG_BITS == 32
 946     /* and addr_reg, x, arg0 */
 947     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
 948     tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
 949     /* add arg0, arg1, arg0 */
 950     tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
 951 #else
 952     /* add addr_reg, arg1, arg0 */
 953     tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
 954 #endif
 955
 956 #else
 957     arg0 = addr_reg;
 958 #endif
 959
 960     switch(opc) {
 961     case 0:
 962         /* stb data_reg, [arg0] */
 963         tcg_out_ldst(s, data_reg, arg0, 0, STB);
 964         break;
 965     case 1:
 966 #ifdef TARGET_WORDS_BIGENDIAN
 967         /* sth data_reg, [arg0] */
 968         tcg_out_ldst(s, data_reg, arg0, 0, STH);
 969 #else
 970         /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
 971         tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
 972 #endif
 973         break;
 974     case 2:
 975 #ifdef TARGET_WORDS_BIGENDIAN
 976         /* stw data_reg, [arg0] */
 977         tcg_out_ldst(s, data_reg, arg0, 0, STW);
 978 #else
 979         /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
 980         tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
 981 #endif
 982         break;
 983     case 3:
 984 #ifdef TARGET_WORDS_BIGENDIAN
 985         /* stx data_reg, [arg0] */
 986         tcg_out_ldst(s, data_reg, arg0, 0, STX);
 987 #else
 988         /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
 989         tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
 990 #endif
 991         break;
 992     default:
 993         tcg_abort();
 994     }
 995
 996 #if defined(CONFIG_SOFTMMU)
 997     /* label2: */
 998     *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
 999                    INSN_OFF22((unsigned long)s->code_ptr -
1000                               (unsigned long)label2_ptr));
1001 #endif
1002 }
1003
1004 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1005                               const int *const_args)
1006 {
1007     int c;
1008
1009     switch (opc) {
1010     case INDEX_op_exit_tb:
1011         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
1012         tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
1013                   INSN_IMM13(8));
1014         tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
1015                       INSN_RS2(TCG_REG_G0));
1016         break;
1017     case INDEX_op_goto_tb:
1018         if (s->tb_jmp_offset) {
1019             /* direct jump method */
1020             tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
1021             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1022                       INSN_IMM13((args[0] & 0x1fff)));
1023             s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1024         } else {
1025             /* indirect jump method */
1026             tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
1027             tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1028                       INSN_RS2(TCG_REG_G0));
1029         }
1030         tcg_out_nop(s);
1031         s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1032         break;
1033     case INDEX_op_call:
1034         if (const_args[0])
1035             tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
1036                                    - (tcg_target_ulong)s->code_ptr) >> 2)
1037                                  & 0x3fffffff));
1038         else {
1039             tcg_out_ld_ptr(s, TCG_REG_I5,
1040                            (tcg_target_long)(s->tb_next + args[0]));
1041             tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
1042                       INSN_RS2(TCG_REG_G0));
1043         }
1044         /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1045            global registers */
1046         // delay slot
1047         tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1048                      TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1049                      sizeof(long), HOST_ST_OP);
1050         tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1051                      TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1052                      sizeof(long), HOST_LD_OP);
1053         break;
1054     case INDEX_op_jmp:
1055     case INDEX_op_br:
1056         tcg_out_branch_i32(s, COND_A, args[0]);
1057         tcg_out_nop(s);
1058         break;
1059     case INDEX_op_movi_i32:
1060         tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1061         break;
1062
1063 #if TCG_TARGET_REG_BITS == 64
1064 #define OP_32_64(x)                             \
1065         glue(glue(case INDEX_op_, x), _i32):    \
1066         glue(glue(case INDEX_op_, x), _i64)
1067 #else
1068 #define OP_32_64(x)                             \
1069         glue(glue(case INDEX_op_, x), _i32)
1070 #endif
1071     OP_32_64(ld8u):
1072         tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
1073         break;
1074     OP_32_64(ld8s):
1075         tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
1076         break;
1077     OP_32_64(ld16u):
1078         tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
1079         break;
1080     OP_32_64(ld16s):
1081         tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
1082         break;
1083     case INDEX_op_ld_i32:
1084 #if TCG_TARGET_REG_BITS == 64
1085     case INDEX_op_ld32u_i64:
1086 #endif
1087         tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
1088         break;
1089     OP_32_64(st8):
1090         tcg_out_ldst(s, args[0], args[1], args[2], STB);
1091         break;
1092     OP_32_64(st16):
1093         tcg_out_ldst(s, args[0], args[1], args[2], STH);
1094         break;
1095     case INDEX_op_st_i32:
1096 #if TCG_TARGET_REG_BITS == 64
1097     case INDEX_op_st32_i64:
1098 #endif
1099         tcg_out_ldst(s, args[0], args[1], args[2], STW);
1100         break;
1101     OP_32_64(add):
1102         c = ARITH_ADD;
1103         goto gen_arith;
1104     OP_32_64(sub):
1105         c = ARITH_SUB;
1106         goto gen_arith;
1107     OP_32_64(and):
1108         c = ARITH_AND;
1109         goto gen_arith;
1110     OP_32_64(or):
1111         c = ARITH_OR;
1112         goto gen_arith;
1113     OP_32_64(xor):
1114         c = ARITH_XOR;
1115         goto gen_arith;
1116     case INDEX_op_shl_i32:
1117         c = SHIFT_SLL;
1118         goto gen_arith;
1119     case INDEX_op_shr_i32:
1120         c = SHIFT_SRL;
1121         goto gen_arith;
1122     case INDEX_op_sar_i32:
1123         c = SHIFT_SRA;
1124         goto gen_arith;
1125     case INDEX_op_mul_i32:
1126         c = ARITH_UMUL;
1127         goto gen_arith;
1128
1129     case INDEX_op_div_i32:
1130         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
1131         break;
1132     case INDEX_op_divu_i32:
1133         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1);
1134         break;
1135
1136     case INDEX_op_rem_i32:
1137     case INDEX_op_remu_i32:
1138         tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2],
1139                       opc == INDEX_op_remu_i32);
1140         tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1141                        ARITH_UMUL);
1142         tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1143         break;
1144
1145     case INDEX_op_brcond_i32:
1146         tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
1147                            args[3]);
1148         break;
1149 #if TCG_TARGET_REG_BITS == 32
1150     case INDEX_op_brcond2_i32:
1151         tcg_out_brcond2_i32(s, args[4], args[0], args[1],
1152                             args[2], const_args[2],
1153                             args[3], const_args[3], args[5]);
1154         break;
1155     case INDEX_op_add2_i32:
1156         tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1157                        ARITH_ADDCC);
1158         tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1159                        ARITH_ADDX);
1160         break;
1161     case INDEX_op_sub2_i32:
1162         tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1163                        ARITH_SUBCC);
1164         tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1165                        ARITH_SUBX);
1166         break;
1167     case INDEX_op_mulu2_i32:
1168         tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
1169                        ARITH_UMUL);
1170         tcg_out_rdy(s, args[1]);
1171         break;
1172 #endif
1173
1174     case INDEX_op_qemu_ld8u:
1175         tcg_out_qemu_ld(s, args, 0);
1176         break;
1177     case INDEX_op_qemu_ld8s:
1178         tcg_out_qemu_ld(s, args, 0 | 4);
1179         break;
1180     case INDEX_op_qemu_ld16u:
1181         tcg_out_qemu_ld(s, args, 1);
1182         break;
1183     case INDEX_op_qemu_ld16s:
1184         tcg_out_qemu_ld(s, args, 1 | 4);
1185         break;
1186     case INDEX_op_qemu_ld32u:
1187         tcg_out_qemu_ld(s, args, 2);
1188         break;
1189     case INDEX_op_qemu_ld32s:
1190         tcg_out_qemu_ld(s, args, 2 | 4);
1191         break;
1192     case INDEX_op_qemu_st8:
1193         tcg_out_qemu_st(s, args, 0);
1194         break;
1195     case INDEX_op_qemu_st16:
1196         tcg_out_qemu_st(s, args, 1);
1197         break;
1198     case INDEX_op_qemu_st32:
1199         tcg_out_qemu_st(s, args, 2);
1200         break;
1201
1202 #if TCG_TARGET_REG_BITS == 64
1203     case INDEX_op_movi_i64:
1204         tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1205         break;
1206     case INDEX_op_ld32s_i64:
1207         tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1208         break;
1209     case INDEX_op_ld_i64:
1210         tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1211         break;
1212     case INDEX_op_st_i64:
1213         tcg_out_ldst(s, args[0], args[1], args[2], STX);
1214         break;
1215     case INDEX_op_shl_i64:
1216         c = SHIFT_SLLX;
1217         goto gen_arith;
1218     case INDEX_op_shr_i64:
1219         c = SHIFT_SRLX;
1220         goto gen_arith;
1221     case INDEX_op_sar_i64:
1222         c = SHIFT_SRAX;
1223         goto gen_arith;
1224     case INDEX_op_mul_i64:
1225         c = ARITH_MULX;
1226         goto gen_arith;
1227     case INDEX_op_div_i64:
1228         c = ARITH_SDIVX;
1229         goto gen_arith;
1230     case INDEX_op_divu_i64:
1231         c = ARITH_UDIVX;
1232         goto gen_arith;
1233     case INDEX_op_rem_i64:
1234     case INDEX_op_remu_i64:
1235         tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2],
1236                        opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
1237         tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1238                        ARITH_MULX);
1239         tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1240         break;
1241     case INDEX_op_ext32s_i64:
1242         if (const_args[1]) {
1243             tcg_out_movi(s, TCG_TYPE_I64, args[0], (int32_t)args[1]);
1244         } else {
1245             tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA);
1246         }
1247         break;
1248     case INDEX_op_ext32u_i64:
1249         if (const_args[1]) {
1250             tcg_out_movi_imm32(s, args[0], args[1]);
1251         } else {
1252             tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
1253         }
1254         break;
1255
1256     case INDEX_op_brcond_i64:
1257         tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
1258                            args[3]);
1259         break;
1260     case INDEX_op_qemu_ld64:
1261         tcg_out_qemu_ld(s, args, 3);
1262         break;
1263     case INDEX_op_qemu_st64:
1264         tcg_out_qemu_st(s, args, 3);
1265         break;
1266
1267 #endif
1268     gen_arith:
1269         tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
1270         break;
1271
1272     default:
1273         fprintf(stderr, "unknown opcode 0x%x\n", opc);
1274         tcg_abort();
1275     }
1276 }
1277
1278 static const TCGTargetOpDef sparc_op_defs[] = {
1279     { INDEX_op_exit_tb, { } },
1280     { INDEX_op_goto_tb, { } },
1281     { INDEX_op_call, { "ri" } },
1282     { INDEX_op_jmp, { "ri" } },
1283     { INDEX_op_br, { } },
1284
1285     { INDEX_op_mov_i32, { "r", "r" } },
1286     { INDEX_op_movi_i32, { "r" } },
1287     { INDEX_op_ld8u_i32, { "r", "r" } },
1288     { INDEX_op_ld8s_i32, { "r", "r" } },
1289     { INDEX_op_ld16u_i32, { "r", "r" } },
1290     { INDEX_op_ld16s_i32, { "r", "r" } },
1291     { INDEX_op_ld_i32, { "r", "r" } },
1292     { INDEX_op_st8_i32, { "r", "r" } },
1293     { INDEX_op_st16_i32, { "r", "r" } },
1294     { INDEX_op_st_i32, { "r", "r" } },
1295
1296     { INDEX_op_add_i32, { "r", "r", "rJ" } },
1297     { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1298     { INDEX_op_div_i32, { "r", "r", "rJ" } },
1299     { INDEX_op_divu_i32, { "r", "r", "rJ" } },
1300     { INDEX_op_rem_i32, { "r", "r", "rJ" } },
1301     { INDEX_op_remu_i32, { "r", "r", "rJ" } },
1302     { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1303     { INDEX_op_and_i32, { "r", "r", "rJ" } },
1304     { INDEX_op_or_i32, { "r", "r", "rJ" } },
1305     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1306
1307     { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1308     { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1309     { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1310
1311     { INDEX_op_brcond_i32, { "r", "rJ" } },
1312 #if TCG_TARGET_REG_BITS == 32
1313     { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
1314     { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1315     { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1316     { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
1317 #endif
1318
1319     { INDEX_op_qemu_ld8u, { "r", "L" } },
1320     { INDEX_op_qemu_ld8s, { "r", "L" } },
1321     { INDEX_op_qemu_ld16u, { "r", "L" } },
1322     { INDEX_op_qemu_ld16s, { "r", "L" } },
1323     { INDEX_op_qemu_ld32u, { "r", "L" } },
1324     { INDEX_op_qemu_ld32s, { "r", "L" } },
1325
1326     { INDEX_op_qemu_st8, { "L", "L" } },
1327     { INDEX_op_qemu_st16, { "L", "L" } },
1328     { INDEX_op_qemu_st32, { "L", "L" } },
1329
1330 #if TCG_TARGET_REG_BITS == 64
1331     { INDEX_op_mov_i64, { "r", "r" } },
1332     { INDEX_op_movi_i64, { "r" } },
1333     { INDEX_op_ld8u_i64, { "r", "r" } },
1334     { INDEX_op_ld8s_i64, { "r", "r" } },
1335     { INDEX_op_ld16u_i64, { "r", "r" } },
1336     { INDEX_op_ld16s_i64, { "r", "r" } },
1337     { INDEX_op_ld32u_i64, { "r", "r" } },
1338     { INDEX_op_ld32s_i64, { "r", "r" } },
1339     { INDEX_op_ld_i64, { "r", "r" } },
1340     { INDEX_op_st8_i64, { "r", "r" } },
1341     { INDEX_op_st16_i64, { "r", "r" } },
1342     { INDEX_op_st32_i64, { "r", "r" } },
1343     { INDEX_op_st_i64, { "r", "r" } },
1344     { INDEX_op_qemu_ld64, { "L", "L" } },
1345     { INDEX_op_qemu_st64, { "L", "L" } },
1346
1347     { INDEX_op_add_i64, { "r", "r", "rJ" } },
1348     { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1349     { INDEX_op_div_i64, { "r", "r", "rJ" } },
1350     { INDEX_op_divu_i64, { "r", "r", "rJ" } },
1351     { INDEX_op_rem_i64, { "r", "r", "rJ" } },
1352     { INDEX_op_remu_i64, { "r", "r", "rJ" } },
1353     { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1354     { INDEX_op_and_i64, { "r", "r", "rJ" } },
1355     { INDEX_op_or_i64, { "r", "r", "rJ" } },
1356     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1357
1358     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1359     { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1360     { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1361     { INDEX_op_ext32s_i64, { "r", "ri" } },
1362     { INDEX_op_ext32u_i64, { "r", "ri" } },
1363
1364     { INDEX_op_brcond_i64, { "r", "rJ" } },
1365 #endif
1366     { -1 },
1367 };
1368
1369 void tcg_target_init(TCGContext *s)
1370 {
1371     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1372 #if TCG_TARGET_REG_BITS == 64
1373     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1374 #endif
1375     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1376                      (1 << TCG_REG_G1) |
1377                      (1 << TCG_REG_G2) |
1378                      (1 << TCG_REG_G3) |
1379                      (1 << TCG_REG_G4) |
1380                      (1 << TCG_REG_G5) |
1381                      (1 << TCG_REG_G6) |
1382                      (1 << TCG_REG_G7) |
1383                      (1 << TCG_REG_O0) |
1384                      (1 << TCG_REG_O1) |
1385                      (1 << TCG_REG_O2) |
1386                      (1 << TCG_REG_O3) |
1387                      (1 << TCG_REG_O4) |
1388                      (1 << TCG_REG_O5) |
1389                      (1 << TCG_REG_O7));
1390
1391     tcg_regset_clear(s->reserved_regs);
1392     tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1393 #if TCG_TARGET_REG_BITS == 64
1394     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1395 #endif
1396     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1397     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1398     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1399     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1400     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1401     tcg_add_target_add_op_defs(sparc_op_defs);
1402 }