hw/fw_cfg.c

   1 /*
   2  * QEMU Firmware configuration device emulation
   3  *
   4  * Copyright (c) 2008 Gleb Natapov
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sysemu.h"
  26 #include "isa.h"
  27 #include "fw_cfg.h"
  28
  29 /* debug firmware config */
  30 //#define DEBUG_FW_CFG
  31
  32 #ifdef DEBUG_FW_CFG
  33 #define FW_CFG_DPRINTF(fmt, ...)                        \
  34     do { printf("FW_CFG: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define FW_CFG_DPRINTF(fmt, ...)
  37 #endif
  38
  39 #define FW_CFG_SIZE 2
  40
  41 typedef struct _FWCfgEntry {
  42     uint16_t len;
  43     uint8_t *data;
  44     void *callback_opaque;
  45     FWCfgCallback callback;
  46 } FWCfgEntry;
  47
  48 typedef struct _FWCfgState {
  49     FWCfgEntry entries[2][FW_CFG_MAX_ENTRY];
  50     uint16_t cur_entry;
  51     uint16_t cur_offset;
  52 } FWCfgState;
  53
  54 static void fw_cfg_write(FWCfgState *s, uint8_t value)
  55 {
  56     int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
  57     FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
  58
  59     FW_CFG_DPRINTF("write %d\n", value);
  60
  61     if (s->cur_entry & FW_CFG_WRITE_CHANNEL && s->cur_offset < e->len) {
  62         e->data[s->cur_offset++] = value;
  63         if (s->cur_offset == e->len) {
  64             e->callback(e->callback_opaque, e->data);
  65             s->cur_offset = 0;
  66         }
  67     }
  68 }
  69
  70 static int fw_cfg_select(FWCfgState *s, uint16_t key)
  71 {
  72     int ret;
  73
  74     s->cur_offset = 0;
  75     if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) {
  76         s->cur_entry = FW_CFG_INVALID;
  77         ret = 0;
  78     } else {
  79         s->cur_entry = key;
  80         ret = 1;
  81     }
  82
  83     FW_CFG_DPRINTF("select key %d (%sfound)\n", key, ret ? "" : "not ");
  84
  85     return ret;
  86 }
  87
  88 static uint8_t fw_cfg_read(FWCfgState *s)
  89 {
  90     int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
  91     FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
  92     uint8_t ret;
  93
  94     if (s->cur_entry == FW_CFG_INVALID || !e->data || s->cur_offset >= e->len)
  95         ret = 0;
  96     else
  97         ret = e->data[s->cur_offset++];
  98
  99     FW_CFG_DPRINTF("read %d\n", ret);
 100
 101     return ret;
 102 }
 103
 104 static uint32_t fw_cfg_io_readb(void *opaque, uint32_t addr)
 105 {
 106     return fw_cfg_read(opaque);
 107 }
 108
 109 static void fw_cfg_io_writeb(void *opaque, uint32_t addr, uint32_t value)
 110 {
 111     fw_cfg_write(opaque, (uint8_t)value);
 112 }
 113
 114 static void fw_cfg_io_writew(void *opaque, uint32_t addr, uint32_t value)
 115 {
 116     fw_cfg_select(opaque, (uint16_t)value);
 117 }
 118
 119 static uint32_t fw_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
 120 {
 121     return fw_cfg_read(opaque);
 122 }
 123
 124 static void fw_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
 125                               uint32_t value)
 126 {
 127     fw_cfg_write(opaque, (uint8_t)value);
 128 }
 129
 130 static void fw_cfg_mem_writew(void *opaque, target_phys_addr_t addr,
 131                               uint32_t value)
 132 {
 133     fw_cfg_select(opaque, (uint16_t)value);
 134 }
 135
 136 static CPUReadMemoryFunc * const fw_cfg_ctl_mem_read[3] = {
 137     NULL,
 138     NULL,
 139     NULL,
 140 };
 141
 142 static CPUWriteMemoryFunc * const fw_cfg_ctl_mem_write[3] = {
 143     NULL,
 144     fw_cfg_mem_writew,
 145     NULL,
 146 };
 147
 148 static CPUReadMemoryFunc * const fw_cfg_data_mem_read[3] = {
 149     fw_cfg_mem_readb,
 150     NULL,
 151     NULL,
 152 };
 153
 154 static CPUWriteMemoryFunc * const fw_cfg_data_mem_write[3] = {
 155     fw_cfg_mem_writeb,
 156     NULL,
 157     NULL,
 158 };
 159
 160 static void fw_cfg_reset(void *opaque)
 161 {
 162     FWCfgState *s = opaque;
 163
 164     fw_cfg_select(s, 0);
 165 }
 166
 167 static const VMStateDescription vmstate_fw_cfg = {
 168     .name = "fw_cfg",
 169     .version_id = 1,
 170     .minimum_version_id = 1,
 171     .minimum_version_id_old = 1,
 172     .fields      = (VMStateField []) {
 173         VMSTATE_UINT16(cur_entry, FWCfgState),
 174         VMSTATE_UINT16(cur_offset, FWCfgState),
 175         VMSTATE_END_OF_LIST()
 176     }
 177 };
 178
 179 int fw_cfg_add_bytes(void *opaque, uint16_t key, uint8_t *data, uint16_t len)
 180 {
 181     FWCfgState *s = opaque;
 182     int arch = !!(key & FW_CFG_ARCH_LOCAL);
 183
 184     key &= FW_CFG_ENTRY_MASK;
 185
 186     if (key >= FW_CFG_MAX_ENTRY)
 187         return 0;
 188
 189     s->entries[arch][key].data = data;
 190     s->entries[arch][key].len = len;
 191
 192     return 1;
 193 }
 194
 195 int fw_cfg_add_i16(void *opaque, uint16_t key, uint16_t value)
 196 {
 197     uint16_t *copy;
 198
 199     copy = qemu_malloc(sizeof(value));
 200     *copy = cpu_to_le16(value);
 201     return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value));
 202 }
 203
 204 int fw_cfg_add_i32(void *opaque, uint16_t key, uint32_t value)
 205 {
 206     uint32_t *copy;
 207
 208     copy = qemu_malloc(sizeof(value));
 209     *copy = cpu_to_le32(value);
 210     return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value));
 211 }
 212
 213 int fw_cfg_add_i64(void *opaque, uint16_t key, uint64_t value)
 214 {
 215     uint64_t *copy;
 216
 217     copy = qemu_malloc(sizeof(value));
 218     *copy = cpu_to_le64(value);
 219     return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value));
 220 }
 221
 222 int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
 223                         void *callback_opaque, uint8_t *data, size_t len)
 224 {
 225     FWCfgState *s = opaque;
 226     int arch = !!(key & FW_CFG_ARCH_LOCAL);
 227
 228     if (!(key & FW_CFG_WRITE_CHANNEL))
 229         return 0;
 230
 231     key &= FW_CFG_ENTRY_MASK;
 232
 233     if (key >= FW_CFG_MAX_ENTRY || len > 65535)
 234         return 0;
 235
 236     s->entries[arch][key].data = data;
 237     s->entries[arch][key].len = len;
 238     s->entries[arch][key].callback_opaque = callback_opaque;
 239     s->entries[arch][key].callback = callback;
 240
 241     return 1;
 242 }
 243
 244 void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
 245                 target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
 246 {
 247     FWCfgState *s;
 248     int io_ctl_memory, io_data_memory;
 249
 250     s = qemu_mallocz(sizeof(FWCfgState));
 251
 252     if (ctl_port) {
 253         register_ioport_write(ctl_port, 2, 2, fw_cfg_io_writew, s);
 254     }
 255     if (data_port) {
 256         register_ioport_read(data_port, 1, 1, fw_cfg_io_readb, s);
 257         register_ioport_write(data_port, 1, 1, fw_cfg_io_writeb, s);
 258     }
 259     if (ctl_addr) {
 260         io_ctl_memory = cpu_register_io_memory(fw_cfg_ctl_mem_read,
 261                                            fw_cfg_ctl_mem_write, s);
 262         cpu_register_physical_memory(ctl_addr, FW_CFG_SIZE, io_ctl_memory);
 263     }
 264     if (data_addr) {
 265         io_data_memory = cpu_register_io_memory(fw_cfg_data_mem_read,
 266                                            fw_cfg_data_mem_write, s);
 267         cpu_register_physical_memory(data_addr, FW_CFG_SIZE, io_data_memory);
 268     }
 269     fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (uint8_t *)"QEMU", 4);
 270     fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
 271     fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC));
 272     fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
 273     fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 274     fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
 275
 276     vmstate_register(-1, &vmstate_fw_cfg, s);
 277     qemu_register_reset(fw_cfg_reset, s);
 278     fw_cfg_reset(s);
 279
 280     return s;
 281 }