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pci: irq_state vmstate breakage
[qemu/aliguori-queue.git] / hw / pci.c
blob1e143d9bf01f3fd8e0540b9fbacd296d76facd2c
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "monitor.h"
27 #include "net.h"
28 #include "sysemu.h"
29 #include "loader.h"
30 #include "qemu-objects.h"
31
32 //#define DEBUG_PCI
33 #ifdef DEBUG_PCI
34 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
35 #else
36 # define PCI_DPRINTF(format, ...) do { } while (0)
37 #endif
38
39 struct PCIBus {
40 BusState qbus;
41 int devfn_min;
42 pci_set_irq_fn set_irq;
43 pci_map_irq_fn map_irq;
44 pci_hotplug_fn hotplug;
45 void *irq_opaque;
46 PCIDevice *devices[256];
47 PCIDevice *parent_dev;
48 target_phys_addr_t mem_base;
49
50 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
51 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
52
53 /* The bus IRQ state is the logical OR of the connected devices.
54 Keep a count of the number of devices with raised IRQs. */
55 int nirq;
56 int *irq_count;
57 };
58
59 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
60
61 static struct BusInfo pci_bus_info = {
62 .name = "PCI",
63 .size = sizeof(PCIBus),
64 .print_dev = pcibus_dev_print,
65 .props = (Property[]) {
66 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
67 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
68 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
69 DEFINE_PROP_END_OF_LIST()
70 }
71 };
72
73 static void pci_update_mappings(PCIDevice *d);
74 static void pci_set_irq(void *opaque, int irq_num, int level);
75 static int pci_add_option_rom(PCIDevice *pdev);
76
77 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
78 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
79
80 struct PCIHostBus {
81 int domain;
82 struct PCIBus *bus;
83 QLIST_ENTRY(PCIHostBus) next;
84 };
85 static QLIST_HEAD(, PCIHostBus) host_buses;
86
87 static const VMStateDescription vmstate_pcibus = {
88 .name = "PCIBUS",
89 .version_id = 1,
90 .minimum_version_id = 1,
91 .minimum_version_id_old = 1,
92 .fields = (VMStateField []) {
93 VMSTATE_INT32_EQUAL(nirq, PCIBus),
94 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
95 VMSTATE_END_OF_LIST()
96 }
97 };
98
99 static int pci_bar(PCIDevice *d, int reg)
100 {
101 uint8_t type;
102
103 if (reg != PCI_ROM_SLOT)
104 return PCI_BASE_ADDRESS_0 + reg * 4;
105
106 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
107 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
108 }
109
110 static inline int pci_irq_state(PCIDevice *d, int irq_num)
111 {
112 return (d->irq_state >> irq_num) & 0x1;
113 }
114
115 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
116 {
117 d->irq_state &= ~(0x1 << irq_num);
118 d->irq_state |= level << irq_num;
119 }
120
121 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
122 {
123 PCIBus *bus;
124 for (;;) {
125 bus = pci_dev->bus;
126 irq_num = bus->map_irq(pci_dev, irq_num);
127 if (bus->set_irq)
128 break;
129 pci_dev = bus->parent_dev;
130 }
131 bus->irq_count[irq_num] += change;
132 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
133 }
134
135 /* Update interrupt status bit in config space on interrupt
136 * state change. */
137 static void pci_update_irq_status(PCIDevice *dev)
138 {
139 if (dev->irq_state) {
140 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
141 } else {
142 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
143 }
144 }
145
146 static void pci_device_reset(PCIDevice *dev)
147 {
148 int r;
149
150 dev->irq_state = 0;
151 pci_update_irq_status(dev);
152 dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
153 PCI_COMMAND_MASTER);
154 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
155 dev->config[PCI_INTERRUPT_LINE] = 0x0;
156 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
157 if (!dev->io_regions[r].size) {
158 continue;
159 }
160 pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
161 }
162 pci_update_mappings(dev);
163 }
164
165 static void pci_bus_reset(void *opaque)
166 {
167 PCIBus *bus = opaque;
168 int i;
169
170 for (i = 0; i < bus->nirq; i++) {
171 bus->irq_count[i] = 0;
172 }
173 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
174 if (bus->devices[i]) {
175 pci_device_reset(bus->devices[i]);
176 }
177 }
178 }
179
180 static void pci_host_bus_register(int domain, PCIBus *bus)
181 {
182 struct PCIHostBus *host;
183 host = qemu_mallocz(sizeof(*host));
184 host->domain = domain;
185 host->bus = bus;
186 QLIST_INSERT_HEAD(&host_buses, host, next);
187 }
188
189 PCIBus *pci_find_root_bus(int domain)
190 {
191 struct PCIHostBus *host;
192
193 QLIST_FOREACH(host, &host_buses, next) {
194 if (host->domain == domain) {
195 return host->bus;
196 }
197 }
198
199 return NULL;
200 }
201
202 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
203 const char *name, int devfn_min)
204 {
205 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
206 bus->devfn_min = devfn_min;
207
208 /* host bridge */
209 QLIST_INIT(&bus->child);
210 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
211
212 vmstate_register(-1, &vmstate_pcibus, bus);
213 qemu_register_reset(pci_bus_reset, bus);
214 }
215
216 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
217 {
218 PCIBus *bus;
219
220 bus = qemu_mallocz(sizeof(*bus));
221 bus->qbus.qdev_allocated = 1;
222 pci_bus_new_inplace(bus, parent, name, devfn_min);
223 return bus;
224 }
225
226 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
227 void *irq_opaque, int nirq)
228 {
229 bus->set_irq = set_irq;
230 bus->map_irq = map_irq;
231 bus->irq_opaque = irq_opaque;
232 bus->nirq = nirq;
233 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
234 }
235
236 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
237 {
238 bus->qbus.allow_hotplug = 1;
239 bus->hotplug = hotplug;
240 }
241
242 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
243 {
244 bus->mem_base = base;
245 }
246
247 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
248 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
249 void *irq_opaque, int devfn_min, int nirq)
250 {
251 PCIBus *bus;
252
253 bus = pci_bus_new(parent, name, devfn_min);
254 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
255 return bus;
256 }
257
258 static void pci_register_secondary_bus(PCIBus *parent,
259 PCIBus *bus,
260 PCIDevice *dev,
261 pci_map_irq_fn map_irq,
262 const char *name)
263 {
264 qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
265 bus->map_irq = map_irq;
266 bus->parent_dev = dev;
267
268 QLIST_INIT(&bus->child);
269 QLIST_INSERT_HEAD(&parent->child, bus, sibling);
270 }
271
272 static void pci_unregister_secondary_bus(PCIBus *bus)
273 {
274 assert(QLIST_EMPTY(&bus->child));
275 QLIST_REMOVE(bus, sibling);
276 }
277
278 int pci_bus_num(PCIBus *s)
279 {
280 if (!s->parent_dev)
281 return 0; /* pci host bridge */
282 return s->parent_dev->config[PCI_SECONDARY_BUS];
283 }
284
285 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
286 {
287 PCIDevice *s = container_of(pv, PCIDevice, config);
288 uint8_t *config;
289 int i;
290
291 assert(size == pci_config_size(s));
292 config = qemu_malloc(size);
293
294 qemu_get_buffer(f, config, size);
295 for (i = 0; i < size; ++i) {
296 if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
297 qemu_free(config);
298 return -EINVAL;
299 }
300 }
301 memcpy(s->config, config, size);
302
303 pci_update_mappings(s);
304
305 qemu_free(config);
306 return 0;
307 }
308
309 /* just put buffer */
310 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
311 {
312 const uint8_t **v = pv;
313 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
314 qemu_put_buffer(f, *v, size);
315 }
316
317 static VMStateInfo vmstate_info_pci_config = {
318 .name = "pci config",
319 .get = get_pci_config_device,
320 .put = put_pci_config_device,
321 };
322
323 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
324 {
325 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
326 uint32_t irq_state[PCI_NUM_PINS];
327 int i;
328 for (i = 0; i < PCI_NUM_PINS; ++i) {
329 irq_state[i] = qemu_get_be32(f);
330 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
331 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
332 irq_state[i]);
333 return -EINVAL;
334 }
335 }
336
337 for (i = 0; i < PCI_NUM_PINS; ++i) {
338 pci_set_irq_state(s, i, irq_state[i]);
339 }
340
341 return 0;
342 }
343
344 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
345 {
346 int i;
347 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
348
349 for (i = 0; i < PCI_NUM_PINS; ++i) {
350 qemu_put_be32(f, pci_irq_state(s, i));
351 }
352 }
353
354 static VMStateInfo vmstate_info_pci_irq_state = {
355 .name = "pci irq state",
356 .get = get_pci_irq_state,
357 .put = put_pci_irq_state,
358 };
359
360 const VMStateDescription vmstate_pci_device = {
361 .name = "PCIDevice",
362 .version_id = 2,
363 .minimum_version_id = 1,
364 .minimum_version_id_old = 1,
365 .fields = (VMStateField []) {
366 VMSTATE_INT32_LE(version_id, PCIDevice),
367 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
368 vmstate_info_pci_config,
369 PCI_CONFIG_SPACE_SIZE),
370 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
371 vmstate_info_pci_irq_state,
372 PCI_NUM_PINS * sizeof(int32_t)),
373 VMSTATE_END_OF_LIST()
374 }
375 };
376
377 const VMStateDescription vmstate_pcie_device = {
378 .name = "PCIDevice",
379 .version_id = 2,
380 .minimum_version_id = 1,
381 .minimum_version_id_old = 1,
382 .fields = (VMStateField []) {
383 VMSTATE_INT32_LE(version_id, PCIDevice),
384 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
385 vmstate_info_pci_config,
386 PCIE_CONFIG_SPACE_SIZE),
387 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
388 vmstate_info_pci_irq_state,
389 PCI_NUM_PINS * sizeof(int32_t)),
390 VMSTATE_END_OF_LIST()
391 }
392 };
393
394 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
395 {
396 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
397 }
398
399 void pci_device_save(PCIDevice *s, QEMUFile *f)
400 {
401 /* Clear interrupt status bit: it is implicit
402 * in irq_state which we are saving.
403 * This makes us compatible with old devices
404 * which never set or clear this bit. */
405 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
406 vmstate_save_state(f, pci_get_vmstate(s), s);
407 /* Restore the interrupt status bit. */
408 pci_update_irq_status(s);
409 }
410
411 int pci_device_load(PCIDevice *s, QEMUFile *f)
412 {
413 int ret;
414 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
415 /* Restore the interrupt status bit. */
416 pci_update_irq_status(s);
417 return ret;
418 }
419
420 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
421 {
422 uint16_t *id;
423
424 id = (void*)(&pci_dev->config[PCI_SUBSYSTEM_VENDOR_ID]);
425 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
426 id[1] = cpu_to_le16(pci_default_sub_device_id);
427 return 0;
428 }
429
430 /*
431 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
432 */
433 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
434 {
435 const char *p;
436 char *e;
437 unsigned long val;
438 unsigned long dom = 0, bus = 0;
439 unsigned slot = 0;
440
441 p = addr;
442 val = strtoul(p, &e, 16);
443 if (e == p)
444 return -1;
445 if (*e == ':') {
446 bus = val;
447 p = e + 1;
448 val = strtoul(p, &e, 16);
449 if (e == p)
450 return -1;
451 if (*e == ':') {
452 dom = bus;
453 bus = val;
454 p = e + 1;
455 val = strtoul(p, &e, 16);
456 if (e == p)
457 return -1;
458 }
459 }
460
461 if (dom > 0xffff || bus > 0xff || val > 0x1f)
462 return -1;
463
464 slot = val;
465
466 if (*e)
467 return -1;
468
469 /* Note: QEMU doesn't implement domains other than 0 */
470 if (!pci_find_bus(pci_find_root_bus(dom), bus))
471 return -1;
472
473 *domp = dom;
474 *busp = bus;
475 *slotp = slot;
476 return 0;
477 }
478
479 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
480 unsigned *slotp)
481 {
482 /* strip legacy tag */
483 if (!strncmp(addr, "pci_addr=", 9)) {
484 addr += 9;
485 }
486 if (pci_parse_devaddr(addr, domp, busp, slotp)) {
487 monitor_printf(mon, "Invalid pci address\n");
488 return -1;
489 }
490 return 0;
491 }
492
493 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
494 {
495 int dom, bus;
496 unsigned slot;
497
498 if (!devaddr) {
499 *devfnp = -1;
500 return pci_find_bus(pci_find_root_bus(0), 0);
501 }
502
503 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
504 return NULL;
505 }
506
507 *devfnp = slot << 3;
508 return pci_find_bus(pci_find_root_bus(0), bus);
509 }
510
511 static void pci_init_cmask(PCIDevice *dev)
512 {
513 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
514 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
515 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
516 dev->cmask[PCI_REVISION_ID] = 0xff;
517 dev->cmask[PCI_CLASS_PROG] = 0xff;
518 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
519 dev->cmask[PCI_HEADER_TYPE] = 0xff;
520 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
521 }
522
523 static void pci_init_wmask(PCIDevice *dev)
524 {
525 int config_size = pci_config_size(dev);
526
527 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
528 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
529 pci_set_word(dev->wmask + PCI_COMMAND,
530 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
531 PCI_COMMAND_INTX_DISABLE);
532
533 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
534 config_size - PCI_CONFIG_HEADER_SIZE);
535 }
536
537 static void pci_init_wmask_bridge(PCIDevice *d)
538 {
539 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
540 PCI_SEC_LETENCY_TIMER */
541 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
542
543 /* base and limit */
544 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
545 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
546 pci_set_word(d->wmask + PCI_MEMORY_BASE,
547 PCI_MEMORY_RANGE_MASK & 0xffff);
548 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
549 PCI_MEMORY_RANGE_MASK & 0xffff);
550 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
551 PCI_PREF_RANGE_MASK & 0xffff);
552 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
553 PCI_PREF_RANGE_MASK & 0xffff);
554
555 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
556 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
557
558 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
559 }
560
561 static void pci_config_alloc(PCIDevice *pci_dev)
562 {
563 int config_size = pci_config_size(pci_dev);
564
565 pci_dev->config = qemu_mallocz(config_size);
566 pci_dev->cmask = qemu_mallocz(config_size);
567 pci_dev->wmask = qemu_mallocz(config_size);
568 pci_dev->used = qemu_mallocz(config_size);
569 }
570
571 static void pci_config_free(PCIDevice *pci_dev)
572 {
573 qemu_free(pci_dev->config);
574 qemu_free(pci_dev->cmask);
575 qemu_free(pci_dev->wmask);
576 qemu_free(pci_dev->used);
577 }
578
579 /* -1 for devfn means auto assign */
580 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
581 const char *name, int devfn,
582 PCIConfigReadFunc *config_read,
583 PCIConfigWriteFunc *config_write,
584 uint8_t header_type)
585 {
586 if (devfn < 0) {
587 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
588 devfn += 8) {
589 if (!bus->devices[devfn])
590 goto found;
591 }
592 error_report("PCI: no devfn available for %s, all in use", name);
593 return NULL;
594 found: ;
595 } else if (bus->devices[devfn]) {
596 error_report("PCI: devfn %d not available for %s, in use by %s",
597 devfn, name, bus->devices[devfn]->name);
598 return NULL;
599 }
600 pci_dev->bus = bus;
601 pci_dev->devfn = devfn;
602 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
603 pci_dev->irq_state = 0;
604 pci_config_alloc(pci_dev);
605
606 header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
607 if (header_type == PCI_HEADER_TYPE_NORMAL) {
608 pci_set_default_subsystem_id(pci_dev);
609 }
610 pci_init_cmask(pci_dev);
611 pci_init_wmask(pci_dev);
612 if (header_type == PCI_HEADER_TYPE_BRIDGE) {
613 pci_init_wmask_bridge(pci_dev);
614 }
615
616 if (!config_read)
617 config_read = pci_default_read_config;
618 if (!config_write)
619 config_write = pci_default_write_config;
620 pci_dev->config_read = config_read;
621 pci_dev->config_write = config_write;
622 bus->devices[devfn] = pci_dev;
623 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
624 pci_dev->version_id = 2; /* Current pci device vmstate version */
625 return pci_dev;
626 }
627
628 static void do_pci_unregister_device(PCIDevice *pci_dev)
629 {
630 qemu_free_irqs(pci_dev->irq);
631 pci_dev->bus->devices[pci_dev->devfn] = NULL;
632 pci_config_free(pci_dev);
633 }
634
635 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
636 int instance_size, int devfn,
637 PCIConfigReadFunc *config_read,
638 PCIConfigWriteFunc *config_write)
639 {
640 PCIDevice *pci_dev;
641
642 pci_dev = qemu_mallocz(instance_size);
643 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
644 config_read, config_write,
645 PCI_HEADER_TYPE_NORMAL);
646 if (pci_dev == NULL) {
647 hw_error("PCI: can't register device\n");
648 }
649 return pci_dev;
650 }
651
652 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
653 target_phys_addr_t addr)
654 {
655 return addr + bus->mem_base;
656 }
657
658 static void pci_unregister_io_regions(PCIDevice *pci_dev)
659 {
660 PCIIORegion *r;
661 int i;
662
663 for(i = 0; i < PCI_NUM_REGIONS; i++) {
664 r = &pci_dev->io_regions[i];
665 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
666 continue;
667 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
668 isa_unassign_ioport(r->addr, r->filtered_size);
669 } else {
670 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
671 r->addr),
672 r->filtered_size,
673 IO_MEM_UNASSIGNED);
674 }
675 }
676 }
677
678 static int pci_unregister_device(DeviceState *dev)
679 {
680 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
681 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
682 int ret = 0;
683
684 if (info->exit)
685 ret = info->exit(pci_dev);
686 if (ret)
687 return ret;
688
689 pci_unregister_io_regions(pci_dev);
690 do_pci_unregister_device(pci_dev);
691 return 0;
692 }
693
694 void pci_register_bar(PCIDevice *pci_dev, int region_num,
695 pcibus_t size, int type,
696 PCIMapIORegionFunc *map_func)
697 {
698 PCIIORegion *r;
699 uint32_t addr;
700 pcibus_t wmask;
701
702 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
703 return;
704
705 if (size & (size-1)) {
706 fprintf(stderr, "ERROR: PCI region size must be pow2 "
707 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
708 exit(1);
709 }
710
711 r = &pci_dev->io_regions[region_num];
712 r->addr = PCI_BAR_UNMAPPED;
713 r->size = size;
714 r->filtered_size = size;
715 r->type = type;
716 r->map_func = map_func;
717
718 wmask = ~(size - 1);
719 addr = pci_bar(pci_dev, region_num);
720 if (region_num == PCI_ROM_SLOT) {
721 /* ROM enable bit is writeable */
722 wmask |= PCI_ROM_ADDRESS_ENABLE;
723 }
724 pci_set_long(pci_dev->config + addr, type);
725 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
726 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
727 pci_set_quad(pci_dev->wmask + addr, wmask);
728 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
729 } else {
730 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
731 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
732 }
733 }
734
735 static uint32_t pci_config_get_io_base(PCIDevice *d,
736 uint32_t base, uint32_t base_upper16)
737 {
738 uint32_t val;
739
740 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
741 if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
742 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
743 }
744 return val;
745 }
746
747 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
748 {
749 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
750 << 16;
751 }
752
753 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
754 uint32_t base, uint32_t upper)
755 {
756 pcibus_t tmp;
757 pcibus_t val;
758
759 tmp = (pcibus_t)pci_get_word(d->config + base);
760 val = (tmp & PCI_PREF_RANGE_MASK) << 16;
761 if (tmp & PCI_PREF_RANGE_TYPE_64) {
762 val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
763 }
764 return val;
765 }
766
767 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
768 {
769 pcibus_t base;
770 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
771 base = pci_config_get_io_base(bridge,
772 PCI_IO_BASE, PCI_IO_BASE_UPPER16);
773 } else {
774 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
775 base = pci_config_get_pref_base(
776 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
777 } else {
778 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
779 }
780 }
781
782 return base;
783 }
784
785 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
786 {
787 pcibus_t limit;
788 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
789 limit = pci_config_get_io_base(bridge,
790 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
791 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
792 } else {
793 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
794 limit = pci_config_get_pref_base(
795 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
796 } else {
797 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
798 }
799 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
800 }
801 return limit;
802 }
803
804 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
805 uint8_t type)
806 {
807 pcibus_t base = *addr;
808 pcibus_t limit = *addr + *size - 1;
809 PCIDevice *br;
810
811 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
812 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
813
814 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
815 if (!(cmd & PCI_COMMAND_IO)) {
816 goto no_map;
817 }
818 } else {
819 if (!(cmd & PCI_COMMAND_MEMORY)) {
820 goto no_map;
821 }
822 }
823
824 base = MAX(base, pci_bridge_get_base(br, type));
825 limit = MIN(limit, pci_bridge_get_limit(br, type));
826 }
827
828 if (base > limit) {
829 goto no_map;
830 }
831 *addr = base;
832 *size = limit - base + 1;
833 return;
834 no_map:
835 *addr = PCI_BAR_UNMAPPED;
836 *size = 0;
837 }
838
839 static pcibus_t pci_bar_address(PCIDevice *d,
840 int reg, uint8_t type, pcibus_t size)
841 {
842 pcibus_t new_addr, last_addr;
843 int bar = pci_bar(d, reg);
844 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
845
846 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
847 if (!(cmd & PCI_COMMAND_IO)) {
848 return PCI_BAR_UNMAPPED;
849 }
850 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
851 last_addr = new_addr + size - 1;
852 /* NOTE: we have only 64K ioports on PC */
853 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
854 return PCI_BAR_UNMAPPED;
855 }
856 return new_addr;
857 }
858
859 if (!(cmd & PCI_COMMAND_MEMORY)) {
860 return PCI_BAR_UNMAPPED;
861 }
862 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
863 new_addr = pci_get_quad(d->config + bar);
864 } else {
865 new_addr = pci_get_long(d->config + bar);
866 }
867 /* the ROM slot has a specific enable bit */
868 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
869 return PCI_BAR_UNMAPPED;
870 }
871 new_addr &= ~(size - 1);
872 last_addr = new_addr + size - 1;
873 /* NOTE: we do not support wrapping */
874 /* XXX: as we cannot support really dynamic
875 mappings, we handle specific values as invalid
876 mappings. */
877 if (last_addr <= new_addr || new_addr == 0 ||
878 last_addr == PCI_BAR_UNMAPPED) {
879 return PCI_BAR_UNMAPPED;
880 }
881
882 /* Now pcibus_t is 64bit.
883 * Check if 32 bit BAR wraps around explicitly.
884 * Without this, PC ide doesn't work well.
885 * TODO: remove this work around.
886 */
887 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
888 return PCI_BAR_UNMAPPED;
889 }
890
891 /*
892 * OS is allowed to set BAR beyond its addressable
893 * bits. For example, 32 bit OS can set 64bit bar
894 * to >4G. Check it. TODO: we might need to support
895 * it in the future for e.g. PAE.
896 */
897 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
898 return PCI_BAR_UNMAPPED;
899 }
900
901 return new_addr;
902 }
903
904 static void pci_update_mappings(PCIDevice *d)
905 {
906 PCIIORegion *r;
907 int i;
908 pcibus_t new_addr, filtered_size;
909
910 for(i = 0; i < PCI_NUM_REGIONS; i++) {
911 r = &d->io_regions[i];
912
913 /* this region isn't registered */
914 if (!r->size)
915 continue;
916
917 new_addr = pci_bar_address(d, i, r->type, r->size);
918
919 /* bridge filtering */
920 filtered_size = r->size;
921 if (new_addr != PCI_BAR_UNMAPPED) {
922 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
923 }
924
925 /* This bar isn't changed */
926 if (new_addr == r->addr && filtered_size == r->filtered_size)
927 continue;
928
929 /* now do the real mapping */
930 if (r->addr != PCI_BAR_UNMAPPED) {
931 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
932 int class;
933 /* NOTE: specific hack for IDE in PC case:
934 only one byte must be mapped. */
935 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
936 if (class == 0x0101 && r->size == 4) {
937 isa_unassign_ioport(r->addr + 2, 1);
938 } else {
939 isa_unassign_ioport(r->addr, r->filtered_size);
940 }
941 } else {
942 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
943 r->filtered_size,
944 IO_MEM_UNASSIGNED);
945 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
946 }
947 }
948 r->addr = new_addr;
949 r->filtered_size = filtered_size;
950 if (r->addr != PCI_BAR_UNMAPPED) {
951 /*
952 * TODO: currently almost all the map funcions assumes
953 * filtered_size == size and addr & ~(size - 1) == addr.
954 * However with bridge filtering, they aren't always true.
955 * Teach them such cases, such that filtered_size < size and
956 * addr & (size - 1) != 0.
957 */
958 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
959 r->map_func(d, i, r->addr, r->filtered_size, r->type);
960 } else {
961 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
962 r->filtered_size, r->type);
963 }
964 }
965 }
966 }
967
968 static inline int pci_irq_disabled(PCIDevice *d)
969 {
970 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
971 }
972
973 /* Called after interrupt disabled field update in config space,
974 * assert/deassert interrupts if necessary.
975 * Gets original interrupt disable bit value (before update). */
976 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
977 {
978 int i, disabled = pci_irq_disabled(d);
979 if (disabled == was_irq_disabled)
980 return;
981 for (i = 0; i < PCI_NUM_PINS; ++i) {
982 int state = pci_irq_state(d, i);
983 pci_change_irq_level(d, i, disabled ? -state : state);
984 }
985 }
986
987 uint32_t pci_default_read_config(PCIDevice *d,
988 uint32_t address, int len)
989 {
990 uint32_t val = 0;
991 assert(len == 1 || len == 2 || len == 4);
992 len = MIN(len, pci_config_size(d) - address);
993 memcpy(&val, d->config + address, len);
994 return le32_to_cpu(val);
995 }
996
997 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
998 {
999 int i, was_irq_disabled = pci_irq_disabled(d);
1000 uint32_t config_size = pci_config_size(d);
1001
1002 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1003 uint8_t wmask = d->wmask[addr + i];
1004 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1005 }
1006 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1007 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1008 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1009 range_covers_byte(addr, l, PCI_COMMAND))
1010 pci_update_mappings(d);
1011
1012 if (range_covers_byte(addr, l, PCI_COMMAND))
1013 pci_update_irq_disabled(d, was_irq_disabled);
1014 }
1015
1016 /***********************************************************/
1017 /* generic PCI irq support */
1018
1019 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1020 static void pci_set_irq(void *opaque, int irq_num, int level)
1021 {
1022 PCIDevice *pci_dev = opaque;
1023 int change;
1024
1025 change = level - pci_irq_state(pci_dev, irq_num);
1026 if (!change)
1027 return;
1028
1029 pci_set_irq_state(pci_dev, irq_num, level);
1030 pci_update_irq_status(pci_dev);
1031 if (pci_irq_disabled(pci_dev))
1032 return;
1033 pci_change_irq_level(pci_dev, irq_num, change);
1034 }
1035
1036 /***********************************************************/
1037 /* monitor info on PCI */
1038
1039 typedef struct {
1040 uint16_t class;
1041 const char *desc;
1042 } pci_class_desc;
1043
1044 static const pci_class_desc pci_class_descriptions[] =
1045 {
1046 { 0x0100, "SCSI controller"},
1047 { 0x0101, "IDE controller"},
1048 { 0x0102, "Floppy controller"},
1049 { 0x0103, "IPI controller"},
1050 { 0x0104, "RAID controller"},
1051 { 0x0106, "SATA controller"},
1052 { 0x0107, "SAS controller"},
1053 { 0x0180, "Storage controller"},
1054 { 0x0200, "Ethernet controller"},
1055 { 0x0201, "Token Ring controller"},
1056 { 0x0202, "FDDI controller"},
1057 { 0x0203, "ATM controller"},
1058 { 0x0280, "Network controller"},
1059 { 0x0300, "VGA controller"},
1060 { 0x0301, "XGA controller"},
1061 { 0x0302, "3D controller"},
1062 { 0x0380, "Display controller"},
1063 { 0x0400, "Video controller"},
1064 { 0x0401, "Audio controller"},
1065 { 0x0402, "Phone"},
1066 { 0x0480, "Multimedia controller"},
1067 { 0x0500, "RAM controller"},
1068 { 0x0501, "Flash controller"},
1069 { 0x0580, "Memory controller"},
1070 { 0x0600, "Host bridge"},
1071 { 0x0601, "ISA bridge"},
1072 { 0x0602, "EISA bridge"},
1073 { 0x0603, "MC bridge"},
1074 { 0x0604, "PCI bridge"},
1075 { 0x0605, "PCMCIA bridge"},
1076 { 0x0606, "NUBUS bridge"},
1077 { 0x0607, "CARDBUS bridge"},
1078 { 0x0608, "RACEWAY bridge"},
1079 { 0x0680, "Bridge"},
1080 { 0x0c03, "USB controller"},
1081 { 0, NULL}
1082 };
1083
1084 static void pci_for_each_device_under_bus(PCIBus *bus,
1085 void (*fn)(PCIBus *b, PCIDevice *d))
1086 {
1087 PCIDevice *d;
1088 int devfn;
1089
1090 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1091 d = bus->devices[devfn];
1092 if (d) {
1093 fn(bus, d);
1094 }
1095 }
1096 }
1097
1098 void pci_for_each_device(PCIBus *bus, int bus_num,
1099 void (*fn)(PCIBus *b, PCIDevice *d))
1100 {
1101 bus = pci_find_bus(bus, bus_num);
1102
1103 if (bus) {
1104 pci_for_each_device_under_bus(bus, fn);
1105 }
1106 }
1107
1108 static void pci_device_print(Monitor *mon, QDict *device)
1109 {
1110 QDict *qdict;
1111 QListEntry *entry;
1112 uint64_t addr, size;
1113
1114 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1115 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1116 qdict_get_int(device, "slot"),
1117 qdict_get_int(device, "function"));
1118 monitor_printf(mon, " ");
1119
1120 qdict = qdict_get_qdict(device, "class_info");
1121 if (qdict_haskey(qdict, "desc")) {
1122 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1123 } else {
1124 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1125 }
1126
1127 qdict = qdict_get_qdict(device, "id");
1128 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1129 qdict_get_int(qdict, "device"),
1130 qdict_get_int(qdict, "vendor"));
1131
1132 if (qdict_haskey(device, "irq")) {
1133 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1134 qdict_get_int(device, "irq"));
1135 }
1136
1137 if (qdict_haskey(device, "pci_bridge")) {
1138 QDict *info;
1139
1140 qdict = qdict_get_qdict(device, "pci_bridge");
1141
1142 info = qdict_get_qdict(qdict, "bus");
1143 monitor_printf(mon, " BUS %" PRId64 ".\n",
1144 qdict_get_int(info, "number"));
1145 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1146 qdict_get_int(info, "secondary"));
1147 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1148 qdict_get_int(info, "subordinate"));
1149
1150 info = qdict_get_qdict(qdict, "io_range");
1151 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1152 qdict_get_int(info, "base"),
1153 qdict_get_int(info, "limit"));
1154
1155 info = qdict_get_qdict(qdict, "memory_range");
1156 monitor_printf(mon,
1157 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1158 qdict_get_int(info, "base"),
1159 qdict_get_int(info, "limit"));
1160
1161 info = qdict_get_qdict(qdict, "prefetchable_range");
1162 monitor_printf(mon, " prefetchable memory range "
1163 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1164 qdict_get_int(info, "base"),
1165 qdict_get_int(info, "limit"));
1166 }
1167
1168 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1169 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1170 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1171
1172 addr = qdict_get_int(qdict, "address");
1173 size = qdict_get_int(qdict, "size");
1174
1175 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1176 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1177 " [0x%04"FMT_PCIBUS"].\n",
1178 addr, addr + size - 1);
1179 } else {
1180 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1181 " [0x%08"FMT_PCIBUS"].\n",
1182 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1183 qdict_get_bool(qdict, "prefetch") ?
1184 " prefetchable" : "", addr, addr + size - 1);
1185 }
1186 }
1187
1188 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1189
1190 if (qdict_haskey(device, "pci_bridge")) {
1191 qdict = qdict_get_qdict(device, "pci_bridge");
1192 if (qdict_haskey(qdict, "devices")) {
1193 QListEntry *dev;
1194 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1195 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1196 }
1197 }
1198 }
1199 }
1200
1201 void do_pci_info_print(Monitor *mon, const QObject *data)
1202 {
1203 QListEntry *bus, *dev;
1204
1205 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1206 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1207 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1208 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1209 }
1210 }
1211 }
1212
1213 static QObject *pci_get_dev_class(const PCIDevice *dev)
1214 {
1215 int class;
1216 const pci_class_desc *desc;
1217
1218 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1219 desc = pci_class_descriptions;
1220 while (desc->desc && class != desc->class)
1221 desc++;
1222
1223 if (desc->desc) {
1224 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1225 desc->desc, class);
1226 } else {
1227 return qobject_from_jsonf("{ 'class': %d }", class);
1228 }
1229 }
1230
1231 static QObject *pci_get_dev_id(const PCIDevice *dev)
1232 {
1233 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1234 pci_get_word(dev->config + PCI_VENDOR_ID),
1235 pci_get_word(dev->config + PCI_DEVICE_ID));
1236 }
1237
1238 static QObject *pci_get_regions_list(const PCIDevice *dev)
1239 {
1240 int i;
1241 QList *regions_list;
1242
1243 regions_list = qlist_new();
1244
1245 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1246 QObject *obj;
1247 const PCIIORegion *r = &dev->io_regions[i];
1248
1249 if (!r->size) {
1250 continue;
1251 }
1252
1253 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1254 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1255 "'address': %" PRId64 ", "
1256 "'size': %" PRId64 " }",
1257 i, r->addr, r->size);
1258 } else {
1259 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1260
1261 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1262 "'mem_type_64': %i, 'prefetch': %i, "
1263 "'address': %" PRId64 ", "
1264 "'size': %" PRId64 " }",
1265 i, mem_type_64,
1266 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1267 r->addr, r->size);
1268 }
1269
1270 qlist_append_obj(regions_list, obj);
1271 }
1272
1273 return QOBJECT(regions_list);
1274 }
1275
1276 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1277
1278 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1279 {
1280 uint8_t type;
1281 QObject *obj;
1282
1283 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1284 " 'qdev_id': %s }",
1285 bus_num,
1286 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1287 pci_get_dev_class(dev), pci_get_dev_id(dev),
1288 pci_get_regions_list(dev),
1289 dev->qdev.id ? dev->qdev.id : "");
1290
1291 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1292 QDict *qdict = qobject_to_qdict(obj);
1293 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1294 }
1295
1296 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1297 if (type == PCI_HEADER_TYPE_BRIDGE) {
1298 QDict *qdict;
1299 QObject *pci_bridge;
1300
1301 pci_bridge = qobject_from_jsonf("{ 'bus': "
1302 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1303 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1304 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1305 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1306 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1307 dev->config[PCI_SUBORDINATE_BUS],
1308 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1309 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1310 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1311 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1312 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1313 PCI_BASE_ADDRESS_MEM_PREFETCH),
1314 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1315 PCI_BASE_ADDRESS_MEM_PREFETCH));
1316
1317 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1318 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1319
1320 if (child_bus) {
1321 qdict = qobject_to_qdict(pci_bridge);
1322 qdict_put_obj(qdict, "devices",
1323 pci_get_devices_list(child_bus,
1324 dev->config[PCI_SECONDARY_BUS]));
1325 }
1326 }
1327 qdict = qobject_to_qdict(obj);
1328 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1329 }
1330
1331 return obj;
1332 }
1333
1334 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1335 {
1336 int devfn;
1337 PCIDevice *dev;
1338 QList *dev_list;
1339
1340 dev_list = qlist_new();
1341
1342 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1343 dev = bus->devices[devfn];
1344 if (dev) {
1345 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1346 }
1347 }
1348
1349 return QOBJECT(dev_list);
1350 }
1351
1352 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1353 {
1354 bus = pci_find_bus(bus, bus_num);
1355 if (bus) {
1356 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1357 bus_num, pci_get_devices_list(bus, bus_num));
1358 }
1359
1360 return NULL;
1361 }
1362
1363 /**
1364 * do_pci_info(): PCI buses and devices information
1365 *
1366 * The returned QObject is a QList of all buses. Each bus is
1367 * represented by a QDict, which has a key with a QList of all
1368 * PCI devices attached to it. Each device is represented by
1369 * a QDict.
1370 *
1371 * The bus QDict contains the following:
1372 *
1373 * - "bus": bus number
1374 * - "devices": a QList of QDicts, each QDict represents a PCI
1375 * device
1376 *
1377 * The PCI device QDict contains the following:
1378 *
1379 * - "bus": identical to the parent's bus number
1380 * - "slot": slot number
1381 * - "function": function number
1382 * - "class_info": a QDict containing:
1383 * - "desc": device class description (optional)
1384 * - "class": device class number
1385 * - "id": a QDict containing:
1386 * - "device": device ID
1387 * - "vendor": vendor ID
1388 * - "irq": device's IRQ if assigned (optional)
1389 * - "qdev_id": qdev id string
1390 * - "pci_bridge": It's a QDict, only present if this device is a
1391 * PCI bridge, contains:
1392 * - "bus": bus number
1393 * - "secondary": secondary bus number
1394 * - "subordinate": subordinate bus number
1395 * - "io_range": a QDict with memory range information
1396 * - "memory_range": a QDict with memory range information
1397 * - "prefetchable_range": a QDict with memory range information
1398 * - "devices": a QList of PCI devices if there's any attached (optional)
1399 * - "regions": a QList of QDicts, each QDict represents a
1400 * memory region of this device
1401 *
1402 * The memory range QDict contains the following:
1403 *
1404 * - "base": base memory address
1405 * - "limit": limit value
1406 *
1407 * The region QDict can be an I/O region or a memory region,
1408 * an I/O region QDict contains the following:
1409 *
1410 * - "type": "io"
1411 * - "bar": BAR number
1412 * - "address": memory address
1413 * - "size": memory size
1414 *
1415 * A memory region QDict contains the following:
1416 *
1417 * - "type": "memory"
1418 * - "bar": BAR number
1419 * - "address": memory address
1420 * - "size": memory size
1421 * - "mem_type_64": true or false
1422 * - "prefetch": true or false
1423 */
1424 void do_pci_info(Monitor *mon, QObject **ret_data)
1425 {
1426 QList *bus_list;
1427 struct PCIHostBus *host;
1428
1429 bus_list = qlist_new();
1430
1431 QLIST_FOREACH(host, &host_buses, next) {
1432 QObject *obj = pci_get_bus_dict(host->bus, 0);
1433 if (obj) {
1434 qlist_append_obj(bus_list, obj);
1435 }
1436 }
1437
1438 *ret_data = QOBJECT(bus_list);
1439 }
1440
1441 static const char * const pci_nic_models[] = {
1442 "ne2k_pci",
1443 "i82551",
1444 "i82557b",
1445 "i82559er",
1446 "rtl8139",
1447 "e1000",
1448 "pcnet",
1449 "virtio",
1450 NULL
1451 };
1452
1453 static const char * const pci_nic_names[] = {
1454 "ne2k_pci",
1455 "i82551",
1456 "i82557b",
1457 "i82559er",
1458 "rtl8139",
1459 "e1000",
1460 "pcnet",
1461 "virtio-net-pci",
1462 NULL
1463 };
1464
1465 /* Initialize a PCI NIC. */
1466 /* FIXME callers should check for failure, but don't */
1467 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1468 const char *default_devaddr)
1469 {
1470 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1471 PCIBus *bus;
1472 int devfn;
1473 PCIDevice *pci_dev;
1474 DeviceState *dev;
1475 int i;
1476
1477 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1478 if (i < 0)
1479 return NULL;
1480
1481 bus = pci_get_bus_devfn(&devfn, devaddr);
1482 if (!bus) {
1483 error_report("Invalid PCI device address %s for device %s",
1484 devaddr, pci_nic_names[i]);
1485 return NULL;
1486 }
1487
1488 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1489 dev = &pci_dev->qdev;
1490 if (nd->name)
1491 dev->id = qemu_strdup(nd->name);
1492 qdev_set_nic_properties(dev, nd);
1493 if (qdev_init(dev) < 0)
1494 return NULL;
1495 return pci_dev;
1496 }
1497
1498 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1499 const char *default_devaddr)
1500 {
1501 PCIDevice *res;
1502
1503 if (qemu_show_nic_models(nd->model, pci_nic_models))
1504 exit(0);
1505
1506 res = pci_nic_init(nd, default_model, default_devaddr);
1507 if (!res)
1508 exit(1);
1509 return res;
1510 }
1511
1512 typedef struct {
1513 PCIDevice dev;
1514 PCIBus bus;
1515 uint32_t vid;
1516 uint32_t did;
1517 } PCIBridge;
1518
1519
1520 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1521 {
1522 pci_update_mappings(d);
1523 }
1524
1525 static void pci_bridge_update_mappings(PCIBus *b)
1526 {
1527 PCIBus *child;
1528
1529 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1530
1531 QLIST_FOREACH(child, &b->child, sibling) {
1532 pci_bridge_update_mappings(child);
1533 }
1534 }
1535
1536 static void pci_bridge_write_config(PCIDevice *d,
1537 uint32_t address, uint32_t val, int len)
1538 {
1539 pci_default_write_config(d, address, val, len);
1540
1541 if (/* io base/limit */
1542 ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1543
1544 /* memory base/limit, prefetchable base/limit and
1545 io base/limit upper 16 */
1546 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1547 pci_bridge_update_mappings(d->bus);
1548 }
1549 }
1550
1551 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1552 {
1553 PCIBus *sec;
1554
1555 if (!bus) {
1556 return NULL;
1557 }
1558
1559 if (pci_bus_num(bus) == bus_num) {
1560 return bus;
1561 }
1562
1563 /* try child bus */
1564 if (!bus->parent_dev /* host pci bridge */ ||
1565 (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1566 bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1567 for (; bus; bus = sec) {
1568 QLIST_FOREACH(sec, &bus->child, sibling) {
1569 assert(sec->parent_dev);
1570 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1571 return sec;
1572 }
1573 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1574 bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1575 break;
1576 }
1577 }
1578 }
1579 }
1580
1581 return NULL;
1582 }
1583
1584 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1585 {
1586 bus = pci_find_bus(bus, bus_num);
1587
1588 if (!bus)
1589 return NULL;
1590
1591 return bus->devices[PCI_DEVFN(slot, function)];
1592 }
1593
1594 static int pci_bridge_initfn(PCIDevice *dev)
1595 {
1596 PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1597
1598 pci_config_set_vendor_id(s->dev.config, s->vid);
1599 pci_config_set_device_id(s->dev.config, s->did);
1600
1601 pci_set_word(dev->config + PCI_STATUS,
1602 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1603 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1604 dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE;
1605 pci_set_word(dev->config + PCI_SEC_STATUS,
1606 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1607 return 0;
1608 }
1609
1610 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1611 {
1612 PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1613 PCIBus *bus = &s->bus;
1614 pci_unregister_secondary_bus(bus);
1615 return 0;
1616 }
1617
1618 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1619 pci_map_irq_fn map_irq, const char *name)
1620 {
1621 PCIDevice *dev;
1622 PCIBridge *s;
1623
1624 dev = pci_create(bus, devfn, "pci-bridge");
1625 qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1626 qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1627 qdev_init_nofail(&dev->qdev);
1628
1629 s = DO_UPCAST(PCIBridge, dev, dev);
1630 pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1631 return &s->bus;
1632 }
1633
1634 PCIDevice *pci_bridge_get_device(PCIBus *bus)
1635 {
1636 return bus->parent_dev;
1637 }
1638
1639 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1640 {
1641 PCIDevice *pci_dev = (PCIDevice *)qdev;
1642 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1643 PCIBus *bus;
1644 int devfn, rc;
1645
1646 /* initialize cap_present for pci_is_express() and pci_config_size() */
1647 if (info->is_express) {
1648 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1649 }
1650
1651 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1652 devfn = pci_dev->devfn;
1653 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1654 info->config_read, info->config_write,
1655 info->header_type);
1656 if (pci_dev == NULL)
1657 return -1;
1658 rc = info->init(pci_dev);
1659 if (rc != 0) {
1660 do_pci_unregister_device(pci_dev);
1661 return rc;
1662 }
1663
1664 /* rom loading */
1665 if (pci_dev->romfile == NULL && info->romfile != NULL)
1666 pci_dev->romfile = qemu_strdup(info->romfile);
1667 pci_add_option_rom(pci_dev);
1668
1669 if (qdev->hotplugged)
1670 bus->hotplug(pci_dev, 1);
1671 return 0;
1672 }
1673
1674 static int pci_unplug_device(DeviceState *qdev)
1675 {
1676 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1677
1678 dev->bus->hotplug(dev, 0);
1679 return 0;
1680 }
1681
1682 void pci_qdev_register(PCIDeviceInfo *info)
1683 {
1684 info->qdev.init = pci_qdev_init;
1685 info->qdev.unplug = pci_unplug_device;
1686 info->qdev.exit = pci_unregister_device;
1687 info->qdev.bus_info = &pci_bus_info;
1688 qdev_register(&info->qdev);
1689 }
1690
1691 void pci_qdev_register_many(PCIDeviceInfo *info)
1692 {
1693 while (info->qdev.name) {
1694 pci_qdev_register(info);
1695 info++;
1696 }
1697 }
1698
1699 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1700 {
1701 DeviceState *dev;
1702
1703 dev = qdev_create(&bus->qbus, name);
1704 qdev_prop_set_uint32(dev, "addr", devfn);
1705 return DO_UPCAST(PCIDevice, qdev, dev);
1706 }
1707
1708 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1709 {
1710 PCIDevice *dev = pci_create(bus, devfn, name);
1711 qdev_init_nofail(&dev->qdev);
1712 return dev;
1713 }
1714
1715 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1716 {
1717 int config_size = pci_config_size(pdev);
1718 int offset = PCI_CONFIG_HEADER_SIZE;
1719 int i;
1720 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1721 if (pdev->used[i])
1722 offset = i + 1;
1723 else if (i - offset + 1 == size)
1724 return offset;
1725 return 0;
1726 }
1727
1728 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1729 uint8_t *prev_p)
1730 {
1731 uint8_t next, prev;
1732
1733 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1734 return 0;
1735
1736 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1737 prev = next + PCI_CAP_LIST_NEXT)
1738 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1739 break;
1740
1741 if (prev_p)
1742 *prev_p = prev;
1743 return next;
1744 }
1745
1746 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1747 {
1748 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1749 }
1750
1751 /* Add an option rom for the device */
1752 static int pci_add_option_rom(PCIDevice *pdev)
1753 {
1754 int size;
1755 char *path;
1756 void *ptr;
1757
1758 if (!pdev->romfile)
1759 return 0;
1760 if (strlen(pdev->romfile) == 0)
1761 return 0;
1762
1763 if (!pdev->rom_bar) {
1764 /*
1765 * Load rom via fw_cfg instead of creating a rom bar,
1766 * for 0.11 compatibility.
1767 */
1768 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1769 if (class == 0x0300) {
1770 rom_add_vga(pdev->romfile);
1771 } else {
1772 rom_add_option(pdev->romfile);
1773 }
1774 return 0;
1775 }
1776
1777 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1778 if (path == NULL) {
1779 path = qemu_strdup(pdev->romfile);
1780 }
1781
1782 size = get_image_size(path);
1783 if (size < 0) {
1784 error_report("%s: failed to find romfile \"%s\"",
1785 __FUNCTION__, pdev->romfile);
1786 return -1;
1787 }
1788 if (size & (size - 1)) {
1789 size = 1 << qemu_fls(size);
1790 }
1791
1792 pdev->rom_offset = qemu_ram_alloc(size);
1793
1794 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1795 load_image(path, ptr);
1796 qemu_free(path);
1797
1798 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1799 0, pci_map_option_rom);
1800
1801 return 0;
1802 }
1803
1804 /* Reserve space and add capability to the linked list in pci config space */
1805 int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id,
1806 uint8_t offset, uint8_t size)
1807 {
1808 uint8_t *config = pdev->config + offset;
1809 config[PCI_CAP_LIST_ID] = cap_id;
1810 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1811 pdev->config[PCI_CAPABILITY_LIST] = offset;
1812 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1813 memset(pdev->used + offset, 0xFF, size);
1814 /* Make capability read-only by default */
1815 memset(pdev->wmask + offset, 0, size);
1816 /* Check capability by default */
1817 memset(pdev->cmask + offset, 0xFF, size);
1818 return offset;
1819 }
1820
1821 /* Find and reserve space and add capability to the linked list
1822 * in pci config space */
1823 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1824 {
1825 uint8_t offset = pci_find_space(pdev, size);
1826 if (!offset) {
1827 return -ENOSPC;
1828 }
1829 return pci_add_capability_at_offset(pdev, cap_id, offset, size);
1830 }
1831
1832 /* Unlink capability from the pci config space. */
1833 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1834 {
1835 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1836 if (!offset)
1837 return;
1838 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1839 /* Make capability writeable again */
1840 memset(pdev->wmask + offset, 0xff, size);
1841 /* Clear cmask as device-specific registers can't be checked */
1842 memset(pdev->cmask + offset, 0, size);
1843 memset(pdev->used + offset, 0, size);
1844
1845 if (!pdev->config[PCI_CAPABILITY_LIST])
1846 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1847 }
1848
1849 /* Reserve space for capability at a known offset (to call after load). */
1850 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1851 {
1852 memset(pdev->used + offset, 0xff, size);
1853 }
1854
1855 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1856 {
1857 return pci_find_capability_list(pdev, cap_id, NULL);
1858 }
1859
1860 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1861 {
1862 PCIDevice *d = (PCIDevice *)dev;
1863 const pci_class_desc *desc;
1864 char ctxt[64];
1865 PCIIORegion *r;
1866 int i, class;
1867
1868 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1869 desc = pci_class_descriptions;
1870 while (desc->desc && class != desc->class)
1871 desc++;
1872 if (desc->desc) {
1873 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1874 } else {
1875 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1876 }
1877
1878 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1879 "pci id %04x:%04x (sub %04x:%04x)\n",
1880 indent, "", ctxt,
1881 d->config[PCI_SECONDARY_BUS],
1882 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1883 pci_get_word(d->config + PCI_VENDOR_ID),
1884 pci_get_word(d->config + PCI_DEVICE_ID),
1885 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1886 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1887 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1888 r = &d->io_regions[i];
1889 if (!r->size)
1890 continue;
1891 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1892 " [0x%"FMT_PCIBUS"]\n",
1893 indent, "",
1894 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1895 r->addr, r->addr + r->size - 1);
1896 }
1897 }
1898
1899 static PCIDeviceInfo bridge_info = {
1900 .qdev.name = "pci-bridge",
1901 .qdev.size = sizeof(PCIBridge),
1902 .init = pci_bridge_initfn,
1903 .exit = pci_bridge_exitfn,
1904 .config_write = pci_bridge_write_config,
1905 .header_type = PCI_HEADER_TYPE_BRIDGE,
1906 .qdev.props = (Property[]) {
1907 DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1908 DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1909 DEFINE_PROP_END_OF_LIST(),
1910 }
1911 };
1912
1913 static void pci_register_devices(void)
1914 {
1915 pci_qdev_register(&bridge_info);
1916 }
1917
1918 device_init(pci_register_devices)
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